1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This file and its contents are supplied under the terms of the 31 * Common Development and Distribution License ("CDDL"), version 1.0. 32 * You may only use this file in accordance with the terms of version 33 * 1.0 of the CDDL. 34 * 35 * A full copy of the text of the CDDL should have accompanied this 36 * source. A copy of the CDDL is also available via the Internet at 37 * http://www.illumos.org/license/CDDL. 38 * 39 * Copyright 2018 Joyent, Inc. 40 * Copyright 2021 Oxide Computer Company 41 */ 42 43 #ifndef _VMX_H_ 44 #define _VMX_H_ 45 46 #include "vmcs.h" 47 48 struct vmxctx { 49 uint64_t guest_rdi; /* Guest state */ 50 uint64_t guest_rsi; 51 uint64_t guest_rdx; 52 uint64_t guest_rcx; 53 uint64_t guest_r8; 54 uint64_t guest_r9; 55 uint64_t guest_rax; 56 uint64_t guest_rbx; 57 uint64_t guest_rbp; 58 uint64_t guest_r10; 59 uint64_t guest_r11; 60 uint64_t guest_r12; 61 uint64_t guest_r13; 62 uint64_t guest_r14; 63 uint64_t guest_r15; 64 uint64_t guest_cr2; 65 uint64_t guest_dr0; 66 uint64_t guest_dr1; 67 uint64_t guest_dr2; 68 uint64_t guest_dr3; 69 uint64_t guest_dr6; 70 71 uint64_t host_dr0; 72 uint64_t host_dr1; 73 uint64_t host_dr2; 74 uint64_t host_dr3; 75 uint64_t host_dr6; 76 uint64_t host_dr7; 77 uint64_t host_debugctl; 78 int host_tf; 79 80 int inst_fail_status; 81 }; 82 83 struct vmxcap { 84 int set; 85 uint32_t proc_ctls; 86 uint32_t proc_ctls2; 87 uint32_t exc_bitmap; 88 }; 89 90 struct vmxstate { 91 uint64_t nextrip; /* next instruction to be executed by guest */ 92 int lastcpu; /* host cpu that this 'vcpu' last ran on */ 93 uint16_t vpid; 94 }; 95 96 struct apic_page { 97 uint32_t reg[PAGE_SIZE / 4]; 98 }; 99 CTASSERT(sizeof (struct apic_page) == PAGE_SIZE); 100 101 /* Posted Interrupt Descriptor (described in section 29.6 of the Intel SDM) */ 102 struct pir_desc { 103 uint32_t pir[8]; 104 uint64_t pending; 105 uint64_t unused[3]; 106 } __aligned(64); 107 CTASSERT(sizeof (struct pir_desc) == 64); 108 109 /* Index into the 'guest_msrs[]' array */ 110 enum { 111 IDX_MSR_LSTAR, 112 IDX_MSR_CSTAR, 113 IDX_MSR_STAR, 114 IDX_MSR_SF_MASK, 115 IDX_MSR_KGSBASE, 116 IDX_MSR_PAT, 117 GUEST_MSR_NUM /* must be the last enumeration */ 118 }; 119 120 typedef enum { 121 VS_NONE = 0x0, 122 VS_LAUNCHED = 0x1, 123 VS_LOADED = 0x2 124 } vmcs_state_t; 125 126 /* virtual machine softc */ 127 struct vmx { 128 struct vmcs vmcs[VM_MAXCPU]; /* one vmcs per virtual cpu */ 129 struct apic_page apic_page[VM_MAXCPU]; /* one apic page per vcpu */ 130 uint8_t *msr_bitmap[VM_MAXCPU]; /* one MSR bitmap per vCPU */ 131 struct pir_desc pir_desc[VM_MAXCPU]; 132 uint64_t guest_msrs[VM_MAXCPU][GUEST_MSR_NUM]; 133 uint64_t host_msrs[VM_MAXCPU][GUEST_MSR_NUM]; 134 uint64_t tsc_offset_active[VM_MAXCPU]; 135 vmcs_state_t vmcs_state[VM_MAXCPU]; 136 uintptr_t vmcs_pa[VM_MAXCPU]; 137 void *apic_access_page; 138 struct vmxctx ctx[VM_MAXCPU]; 139 struct vmxcap cap[VM_MAXCPU]; 140 struct vmxstate state[VM_MAXCPU]; 141 uint64_t eptp; 142 enum vmx_caps vmx_caps; 143 struct vm *vm; 144 /* 145 * Track the latest vmspace generation as it is run on a given host CPU. 146 * This allows us to react to modifications to the vmspace (such as 147 * unmap or changed protection) which necessitate flushing any 148 * guest-physical TLB entries tagged for this guest via 'invept'. 149 */ 150 uint64_t eptgen[MAXCPU]; 151 }; 152 CTASSERT((offsetof(struct vmx, vmcs) & PAGE_MASK) == 0); 153 CTASSERT((offsetof(struct vmx, msr_bitmap) & PAGE_MASK) == 0); 154 CTASSERT((offsetof(struct vmx, pir_desc[0]) & 63) == 0); 155 156 static __inline bool 157 vmx_cap_en(const struct vmx *vmx, enum vmx_caps cap) 158 { 159 return ((vmx->vmx_caps & cap) == cap); 160 } 161 162 163 /* 164 * Section 5.2 "Conventions" from Intel Architecture Manual 2B. 165 * 166 * error 167 * VMsucceed 0 168 * VMFailInvalid 1 169 * VMFailValid 2 see also VMCS VM-Instruction Error Field 170 */ 171 #define VM_SUCCESS 0 172 #define VM_FAIL_INVALID 1 173 #define VM_FAIL_VALID 2 174 #define VMX_SET_ERROR_CODE_ASM \ 175 " jnc 1f;" \ 176 " mov $1, %[error];" /* CF: error = 1 */ \ 177 " jmp 3f;" \ 178 "1: jnz 2f;" \ 179 " mov $2, %[error];" /* ZF: error = 2 */ \ 180 " jmp 3f;" \ 181 "2: mov $0, %[error];" \ 182 "3:" 183 184 185 #define VMX_GUEST_VMEXIT 0 186 #define VMX_VMRESUME_ERROR 1 187 #define VMX_VMLAUNCH_ERROR 2 188 #define VMX_INVEPT_ERROR 3 189 #define VMX_VMWRITE_ERROR 4 190 191 int vmx_enter_guest(struct vmxctx *ctx, struct vmx *vmx, int launched); 192 void vmx_call_isr(uintptr_t entry); 193 194 int vmx_set_tsc_offset(struct vmx *vmx, int vcpu, uint64_t offset); 195 196 extern char vmx_exit_guest[]; 197 extern char vmx_exit_guest_flush_rsb[]; 198 199 #endif 200