1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013 Anish Gupta (akgupt3@gmail.com) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* 32 * This file and its contents are supplied under the terms of the 33 * Common Development and Distribution License ("CDDL"), version 1.0. 34 * You may only use this file in accordance with the terms of version 35 * 1.0 of the CDDL. 36 * 37 * A full copy of the text of the CDDL should have accompanied this 38 * source. A copy of the CDDL is also available via the Internet at 39 * http://www.illumos.org/license/CDDL. 40 * 41 * Copyright 2022 Oxide Computer Company 42 */ 43 44 #ifndef _VMCB_H_ 45 #define _VMCB_H_ 46 47 struct svm_softc; 48 49 #define BIT(n) (1ULL << n) 50 51 /* 52 * Secure Virtual Machine: AMD64 Programmer's Manual Vol2, Chapter 15 53 * Layout of VMCB: AMD64 Programmer's Manual Vol2, Appendix B 54 */ 55 56 /* vmcb_ctrl->intercept[] array indices */ 57 #define VMCB_CR_INTCPT 0 58 #define VMCB_DR_INTCPT 1 59 #define VMCB_EXC_INTCPT 2 60 #define VMCB_CTRL1_INTCPT 3 61 #define VMCB_CTRL2_INTCPT 4 62 63 /* intercept[VMCB_CTRL1_INTCPT] fields */ 64 #define VMCB_INTCPT_INTR BIT(0) 65 #define VMCB_INTCPT_NMI BIT(1) 66 #define VMCB_INTCPT_SMI BIT(2) 67 #define VMCB_INTCPT_INIT BIT(3) 68 #define VMCB_INTCPT_VINTR BIT(4) 69 #define VMCB_INTCPT_CR0_WRITE BIT(5) 70 #define VMCB_INTCPT_IDTR_READ BIT(6) 71 #define VMCB_INTCPT_GDTR_READ BIT(7) 72 #define VMCB_INTCPT_LDTR_READ BIT(8) 73 #define VMCB_INTCPT_TR_READ BIT(9) 74 #define VMCB_INTCPT_IDTR_WRITE BIT(10) 75 #define VMCB_INTCPT_GDTR_WRITE BIT(11) 76 #define VMCB_INTCPT_LDTR_WRITE BIT(12) 77 #define VMCB_INTCPT_TR_WRITE BIT(13) 78 #define VMCB_INTCPT_RDTSC BIT(14) 79 #define VMCB_INTCPT_RDPMC BIT(15) 80 #define VMCB_INTCPT_PUSHF BIT(16) 81 #define VMCB_INTCPT_POPF BIT(17) 82 #define VMCB_INTCPT_CPUID BIT(18) 83 #define VMCB_INTCPT_RSM BIT(19) 84 #define VMCB_INTCPT_IRET BIT(20) 85 #define VMCB_INTCPT_INTn BIT(21) 86 #define VMCB_INTCPT_INVD BIT(22) 87 #define VMCB_INTCPT_PAUSE BIT(23) 88 #define VMCB_INTCPT_HLT BIT(24) 89 #define VMCB_INTCPT_INVLPG BIT(25) 90 #define VMCB_INTCPT_INVLPGA BIT(26) 91 #define VMCB_INTCPT_IO BIT(27) 92 #define VMCB_INTCPT_MSR BIT(28) 93 #define VMCB_INTCPT_TASK_SWITCH BIT(29) 94 #define VMCB_INTCPT_FERR_FREEZE BIT(30) 95 #define VMCB_INTCPT_SHUTDOWN BIT(31) 96 97 /* intercept[VMCB_CTRL2_INTCPT] fields */ 98 #define VMCB_INTCPT_VMRUN BIT(0) 99 #define VMCB_INTCPT_VMMCALL BIT(1) 100 #define VMCB_INTCPT_VMLOAD BIT(2) 101 #define VMCB_INTCPT_VMSAVE BIT(3) 102 #define VMCB_INTCPT_STGI BIT(4) 103 #define VMCB_INTCPT_CLGI BIT(5) 104 #define VMCB_INTCPT_SKINIT BIT(6) 105 #define VMCB_INTCPT_RDTSCP BIT(7) 106 #define VMCB_INTCPT_ICEBP BIT(8) 107 #define VMCB_INTCPT_WBINVD BIT(9) 108 #define VMCB_INTCPT_MONITOR BIT(10) 109 #define VMCB_INTCPT_MWAIT BIT(11) 110 #define VMCB_INTCPT_MWAIT_ARMED BIT(12) 111 #define VMCB_INTCPT_XSETBV BIT(13) 112 113 /* VMCB TLB control */ 114 #define VMCB_TLB_FLUSH_NOTHING 0 /* Flush nothing */ 115 #define VMCB_TLB_FLUSH_ALL 1 /* Flush entire TLB */ 116 #define VMCB_TLB_FLUSH_GUEST 3 /* Flush all guest entries */ 117 #define VMCB_TLB_FLUSH_GUEST_NONGLOBAL 7 /* Flush guest non-PG entries */ 118 119 /* VMCB state caching */ 120 #define VMCB_CACHE_NONE 0 /* No caching */ 121 #define VMCB_CACHE_I BIT(0) /* Intercept, TSC off, Pause filter */ 122 #define VMCB_CACHE_IOPM BIT(1) /* I/O and MSR permission */ 123 #define VMCB_CACHE_ASID BIT(2) /* ASID */ 124 #define VMCB_CACHE_TPR BIT(3) /* V_TPR to V_INTR_VECTOR */ 125 #define VMCB_CACHE_NP BIT(4) /* Nested Paging */ 126 #define VMCB_CACHE_CR BIT(5) /* CR0, CR3, CR4 & EFER */ 127 #define VMCB_CACHE_DR BIT(6) /* Debug registers */ 128 #define VMCB_CACHE_DT BIT(7) /* GDT/IDT */ 129 #define VMCB_CACHE_SEG BIT(8) /* User segments, CPL */ 130 #define VMCB_CACHE_CR2 BIT(9) /* page fault address */ 131 #define VMCB_CACHE_LBR BIT(10) /* Last branch */ 132 133 /* VMCB control event injection */ 134 #define VMCB_EVENTINJ_EC_VALID BIT(11) /* Error Code valid */ 135 #define VMCB_EVENTINJ_VALID BIT(31) /* Event valid */ 136 137 /* Event types that can be injected */ 138 #define VMCB_EVENTINJ_TYPE_INTR 0 139 #define VMCB_EVENTINJ_TYPE_NMI (2 << 8) 140 #define VMCB_EVENTINJ_TYPE_EXCEPTION (3 << 8) 141 #define VMCB_EVENTINJ_TYPE_INTn (4 << 8) 142 143 /* VMCB exit code, APM vol2 Appendix C */ 144 #define VMCB_EXIT_CR0_READ 0x00 145 #define VMCB_EXIT_CR15_READ 0x0f 146 #define VMCB_EXIT_CR0_WRITE 0x10 147 #define VMCB_EXIT_CR15_WRITE 0x1f 148 #define VMCB_EXIT_EXCP0 0x40 149 #define VMCB_EXIT_EXCP31 0x5f 150 #define VMCB_EXIT_INTR 0x60 151 #define VMCB_EXIT_NMI 0x61 152 #define VMCB_EXIT_SMI 0x62 153 #define VMCB_EXIT_INIT 0x63 154 #define VMCB_EXIT_VINTR 0x64 155 #define VMCB_EXIT_CR0_SEL_WRITE 0x65 156 #define VMCB_EXIT_PUSHF 0x70 157 #define VMCB_EXIT_POPF 0x71 158 #define VMCB_EXIT_CPUID 0x72 159 #define VMCB_EXIT_IRET 0x74 160 #define VMCB_EXIT_INVD 0x76 161 #define VMCB_EXIT_PAUSE 0x77 162 #define VMCB_EXIT_HLT 0x78 163 #define VMCB_EXIT_INVLPG 0x79 164 #define VMCB_EXIT_INVLPGA 0x7A 165 #define VMCB_EXIT_IO 0x7B 166 #define VMCB_EXIT_MSR 0x7C 167 #define VMCB_EXIT_SHUTDOWN 0x7F 168 #define VMCB_EXIT_VMRUN 0x80 169 #define VMCB_EXIT_VMMCALL 0x81 170 #define VMCB_EXIT_VMLOAD 0x82 171 #define VMCB_EXIT_VMSAVE 0x83 172 #define VMCB_EXIT_STGI 0x84 173 #define VMCB_EXIT_CLGI 0x85 174 #define VMCB_EXIT_SKINIT 0x86 175 #define VMCB_EXIT_WBINVD 0x89 176 #define VMCB_EXIT_MONITOR 0x8A 177 #define VMCB_EXIT_MWAIT 0x8B 178 #define VMCB_EXIT_NPF 0x400 179 #define VMCB_EXIT_INVALID -1 180 181 /* 182 * Move to/from CRx 183 * Bit definitions to decode EXITINFO1 184 */ 185 #define VMCB_CRx_INFO1_GPR(x) ((x) & 0xf) 186 #define VMCB_CRx_INFO1_VALID(x) ((x) & (1UL << 63)) 187 188 /* 189 * Nested page fault. 190 * Bit definitions to decode EXITINFO1. 191 */ 192 #define VMCB_NPF_INFO1_P BIT(0) /* Nested page present. */ 193 #define VMCB_NPF_INFO1_W BIT(1) /* Access was write. */ 194 #define VMCB_NPF_INFO1_U BIT(2) /* Access was user access. */ 195 #define VMCB_NPF_INFO1_RSV BIT(3) /* Reserved bits present. */ 196 #define VMCB_NPF_INFO1_ID BIT(4) /* Code read. */ 197 198 #define VMCB_NPF_INFO1_GPA BIT(32) /* Guest physical address. */ 199 #define VMCB_NPF_INFO1_GPT BIT(33) /* Guest page table. */ 200 201 /* 202 * EXITINTINFO, Interrupt exit info for all intrecepts. 203 * Section 15.7.2, Intercepts during IDT Interrupt Delivery. 204 */ 205 #define VMCB_EXITINTINFO_VECTOR(x) ((x) & 0xFF) 206 #define VMCB_EXITINTINFO_TYPE(x) ((x) & (0x7 << 8)) 207 #define VMCB_EXITINTINFO_EC_VALID(x) (((x) & BIT(11)) != 0) 208 #define VMCB_EXITINTINFO_VALID(x) (((x) & BIT(31)) != 0) 209 #define VMCB_EXITINTINFO_EC(x) (((x) >> 32) & 0xFFFFFFFF) 210 211 /* Offset of various VMCB fields. */ 212 #define VMCB_OFF_CTRL(x) (x) 213 #define VMCB_OFF_STATE(x) ((x) + 0x400) 214 215 #define VMCB_OFF_CR_INTERCEPT VMCB_OFF_CTRL(0x0) 216 #define VMCB_OFF_DR_INTERCEPT VMCB_OFF_CTRL(0x4) 217 #define VMCB_OFF_EXC_INTERCEPT VMCB_OFF_CTRL(0x8) 218 #define VMCB_OFF_INST1_INTERCEPT VMCB_OFF_CTRL(0xC) 219 #define VMCB_OFF_INST2_INTERCEPT VMCB_OFF_CTRL(0x10) 220 #define VMCB_OFF_IO_PERM VMCB_OFF_CTRL(0x40) 221 #define VMCB_OFF_MSR_PERM VMCB_OFF_CTRL(0x48) 222 #define VMCB_OFF_TSC_OFFSET VMCB_OFF_CTRL(0x50) 223 #define VMCB_OFF_ASID VMCB_OFF_CTRL(0x58) 224 #define VMCB_OFF_TLB_CTRL VMCB_OFF_CTRL(0x5C) 225 #define VMCB_OFF_VIRQ VMCB_OFF_CTRL(0x60) 226 #define VMCB_OFF_EXIT_REASON VMCB_OFF_CTRL(0x70) 227 #define VMCB_OFF_EXITINFO1 VMCB_OFF_CTRL(0x78) 228 #define VMCB_OFF_EXITINFO2 VMCB_OFF_CTRL(0x80) 229 #define VMCB_OFF_EXITINTINFO VMCB_OFF_CTRL(0x88) 230 #define VMCB_OFF_AVIC_BAR VMCB_OFF_CTRL(0x98) 231 #define VMCB_OFF_NPT_BASE VMCB_OFF_CTRL(0xB0) 232 #define VMCB_OFF_AVIC_PAGE VMCB_OFF_CTRL(0xE0) 233 #define VMCB_OFF_AVIC_LT VMCB_OFF_CTRL(0xF0) 234 #define VMCB_OFF_AVIC_PT VMCB_OFF_CTRL(0xF8) 235 #define VMCB_OFF_SYSENTER_CS VMCB_OFF_STATE(0x228) 236 #define VMCB_OFF_SYSENTER_ESP VMCB_OFF_STATE(0x230) 237 #define VMCB_OFF_SYSENTER_EIP VMCB_OFF_STATE(0x238) 238 #define VMCB_OFF_GUEST_PAT VMCB_OFF_STATE(0x268) 239 240 #ifdef _KERNEL 241 /* VMCB save state area segment format */ 242 struct vmcb_segment { 243 uint16_t selector; 244 uint16_t attrib; 245 uint32_t limit; 246 uint64_t base; 247 }; 248 CTASSERT(sizeof (struct vmcb_segment) == 16); 249 250 /* Convert to/from vmcb segment access to generic (VMX) access */ 251 #define VMCB_ATTR2ACCESS(attr) ((((attr) & 0xf00) << 4) | ((attr) & 0xff)) 252 #define VMCB_ACCESS2ATTR(acc) ((((acc) & 0xf000) >> 4) | ((acc) & 0xff)) 253 254 /* Code segment descriptor attribute in 12 bit format as saved by VMCB. */ 255 #define VMCB_CS_ATTRIB_L BIT(9) /* Long mode. */ 256 #define VMCB_CS_ATTRIB_D BIT(10) /* OPerand size bit. */ 257 258 /* Fields for Virtual Interrupt Control (v_irq) */ 259 #define V_IRQ BIT(0) /* Offset 0x60 bit 8 (0x61 bit 0) */ 260 #define V_VGIF_VALUE BIT(1) /* Offset 0x60 bit 9 (0x61 bit 1) */ 261 262 /* Fields for Virtual Interrupt Control (v_intr_prio) */ 263 #define V_INTR_PRIO 0xf /* Offset 0x60 bits 16-19 (0x62 bits 0-3) */ 264 #define V_IGN_TPR BIT(4) /* Offset 0x60 bit 20 (0x62 bit 4) */ 265 266 /* Fields for Virtual Interrupt Control (v_intr_ctrl) */ 267 #define V_INTR_MASKING BIT(0) /* Offset 0x60 bit 24 (0x63 bit 0) */ 268 #define V_VGIF_ENABLE BIT(1) /* Offset 0x60 bit 25 (0x63 bit 1) */ 269 #define V_AVIC_ENABLE BIT(7) /* Offset 0x60 bit 31 (0x63 bit 7) */ 270 271 /* Fields in Interrupt Shadow, offset 0x68 */ 272 #define VIRTUAL_INTR_SHADOW BIT(0) 273 #define GUEST_INTERRUPT_MASK BIT(1) 274 275 /* Fields in Nested Paging, offset 0x90 */ 276 #define NP_ENABLE BIT(0) /* Enable nested paging */ 277 #define SEV_ENABLE BIT(1) /* Enable SEV */ 278 #define SEV_ES_ENABLE BIT(2) /* Enable SEV-ES */ 279 #define GUEST_MODE_EXEC_TRAP BIT(3) /* Guest mode execute trap */ 280 #define VIRT_TRANSPAR_ENCRYPT BIT(5) /* Virtual transparent encryption */ 281 282 /* Fields in Misc virt controls, offset 0xB8 */ 283 #define LBR_VIRT_ENABLE BIT(0) /* Enable LBR virtualization accel */ 284 #define VIRT_VMSAVE_VMLOAD BIT(1) /* Virtualized VMSAVE/VMLOAD */ 285 286 /* 287 * The VMCB is divided into two areas - the first one contains various 288 * control bits including the intercept vector and the second one contains 289 * the guest state. 290 */ 291 292 /* VMCB control area - padded up to 1024 bytes */ 293 struct vmcb_ctrl { 294 uint32_t intercept[5]; /* 0x00-0x13: all intercepts */ 295 uint32_t _pad1[10]; /* 0x14-0x3B: Reserved. */ 296 uint32_t pause_ctrl; /* 0x3C, PAUSE filter thresh/count */ 297 uint64_t iopm_base_pa; /* 0x40: IOPM_BASE_PA */ 298 uint64_t msrpm_base_pa; /* 0x48: MSRPM_BASE_PA */ 299 uint64_t tsc_offset; /* 0x50: TSC_OFFSET */ 300 uint32_t asid; /* 0x58: Guest ASID */ 301 uint8_t tlb_ctrl; /* 0x5C: TLB_CONTROL */ 302 uint8_t _pad2[3]; /* 0x5D-0x5F: Reserved. */ 303 uint8_t v_tpr; /* 0x60: Virtual TPR */ 304 uint8_t v_irq; /* 0x61: V_IRQ, V_GIF_VALUE + Reserved */ 305 uint8_t v_intr_prio; /* 0x62: V_INTR_PRIO, V_IGN_TPR */ 306 uint8_t v_intr_ctrl; /* 0x63: V_INTR_MASKING, vGIF and AVIC enable */ 307 uint8_t v_intr_vector; /* 0x64: Virtual interrupt vector */ 308 uint8_t _pad3[3]; /* 0x65-0x67: Reserved */ 309 uint64_t intr_shadow; /* 0x68: Interrupt shadow (and more) */ 310 uint64_t exitcode; /* 0x70, Exitcode */ 311 uint64_t exitinfo1; /* 0x78, EXITINFO1 */ 312 uint64_t exitinfo2; /* 0x80, EXITINFO2 */ 313 uint64_t exitintinfo; /* 0x88, Interrupt exit value. */ 314 uint64_t np_ctrl; /* 0x90, Nested paging control. */ 315 uint64_t _pad4[2]; /* 0x98-0xA7 reserved. */ 316 uint64_t eventinj; /* 0xA8, Event injection. */ 317 uint64_t n_cr3; /* 0xB0, Nested page table. */ 318 uint64_t misc_ctrl; /* 0xB8, Misc virt controls */ 319 uint32_t vmcb_clean; /* 0xC0: VMCB clean bits for caching */ 320 uint32_t _pad5; /* 0xC4: Reserved */ 321 uint64_t nrip; /* 0xC8: Guest next nRIP. */ 322 uint8_t inst_len; /* 0xD0: #NPF decode assist */ 323 uint8_t inst_bytes[15]; /* 0xD1-0xDF: guest instr bytes */ 324 uint64_t avic_page_pa; /* 0xEO: AVIC backing page */ 325 uint64_t _pad6; /* 0xE8-0xEF: Reserved */ 326 uint64_t avic_log_tbl; /* 0xFO: AVIC logical table */ 327 uint64_t avic_phys_tbl; /* 0xF8: AVIC physical page */ 328 uint64_t _pad7; /* 0x100-0x107: Reserved */ 329 uint64_t vmsa_pa; /* 0x108: VMSA pointer */ 330 uint64_t _pad8[94]; /* 0x110-0x3FF: Reserved */ 331 }; 332 CTASSERT(sizeof (struct vmcb_ctrl) == 1024); 333 CTASSERT(offsetof(struct vmcb_ctrl, vmsa_pa) == 0x108); 334 335 struct vmcb_state { 336 struct vmcb_segment es; /* 0x00: 32bit base */ 337 struct vmcb_segment cs; /* 0x10: 32bit base */ 338 struct vmcb_segment ss; /* 0x20: 32bit base */ 339 struct vmcb_segment ds; /* 0x30: 32bit base */ 340 struct vmcb_segment fs; /* 0x40 */ 341 struct vmcb_segment gs; /* 0x50 */ 342 struct vmcb_segment gdt; /* 0x60: base + 16bit limit */ 343 struct vmcb_segment ldt; /* 0x70 */ 344 struct vmcb_segment idt; /* 0x80: base + 16bit limit */ 345 struct vmcb_segment tr; /* 0x90 */ 346 uint8_t _pad1[43]; /* 0xA0-0xCA: Reserved */ 347 uint8_t cpl; /* 0xCB: CPL (real mode: 0, virt: 3) */ 348 uint32_t _pad2; /* 0xCC-0xCF: Reserved */ 349 uint64_t efer; /* 0xD0 */ 350 uint64_t _pad3[14]; /* 0xD8-0x147: Reserved */ 351 uint64_t cr4; /* 0x148 */ 352 uint64_t cr3; /* 0x150 */ 353 uint64_t cr0; /* 0x158 */ 354 uint64_t dr7; /* 0x160 */ 355 uint64_t dr6; /* 0x168 */ 356 uint64_t rflags; /* 0x170 */ 357 uint64_t rip; /* 0x178 */ 358 uint64_t _pad4[11]; /* 0x180-0x1D7: Reserved */ 359 uint64_t rsp; /* 0x1D8 */ 360 uint64_t _pad5[3]; /* 0x1E0-0x1F7: Reserved */ 361 uint64_t rax; /* 0x1F8 */ 362 uint64_t star; /* 0x200 */ 363 uint64_t lstar; /* 0x208 */ 364 uint64_t cstar; /* 0x210 */ 365 uint64_t sfmask; /* 0x218 */ 366 uint64_t kernelgsbase; /* 0x220 */ 367 uint64_t sysenter_cs; /* 0x228 */ 368 uint64_t sysenter_esp; /* 0x230 */ 369 uint64_t sysenter_eip; /* 0x238 */ 370 uint64_t cr2; /* 0x240 */ 371 uint64_t _pad6[4]; /* 0x248-0x267: Reserved */ 372 uint64_t g_pat; /* 0x268 */ 373 uint64_t dbgctl; /* 0x270 */ 374 uint64_t br_from; /* 0x278 */ 375 uint64_t br_to; /* 0x280 */ 376 uint64_t int_from; /* 0x288 */ 377 uint64_t int_to; /* 0x290 */ 378 uint64_t _pad7[301]; /* Reserved up to end of VMCB */ 379 }; 380 CTASSERT(sizeof (struct vmcb_state) == 0xC00); 381 CTASSERT(offsetof(struct vmcb_state, int_to) == 0x290); 382 383 /* 384 * The VMCB aka Virtual Machine Control Block is a 4KB aligned page 385 * in memory that describes the virtual machine. 386 * 387 * The VMCB contains: 388 * - instructions or events in the guest to intercept 389 * - control bits that modify execution environment of the guest 390 * - guest processor state (e.g. general purpose registers) 391 */ 392 struct vmcb { 393 struct vmcb_ctrl ctrl; 394 struct vmcb_state state; 395 }; 396 CTASSERT(sizeof (struct vmcb) == PAGE_SIZE); 397 CTASSERT(offsetof(struct vmcb, state) == 0x400); 398 399 struct vmcb_segment *vmcb_segptr(struct vmcb *vmcb, int type); 400 uint64_t *vmcb_regptr(struct vmcb *vmcb, int ident, uint32_t *dirtyp); 401 uint64_t *vmcb_msr_ptr(struct vmcb *vmcb, uint32_t ident, uint32_t *dirtyp); 402 403 #endif /* _KERNEL */ 404 #endif /* _VMCB_H_ */ 405