1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2014, Neel Natu (neel@freebsd.org) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 /* 29 * This file and its contents are supplied under the terms of the 30 * Common Development and Distribution License ("CDDL"), version 1.0. 31 * You may only use this file in accordance with the terms of version 32 * 1.0 of the CDDL. 33 * 34 * A full copy of the text of the CDDL should have accompanied this 35 * source. A copy of the CDDL is also available via the Internet at 36 * http://www.illumos.org/license/CDDL. 37 */ 38 /* This file is dual-licensed; see usr/src/contrib/bhyve/LICENSE */ 39 40 /* 41 * Copyright 2020 Oxide Computer Company 42 */ 43 44 #include <sys/cdefs.h> 45 46 #include <sys/param.h> 47 #include <sys/errno.h> 48 #include <sys/systm.h> 49 #include <sys/x86_archext.h> 50 #include <sys/privregs.h> 51 52 #include <machine/cpufunc.h> 53 #include <machine/specialreg.h> 54 #include <machine/vmm.h> 55 #include <sys/vmm_kernel.h> 56 57 #include "svm.h" 58 #include "vmcb.h" 59 #include "svm_softc.h" 60 #include "svm_msr.h" 61 62 #ifndef MSR_AMDK8_IPM 63 #define MSR_AMDK8_IPM 0xc0010055 64 #endif 65 66 enum { 67 IDX_MSR_LSTAR, 68 IDX_MSR_CSTAR, 69 IDX_MSR_STAR, 70 IDX_MSR_SF_MASK, 71 HOST_MSR_NUM /* must be the last enumeration */ 72 }; 73 CTASSERT(HOST_MSR_NUM == SVM_HOST_MSR_NUM); 74 75 void 76 svm_msr_guest_init(struct svm_softc *sc, int vcpu) 77 { 78 /* 79 * All the MSRs accessible to the guest are either saved/restored by 80 * hardware on every #VMEXIT/VMRUN (e.g., G_PAT) or are saved/restored 81 * by VMSAVE/VMLOAD (e.g., MSR_GSBASE). 82 * 83 * There are no guest MSRs that are saved/restored "by hand" so nothing 84 * more to do here. 85 */ 86 } 87 88 void 89 svm_msr_guest_enter(struct svm_softc *sc, int vcpu) 90 { 91 uint64_t *host_msrs = sc->host_msrs[vcpu]; 92 93 /* 94 * Save host MSRs (if any) and restore guest MSRs (if any). 95 */ 96 host_msrs[IDX_MSR_LSTAR] = rdmsr(MSR_LSTAR); 97 host_msrs[IDX_MSR_CSTAR] = rdmsr(MSR_CSTAR); 98 host_msrs[IDX_MSR_STAR] = rdmsr(MSR_STAR); 99 host_msrs[IDX_MSR_SF_MASK] = rdmsr(MSR_SF_MASK); 100 101 /* 102 * Set the frequency multiplier MSR to enable guest TSC scaling if 103 * needed. 104 */ 105 uint64_t mult = vm_get_freq_multiplier(sc->vm); 106 if (mult != VM_TSCM_NOSCALE) { 107 wrmsr(MSR_AMD_TSC_RATIO, mult); 108 } 109 } 110 111 void 112 svm_msr_guest_exit(struct svm_softc *sc, int vcpu) 113 { 114 uint64_t *host_msrs = sc->host_msrs[vcpu]; 115 116 /* 117 * Save guest MSRs (if any) and restore host MSRs. 118 */ 119 wrmsr(MSR_LSTAR, host_msrs[IDX_MSR_LSTAR]); 120 wrmsr(MSR_CSTAR, host_msrs[IDX_MSR_CSTAR]); 121 wrmsr(MSR_STAR, host_msrs[IDX_MSR_STAR]); 122 wrmsr(MSR_SF_MASK, host_msrs[IDX_MSR_SF_MASK]); 123 124 /* Reset frequency multiplier MSR if any scaling is configured */ 125 if (vm_get_freq_multiplier(sc->vm) != VM_TSCM_NOSCALE) { 126 wrmsr(MSR_AMD_TSC_RATIO, AMD_TSCM_RESET_VAL); 127 } 128 129 /* MSR_KGSBASE will be restored on the way back to userspace */ 130 } 131 132 vm_msr_result_t 133 svm_rdmsr(struct svm_softc *sc, int vcpu, uint32_t num, uint64_t *result) 134 { 135 switch (num) { 136 case MSR_SYSCFG: 137 case MSR_AMDK8_IPM: 138 case MSR_EXTFEATURES: 139 *result = 0; 140 break; 141 case MSR_AMD_DE_CFG: 142 *result = 0; 143 /* 144 * Bit 1 of DE_CFG is defined by AMD to control whether the 145 * lfence instruction is serializing. Practically all CPUs 146 * supported by bhyve also contain this MSR, making it safe to 147 * expose unconditionally. 148 */ 149 if (is_x86_feature(x86_featureset, X86FSET_LFENCE_SER)) { 150 *result |= AMD_DE_CFG_LFENCE_DISPATCH; 151 } 152 break; 153 default: 154 return (VMR_UNHANLDED); 155 } 156 return (VMR_OK); 157 } 158 159 vm_msr_result_t 160 svm_wrmsr(struct svm_softc *sc, int vcpu, uint32_t num, uint64_t val) 161 { 162 switch (num) { 163 case MSR_SYSCFG: 164 /* Ignore writes */ 165 break; 166 case MSR_AMD_DE_CFG: 167 /* Ignore writes */ 168 break; 169 case MSR_AMDK8_IPM: 170 /* 171 * Ignore writes to the "Interrupt Pending Message" MSR. 172 */ 173 break; 174 case MSR_K8_UCODE_UPDATE: 175 /* 176 * Ignore writes to microcode update register. 177 */ 178 break; 179 case MSR_EXTFEATURES: 180 break; 181 default: 182 return (VMR_UNHANLDED); 183 } 184 185 return (VMR_OK); 186 } 187