17c8c0b82SPatrick Mooney /*-
232640292SAndy Fiddaman * SPDX-License-Identifier: BSD-2-Clause
37c8c0b82SPatrick Mooney *
47c8c0b82SPatrick Mooney * Copyright (c) 2014, Neel Natu (neel@freebsd.org)
57c8c0b82SPatrick Mooney * All rights reserved.
67c8c0b82SPatrick Mooney *
77c8c0b82SPatrick Mooney * Redistribution and use in source and binary forms, with or without
87c8c0b82SPatrick Mooney * modification, are permitted provided that the following conditions
97c8c0b82SPatrick Mooney * are met:
107c8c0b82SPatrick Mooney * 1. Redistributions of source code must retain the above copyright
117c8c0b82SPatrick Mooney * notice unmodified, this list of conditions, and the following
127c8c0b82SPatrick Mooney * disclaimer.
137c8c0b82SPatrick Mooney * 2. Redistributions in binary form must reproduce the above copyright
147c8c0b82SPatrick Mooney * notice, this list of conditions and the following disclaimer in the
157c8c0b82SPatrick Mooney * documentation and/or other materials provided with the distribution.
167c8c0b82SPatrick Mooney *
177c8c0b82SPatrick Mooney * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
187c8c0b82SPatrick Mooney * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
197c8c0b82SPatrick Mooney * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
207c8c0b82SPatrick Mooney * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
217c8c0b82SPatrick Mooney * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
227c8c0b82SPatrick Mooney * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
237c8c0b82SPatrick Mooney * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
247c8c0b82SPatrick Mooney * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
257c8c0b82SPatrick Mooney * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
267c8c0b82SPatrick Mooney * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
277c8c0b82SPatrick Mooney */
287c8c0b82SPatrick Mooney /*
297c8c0b82SPatrick Mooney * This file and its contents are supplied under the terms of the
307c8c0b82SPatrick Mooney * Common Development and Distribution License ("CDDL"), version 1.0.
317c8c0b82SPatrick Mooney * You may only use this file in accordance with the terms of version
327c8c0b82SPatrick Mooney * 1.0 of the CDDL.
337c8c0b82SPatrick Mooney *
347c8c0b82SPatrick Mooney * A full copy of the text of the CDDL should have accompanied this
357c8c0b82SPatrick Mooney * source. A copy of the CDDL is also available via the Internet at
367c8c0b82SPatrick Mooney * http://www.illumos.org/license/CDDL.
377c8c0b82SPatrick Mooney *
387c8c0b82SPatrick Mooney * Copyright 2020 Oxide Computer Company
397c8c0b82SPatrick Mooney */
407c8c0b82SPatrick Mooney
417c8c0b82SPatrick Mooney #include <sys/cdefs.h>
427c8c0b82SPatrick Mooney
437c8c0b82SPatrick Mooney #include <sys/param.h>
447c8c0b82SPatrick Mooney #include <sys/errno.h>
457c8c0b82SPatrick Mooney #include <sys/systm.h>
467c8c0b82SPatrick Mooney #include <sys/x86_archext.h>
477c8c0b82SPatrick Mooney #include <sys/privregs.h>
487c8c0b82SPatrick Mooney
497c8c0b82SPatrick Mooney #include <machine/cpufunc.h>
507c8c0b82SPatrick Mooney #include <machine/specialreg.h>
517c8c0b82SPatrick Mooney #include <machine/vmm.h>
527c8c0b82SPatrick Mooney #include <sys/vmm_kernel.h>
537c8c0b82SPatrick Mooney
547c8c0b82SPatrick Mooney #include "svm.h"
557c8c0b82SPatrick Mooney #include "vmcb.h"
567c8c0b82SPatrick Mooney #include "svm_softc.h"
577c8c0b82SPatrick Mooney #include "svm_msr.h"
587c8c0b82SPatrick Mooney
597c8c0b82SPatrick Mooney #ifndef MSR_AMDK8_IPM
607c8c0b82SPatrick Mooney #define MSR_AMDK8_IPM 0xc0010055
617c8c0b82SPatrick Mooney #endif
627c8c0b82SPatrick Mooney
637c8c0b82SPatrick Mooney enum {
647c8c0b82SPatrick Mooney IDX_MSR_LSTAR,
657c8c0b82SPatrick Mooney IDX_MSR_CSTAR,
667c8c0b82SPatrick Mooney IDX_MSR_STAR,
677c8c0b82SPatrick Mooney IDX_MSR_SF_MASK,
687c8c0b82SPatrick Mooney HOST_MSR_NUM /* must be the last enumeration */
697c8c0b82SPatrick Mooney };
707c8c0b82SPatrick Mooney CTASSERT(HOST_MSR_NUM == SVM_HOST_MSR_NUM);
717c8c0b82SPatrick Mooney
727c8c0b82SPatrick Mooney void
svm_msr_guest_init(struct svm_softc * sc,int vcpu)737c8c0b82SPatrick Mooney svm_msr_guest_init(struct svm_softc *sc, int vcpu)
747c8c0b82SPatrick Mooney {
757c8c0b82SPatrick Mooney /*
767c8c0b82SPatrick Mooney * All the MSRs accessible to the guest are either saved/restored by
777c8c0b82SPatrick Mooney * hardware on every #VMEXIT/VMRUN (e.g., G_PAT) or are saved/restored
787c8c0b82SPatrick Mooney * by VMSAVE/VMLOAD (e.g., MSR_GSBASE).
797c8c0b82SPatrick Mooney *
807c8c0b82SPatrick Mooney * There are no guest MSRs that are saved/restored "by hand" so nothing
817c8c0b82SPatrick Mooney * more to do here.
827c8c0b82SPatrick Mooney */
837c8c0b82SPatrick Mooney }
847c8c0b82SPatrick Mooney
857c8c0b82SPatrick Mooney void
svm_msr_guest_enter(struct svm_softc * sc,int vcpu)867c8c0b82SPatrick Mooney svm_msr_guest_enter(struct svm_softc *sc, int vcpu)
877c8c0b82SPatrick Mooney {
887c8c0b82SPatrick Mooney uint64_t *host_msrs = sc->host_msrs[vcpu];
897c8c0b82SPatrick Mooney
907c8c0b82SPatrick Mooney /*
917c8c0b82SPatrick Mooney * Save host MSRs (if any) and restore guest MSRs (if any).
927c8c0b82SPatrick Mooney */
937c8c0b82SPatrick Mooney host_msrs[IDX_MSR_LSTAR] = rdmsr(MSR_LSTAR);
947c8c0b82SPatrick Mooney host_msrs[IDX_MSR_CSTAR] = rdmsr(MSR_CSTAR);
957c8c0b82SPatrick Mooney host_msrs[IDX_MSR_STAR] = rdmsr(MSR_STAR);
967c8c0b82SPatrick Mooney host_msrs[IDX_MSR_SF_MASK] = rdmsr(MSR_SF_MASK);
97717646f7SJordan Paige Hendricks
98717646f7SJordan Paige Hendricks /*
99717646f7SJordan Paige Hendricks * Set the frequency multiplier MSR to enable guest TSC scaling if
100717646f7SJordan Paige Hendricks * needed.
101717646f7SJordan Paige Hendricks */
102717646f7SJordan Paige Hendricks uint64_t mult = vm_get_freq_multiplier(sc->vm);
103717646f7SJordan Paige Hendricks if (mult != VM_TSCM_NOSCALE) {
104717646f7SJordan Paige Hendricks wrmsr(MSR_AMD_TSC_RATIO, mult);
105717646f7SJordan Paige Hendricks }
1067c8c0b82SPatrick Mooney }
1077c8c0b82SPatrick Mooney
1087c8c0b82SPatrick Mooney void
svm_msr_guest_exit(struct svm_softc * sc,int vcpu)1097c8c0b82SPatrick Mooney svm_msr_guest_exit(struct svm_softc *sc, int vcpu)
1107c8c0b82SPatrick Mooney {
1117c8c0b82SPatrick Mooney uint64_t *host_msrs = sc->host_msrs[vcpu];
1127c8c0b82SPatrick Mooney
1137c8c0b82SPatrick Mooney /*
1147c8c0b82SPatrick Mooney * Save guest MSRs (if any) and restore host MSRs.
1157c8c0b82SPatrick Mooney */
1167c8c0b82SPatrick Mooney wrmsr(MSR_LSTAR, host_msrs[IDX_MSR_LSTAR]);
1177c8c0b82SPatrick Mooney wrmsr(MSR_CSTAR, host_msrs[IDX_MSR_CSTAR]);
1187c8c0b82SPatrick Mooney wrmsr(MSR_STAR, host_msrs[IDX_MSR_STAR]);
1197c8c0b82SPatrick Mooney wrmsr(MSR_SF_MASK, host_msrs[IDX_MSR_SF_MASK]);
1207c8c0b82SPatrick Mooney
121*4bd36be4SPatrick Mooney /* Reset frequency multiplier MSR if any scaling is configured */
122*4bd36be4SPatrick Mooney if (vm_get_freq_multiplier(sc->vm) != VM_TSCM_NOSCALE) {
123717646f7SJordan Paige Hendricks wrmsr(MSR_AMD_TSC_RATIO, AMD_TSCM_RESET_VAL);
124*4bd36be4SPatrick Mooney }
125717646f7SJordan Paige Hendricks
1267c8c0b82SPatrick Mooney /* MSR_KGSBASE will be restored on the way back to userspace */
1277c8c0b82SPatrick Mooney }
1287c8c0b82SPatrick Mooney
1297c8c0b82SPatrick Mooney vm_msr_result_t
svm_rdmsr(struct svm_softc * sc,int vcpu,uint32_t num,uint64_t * result)1307c8c0b82SPatrick Mooney svm_rdmsr(struct svm_softc *sc, int vcpu, uint32_t num, uint64_t *result)
1317c8c0b82SPatrick Mooney {
1327c8c0b82SPatrick Mooney switch (num) {
1337c8c0b82SPatrick Mooney case MSR_SYSCFG:
1347c8c0b82SPatrick Mooney case MSR_AMDK8_IPM:
1357c8c0b82SPatrick Mooney case MSR_EXTFEATURES:
1367c8c0b82SPatrick Mooney *result = 0;
1377c8c0b82SPatrick Mooney break;
1387c8c0b82SPatrick Mooney case MSR_AMD_DE_CFG:
1397c8c0b82SPatrick Mooney *result = 0;
1407c8c0b82SPatrick Mooney /*
1417c8c0b82SPatrick Mooney * Bit 1 of DE_CFG is defined by AMD to control whether the
1427c8c0b82SPatrick Mooney * lfence instruction is serializing. Practically all CPUs
1437c8c0b82SPatrick Mooney * supported by bhyve also contain this MSR, making it safe to
1447c8c0b82SPatrick Mooney * expose unconditionally.
1457c8c0b82SPatrick Mooney */
1467c8c0b82SPatrick Mooney if (is_x86_feature(x86_featureset, X86FSET_LFENCE_SER)) {
1477c8c0b82SPatrick Mooney *result |= AMD_DE_CFG_LFENCE_DISPATCH;
1487c8c0b82SPatrick Mooney }
1497c8c0b82SPatrick Mooney break;
1507c8c0b82SPatrick Mooney default:
1517c8c0b82SPatrick Mooney return (VMR_UNHANLDED);
1527c8c0b82SPatrick Mooney }
1537c8c0b82SPatrick Mooney return (VMR_OK);
1547c8c0b82SPatrick Mooney }
1557c8c0b82SPatrick Mooney
1567c8c0b82SPatrick Mooney vm_msr_result_t
svm_wrmsr(struct svm_softc * sc,int vcpu,uint32_t num,uint64_t val)1577c8c0b82SPatrick Mooney svm_wrmsr(struct svm_softc *sc, int vcpu, uint32_t num, uint64_t val)
1587c8c0b82SPatrick Mooney {
1597c8c0b82SPatrick Mooney switch (num) {
1607c8c0b82SPatrick Mooney case MSR_SYSCFG:
1617c8c0b82SPatrick Mooney /* Ignore writes */
1627c8c0b82SPatrick Mooney break;
1637c8c0b82SPatrick Mooney case MSR_AMD_DE_CFG:
1647c8c0b82SPatrick Mooney /* Ignore writes */
1657c8c0b82SPatrick Mooney break;
1667c8c0b82SPatrick Mooney case MSR_AMDK8_IPM:
1677c8c0b82SPatrick Mooney /*
1687c8c0b82SPatrick Mooney * Ignore writes to the "Interrupt Pending Message" MSR.
1697c8c0b82SPatrick Mooney */
1707c8c0b82SPatrick Mooney break;
1717c8c0b82SPatrick Mooney case MSR_K8_UCODE_UPDATE:
1727c8c0b82SPatrick Mooney /*
1737c8c0b82SPatrick Mooney * Ignore writes to microcode update register.
1747c8c0b82SPatrick Mooney */
1757c8c0b82SPatrick Mooney break;
1767c8c0b82SPatrick Mooney case MSR_EXTFEATURES:
1777c8c0b82SPatrick Mooney break;
1787c8c0b82SPatrick Mooney default:
1797c8c0b82SPatrick Mooney return (VMR_UNHANLDED);
1807c8c0b82SPatrick Mooney }
1817c8c0b82SPatrick Mooney
1827c8c0b82SPatrick Mooney return (VMR_OK);
1837c8c0b82SPatrick Mooney }
184