1 /* 2 * 3 * O.S : Solaris 4 * FILE NAME : arcmsr.h 5 * BY : Erich Chen 6 * Description: SCSI RAID Device Driver for 7 * ARECA RAID Host adapter 8 * *************************************************************************** 9 * Copyright (C) 2002,2007 Areca Technology Corporation All rights reserved. 10 * Copyright (C) 2002,2007 Erich Chen 11 * Web site: www.areca.com.tw 12 * E-mail: erich@areca.com.tw 13 * *********************************************************************** 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. The party using or redistributing the source code and binary forms 23 * agrees to the disclaimer below and the terms and conditions set forth 24 * herein. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * ************************************************************************* 38 */ 39 /* 40 * CDDL HEADER START 41 * 42 * The contents of this file are subject to the terms of the 43 * Common Development and Distribution License (the "License"). 44 * You may not use this file except in compliance with the License. 45 * 46 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 47 * or http://www.opensolaris.org/os/licensing. 48 * See the License for the specific language governing permissions 49 * and limitations under the License. 50 * 51 * When distributing Covered Code, include this CDDL HEADER in each 52 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 53 * If applicable, add the following below this CDDL HEADER, with the 54 * fields enclosed by brackets "[]" replaced with your own identifying 55 * information: Portions Copyright [yyyy] [name of copyright owner] 56 * 57 * CDDL HEADER END 58 */ 59 /* 60 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 61 * Use is subject to license terms. 62 */ 63 64 #ifndef _SYS_SCSI_ADAPTERS_ARCMSR_H 65 #define _SYS_SCSI_ADAPTERS_ARCMSR_H 66 67 #ifdef __cplusplus 68 extern "C" { 69 #endif 70 71 #include <sys/sysmacros.h> 72 73 #ifndef TRUE 74 #define TRUE 1 75 #define FALSE 0 76 #endif 77 78 79 #ifdef DEBUG 80 #define ARCMSR_DEBUG 1 81 #endif /* DEBUG */ 82 83 84 #define ARCMSR_DRIVER_VERSION "1.20.00.15Sun" 85 #define ARCMSR_SCSI_INITIATOR_ID 255 86 #define ARCMSR_DEV_SECTOR_SIZE 512 87 #define ARCMSR_MAX_XFER_SECTORS 256 88 #define ARCMSR_MAX_SG_ENTRIES 38 /* max 38 */ 89 #define ARCMSR_MAX_XFER_LEN 0x00200000 /* 2M */ 90 #define ARCMSR_MAX_TARGETID 17 /* 0-16 */ 91 #define ARCMSR_MAX_TARGETLUN 8 /* 0-7 */ 92 #define ARCMSR_MAX_DPC 16 /* defer procedure call */ 93 #define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */ 94 #define ARCMSR_MAX_ADAPTER 4 /* limitation due to pci-e slots */ 95 #define ARCMSR_MAX_HBB_POSTQUEUE 264 /* ARCMSR_MAX_OUTSTANDING_CMD+8 */ 96 97 #define ARCMSR_MAX_OUTSTANDING_CMD 256 98 #define ARCMSR_MAX_FREECCB_NUM 320 99 100 #define CHIP_REG_READ8(handle, a) \ 101 (ddi_get8(handle, (uint8_t *)(a))) 102 #define CHIP_REG_READ16(handle, a) \ 103 (ddi_get16(handle, (uint16_t *)(a))) 104 #define CHIP_REG_READ32(handle, a) \ 105 (ddi_get32(handle, (uint32_t *)(a))) 106 #define CHIP_REG_READ64(handle, a) \ 107 (ddi_get64(handle, (uint64_t *)(a))) 108 #define CHIP_REG_WRITE8(handle, a, d) \ 109 ddi_put8(handle, (uint8_t *)(a), (uint8_t)(d)) 110 #define CHIP_REG_WRITE16(handle, a, d) \ 111 ddi_put16(handle, (uint16_t *)(a), (uint16_t)(d)) 112 #define CHIP_REG_WRITE32(handle, a, d) \ 113 ddi_put32(handle, (uint32_t *)(a), (uint32_t)(d)) 114 #define CHIP_REG_WRITE64(handle, a, d) \ 115 ddi_put64(handle, (uint64_t *)(a), (uint64_t)(d)) 116 117 118 #define ARCOFFSET(type, member) \ 119 ((size_t)(&((type *)0)->member)) 120 121 122 #define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */ 123 #define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */ 124 #define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */ 125 #define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */ 126 #define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */ 127 #define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */ 128 #define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */ 129 #define PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID */ 130 #define PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID */ 131 #define PCI_DEVICE_ID_ARECA_1260 0x1260 /* Device ID */ 132 #define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */ 133 #define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */ 134 #define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */ 135 #define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */ 136 #define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */ 137 #define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */ 138 #define PCI_DEVICE_ID_ARECA_1201 0x1201 /* Device ID */ 139 140 141 #define dma_addr_hi32(addr) (uint32_t)((addr>>16)>>16) 142 #define dma_addr_lo32(addr) (uint32_t)(addr & 0xffffffff) 143 144 /* 145 * IOCTL CONTROL CODE 146 */ 147 struct CMD_MESSAGE { 148 uint32_t HeaderLength; 149 uint8_t Signature[8]; 150 uint32_t Timeout; 151 uint32_t ControlCode; 152 uint32_t ReturnCode; 153 uint32_t Length; 154 }; 155 156 157 #define MSGDATABUFLEN 224 158 struct CMD_MESSAGE_FIELD { 159 struct CMD_MESSAGE cmdmessage; /* 28 byte ioctl header */ 160 uint8_t messagedatabuffer[224]; /* 1032 */ 161 /* areca gui program does not accept more than 1031 byte */ 162 }; 163 164 /* IOP message transfer */ 165 #define ARCMSR_MESSAGE_FAIL 0x0001 166 167 /* error code for StorPortLogError,ScsiPortLogError */ 168 #define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001 169 #define ARCMSR_IOP_ERROR_VENDORID 0x0002 170 #define ARCMSR_IOP_ERROR_DEVICEID 0x0002 171 #define ARCMSR_IOP_ERROR_ILLEGALCDB 0x0003 172 #define ARCMSR_IOP_ERROR_UNKNOW_CDBERR 0x0004 173 #define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE 0x0005 174 #define ARCMSR_SYS_ERROR_MEMORY_CROSS4G 0x0006 175 #define ARCMSR_SYS_ERROR_MEMORY_LACK 0x0007 176 #define ARCMSR_SYS_ERROR_MEMORY_RANGE 0x0008 177 #define ARCMSR_SYS_ERROR_DEVICE_BASE 0x0009 178 #define ARCMSR_SYS_ERROR_PORT_VALIDATE 0x000A 179 /* DeviceType */ 180 #define ARECA_SATA_RAID 0x9000000 181 /* FunctionCode */ 182 #define FUNCTION_READ_RQBUFFER 0x0801 183 #define FUNCTION_WRITE_WQBUFFER 0x0802 184 #define FUNCTION_CLEAR_RQBUFFER 0x0803 185 #define FUNCTION_CLEAR_WQBUFFER 0x0804 186 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805 187 #define FUNCTION_REQUEST_RETURN_CODE_3F 0x0806 188 #define FUNCTION_SAY_HELLO 0x0807 189 #define FUNCTION_SAY_GOODBYE 0x0808 190 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 191 192 /* ARECA IO CONTROL CODE */ 193 #define ARCMSR_MESSAGE_READ_RQBUFFER \ 194 ARECA_SATA_RAID | FUNCTION_READ_RQBUFFER 195 #define ARCMSR_MESSAGE_WRITE_WQBUFFER \ 196 ARECA_SATA_RAID | FUNCTION_WRITE_WQBUFFER 197 #define ARCMSR_MESSAGE_CLEAR_RQBUFFER \ 198 ARECA_SATA_RAID | FUNCTION_CLEAR_RQBUFFER 199 #define ARCMSR_MESSAGE_CLEAR_WQBUFFER \ 200 ARECA_SATA_RAID | FUNCTION_CLEAR_WQBUFFER 201 #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER \ 202 ARECA_SATA_RAID | FUNCTION_CLEAR_ALLQBUFFER 203 #define ARCMSR_MESSAGE_REQUEST_RETURN_CODE_3F \ 204 ARECA_SATA_RAID | FUNCTION_REQUEST_RETURN_CODE_3F 205 #define ARCMSR_MESSAGE_SAY_HELLO \ 206 ARECA_SATA_RAID | FUNCTION_SAY_HELLO 207 #define ARCMSR_MESSAGE_SAY_GOODBYE \ 208 ARECA_SATA_RAID | FUNCTION_SAY_GOODBYE 209 #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE \ 210 ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE 211 212 /* ARECA IOCTL ReturnCode */ 213 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 214 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 215 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 216 217 /* 218 * SPEC. for Areca HBB adapter 219 */ 220 /* ARECA HBB COMMAND for its FIRMWARE */ 221 /* window of "instruction flags" from driver to iop */ 222 #define ARCMSR_DRV2IOP_DOORBELL 0x00020400 223 #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404 224 /* window of "instruction flags" from iop to driver */ 225 #define ARCMSR_IOP2DRV_DOORBELL 0x00020408 226 #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C 227 228 229 /* ARECA FLAG LANGUAGE */ 230 #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 /* ioctl xfer */ 231 #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 /* ioctl xfer */ 232 #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004 233 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 234 235 #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F 236 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0 237 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7 238 239 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 240 #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 241 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 242 #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 243 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 244 #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 245 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 246 #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 247 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 248 #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 249 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 250 #define ARCMSR_MESSAGE_START_BGRB 0x00060008 251 #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008 252 #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008 253 #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008 254 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */ 255 #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 256 257 #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 /* ioctl xfer */ 258 #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 /* ioctl xfer */ 259 #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004 260 #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008 261 #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 262 263 /* data tunnel buffer between user space program and its firmware */ 264 /* iop msgcode_rwbuffer for message command */ 265 #define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00 266 /* user space data to iop 128bytes */ 267 #define ARCMSR_IOCTL_WBUFFER 0x0000fe00 268 /* iop data to user space 128bytes */ 269 #define ARCMSR_IOCTL_RBUFFER 0x0000ff00 270 #define ARCMSR_HBB_BASE0_OFFSET 0x00000010 271 #define ARCMSR_HBB_BASE1_OFFSET 0x00000018 272 #define ARCMSR_HBB_BASE0_LEN 0x00021000 273 #define ARCMSR_HBB_BASE1_LEN 0x00010000 274 275 /* 276 * structure for holding DMA address data 277 */ 278 #define IS_SG64_ADDR 0x01000000 /* bit24 */ 279 280 /* 32bit Scatter-Gather list */ 281 struct SG32ENTRY { 282 /* bit 24 = 0, high 8 bit = flag, low 24 bit = length */ 283 uint32_t length; 284 uint32_t address; 285 }; 286 287 /* 64bit Scatter-Gather list */ 288 struct SG64ENTRY { 289 /* bit 24 = 1, high 8 bit = flag, low 24 bit = length */ 290 uint32_t length; 291 uint32_t address; 292 uint32_t addresshigh; 293 }; 294 295 296 struct QBUFFER { 297 uint32_t data_len; 298 uint8_t data[124]; 299 }; 300 301 /* 302 * FIRMWARE INFO 303 */ 304 #define ARCMSR_FW_MODEL_OFFSET 0x0f 305 #define ARCMSR_FW_VERS_OFFSET 0x11 306 307 struct FIRMWARE_INFO { 308 uint32_t signature; 309 uint32_t request_len; 310 uint32_t numbers_queue; 311 uint32_t sdram_size; 312 uint32_t ide_channels; 313 char vendor[40]; 314 char model[8]; 315 char firmware_ver[16]; 316 char device_map[16]; 317 }; 318 319 /* 320 * ARECA FIRMWARE SPEC 321 * 322 * Usage of IOP331 adapter 323 * 324 * (All In/Out is in IOP331's view) 325 * 1. Message 0 --> InitThread message and retrun code 326 * 2. Doorbell is used for RS-232 emulation 327 * InDoorBell : 328 * bit0 -- data in ready (DRIVER DATA WRITE OK) 329 * bit1 -- data out has been read 330 * (DRIVER DATA READ OK) 331 * outDoorBell: 332 * bit0 -- data out ready (IOP331 DATA WRITE OK) 333 * bit1 -- data in has been read 334 * (IOP331 DATA READ OK) 335 * 3. Index Memory Usage 336 * offset 0xf00 : for RS232 out (request buffer) 337 * offset 0xe00 : for RS232 in (scratch buffer) 338 * offset 0xa00 : for inbound message code msgcode_rwbuffer 339 * (driver send to IOP331) 340 * offset 0xa00 : for outbound message code msgcode_rwbuffer 341 * (IOP331 send to driver) 342 * 4. RS-232 emulation 343 * Currently 128 byte buffer is used: 344 * 1st uint32_t : Data length (1--124) 345 * Byte 4--127 : Max 124 bytes of data 346 * 5. PostQ 347 * All SCSI Command must be sent through postQ: 348 * (inbound queue port) Request frame must be 32 bytes aligned 349 * # bits 31:27 => flag for post ccb 350 * # bits 26:00 => real address (bit 31:27) of post arcmsr_cdb 351 * bit31 : 0 : 256 bytes frame 352 * 1 : 512 bytes frame 353 * bit30 : 0 : normal request 354 * 1 : BIOS request 355 * bit29 : reserved 356 * bit28 : reserved 357 * bit27 : reserved 358 * ----------------------------------------------------------------------- 359 * (outbount queue port) Request reply 360 * # bits 31:27 => flag for reply 361 * # bits 26:00 => real address (bits 31:27) of reply arcmsr_cdb 362 * # bit31 : must be 0 (for this type of reply) 363 * # bit30 : reserved for BIOS handshake 364 * # bit29 : reserved 365 * # bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData 366 * 1 : Error, see in AdapStatus/DevStatus/SenseData 367 * # bit27 : reserved 368 * 6. BIOS request 369 * All BIOS request is the same with request from PostQ 370 * Except : 371 * Request frame is sent from configuration space 372 * offset: 0x78 : Request Frame (bit30 == 1) 373 * offset: 0x18 : writeonly to generate IRQ to IOP331 374 * Completion of request: 375 * (bit30 == 0, bit28==err flag) 376 * 7. Definition of SGL entry (structure) 377 * 8. Message1 Out - Diag Status Code (????) 378 * 9. Message0 message code : 379 * 0x00 : NOP 380 * 0x01 : Get Config ->offset 0xa00 381 * : for outbound message code msgcode_rwbuffer 382 * (IOP331 send to driver) 383 * Signature 0x87974060(4) 384 * Request len 0x00000200(4) 385 * numbers of queue 0x00000100(4) 386 * SDRAM Size 0x00000100(4)-->256 MB 387 * IDE Channels 0x00000008(4) 388 * vendor 40 bytes char 389 * model 8 bytes char 390 * FirmVer 16 bytes char 391 * Device Map 16 bytes char 392 * 393 * FirmwareVersion DWORD 394 * <== Added for checking of new firmware capability 395 * 0x02 : Set Config ->offset 0xa00 396 * :for inbound message code msgcode_rwbuffer 397 * (driver send to IOP331) 398 * Signature 0x87974063(4) 399 * UPPER32 of Request Frame (4)-->Driver Only 400 * 0x03 : Reset (Abort all queued Command) 401 * 0x04 : Stop Background Activity 402 * 0x05 : Flush Cache 403 * 0x06 : Start Background Activity 404 * (re-start if background is halted) 405 * 0x07 : Check If Host Command Pending 406 * (Novell May Need This Function) 407 * 0x08 : Set controller time ->offset 0xa00 (driver to IOP331) 408 * : for inbound message code msgcode_rwbuffer 409 * byte 0 : 0xaa <-- signature 410 * byte 1 : 0x55 <-- signature 411 * byte 2 : year (04) 412 * byte 3 : month (1..12) 413 * byte 4 : date (1..31) 414 * byte 5 : hour (0..23) 415 * byte 6 : minute (0..59) 416 * byte 7 : second (0..59) 417 * 418 */ 419 420 421 /* signature of set and get firmware config */ 422 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 423 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 424 425 426 /* message code of inbound message register */ 427 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000 428 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 429 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 430 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 431 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 432 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 433 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 434 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 435 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 436 /* doorbell interrupt generator */ 437 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 438 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 439 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 440 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 441 /* ccb areca cdb flag */ 442 #define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000 443 #define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000 444 #define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000 445 #define ARCMSR_CCBREPLY_FLAG_ERROR 0x10000000 446 /* outbound firmware ok */ 447 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 448 449 /* SBus dma burst sizes */ 450 #ifndef BURSTSIZE 451 #define BURSTSIZE 452 #define BURST1 0x01 453 #define BURST2 0x02 454 #define BURST4 0x04 455 #define BURST8 0x08 456 #define BURST16 0x10 457 #define BURST32 0x20 458 #define BURST64 0x40 459 #define BURSTSIZE_MASK 0x7f 460 #define DEFAULT_BURSTSIZE BURST16|BURST8|BURST4|BURST2|BURST1 461 #endif /* BURSTSIZE */ 462 463 464 /* 465 * 466 */ 467 struct ARCMSR_CDB { 468 uint8_t Bus; /* should be 0 */ 469 uint8_t TargetID; /* should be 0..15 */ 470 uint8_t LUN; /* should be 0..7 */ 471 uint8_t Function; /* should be 1 */ 472 473 uint8_t CdbLength; /* set in arcmsr_tran_init_pkt */ 474 uint8_t sgcount; 475 uint8_t Flags; 476 477 /* bit 0: 0(256) / 1(512) bytes */ 478 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 479 /* bit 1: 0(from driver) / 1(from BIOS) */ 480 #define ARCMSR_CDB_FLAG_BIOS 0x02 481 /* bit 2: 0(Data in) / 1(Data out) */ 482 #define ARCMSR_CDB_FLAG_WRITE 0x04 483 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */ 484 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 485 #define ARCMSR_CDB_FLAG_HEADQ 0x08 486 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 487 488 uint8_t Reserved1; 489 490 uint32_t Context; /* Address of this request */ 491 uint32_t DataLength; /* currently unused */ 492 493 uint8_t Cdb[16]; /* SCSI CDB */ 494 /* 495 * Device Status : the same from SCSI bus if error occur 496 * SCSI bus status codes. 497 */ 498 uint8_t DeviceStatus; 499 500 #define SCSISTAT_GOOD 0x00 501 #define SCSISTAT_CHECK_CONDITION 0x02 502 #define SCSISTAT_CONDITION_MET 0x04 503 #define SCSISTAT_BUSY 0x08 504 #define SCSISTAT_INTERMEDIATE 0x10 505 #define SCSISTAT_INTERMEDIATE_COND_MET 0x14 506 #define SCSISTAT_RESERVATION_CONFLICT 0x18 507 #define SCSISTAT_COMMAND_TERMINATED 0x22 508 #define SCSISTAT_QUEUE_FULL 0x28 509 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 510 #define ARCMSR_DEV_ABORTED 0xF1 511 #define ARCMSR_DEV_INIT_FAIL 0xF2 512 513 uint8_t SenseData[15]; 514 515 /* Scatter gather address */ 516 union { 517 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; 518 struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; 519 } sgu; 520 }; 521 522 523 struct HBA_msgUnit { 524 uint32_t resrved0[4]; 525 uint32_t inbound_msgaddr0; 526 uint32_t inbound_msgaddr1; 527 uint32_t outbound_msgaddr0; 528 uint32_t outbound_msgaddr1; 529 uint32_t inbound_doorbell; 530 uint32_t inbound_intstatus; 531 uint32_t inbound_intmask; 532 uint32_t outbound_doorbell; 533 uint32_t outbound_intstatus; 534 uint32_t outbound_intmask; 535 uint32_t reserved1[2]; 536 uint32_t inbound_queueport; 537 uint32_t outbound_queueport; 538 uint32_t reserved2[2]; 539 /* ......local_buffer */ 540 uint32_t reserved3[492]; 541 uint32_t reserved4[128]; 542 uint32_t msgcode_rwbuffer[256]; 543 uint32_t message_wbuffer[32]; 544 uint32_t reserved5[32]; 545 uint32_t message_rbuffer[32]; 546 uint32_t reserved6[32]; 547 }; 548 549 550 struct HBB_DOORBELL { 551 uint8_t doorbell_reserved[132096]; 552 /* 553 * offset 0x00020400:00,01,02,03: window of "instruction flags" 554 * from driver to iop 555 */ 556 uint32_t drv2iop_doorbell; 557 /* 04,05,06,07: doorbell mask */ 558 uint32_t drv2iop_doorbell_mask; 559 /* 08,09,10,11: window of "instruction flags" from iop to driver */ 560 uint32_t iop2drv_doorbell; 561 /* 12,13,14,15: doorbell mask */ 562 uint32_t iop2drv_doorbell_mask; 563 }; 564 565 566 struct HBB_RWBUFFER { 567 uint8_t message_reserved0[64000]; 568 /* offset 0x0000fa00: 0..1023: message code read write 1024bytes */ 569 uint32_t msgcode_rwbuffer[256]; 570 /* offset 0x0000fe00:1024...1151: user space data to iop 128bytes */ 571 uint32_t message_wbuffer[32]; 572 /* 1152...1279: message reserved */ 573 uint32_t message_reserved1[32]; 574 /* offset 0x0000ff00:1280...1407: iop data to user space 128bytes */ 575 uint32_t message_rbuffer[32]; 576 }; 577 578 struct HBB_msgUnit { 579 /* post queue buffer for iop */ 580 uint32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; 581 /* done queue buffer for iop */ 582 uint32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; 583 584 int32_t postq_index; /* post queue index */ 585 int32_t doneq_index; /* done queue index */ 586 struct HBB_DOORBELL *hbb_doorbell; 587 struct HBB_RWBUFFER *hbb_rwbuffer; 588 }; 589 590 struct msgUnit { 591 union { 592 struct HBA_msgUnit hbamu; 593 struct HBB_msgUnit hbbmu; 594 } muu; 595 }; 596 597 598 /* 599 * Adapter Control Block 600 */ 601 struct ACB { 602 uint32_t adapter_type; /* A/B/C/D */ 603 604 #define ACB_ADAPTER_TYPE_A 0x00000001 /* hba (Intel) IOP */ 605 #define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb (Marvell) IOP */ 606 #define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc P IOP */ 607 #define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd A IOP */ 608 609 int32_t dma_sync_size; 610 scsi_hba_tran_t *scsi_hba_transport; 611 dev_info_t *dev_info; 612 ddi_acc_handle_t reg_mu_acc_handle0; 613 ddi_acc_handle_t reg_mu_acc_handle1; 614 ddi_acc_handle_t ccbs_acc_handle; 615 ddi_dma_handle_t ccbs_pool_handle; 616 ddi_dma_cookie_t ccb_cookie; 617 ddi_device_acc_attr_t dev_acc_attr; 618 kmutex_t acb_mutex; 619 kmutex_t postq_mutex; 620 kmutex_t workingQ_mutex; 621 kmutex_t ioctl_mutex; 622 timeout_id_t timeout_id; 623 ddi_iblock_cookie_t iblock_cookie; 624 /* Offset for arc cdb physical to virtual calculations */ 625 unsigned long vir2phy_offset; 626 uint32_t outbound_int_enable; 627 628 /* message unit ATU inbound base address0 virtual */ 629 struct msgUnit *pmu; 630 631 uint8_t adapter_index; 632 uint8_t irq; 633 uint16_t acb_flags; 634 635 #define ACB_F_SCSISTOPADAPTER 0x0001 636 /* stop RAID background rebuild */ 637 #define ACB_F_MSG_STOP_BGRB 0x0002 638 /* stop RAID background rebuild */ 639 #define ACB_F_MSG_START_BGRB 0x0004 640 /* iop ioctl data rqbuffer overflow */ 641 #define ACB_F_IOPDATA_OVERFLOW 0x0008 642 /* ioctl clear wqbuffer */ 643 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 644 /* ioctl clear rqbuffer */ 645 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 646 /* ioctl iop wqbuffer data readed */ 647 #define ACB_F_MESSAGE_WQBUFFER_READ 0x0040 648 #define ACB_F_BUS_RESET 0x0080 649 /* iop init */ 650 #define ACB_F_IOP_INITED 0x0100 651 652 /* serial ccb pointer array */ 653 struct CCB *pccb_pool[ARCMSR_MAX_FREECCB_NUM]; 654 /* working ccb pointer array */ 655 struct CCB *ccbworkingQ[ARCMSR_MAX_FREECCB_NUM]; 656 /* done ccb array index */ 657 int32_t workingccb_doneindex; 658 /* start ccb array index */ 659 int32_t workingccb_startindex; 660 int32_t ccboutstandingcount; 661 662 /* data collection buffer for read from 80331 */ 663 uint8_t rqbuffer[ARCMSR_MAX_QBUFFER]; 664 /* first of read buffer */ 665 int32_t rqbuf_firstidx; 666 /* last of read buffer */ 667 int32_t rqbuf_lastidx; 668 669 /* data collection buffer for write to 80331 */ 670 uint8_t wqbuffer[ARCMSR_MAX_QBUFFER]; 671 /* first of write buffer */ 672 int32_t wqbuf_firstidx; 673 /* last of write buffer */ 674 int32_t wqbuf_lastidx; 675 /* id0 ..... id15,lun0...lun7 */ 676 uint8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; 677 #define ARECA_RAID_GONE 0x55 678 #define ARECA_RAID_GOOD 0xaa 679 680 uint32_t num_resets; 681 uint32_t num_aborts; 682 uint32_t firm_request_len; 683 uint32_t firm_numbers_queue; 684 uint32_t firm_sdram_size; 685 uint32_t firm_ide_channels; 686 char firm_model[12]; 687 char firm_version[20]; 688 ddi_acc_handle_t pci_acc_handle; 689 int tgt_scsi_opts[ARCMSR_MAX_TARGETID]; 690 }; 691 692 693 /* 694 * Command Control Block (SrbExtension) 695 * 696 * CCB must be not cross page boundary,and the order from offset 0 697 * structure describing an ATA disk request this CCB length must be 698 * 32 bytes boundary 699 * 700 */ 701 struct CCB 702 { 703 struct ARCMSR_CDB arcmsr_cdb; 704 uint32_t cdb_shifted_phyaddr; 705 uint16_t ccb_flags; 706 #define CCB_FLAG_READ 0x0000 707 #define CCB_FLAG_WRITE 0x0001 708 #define CCB_FLAG_ERROR 0x0002 709 #define CCB_FLAG_FLUSHCACHE 0x0004 710 #define CCB_FLAG_MASTER_ABORTED 0x0008 711 #define CCB_FLAG_DMAVALID 0x0010 712 #define CCB_FLAG_DMACONSISTENT 0x0020 713 #define CCB_FLAG_DMAWRITE 0x0040 714 #define CCB_FLAG_PKTBIND 0x0080 715 uint16_t startdone; 716 #define ARCMSR_CCB_DONE 0x0000 717 #define ARCMSR_CCB_UNBUILD 0x0000 718 #define ARCMSR_CCB_START 0x55AA 719 #define ARCMSR_CCB_PENDING 0xAA55 720 #define ARCMSR_CCB_RESET 0xA5A5 721 #define ARCMSR_CCB_ABORTED 0x5A5A 722 #define ARCMSR_CCB_ILLEGAL 0xFFFF 723 struct scsi_pkt *pkt; 724 struct ACB *acb; 725 ddi_dma_cookie_t pkt_dmacookies[ARCMSR_MAX_SG_ENTRIES]; 726 ddi_dma_handle_t pkt_dma_handle; 727 uint_t pkt_cookie; 728 uint_t pkt_ncookies; 729 uint_t pkt_nwin; 730 uint_t pkt_curwin; 731 off_t pkt_dma_offset; 732 size_t pkt_dma_len; 733 size_t total_dmac_size; 734 time_t ccb_time; 735 struct buf *bp; 736 ddi_dma_cookie_t resid_dmacookie; 737 #ifdef _LP64 738 uint32_t reserved; 739 #endif 740 }; 741 742 743 /* SenseData[15] */ 744 struct SENSE_DATA { 745 DECL_BITFIELD3( 746 ErrorCode :4, /* Vendor Unique error code */ 747 ErrorClass :3, /* Error Class- fixed at 0x7 */ 748 Valid :1); /* sense data is valid */ 749 750 uint8_t SegmentNumber; /* segment number: for COPY cmd */ 751 752 DECL_BITFIELD5( 753 SenseKey :4, /* Sense key (see below) */ 754 Reserved :1, /* reserved */ 755 IncorrectLength :1, /* Incorrect Length Indicator */ 756 EndOfMedia :1, /* End of Media */ 757 FileMark :1); /* File Mark Detected */ 758 759 uint8_t Information[4]; 760 uint8_t AdditionalSenseLength; 761 uint8_t CommandSpecificInformation[4]; 762 uint8_t AdditionalSenseCode; 763 uint8_t AdditionalSenseCodeQualifier; 764 uint8_t FieldReplaceableUnitCode; 765 }; 766 767 #define VIDLEN 8 768 #define PIDLEN 16 769 #define REVLEN 4 770 struct SCSIInqData { 771 uint8_t DevType; /* Periph Qualifier & Periph Dev Type */ 772 uint8_t RMB_TypeMod; /* rem media bit & Dev Type Modifier */ 773 uint8_t Vers; /* ISO, ECMA, & ANSI versions */ 774 uint8_t RDF; /* AEN, TRMIOP, & response data format */ 775 uint8_t AddLen; /* length of additional data */ 776 uint8_t Res1; /* reserved */ 777 uint8_t Res2; /* reserved */ 778 uint8_t Flags; /* RelADr, Wbus32, Wbus16, Sync etc */ 779 uint8_t VendorID[8]; /* Vendor Identification */ 780 uint8_t ProductID[16]; /* Product Identification */ 781 uint8_t ProductRev[4]; /* Product Revision */ 782 }; 783 784 785 786 /* 787 * These definitions are the register offsets as defined in the Intel 788 * IOP manuals. See (correct as of 18 January 2008) 789 * http://developer.intel.com/design/iio/index.htm?iid=ncdcnav2+stor_ioproc 790 * for more details 791 */ 792 #define ARCMSR_PCI2PCI_VENDORID_REG 0x00 793 #define ARCMSR_PCI2PCI_DEVICEID_REG 0x02 794 #define ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG 0x04 795 #define PCI_DISABLE_INTERRUPT 0x0400 796 #define ARCMSR_PCI2PCI_PRIMARY_STATUS_REG 0x06 797 #define ARCMSR_ADAP_66MHZ 0x20 798 #define ARCMSR_PCI2PCI_REVISIONID_REG 0x08 799 #define ARCMSR_PCI2PCI_CLASSCODE_REG 0x09 800 801 #define ARCMSR_PCI2PCI_PRIMARY_CACHELINESIZE_REG 0x0C 802 #define ARCMSR_PCI2PCI_PRIMARY_LATENCYTIMER_REG 0x0D 803 #define ARCMSR_PCI2PCI_HEADERTYPE_REG 0x0E 804 #define ARCMSR_PCI2PCI_PRIMARY_BUSNUMBER_REG 0x18 805 #define ARCMSR_PCI2PCI_SECONDARY_BUSNUMBER_REG 0x19 806 #define ARCMSR_PCI2PCI_SUBORDINATE_BUSNUMBER_REG 0x1A 807 #define ARCMSR_PCI2PCI_SECONDARY_LATENCYTIMER_REG 0x1B 808 #define ARCMSR_PCI2PCI_IO_BASE_REG 0x1C 809 #define ARCMSR_PCI2PCI_IO_LIMIT_REG 0x1D 810 #define ARCMSR_PCI2PCI_SECONDARY_STATUS_REG 0x1E 811 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_BASE_REG 0x20 812 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_LIMIT_REG 0x22 813 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_REG 0x24 814 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_REG 0x26 815 816 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_UPPER32_REG 0x28 817 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_UPPER32_REG 0x2C 818 819 #define ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG 0x34 820 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG 0x3C 821 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG 0x3D 822 #define ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG 0x3E 823 824 825 #define ARCMSR_ATU_VENDOR_ID_REG 0x00 826 #define ARCMSR_ATU_DEVICE_ID_REG 0x02 827 #define ARCMSR_ATU_COMMAND_REG 0x04 828 #define ARCMSR_ATU_STATUS_REG 0x06 829 #define ARCMSR_ATU_REVISION_REG 0x08 830 #define ARCMSR_ATU_CLASS_CODE_REG 0x09 831 #define ARCMSR_ATU_CACHELINE_SIZE_REG 0x0C 832 #define ARCMSR_ATU_LATENCY_TIMER_REG 0x0D 833 #define ARCMSR_ATU_HEADER_TYPE_REG 0x0E 834 #define ARCMSR_ATU_BIST_REG 0x0F 835 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS0_REG 0x10 836 #define ARCMSR_INBOUND_ATU_MEMORY_PREFETCHABLE 0x08 837 #define ARCMSR_INBOUND_ATU_MEMORY_WINDOW64 0x04 838 839 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS0_REG 0x14 840 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS1_REG 0x18 841 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS1_REG 0x1C 842 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS2_REG 0x20 843 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS2_REG 0x24 844 #define ARCMSR_ATU_SUBSYSTEM_VENDOR_ID_REG 0x2C 845 #define ARCMSR_ATU_SUBSYSTEM_ID_REG 0x2E 846 #define ARCMSR_EXPANSION_ROM_BASE_ADDRESS_REG 0x30 847 848 #define ARCMSR_EXPANSION_ROM_ADDRESS_DECODE_ENABLE 0x01 849 850 #define ARCMSR_ATU_CAPABILITY_PTR_REG 0x34 851 #define ARCMSR_ATU_INTERRUPT_LINE_REG 0x3C 852 #define ARCMSR_ATU_INTERRUPT_PIN_REG 0x3D 853 #define ARCMSR_ATU_MINIMUM_GRANT_REG 0x3E 854 #define ARCMSR_ATU_MAXIMUM_LATENCY_REG 0x3F 855 #define ARCMSR_INBOUND_ATU_LIMIT0_REG 0x40 856 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE0_REG 0x44 857 #define ARCMSR_EXPANSION_ROM_LIMIT_REG 0x48 858 #define ARCMSR_EXPANSION_ROM_TRANSLATE_VALUE_REG 0x4C 859 #define ARCMSR_INBOUND_ATU_LIMIT1_REG 0x50 860 #define ARCMSR_INBOUND_ATU_LIMIT2_REG 0x54 861 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE2_REG 0x58 862 #define ARCMSR_OUTBOUND_IO_WINDOW_TRANSLATE_VALUE_REG 0x5C 863 864 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x60 865 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x64 866 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x68 867 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x6C 868 #define ARCMSR_OUTBOUND_UPPER32_DIRECT_WINDOW_TRANSLATE_VALUE_REG 0x78 869 870 #define ARCMSR_ATU_CONFIGURATION_REG 0x80 871 #define ARCMSR_PCI_CONFIGURATION_STATUS_REG 0x84 872 #define ARCMSR_ATU_INTERRUPT_STATUS_REG 0x88 873 #define ARCMSR_ATU_INTERRUPT_MASK_REG 0x8C 874 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS3_REG 0x90 875 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS3_REG 0x94 876 #define ARCMSR_INBOUND_ATU_LIMIT3_REG 0x98 877 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE3_REG 0x9C 878 879 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_ADDRESS_REG 0xA4 880 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_DATA_REG 0xAC 881 #define ARCMSR_VPD_CAPABILITY_IDENTIFIER_REG 0xB8 882 #define ARCMSR_VPD_NEXT_ITEM_PTR_REG 0xB9 883 #define ARCMSR_VPD_ADDRESS_REG 0xBA 884 #define ARCMSR_VPD_DATA_REG 0xBC 885 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_IDENTIFIER_REG 0xC0 886 #define ARCMSR_POWER_NEXT_ITEM_PTR_REG 0xC1 887 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_REG 0xC2 888 #define ARCMSR_POWER_MANAGEMENT_CONTROL_STATUS_REG 0xC4 889 #define ARCMSR_PCIX_CAPABILITY_IDENTIFIER_REG 0xE0 890 #define ARCMSR_PCIX_NEXT_ITEM_PTR_REG 0xE1 891 #define ARCMSR_PCIX_COMMAND_REG 0xE2 892 #define ARCMSR_PCIX_STATUS_REG 0xE4 893 894 895 #define ARCMSR_MU_INBOUND_MESSAGE_REG0 0x10 896 #define ARCMSR_MU_INBOUND_MESSAGE_REG1 0x14 897 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG0 0x18 898 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG1 0x1C 899 #define ARCMSR_MU_INBOUND_DOORBELL_REG 0x20 900 #define ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG 0x24 901 #define ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG 0x28 902 #define ARCMSR_MU_OUTBOUND_DOORBELL_REG 0x2C 903 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 904 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 905 #define ARCMSR_MU_INBOUND_QUEUE_PORT_REG 0x40 906 #define ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG 0x44 907 908 909 910 #define ARCMSR_MU_INBOUND_MESSAGE0_INT 0x01 911 #define ARCMSR_MU_INBOUND_MESSAGE1_INT 0x02 912 #define ARCMSR_MU_INBOUND_DOORBELL_INT 0x04 913 #define ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT 0x08 914 #define ARCMSR_MU_INBOUND_POSTQUEUE_INT 0x10 915 #define ARCMSR_MU_INBOUND_QUEUEFULL_INT 0x20 916 #define ARCMSR_MU_INBOUND_INDEX_INT 0x40 917 918 #define ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE 0x01 919 #define ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE 0x02 920 #define ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE 0x04 921 #define ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE 0x08 922 #define ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE 0x10 923 #define ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE 0x20 924 #define ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE 0x40 925 926 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 927 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 928 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 929 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 930 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 931 932 933 #define ARCMSR_MU_OUTBOUND_HANDLE_INT \ 934 (ARCMSR_MU_OUTBOUND_MESSAGE0_INT| \ 935 ARCMSR_MU_OUTBOUND_MESSAGE1_INT| \ 936 ARCMSR_MU_OUTBOUND_DOORBELL_INT| \ 937 ARCMSR_MU_OUTBOUND_POSTQUEUE_INT| \ 938 ARCMSR_MU_OUTBOUND_PCI_INT) 939 940 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 941 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 942 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 943 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 944 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 945 946 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F 947 948 #define ARCMSR_MU_CONFIGURATION_REG 0xFFFFE350 949 #define ARCMSR_MU_QUEUE_BASE_ADDRESS_REG 0xFFFFE354 950 #define ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG 0xFFFFE360 951 #define ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG 0xFFFFE364 952 #define ARCMSR_MU_INBOUND_POST_HEAD_PTR_REG 0xFFFFE368 953 #define ARCMSR_MU_INBOUND_POST_TAIL_PTR_REG 0xFFFFE36C 954 #define ARCMSR_MU_LOCAL_MEMORY_INDEX_REG 0xFFFFE380 955 956 #define ARCMSR_MU_CIRCULAR_QUEUE_ENABLE 0x0001 957 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K 0x0002 958 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K 0x0004 959 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K 0x0008 960 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K 0x0010 961 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K 0x0020 962 963 964 965 #ifdef __cplusplus 966 } 967 #endif 968 /* arcmsr.h */ 969 #endif /* _SYS_SCSI_ADAPTERS_ARCMSR_H */ 970