1 /* 2 * 3 * O.S : Solaris 4 * FILE NAME : arcmsr.h 5 * BY : Erich Chen 6 * Description: SCSI RAID Device Driver for 7 * ARECA RAID Host adapter 8 * 9 * Copyright (C) 2002,2007 Areca Technology Corporation All rights reserved. 10 * Copyright (C) 2002,2007 Erich Chen 11 * Web site: www.areca.com.tw 12 * E-mail: erich@areca.com.tw 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. The party using or redistributing the source code and binary forms 23 * agrees to the disclaimer below and the terms and conditions set forth 24 * herein. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 */ 39 /* 40 * CDDL HEADER START 41 * 42 * The contents of this file are subject to the terms of the 43 * Common Development and Distribution License (the "License"). 44 * You may not use this file except in compliance with the License. 45 * 46 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 47 * or http://www.opensolaris.org/os/licensing. 48 * See the License for the specific language governing permissions 49 * and limitations under the License. 50 * 51 * When distributing Covered Code, include this CDDL HEADER in each 52 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 53 * If applicable, add the following below this CDDL HEADER, with the 54 * fields enclosed by brackets "[]" replaced with your own identifying 55 * information: Portions Copyright [yyyy] [name of copyright owner] 56 * 57 * CDDL HEADER END 58 */ 59 /* 60 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 61 * Use is subject to license terms. 62 */ 63 /* 64 * Copyright 2011 Nexenta Systems, Inc. All rights reserved. 65 */ 66 67 #ifndef _SYS_SCSI_ADAPTERS_ARCMSR_H 68 #define _SYS_SCSI_ADAPTERS_ARCMSR_H 69 70 #ifdef __cplusplus 71 extern "C" { 72 #endif 73 74 #include <sys/sysmacros.h> 75 76 #ifndef TRUE 77 #define TRUE 1 78 #define FALSE 0 79 #endif 80 81 82 typedef struct CCB *PCCB; 83 typedef struct ACB *PACB; 84 85 #define ARCMSR_SCSI_INITIATOR_ID 255 86 #define ARCMSR_DEV_SECTOR_SIZE 512 87 #define ARCMSR_MAX_XFER_SECTORS 256 88 #define ARCMSR_MAX_SG_ENTRIES 38 /* max 38 */ 89 #define ARCMSR_MAX_XFER_LEN 0x00200000 /* 2M */ 90 #define ARCMSR_MAX_TARGETID 17 /* 0-16 */ 91 #define ARCMSR_MAX_TARGETLUN 8 /* 0-7 */ 92 #define ARCMSR_MAX_DPC 16 /* defer procedure call */ 93 #define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */ 94 #define ARCMSR_MAX_HBB_POSTQUEUE 264 /* MAX_OUTSTANDING_CMD+8 */ 95 96 #define ARCMSR_MAX_OUTSTANDING_CMD 256 97 #define ARCMSR_MAX_FREECCB_NUM 384 98 #define ARCMSR_TIMEOUT_WATCH 60 99 #define ARCMSR_DEV_MAP_WATCH 5 100 #define ARCMSR_CCB_EXPIRED_TIME 600 /* 10 min */ 101 102 #define CHIP_REG_READ8(handle, a) \ 103 (ddi_get8(handle, (uint8_t *)(a))) 104 #define CHIP_REG_READ16(handle, a) \ 105 (ddi_get16(handle, (uint16_t *)(a))) 106 #define CHIP_REG_READ32(handle, a) \ 107 (ddi_get32(handle, (uint32_t *)(a))) 108 #define CHIP_REG_READ64(handle, a) \ 109 (ddi_get64(handle, (uint64_t *)(a))) 110 #define CHIP_REG_WRITE8(handle, a, d) \ 111 ddi_put8(handle, (uint8_t *)(a), (uint8_t)(d)) 112 #define CHIP_REG_WRITE16(handle, a, d) \ 113 ddi_put16(handle, (uint16_t *)(a), (uint16_t)(d)) 114 #define CHIP_REG_WRITE32(handle, a, d) \ 115 ddi_put32(handle, (uint32_t *)(a), (uint32_t)(d)) 116 #define CHIP_REG_WRITE64(handle, a, d) \ 117 ddi_put64(handle, (uint64_t *)(a), (uint64_t)(d)) 118 119 120 /* NOTE: GETG4ADDRTL(cdbp) is int32_t */ 121 #define ARCMSR_GETGXADDR(cmdlen, cdbp) \ 122 ((cmdlen == 6) ? GETG0ADDR(cdbp) : \ 123 (cmdlen == 10) ? (uint32_t)GETG1ADDR(cdbp) : \ 124 ((uint64_t)GETG4ADDR(cdbp) << 32) | (uint32_t)GETG4ADDRTL(cdbp)) 125 126 #define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */ 127 #define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */ 128 #define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */ 129 #define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */ 130 #define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */ 131 #define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */ 132 #define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */ 133 #define PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID */ 134 #define PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID */ 135 #define PCI_DEVICE_ID_ARECA_1231 0x1231 /* Device ID */ 136 #define PCI_DEVICE_ID_ARECA_1260 0x1260 /* Device ID */ 137 #define PCI_DEVICE_ID_ARECA_1261 0x1261 /* Device ID */ 138 #define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */ 139 #define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */ 140 #define PCI_DEVICE_ID_ARECA_1212 0x1212 /* Device ID */ 141 #define PCI_DEVICE_ID_ARECA_1222 0x1222 /* Device ID */ 142 #define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */ 143 #define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */ 144 #define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */ 145 #define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */ 146 #define PCI_DEVICE_ID_ARECA_1201 0x1201 /* Device ID */ 147 #define PCI_DEVICE_ID_ARECA_1880 0x1880 /* Device ID */ 148 149 #define dma_addr_hi32(addr) (uint32_t)((addr>>16)>>16) 150 #define dma_addr_lo32(addr) (uint32_t)(addr & 0xffffffff) 151 152 /* 153 * IOCTL CONTROL CODE 154 */ 155 struct CMD_MESSAGE { 156 uint32_t HeaderLength; 157 uint8_t Signature[8]; 158 uint32_t Timeout; 159 uint32_t ControlCode; 160 uint32_t ReturnCode; 161 uint32_t Length; 162 }; 163 164 165 #define MSGDATABUFLEN 1031 166 struct CMD_MESSAGE_FIELD { 167 struct CMD_MESSAGE cmdmessage; /* 28 byte ioctl header */ 168 uint8_t messagedatabuffer[MSGDATABUFLEN]; /* 1032 */ 169 /* areca gui program does not accept more than 1031 byte */ 170 }; 171 172 /* IOP message transfer */ 173 #define ARCMSR_MESSAGE_FAIL 0x0001 174 175 /* error code for StorPortLogError,ScsiPortLogError */ 176 #define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001 177 #define ARCMSR_IOP_ERROR_VENDORID 0x0002 178 #define ARCMSR_IOP_ERROR_DEVICEID 0x0002 179 #define ARCMSR_IOP_ERROR_ILLEGALCDB 0x0003 180 #define ARCMSR_IOP_ERROR_UNKNOW_CDBERR 0x0004 181 #define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE 0x0005 182 #define ARCMSR_SYS_ERROR_MEMORY_CROSS4G 0x0006 183 #define ARCMSR_SYS_ERROR_MEMORY_LACK 0x0007 184 #define ARCMSR_SYS_ERROR_MEMORY_RANGE 0x0008 185 #define ARCMSR_SYS_ERROR_DEVICE_BASE 0x0009 186 #define ARCMSR_SYS_ERROR_PORT_VALIDATE 0x000A 187 /* DeviceType */ 188 #define ARECA_SATA_RAID 0x90000000 189 /* FunctionCode */ 190 #define FUNCTION_READ_RQBUFFER 0x0801 191 #define FUNCTION_WRITE_WQBUFFER 0x0802 192 #define FUNCTION_CLEAR_RQBUFFER 0x0803 193 #define FUNCTION_CLEAR_WQBUFFER 0x0804 194 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805 195 #define FUNCTION_REQUEST_RETURN_CODE_3F 0x0806 196 #define FUNCTION_SAY_HELLO 0x0807 197 #define FUNCTION_SAY_GOODBYE 0x0808 198 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 199 200 /* ARECA IO CONTROL CODE */ 201 #define ARCMSR_MESSAGE_READ_RQBUFFER \ 202 ARECA_SATA_RAID | FUNCTION_READ_RQBUFFER 203 #define ARCMSR_MESSAGE_WRITE_WQBUFFER \ 204 ARECA_SATA_RAID | FUNCTION_WRITE_WQBUFFER 205 #define ARCMSR_MESSAGE_CLEAR_RQBUFFER \ 206 ARECA_SATA_RAID | FUNCTION_CLEAR_RQBUFFER 207 #define ARCMSR_MESSAGE_CLEAR_WQBUFFER \ 208 ARECA_SATA_RAID | FUNCTION_CLEAR_WQBUFFER 209 #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER \ 210 ARECA_SATA_RAID | FUNCTION_CLEAR_ALLQBUFFER 211 #define ARCMSR_MESSAGE_REQUEST_RETURN_CODE_3F \ 212 ARECA_SATA_RAID | FUNCTION_REQUEST_RETURN_CODE_3F 213 #define ARCMSR_MESSAGE_SAY_HELLO \ 214 ARECA_SATA_RAID | FUNCTION_SAY_HELLO 215 #define ARCMSR_MESSAGE_SAY_GOODBYE \ 216 ARECA_SATA_RAID | FUNCTION_SAY_GOODBYE 217 #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE \ 218 ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE 219 220 /* ARECA IOCTL ReturnCode */ 221 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 222 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 223 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 224 225 /* 226 * SPEC. for Areca HBB adapter 227 */ 228 /* ARECA HBB COMMAND for its FIRMWARE */ 229 /* window of "instruction flags" from driver to iop */ 230 #define ARCMSR_DRV2IOP_DOORBELL 0x00020400 231 #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404 232 /* window of "instruction flags" from iop to driver */ 233 #define ARCMSR_IOP2DRV_DOORBELL 0x00020408 234 #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C 235 236 237 /* ARECA FLAG LANGUAGE */ 238 #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 /* ioctl xfer */ 239 #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 /* ioctl xfer */ 240 #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004 241 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 242 243 #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F 244 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0 245 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7 246 247 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 248 #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 249 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 250 #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 251 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 252 #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 253 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 254 #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 255 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 256 #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 257 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 258 #define ARCMSR_MESSAGE_START_BGRB 0x00060008 259 #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008 260 #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008 261 #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008 262 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */ 263 #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 264 265 #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 /* ioctl xfer */ 266 #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 /* ioctl xfer */ 267 #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004 268 #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008 269 #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 270 271 #define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12 272 #define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20 273 /* Host Interrupt Mask */ 274 #define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 275 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 276 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 277 #define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D 278 279 /* Host Interrupt Status */ 280 #define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001 281 /* 282 * Set when the Utility_A Interrupt bit is set in the Outbound 283 * Doorbell Register. It clears by writing a 1 to the 284 * Utility_A bit in the Outbound Doorbell Clear Register or 285 * through automatic clearing (if enabled). 286 */ 287 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004 288 /* 289 * Set if Outbound Doorbell register bits 30:1 have a non-zero 290 * value. This bit clears only when Outbound Doorbell bits 291 * 30:1 are ALL clear. Only a write to the Outbound Doorbell 292 * Clear register clears bits in the Outbound Doorbell 293 * register. 294 */ 295 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008 296 /* 297 * Set whenever the Outbound Post List Producer/Consumer 298 * Register (FIFO) is not empty. It clears when the Outbound 299 * Post List FIFO is empty. 300 */ 301 #define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010 302 /* 303 * This bit indicates a SAS interrupt from a source external to 304 * the PCIe core. This bit is not maskable. 305 */ 306 /* DoorBell */ 307 #define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002 308 #define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004 309 #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008 310 #define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010 311 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002 312 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002 313 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004 314 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004 315 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 316 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008 317 #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000 318 319 /* data tunnel buffer between user space program and its firmware */ 320 /* iop msgcode_rwbuffer for message command */ 321 #define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00 322 /* user space data to iop 128bytes */ 323 #define ARCMSR_IOCTL_WBUFFER 0x0000fe00 324 /* iop data to user space 128bytes */ 325 #define ARCMSR_IOCTL_RBUFFER 0x0000ff00 326 #define ARCMSR_HBB_BASE0_OFFSET 0x00000010 327 #define ARCMSR_HBB_BASE1_OFFSET 0x00000018 328 #define ARCMSR_HBB_BASE0_LEN 0x00021000 329 #define ARCMSR_HBB_BASE1_LEN 0x00010000 330 331 /* 332 * structure for holding DMA address data 333 */ 334 #define IS_SG64_ADDR 0x01000000 /* bit24 */ 335 336 /* 32bit Scatter-Gather list */ 337 struct SG32ENTRY { 338 /* bit 24 = 0, high 8 bit = flag, low 24 bit = length */ 339 uint32_t length; 340 uint32_t address; 341 }; 342 343 /* 64bit Scatter-Gather list */ 344 struct SG64ENTRY { 345 /* bit 24 = 1, high 8 bit = flag, low 24 bit = length */ 346 uint32_t length; 347 uint32_t address; 348 uint32_t addresshigh; 349 }; 350 351 352 struct QBUFFER { 353 uint32_t data_len; 354 uint8_t data[124]; 355 }; 356 357 struct list_head { 358 struct list_head *next, *prev; 359 }; 360 361 /* 362 * FIRMWARE INFO 363 */ 364 #define ARCMSR_FW_MODEL_OFFSET 0x0f 365 #define ARCMSR_FW_VERS_OFFSET 0x11 366 #define ARCMSR_FW_MAP_OFFSET 0x15 367 368 struct FIRMWARE_INFO { 369 uint32_t signature; 370 uint32_t request_len; 371 uint32_t numbers_queue; 372 uint32_t sdram_size; 373 uint32_t ide_channels; 374 char vendor[40]; 375 char model[8]; 376 char firmware_ver[16]; 377 char device_map[16]; 378 }; 379 380 /* 381 * ARECA FIRMWARE SPEC 382 * 383 * Usage of IOP331 adapter 384 * 385 * (All In/Out is in IOP331's view) 386 * 1. Message 0 --> InitThread message and retrun code 387 * 2. Doorbell is used for RS-232 emulation 388 * InDoorBell : 389 * bit0 -- data in ready (DRIVER DATA WRITE OK) 390 * bit1 -- data out has been read 391 * (DRIVER DATA READ OK) 392 * outDoorBell: 393 * bit0 -- data out ready (IOP331 DATA WRITE OK) 394 * bit1 -- data in has been read 395 * (IOP331 DATA READ OK) 396 * 3. Index Memory Usage 397 * offset 0xf00 : for RS232 out (request buffer) 398 * offset 0xe00 : for RS232 in (scratch buffer) 399 * offset 0xa00 : for inbound message code msgcode_rwbuffer 400 * (driver send to IOP331) 401 * offset 0xa00 : for outbound message code msgcode_rwbuffer 402 * (IOP331 send to driver) 403 * 4. RS-232 emulation 404 * Currently 128 byte buffer is used: 405 * 1st uint32_t : Data length (1--124) 406 * Byte 4--127 : Max 124 bytes of data 407 * 5. PostQ 408 * All SCSI Command must be sent through postQ: 409 * (inbound queue port) Request frame must be 32 bytes aligned 410 * # bits 31:27 => flag for post ccb 411 * # bits 26:00 => real address (bit 31:27) of post arcmsr_cdb 412 * bit31 : 0 : 256 bytes frame 413 * 1 : 512 bytes frame 414 * bit30 : 0 : normal request 415 * 1 : BIOS request 416 * bit29 : reserved 417 * bit28 : reserved 418 * bit27 : reserved 419 * ----------------------------------------------------------------------- 420 * (outbount queue port) Request reply 421 * # bits 31:27 => flag for reply 422 * # bits 26:00 => real address (bits 31:27) of reply arcmsr_cdb 423 * # bit31 : must be 0 (for this type of reply) 424 * # bit30 : reserved for BIOS handshake 425 * # bit29 : reserved 426 * # bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData 427 * 1 : Error, see in AdapStatus/DevStatus/SenseData 428 * # bit27 : reserved 429 * 6. BIOS request 430 * All BIOS request is the same with request from PostQ 431 * Except : 432 * Request frame is sent from configuration space 433 * offset: 0x78 : Request Frame (bit30 == 1) 434 * offset: 0x18 : writeonly to generate IRQ to IOP331 435 * Completion of request: 436 * (bit30 == 0, bit28==err flag) 437 * 7. Definition of SGL entry (structure) 438 * 8. Message1 Out - Diag Status Code (????) 439 * 9. Message0 message code : 440 * 0x00 : NOP 441 * 0x01 : Get Config ->offset 0xa00 442 * : for outbound message code msgcode_rwbuffer 443 * (IOP331 send to driver) 444 * Signature 0x87974060(4) 445 * Request len 0x00000200(4) 446 * numbers of queue 0x00000100(4) 447 * SDRAM Size 0x00000100(4)-->256 MB 448 * IDE Channels 0x00000008(4) 449 * vendor 40 bytes char 450 * model 8 bytes char 451 * FirmVer 16 bytes char 452 * Device Map 16 bytes char 453 * 454 * FirmwareVersion DWORD 455 * <== Added for checking of new firmware capability 456 * 0x02 : Set Config ->offset 0xa00 457 * :for inbound message code msgcode_rwbuffer 458 * (driver send to IOP331) 459 * Signature 0x87974063(4) 460 * UPPER32 of Request Frame (4)-->Driver Only 461 * 0x03 : Reset (Abort all queued Command) 462 * 0x04 : Stop Background Activity 463 * 0x05 : Flush Cache 464 * 0x06 : Start Background Activity 465 * (re-start if background is halted) 466 * 0x07 : Check If Host Command Pending 467 * (Novell May Need This Function) 468 * 0x08 : Set controller time ->offset 0xa00 (driver to IOP331) 469 * : for inbound message code msgcode_rwbuffer 470 * byte 0 : 0xaa <-- signature 471 * byte 1 : 0x55 <-- signature 472 * byte 2 : year (04) 473 * byte 3 : month (1..12) 474 * byte 4 : date (1..31) 475 * byte 5 : hour (0..23) 476 * byte 6 : minute (0..59) 477 * byte 7 : second (0..59) 478 * 479 */ 480 481 482 /* signature of set and get firmware config */ 483 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 484 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 485 486 487 /* message code of inbound message register */ 488 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000 489 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 490 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 491 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 492 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 493 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 494 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 495 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 496 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 497 /* doorbell interrupt generator */ 498 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 499 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 500 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 501 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 502 /* ccb areca ccb flag */ 503 #define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000 504 #define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000 505 #define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000 506 #define ARCMSR_CCBREPLY_FLAG_ERROR 0x10000000 507 #define ARCMSR_CCBREPLY_FLAG_ERROR_MODE0 0x10000000 508 #define ARCMSR_CCBREPLY_FLAG_ERROR_MODE1 0x00000001 509 /* outbound firmware ok */ 510 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 511 512 /* dma burst sizes */ 513 #ifndef BURSTSIZE 514 #define BURSTSIZE 515 #define BURST1 0x01 516 #define BURST2 0x02 517 #define BURST4 0x04 518 #define BURST8 0x08 519 #define BURST16 0x10 520 #define BURST32 0x20 521 #define BURST64 0x40 522 #define BURSTSIZE_MASK 0x7f 523 #define DEFAULT_BURSTSIZE BURST16|BURST8|BURST4|BURST2|BURST1 524 #endif /* BURSTSIZE */ 525 526 #define PtrToNum(p) (uintptr_t)((void *)p) 527 #define NumToPtr(ul) (void *)((uintptr_t)ul) 528 529 /* 530 * 531 */ 532 struct ARCMSR_CDB { 533 uint8_t Bus; /* should be 0 */ 534 uint8_t TargetID; /* should be 0..15 */ 535 uint8_t LUN; /* should be 0..7 */ 536 uint8_t Function; /* should be 1 */ 537 538 uint8_t CdbLength; /* set in arcmsr_tran_init_pkt */ 539 uint8_t sgcount; 540 uint8_t Flags; 541 542 /* bit 0: 0(256) / 1(512) bytes */ 543 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 544 /* bit 1: 0(from driver) / 1(from BIOS) */ 545 #define ARCMSR_CDB_FLAG_BIOS 0x02 546 /* bit 2: 0(Data in) / 1(Data out) */ 547 #define ARCMSR_CDB_FLAG_WRITE 0x04 548 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */ 549 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 550 #define ARCMSR_CDB_FLAG_HEADQ 0x08 551 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 552 553 uint8_t Reserved1; 554 555 uint32_t Context; /* Address of this request */ 556 uint32_t DataLength; /* currently unused */ 557 558 uint8_t Cdb[16]; /* SCSI CDB */ 559 /* 560 * Device Status : the same from SCSI bus if error occur 561 * SCSI bus status codes. 562 */ 563 uint8_t DeviceStatus; 564 565 #define SCSISTAT_GOOD 0x00 566 #define SCSISTAT_CHECK_CONDITION 0x02 567 #define SCSISTAT_CONDITION_MET 0x04 568 #define SCSISTAT_BUSY 0x08 569 #define SCSISTAT_INTERMEDIATE 0x10 570 #define SCSISTAT_INTERMEDIATE_COND_MET 0x14 571 #define SCSISTAT_RESERVATION_CONFLICT 0x18 572 #define SCSISTAT_COMMAND_TERMINATED 0x22 573 #define SCSISTAT_QUEUE_FULL 0x28 574 575 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 576 #define ARCMSR_DEV_ABORTED 0xF1 577 #define ARCMSR_DEV_INIT_FAIL 0xF2 578 579 uint8_t SenseData[15]; 580 581 /* Scatter gather address */ 582 union { 583 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; 584 struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; 585 } sgu; 586 }; 587 588 589 struct HBA_msgUnit { 590 uint32_t resrved0[4]; 591 uint32_t inbound_msgaddr0; 592 uint32_t inbound_msgaddr1; 593 uint32_t outbound_msgaddr0; 594 uint32_t outbound_msgaddr1; 595 uint32_t inbound_doorbell; 596 uint32_t inbound_intstatus; 597 uint32_t inbound_intmask; 598 uint32_t outbound_doorbell; 599 uint32_t outbound_intstatus; 600 uint32_t outbound_intmask; 601 uint32_t reserved1[2]; 602 uint32_t inbound_queueport; 603 uint32_t outbound_queueport; 604 uint32_t reserved2[2]; 605 /* ......local_buffer */ 606 uint32_t reserved3[492]; 607 uint32_t reserved4[128]; 608 uint32_t msgcode_rwbuffer[256]; 609 uint32_t message_wbuffer[32]; 610 uint32_t reserved5[32]; 611 uint32_t message_rbuffer[32]; 612 uint32_t reserved6[32]; 613 }; 614 615 616 struct HBB_DOORBELL { 617 uint8_t doorbell_reserved[132096]; 618 /* 619 * offset 0x00020400:00,01,02,03: window of "instruction flags" 620 * from driver to iop 621 */ 622 uint32_t drv2iop_doorbell; 623 /* 04,05,06,07: doorbell mask */ 624 uint32_t drv2iop_doorbell_mask; 625 /* 08,09,10,11: window of "instruction flags" from iop to driver */ 626 uint32_t iop2drv_doorbell; 627 /* 12,13,14,15: doorbell mask */ 628 uint32_t iop2drv_doorbell_mask; 629 }; 630 631 632 struct HBB_RWBUFFER { 633 uint8_t message_reserved0[64000]; 634 /* offset 0x0000fa00: 0..1023: message code read write 1024bytes */ 635 uint32_t msgcode_rwbuffer[256]; 636 /* offset 0x0000fe00:1024...1151: user space data to iop 128bytes */ 637 uint32_t message_wbuffer[32]; 638 /* 1152...1279: message reserved */ 639 uint32_t message_reserved1[32]; 640 /* offset 0x0000ff00:1280...1407: iop data to user space 128bytes */ 641 uint32_t message_rbuffer[32]; 642 }; 643 644 struct HBB_msgUnit { 645 uint32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; 646 uint32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; 647 648 int32_t postq_index; /* post queue index */ 649 int32_t doneq_index; /* done queue index */ 650 struct HBB_DOORBELL *hbb_doorbell; 651 struct HBB_RWBUFFER *hbb_rwbuffer; 652 }; 653 654 struct HBC_msgUnit { 655 uint32_t message_unit_status; /* 0000 0003 */ 656 uint32_t slave_error_attribute; /* 0004 0007 */ 657 uint32_t slave_error_address; /* 0008 000B */ 658 uint32_t posted_outbound_doorbell; /* 000C 000F */ 659 uint32_t master_error_attribute; /* 0010 0013 */ 660 uint32_t master_error_address_low; /* 0014 0017 */ 661 uint32_t master_error_address_high; /* 0018 001B */ 662 uint32_t hcb_size; /* 001C 001F */ 663 uint32_t inbound_doorbell; /* 0020 0023 */ 664 uint32_t diagnostic_rw_data; /* 0024 0027 */ 665 uint32_t diagnostic_rw_address_low; /* 0028 002B */ 666 uint32_t diagnostic_rw_address_high; /* 002C 002F */ 667 uint32_t host_int_status; /* 0030 0033 */ 668 uint32_t host_int_mask; /* 0034 0037 */ 669 uint32_t dcr_data; /* 0038 003B */ 670 uint32_t dcr_address; /* 003C 003F */ 671 uint32_t inbound_queueport; /* 0040 0043 */ 672 uint32_t outbound_queueport; /* 0044 0047 */ 673 uint32_t hcb_pci_address_low; /* 0048 004B */ 674 uint32_t hcb_pci_address_high; /* 004C 004F */ 675 uint32_t iop_int_status; /* 0050 0053 */ 676 uint32_t iop_int_mask; /* 0054 0057 */ 677 uint32_t iop_inbound_queue_port; /* 0058 005B */ 678 uint32_t iop_outbound_queue_port; /* 005C 005F */ 679 uint32_t inbound_free_list_index; /* 0060 0063 */ 680 uint32_t inbound_post_list_index; /* 0064 0067 */ 681 uint32_t outbound_free_list_index; /* 0068 006B */ 682 uint32_t outbound_post_list_index; /* 006C 006F */ 683 uint32_t inbound_doorbell_clear; /* 0070 0073 */ 684 uint32_t i2o_message_unit_control; /* 0074 0077 */ 685 uint32_t last_used_message_source_address_low; /* 0078 007B */ 686 uint32_t last_used_message_source_address_high; /* 007C 007F */ 687 uint32_t pull_mode_data_byte_count[4]; /* 0080 008F */ 688 uint32_t message_dest_address_index; /* 0090 0093 */ 689 uint32_t done_queue_not_empty_int_counter_timer; /* 0094 0097 */ 690 uint32_t utility_A_int_counter_timer; /* 0098 009B */ 691 uint32_t outbound_doorbell; /* 009C 009F */ 692 uint32_t outbound_doorbell_clear; /* 00A0 00A3 */ 693 uint32_t message_source_address_index; /* 00A4 00A7 */ 694 uint32_t message_done_queue_index; /* 00A8 00AB */ 695 uint32_t reserved0; /* 00AC 00AF */ 696 uint32_t inbound_msgaddr0; /* 00B0 00B3 */ 697 uint32_t inbound_msgaddr1; /* 00B4 00B7 */ 698 uint32_t outbound_msgaddr0; /* 00B8 00BB */ 699 uint32_t outbound_msgaddr1; /* 00BC 00BF */ 700 uint32_t inbound_queueport_low; /* 00C0 00C3 */ 701 uint32_t inbound_queueport_high; /* 00C4 00C7 */ 702 uint32_t outbound_queueport_low; /* 00C8 00CB */ 703 uint32_t outbound_queueport_high; /* 00CC 00CF */ 704 uint32_t iop_inbound_queue_port_low; /* 00D0 00D3 */ 705 uint32_t iop_inbound_queue_port_high; /* 00D4 00D7 */ 706 uint32_t iop_outbound_queue_port_low; /* 00D8 00DB */ 707 uint32_t iop_outbound_queue_port_high; /* 00DC 00DF */ 708 uint32_t message_dest_queue_port_low; /* 00E0 00E3 */ 709 uint32_t message_dest_queue_port_high; /* 00E4 00E7 */ 710 uint32_t last_used_message_dest_address_low; /* 00E8 00EB */ 711 uint32_t last_used_message_dest_address_high; /* 00EC 00EF */ 712 uint32_t message_done_queue_base_address_low; /* 00F0 00F3 */ 713 uint32_t message_done_queue_base_address_high; /* 00F4 00F7 */ 714 uint32_t host_diagnostic; /* 00F8 00FB */ 715 uint32_t write_sequence; /* 00FC 00FF */ 716 uint32_t reserved1[34]; /* 0100 0187 */ 717 uint32_t reserved2[1950]; /* 0188 1FFF */ 718 uint32_t message_wbuffer[32]; /* 2000 207F */ 719 uint32_t reserved3[32]; /* 2080 20FF */ 720 uint32_t message_rbuffer[32]; /* 2100 217F */ 721 uint32_t reserved4[32]; /* 2180 21FF */ 722 uint32_t msgcode_rwbuffer[256]; /* 2200 23FF */ 723 }; 724 725 struct msgUnit { 726 union { 727 struct HBA_msgUnit hbamu; 728 struct HBB_msgUnit hbbmu; 729 struct HBC_msgUnit hbcmu; 730 } muu; 731 }; 732 733 734 /* 735 * Adapter Control Block 736 */ 737 struct ACB { 738 uint32_t adapter_type; /* A/B/C/D */ 739 740 #define ACB_ADAPTER_TYPE_A 0x00000001 /* hba (Intel) IOP */ 741 #define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb (Marvell) IOP */ 742 #define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc (Lsi) IOP */ 743 #define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd A IOP */ 744 745 scsi_hba_tran_t *scsi_hba_transport; 746 dev_info_t *dev_info; 747 ddi_acc_handle_t reg_mu_acc_handle0; 748 ddi_acc_handle_t reg_mu_acc_handle1; 749 ddi_acc_handle_t ccbs_acc_handle; 750 ddi_dma_handle_t ccbs_pool_handle; 751 ddi_dma_cookie_t ccb_cookie; 752 ddi_device_acc_attr_t dev_acc_attr; 753 kmutex_t isr_mutex; 754 kmutex_t acb_mutex; 755 kmutex_t postq_mutex; 756 kmutex_t workingQ_mutex; 757 kmutex_t ioctl_mutex; 758 kmutex_t ccb_complete_list_mutex; 759 timeout_id_t timeout_id; 760 timeout_id_t timeout_sc_id; 761 ddi_taskq_t *taskq; 762 ddi_intr_handle_t *phandle; 763 uint_t intr_size; 764 int intr_count; 765 uint_t intr_pri; 766 int intr_cap; 767 768 /* Offset for arc cdb physical to virtual calculations */ 769 uint64_t vir2phy_offset; 770 uint32_t outbound_int_enable; 771 uint32_t cdb_phyaddr_hi32; 772 /* message unit ATU inbound base address0 virtual */ 773 struct msgUnit *pmu; 774 struct list_head ccb_complete_list; 775 776 uint8_t adapter_index; 777 uint16_t acb_flags; 778 779 #define ACB_F_SCSISTOPADAPTER 0x0001 780 /* stop RAID background rebuild */ 781 #define ACB_F_MSG_STOP_BGRB 0x0002 782 /* stop RAID background rebuild */ 783 #define ACB_F_MSG_START_BGRB 0x0004 784 /* iop ioctl data rqbuffer overflow */ 785 #define ACB_F_IOPDATA_OVERFLOW 0x0008 786 /* ioctl clear wqbuffer */ 787 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 788 /* ioctl clear rqbuffer */ 789 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 790 /* ioctl iop wqbuffer data readed */ 791 #define ACB_F_MESSAGE_WQBUFFER_READ 0x0040 792 #define ACB_F_BUS_RESET 0x0080 793 /* iop init */ 794 #define ACB_F_IOP_INITED 0x0100 795 /* need hardware reset bus */ 796 #define ACB_F_BUS_HANG_ON 0x0800 797 798 /* serial ccb pointer array */ 799 struct CCB *pccb_pool[ARCMSR_MAX_FREECCB_NUM]; 800 /* working ccb pointer array */ 801 struct CCB *ccbworkingQ[ARCMSR_MAX_FREECCB_NUM]; 802 /* done ccb array index */ 803 int32_t ccb_put_index; 804 /* start ccb array index */ 805 int32_t ccb_get_index; 806 volatile uint32_t ccboutstandingcount; 807 808 /* data collection buffer for read from 80331 */ 809 uint8_t rqbuffer[ARCMSR_MAX_QBUFFER]; 810 /* first of read buffer */ 811 int32_t rqbuf_firstidx; 812 /* last of read buffer */ 813 int32_t rqbuf_lastidx; 814 815 /* data collection buffer for write to 80331 */ 816 uint8_t wqbuffer[ARCMSR_MAX_QBUFFER]; 817 /* first of write buffer */ 818 int32_t wqbuf_firstidx; 819 /* last of write buffer */ 820 int32_t wqbuf_lastidx; 821 /* id0 ..... id15,lun0...lun7 */ 822 uint8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; 823 #define ARECA_RAID_GONE 0x55 824 #define ARECA_RAID_GOOD 0xaa 825 826 uint32_t timeout_count; 827 uint32_t num_resets; 828 uint32_t num_aborts; 829 uint32_t firm_request_len; 830 uint32_t firm_numbers_queue; 831 uint32_t firm_sdram_size; 832 uint32_t firm_ide_channels; 833 uint32_t firm_cfg_version; 834 char firm_model[12]; 835 char firm_version[20]; 836 char device_map[20]; /* 21,84-99 */ 837 ddi_acc_handle_t pci_acc_handle; 838 }; 839 840 841 /* 842 * Command Control Block (SrbExtension) 843 * 844 * CCB must be not cross page boundary,and the order from offset 0 845 * structure describing an ATA disk request this CCB length must be 846 * 32 bytes boundary 847 * 848 */ 849 struct CCB 850 { 851 struct ARCMSR_CDB arcmsr_cdb; 852 struct list_head complete_queue_pointer; 853 uint32_t cdb_phyaddr_pattern; 854 uint16_t ccb_flags; 855 #define CCB_FLAG_READ 0x0000 856 #define CCB_FLAG_WRITE 0x0001 857 #define CCB_FLAG_ERROR 0x0002 858 #define CCB_FLAG_FLUSHCACHE 0x0004 859 #define CCB_FLAG_MASTER_ABORTED 0x0008 860 #define CCB_FLAG_DMAVALID 0x0010 861 #define CCB_FLAG_DMACONSISTENT 0x0020 862 #define CCB_FLAG_DMAWRITE 0x0040 863 #define CCB_FLAG_PKTBIND 0x0080 864 uint16_t ccb_state; 865 #define ARCMSR_CCB_FREE 0x0000 866 #define ARCMSR_CCB_UNBUILD 0x0100 867 #define ARCMSR_CCB_START 0x0001 868 #define ARCMSR_CCB_RETRY 0x0002 869 #define ARCMSR_CCB_TIMEOUT 0x0004 870 #define ARCMSR_CCB_ABORTED 0x0008 871 #define ARCMSR_CCB_RESET 0x0010 872 #define ARCMSR_CCB_DONE 0x0020 873 #define ARCMSR_CCB_WAIT4_FREE 0x0040 874 #define ARCMSR_CCB_BACK 0x0080 875 #define ARCMSR_CCB_ILLEGAL 0xFFFF 876 #define ARCMSR_ABNORMAL_MASK \ 877 (ARCMSR_CCB_TIMEOUT | ARCMSR_CCB_ABORTED | ARCMSR_CCB_RESET) 878 #define ARCMSR_CCB_CAN_BE_FREE (ARCMSR_CCB_WAIT4_FREE | ARCMSR_CCB_BACK) 879 struct scsi_pkt *pkt; 880 struct ACB *acb; 881 ddi_dma_cookie_t pkt_dmacookies[ARCMSR_MAX_SG_ENTRIES]; 882 ddi_dma_handle_t pkt_dma_handle; 883 uint_t pkt_cookie; 884 uint_t pkt_ncookies; 885 uint_t pkt_nwin; 886 uint_t pkt_curwin; 887 off_t pkt_dma_offset; 888 size_t pkt_dma_len; 889 size_t total_dmac_size; 890 time_t ccb_time; 891 struct buf *bp; 892 ddi_dma_cookie_t resid_dmacookie; 893 uint32_t arc_cdb_size; 894 }; 895 896 897 /* SenseData[15] */ 898 struct SENSE_DATA { 899 DECL_BITFIELD3( 900 ErrorCode :4, /* Vendor Unique error code */ 901 ErrorClass :3, /* Error Class- fixed at 0x7 */ 902 Valid :1); /* sense data is valid */ 903 904 uint8_t SegmentNumber; /* segment number: for COPY cmd */ 905 906 DECL_BITFIELD5( 907 SenseKey :4, /* Sense key (see below) */ 908 Reserved :1, /* reserved */ 909 IncorrectLength :1, /* Incorrect Length Indicator */ 910 EndOfMedia :1, /* End of Media */ 911 FileMark :1); /* File Mark Detected */ 912 913 uint8_t Information[4]; 914 uint8_t AdditionalSenseLength; 915 uint8_t CommandSpecificInformation[4]; 916 uint8_t AdditionalSenseCode; 917 uint8_t AdditionalSenseCodeQualifier; 918 uint8_t FieldReplaceableUnitCode; 919 }; 920 921 #define VIDLEN 8 922 #define PIDLEN 16 923 #define REVLEN 4 924 struct SCSIInqData { 925 uint8_t DevType; /* Periph Qualifier & Periph Dev Type */ 926 uint8_t RMB_TypeMod; /* rem media bit & Dev Type Modifier */ 927 uint8_t Vers; /* ISO, ECMA, & ANSI versions */ 928 uint8_t RDF; /* AEN, TRMIOP, & response data format */ 929 uint8_t AddLen; /* length of additional data */ 930 uint8_t Res1; /* reserved */ 931 uint8_t Res2; /* reserved */ 932 uint8_t Flags; /* RelADr, Wbus32, Wbus16, Sync etc */ 933 uint8_t VendorID[VIDLEN]; /* Vendor Identification */ 934 uint8_t ProductID[PIDLEN]; /* Product Identification */ 935 uint8_t ProductRev[REVLEN]; /* Product Revision */ 936 }; 937 938 939 940 /* 941 * These definitions are the register offsets as defined in the Intel 942 * IOP manuals. See (correct as of 18 January 2008) 943 * http://developer.intel.com/design/iio/index.htm?iid=ncdcnav2+stor_ioproc 944 * for more details 945 */ 946 947 948 #define ARCMSR_MU_INBOUND_MESSAGE_REG0 0x10 949 #define ARCMSR_MU_INBOUND_MESSAGE_REG1 0x14 950 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG0 0x18 951 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG1 0x1C 952 #define ARCMSR_MU_INBOUND_DOORBELL_REG 0x20 953 #define ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG 0x24 954 #define ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG 0x28 955 #define ARCMSR_MU_OUTBOUND_DOORBELL_REG 0x2C 956 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 957 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 958 #define ARCMSR_MU_INBOUND_QUEUE_PORT_REG 0x40 959 #define ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG 0x44 960 961 962 963 #define ARCMSR_MU_INBOUND_MESSAGE0_INT 0x01 964 #define ARCMSR_MU_INBOUND_MESSAGE1_INT 0x02 965 #define ARCMSR_MU_INBOUND_DOORBELL_INT 0x04 966 #define ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT 0x08 967 #define ARCMSR_MU_INBOUND_POSTQUEUE_INT 0x10 968 #define ARCMSR_MU_INBOUND_QUEUEFULL_INT 0x20 969 #define ARCMSR_MU_INBOUND_INDEX_INT 0x40 970 971 #define ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE 0x01 972 #define ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE 0x02 973 #define ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE 0x04 974 #define ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE 0x08 975 #define ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE 0x10 976 #define ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE 0x20 977 #define ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE 0x40 978 979 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 980 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 981 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 982 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 983 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 984 985 986 #define ARCMSR_MU_OUTBOUND_HANDLE_INT ( \ 987 ARCMSR_MU_OUTBOUND_MESSAGE0_INT| \ 988 ARCMSR_MU_OUTBOUND_MESSAGE1_INT| \ 989 ARCMSR_MU_OUTBOUND_DOORBELL_INT| \ 990 ARCMSR_MU_OUTBOUND_POSTQUEUE_INT| \ 991 ARCMSR_MU_OUTBOUND_PCI_INT) 992 993 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 994 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 995 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 996 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 997 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 998 999 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F 1000 1001 #define ARCMSR_MU_CONFIGURATION_REG 0xFFFFE350 1002 #define ARCMSR_MU_QUEUE_BASE_ADDRESS_REG 0xFFFFE354 1003 #define ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG 0xFFFFE360 1004 #define ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG 0xFFFFE364 1005 #define ARCMSR_MU_INBOUND_POST_HEAD_PTR_REG 0xFFFFE368 1006 #define ARCMSR_MU_INBOUND_POST_TAIL_PTR_REG 0xFFFFE36C 1007 #define ARCMSR_MU_LOCAL_MEMORY_INDEX_REG 0xFFFFE380 1008 1009 #define ARCMSR_MU_CIRCULAR_QUEUE_ENABLE 0x0001 1010 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K 0x0002 1011 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K 0x0004 1012 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K 0x0008 1013 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K 0x0010 1014 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K 0x0020 1015 1016 1017 1018 #ifdef __cplusplus 1019 } 1020 #endif 1021 1022 #endif /* _SYS_SCSI_ADAPTERS_ARCMSR_H */ 1023