1 /* 2 * O.S : Solaris 3 * FILE NAME : arcmsr.c 4 * BY : Erich Chen, C.L. Huang 5 * Description: SCSI RAID Device Driver for 6 * ARECA RAID Host adapter 7 * 8 * Copyright (C) 2002,2010 Areca Technology Corporation All rights reserved. 9 * Copyright (C) 2002,2010 Erich Chen 10 * Web site: www.areca.com.tw 11 * E-mail: erich@areca.com.tw; ching2048@areca.com.tw 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. The party using or redistributing the source code and binary forms 22 * agrees to the disclaimer below and the terms and conditions set forth 23 * herein. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 38 * Use is subject to license terms. 39 * 40 */ 41 /* 42 * This file and its contents are supplied under the terms of the 43 * Common Development and Distribution License ("CDDL"), version 1.0. 44 * You may only use this file in accordance with the terms of version 45 * 1.0 of the CDDL. 46 * 47 * A full copy of the text of the CDDL should have accompanied this 48 * source. A copy of the CDDL is also available via the Internet at 49 * http://www.illumos.org/license/CDDL. 50 */ 51 /* 52 * Copyright 2011 Nexenta Systems, Inc. All rights reserved. 53 * Copyright 2023 Oxide Computer Company 54 */ 55 #include <sys/types.h> 56 #include <sys/ddidmareq.h> 57 #include <sys/scsi/scsi.h> 58 #include <sys/ddi.h> 59 #include <sys/sunddi.h> 60 #include <sys/file.h> 61 #include <sys/disp.h> 62 #include <sys/signal.h> 63 #include <sys/debug.h> 64 #include <sys/pci.h> 65 #include <sys/policy.h> 66 #include <sys/atomic.h> 67 #include "arcmsr.h" 68 69 static int arcmsr_attach(dev_info_t *dev_info, ddi_attach_cmd_t cmd); 70 static int arcmsr_cb_ioctl(dev_t dev, int ioctl_cmd, intptr_t arg, 71 int mode, cred_t *credp, int *rvalp); 72 static int arcmsr_detach(dev_info_t *dev_info, ddi_detach_cmd_t cmd); 73 static int arcmsr_reset(dev_info_t *resetdev, ddi_reset_cmd_t cmd); 74 static int arcmsr_tran_start(struct scsi_address *ap, struct scsi_pkt *pkt); 75 static int arcmsr_tran_abort(struct scsi_address *ap, struct scsi_pkt *pkt); 76 static int arcmsr_tran_reset(struct scsi_address *ap, int level); 77 static int arcmsr_tran_getcap(struct scsi_address *ap, char *cap, int whom); 78 static int arcmsr_tran_setcap(struct scsi_address *ap, char *cap, int value, 79 int whom); 80 static int arcmsr_tran_tgt_init(dev_info_t *host_dev_info, 81 dev_info_t *target_dev_info, scsi_hba_tran_t *hosttran, 82 struct scsi_device *sd); 83 static void arcmsr_tran_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt); 84 static void arcmsr_tran_destroy_pkt(struct scsi_address *ap, 85 struct scsi_pkt *pkt); 86 static void arcmsr_tran_sync_pkt(struct scsi_address *ap, 87 struct scsi_pkt *pkt); 88 static struct scsi_pkt *arcmsr_tran_init_pkt(struct scsi_address *ap, 89 struct scsi_pkt *pkt, struct buf *bp, int cmdlen, int statuslen, 90 int tgtlen, int flags, int (*callback)(), caddr_t arg); 91 static int arcmsr_config_child(struct ACB *acb, struct scsi_device *sd, 92 dev_info_t **dipp); 93 94 static int arcmsr_config_lun(struct ACB *acb, uint16_t tgt, uint8_t lun, 95 dev_info_t **ldip); 96 static uint8_t arcmsr_abort_host_command(struct ACB *acb); 97 static uint8_t arcmsr_get_echo_from_iop(struct ACB *acb); 98 static uint_t arcmsr_intr_handler(caddr_t arg, caddr_t arg2); 99 static int arcmsr_initialize(struct ACB *acb); 100 static int arcmsr_dma_alloc(struct ACB *acb, 101 struct scsi_pkt *pkt, struct buf *bp, int flags, int (*callback)()); 102 static int arcmsr_dma_move(struct ACB *acb, 103 struct scsi_pkt *pkt, struct buf *bp); 104 static void arcmsr_handle_iop_bus_hold(struct ACB *acb); 105 static void arcmsr_hbc_message_isr(struct ACB *acb); 106 static void arcmsr_pcidev_disattach(struct ACB *acb); 107 static void arcmsr_ccb_complete(struct CCB *ccb, int flag); 108 static void arcmsr_iop_init(struct ACB *acb); 109 static void arcmsr_iop_parking(struct ACB *acb); 110 /*PRINTFLIKE3*/ 111 static void arcmsr_log(struct ACB *acb, int level, char *fmt, ...); 112 /*PRINTFLIKE2*/ 113 static void arcmsr_warn(struct ACB *acb, char *fmt, ...); 114 static void arcmsr_mutex_init(struct ACB *acb); 115 static void arcmsr_remove_intr(struct ACB *acb); 116 static void arcmsr_ccbs_timeout(void* arg); 117 static void arcmsr_devMap_monitor(void* arg); 118 static void arcmsr_pcidev_disattach(struct ACB *acb); 119 static void arcmsr_iop_message_read(struct ACB *acb); 120 static void arcmsr_free_ccb(struct CCB *ccb); 121 static void arcmsr_post_ioctldata2iop(struct ACB *acb); 122 static void arcmsr_report_sense_info(struct CCB *ccb); 123 static void arcmsr_init_list_head(struct list_head *list); 124 static void arcmsr_enable_allintr(struct ACB *acb, uint32_t intmask_org); 125 static void arcmsr_done4abort_postqueue(struct ACB *acb); 126 static void arcmsr_list_add_tail(kmutex_t *list_lock, 127 struct list_head *new_one, struct list_head *head); 128 static int arcmsr_name_node(dev_info_t *dip, char *name, int len); 129 static int arcmsr_seek_cmd2abort(struct ACB *acb, struct scsi_pkt *abortpkt); 130 static int arcmsr_iop_message_xfer(struct ACB *acb, struct scsi_pkt *pkt); 131 static int arcmsr_post_ccb(struct ACB *acb, struct CCB *ccb); 132 static int arcmsr_parse_devname(char *devnm, int *tgt, int *lun); 133 static int arcmsr_do_ddi_attach(dev_info_t *dev_info, int instance); 134 static uint8_t arcmsr_iop_reset(struct ACB *acb); 135 static uint32_t arcmsr_disable_allintr(struct ACB *acb); 136 static uint32_t arcmsr_iop_confirm(struct ACB *acb); 137 static struct CCB *arcmsr_get_freeccb(struct ACB *acb); 138 static void arcmsr_flush_hba_cache(struct ACB *acb); 139 static void arcmsr_flush_hbb_cache(struct ACB *acb); 140 static void arcmsr_flush_hbc_cache(struct ACB *acb); 141 static void arcmsr_stop_hba_bgrb(struct ACB *acb); 142 static void arcmsr_stop_hbb_bgrb(struct ACB *acb); 143 static void arcmsr_stop_hbc_bgrb(struct ACB *acb); 144 static void arcmsr_start_hba_bgrb(struct ACB *acb); 145 static void arcmsr_start_hbb_bgrb(struct ACB *acb); 146 static void arcmsr_start_hbc_bgrb(struct ACB *acb); 147 static void arcmsr_mutex_destroy(struct ACB *acb); 148 static void arcmsr_polling_hba_ccbdone(struct ACB *acb, struct CCB *poll_ccb); 149 static void arcmsr_polling_hbb_ccbdone(struct ACB *acb, struct CCB *poll_ccb); 150 static void arcmsr_polling_hbc_ccbdone(struct ACB *acb, struct CCB *poll_ccb); 151 static void arcmsr_build_ccb(struct CCB *ccb); 152 static int arcmsr_tran_bus_config(dev_info_t *parent, uint_t flags, 153 ddi_bus_config_op_t op, void *arg, dev_info_t **childp); 154 static int arcmsr_name_node(dev_info_t *dip, char *name, int len); 155 static dev_info_t *arcmsr_find_child(struct ACB *acb, uint16_t tgt, 156 uint8_t lun); 157 static struct QBUFFER *arcmsr_get_iop_rqbuffer(struct ACB *acb); 158 159 static int arcmsr_add_intr(struct ACB *, int); 160 161 static void *arcmsr_soft_state = NULL; 162 163 static ddi_dma_attr_t arcmsr_dma_attr = { 164 DMA_ATTR_V0, /* ddi_dma_attr version */ 165 0, /* low DMA address range */ 166 0xffffffffffffffffull, /* high DMA address range */ 167 0x00ffffff, /* DMA counter counter upper bound */ 168 1, /* DMA address alignment requirements */ 169 DEFAULT_BURSTSIZE | BURST32 | BURST64, /* burst sizes */ 170 1, /* minimum effective DMA size */ 171 ARCMSR_MAX_XFER_LEN, /* maximum DMA xfer size */ 172 /* 173 * The dma_attr_seg field supplies the limit of each Scatter/Gather 174 * list element's "address+length". The Intel IOP331 can not use 175 * segments over the 4G boundary due to segment boundary restrictions 176 */ 177 0xffffffff, 178 ARCMSR_MAX_SG_ENTRIES, /* scatter/gather list count */ 179 1, /* device granularity */ 180 DDI_DMA_FORCE_PHYSICAL /* Bus specific DMA flags */ 181 }; 182 183 184 static ddi_dma_attr_t arcmsr_ccb_attr = { 185 DMA_ATTR_V0, /* ddi_dma_attr version */ 186 0, /* low DMA address range */ 187 0xffffffff, /* high DMA address range */ 188 0x00ffffff, /* DMA counter counter upper bound */ 189 1, /* default byte alignment */ 190 DEFAULT_BURSTSIZE | BURST32 | BURST64, /* burst sizes */ 191 1, /* minimum effective DMA size */ 192 0xffffffff, /* maximum DMA xfer size */ 193 0x00ffffff, /* max segment size, segment boundary restrictions */ 194 1, /* scatter/gather list count */ 195 1, /* device granularity */ 196 DDI_DMA_FORCE_PHYSICAL /* Bus specific DMA flags */ 197 }; 198 199 200 static struct cb_ops arcmsr_cb_ops = { 201 scsi_hba_open, /* open(9E) */ 202 scsi_hba_close, /* close(9E) */ 203 nodev, /* strategy(9E), returns ENXIO */ 204 nodev, /* print(9E) */ 205 nodev, /* dump(9E) Cannot be used as a dump device */ 206 nodev, /* read(9E) */ 207 nodev, /* write(9E) */ 208 arcmsr_cb_ioctl, /* ioctl(9E) */ 209 nodev, /* devmap(9E) */ 210 nodev, /* mmap(9E) */ 211 nodev, /* segmap(9E) */ 212 NULL, /* chpoll(9E) returns ENXIO */ 213 nodev, /* prop_op(9E) */ 214 NULL, /* streamtab(9S) */ 215 D_MP, 216 CB_REV, 217 nodev, /* aread(9E) */ 218 nodev /* awrite(9E) */ 219 }; 220 221 static struct dev_ops arcmsr_ops = { 222 DEVO_REV, /* devo_rev */ 223 0, /* reference count */ 224 nodev, /* getinfo */ 225 nulldev, /* identify */ 226 nulldev, /* probe */ 227 arcmsr_attach, /* attach */ 228 arcmsr_detach, /* detach */ 229 arcmsr_reset, /* reset, shutdown, reboot notify */ 230 &arcmsr_cb_ops, /* driver operations */ 231 NULL, /* bus operations */ 232 NULL /* power */ 233 }; 234 235 static struct modldrv arcmsr_modldrv = { 236 &mod_driverops, /* Type of module. This is a driver. */ 237 "ARECA RAID Controller", /* module name, from arcmsr.h */ 238 &arcmsr_ops, /* driver ops */ 239 }; 240 241 static struct modlinkage arcmsr_modlinkage = { 242 MODREV_1, 243 &arcmsr_modldrv, 244 NULL 245 }; 246 247 248 int 249 _init(void) 250 { 251 int ret; 252 253 ret = ddi_soft_state_init(&arcmsr_soft_state, sizeof (struct ACB), 1); 254 if (ret != 0) { 255 return (ret); 256 } 257 if ((ret = scsi_hba_init(&arcmsr_modlinkage)) != 0) { 258 ddi_soft_state_fini(&arcmsr_soft_state); 259 return (ret); 260 } 261 262 if ((ret = mod_install(&arcmsr_modlinkage)) != 0) { 263 scsi_hba_fini(&arcmsr_modlinkage); 264 if (arcmsr_soft_state != NULL) { 265 ddi_soft_state_fini(&arcmsr_soft_state); 266 } 267 } 268 return (ret); 269 } 270 271 272 int 273 _fini(void) 274 { 275 int ret; 276 277 ret = mod_remove(&arcmsr_modlinkage); 278 if (ret == 0) { 279 /* if ret = 0 , said driver can remove */ 280 scsi_hba_fini(&arcmsr_modlinkage); 281 if (arcmsr_soft_state != NULL) { 282 ddi_soft_state_fini(&arcmsr_soft_state); 283 } 284 } 285 return (ret); 286 } 287 288 289 int 290 _info(struct modinfo *modinfop) 291 { 292 return (mod_info(&arcmsr_modlinkage, modinfop)); 293 } 294 295 296 /* 297 * Function: arcmsr_attach(9E) 298 * Description: Set up all device state and allocate data structures, 299 * mutexes, condition variables, etc. for device operation. 300 * Set mt_attr property for driver to indicate MT-safety. 301 * Add interrupts needed. 302 * Input: dev_info_t *dev_info, ddi_attach_cmd_t cmd 303 * Output: Return DDI_SUCCESS if device is ready, 304 * else return DDI_FAILURE 305 */ 306 static int 307 arcmsr_attach(dev_info_t *dev_info, ddi_attach_cmd_t cmd) 308 { 309 scsi_hba_tran_t *hba_trans; 310 struct ACB *acb; 311 312 switch (cmd) { 313 case DDI_ATTACH: 314 return (arcmsr_do_ddi_attach(dev_info, 315 ddi_get_instance(dev_info))); 316 case DDI_RESUME: 317 /* 318 * There is no hardware state to restart and no 319 * timeouts to restart since we didn't DDI_SUSPEND with 320 * active cmds or active timeouts We just need to 321 * unblock waiting threads and restart I/O the code 322 */ 323 hba_trans = ddi_get_driver_private(dev_info); 324 if (hba_trans == NULL) { 325 return (DDI_FAILURE); 326 } 327 acb = hba_trans->tran_hba_private; 328 mutex_enter(&acb->acb_mutex); 329 arcmsr_iop_init(acb); 330 331 /* restart ccbs "timeout" watchdog */ 332 acb->timeout_count = 0; 333 acb->timeout_id = timeout(arcmsr_ccbs_timeout, (caddr_t)acb, 334 (ARCMSR_TIMEOUT_WATCH * drv_usectohz(1000000))); 335 acb->timeout_sc_id = timeout(arcmsr_devMap_monitor, 336 (caddr_t)acb, 337 (ARCMSR_DEV_MAP_WATCH * drv_usectohz(1000000))); 338 mutex_exit(&acb->acb_mutex); 339 return (DDI_SUCCESS); 340 341 default: 342 return (DDI_FAILURE); 343 } 344 } 345 346 /* 347 * Function: arcmsr_detach(9E) 348 * Description: Remove all device allocation and system resources, disable 349 * device interrupt. 350 * Input: dev_info_t *dev_info 351 * ddi_detach_cmd_t cmd 352 * Output: Return DDI_SUCCESS if done, 353 * else returnDDI_FAILURE 354 */ 355 static int 356 arcmsr_detach(dev_info_t *dev_info, ddi_detach_cmd_t cmd) 357 { 358 int instance; 359 struct ACB *acb; 360 361 instance = ddi_get_instance(dev_info); 362 acb = ddi_get_soft_state(arcmsr_soft_state, instance); 363 if (acb == NULL) 364 return (DDI_FAILURE); 365 366 switch (cmd) { 367 case DDI_DETACH: 368 mutex_enter(&acb->acb_mutex); 369 if (acb->timeout_id != 0) { 370 mutex_exit(&acb->acb_mutex); 371 (void) untimeout(acb->timeout_id); 372 mutex_enter(&acb->acb_mutex); 373 acb->timeout_id = 0; 374 } 375 if (acb->timeout_sc_id != 0) { 376 mutex_exit(&acb->acb_mutex); 377 (void) untimeout(acb->timeout_sc_id); 378 mutex_enter(&acb->acb_mutex); 379 acb->timeout_sc_id = 0; 380 } 381 arcmsr_pcidev_disattach(acb); 382 /* Remove interrupt set up by ddi_add_intr */ 383 arcmsr_remove_intr(acb); 384 /* unbind mapping object to handle */ 385 (void) ddi_dma_unbind_handle(acb->ccbs_pool_handle); 386 /* Free ccb pool memory */ 387 ddi_dma_mem_free(&acb->ccbs_acc_handle); 388 /* Free DMA handle */ 389 ddi_dma_free_handle(&acb->ccbs_pool_handle); 390 ddi_regs_map_free(&acb->reg_mu_acc_handle0); 391 if (scsi_hba_detach(dev_info) != DDI_SUCCESS) 392 arcmsr_warn(acb, "Unable to detach instance cleanly " 393 "(should not happen)"); 394 /* free scsi_hba_transport from scsi_hba_tran_alloc */ 395 scsi_hba_tran_free(acb->scsi_hba_transport); 396 ddi_taskq_destroy(acb->taskq); 397 ddi_prop_remove_all(dev_info); 398 mutex_exit(&acb->acb_mutex); 399 arcmsr_mutex_destroy(acb); 400 pci_config_teardown(&acb->pci_acc_handle); 401 ddi_set_driver_private(dev_info, NULL); 402 ddi_soft_state_free(arcmsr_soft_state, instance); 403 return (DDI_SUCCESS); 404 case DDI_SUSPEND: 405 mutex_enter(&acb->acb_mutex); 406 if (acb->timeout_id != 0) { 407 acb->acb_flags |= ACB_F_SCSISTOPADAPTER; 408 mutex_exit(&acb->acb_mutex); 409 (void) untimeout(acb->timeout_id); 410 (void) untimeout(acb->timeout_sc_id); 411 mutex_enter(&acb->acb_mutex); 412 acb->timeout_id = 0; 413 } 414 415 if (acb->timeout_sc_id != 0) { 416 acb->acb_flags |= ACB_F_SCSISTOPADAPTER; 417 mutex_exit(&acb->acb_mutex); 418 (void) untimeout(acb->timeout_sc_id); 419 mutex_enter(&acb->acb_mutex); 420 acb->timeout_sc_id = 0; 421 } 422 423 /* disable all outbound interrupt */ 424 (void) arcmsr_disable_allintr(acb); 425 /* stop adapter background rebuild */ 426 switch (acb->adapter_type) { 427 case ACB_ADAPTER_TYPE_A: 428 arcmsr_stop_hba_bgrb(acb); 429 arcmsr_flush_hba_cache(acb); 430 break; 431 432 case ACB_ADAPTER_TYPE_B: 433 arcmsr_stop_hbb_bgrb(acb); 434 arcmsr_flush_hbb_cache(acb); 435 break; 436 437 case ACB_ADAPTER_TYPE_C: 438 arcmsr_stop_hbc_bgrb(acb); 439 arcmsr_flush_hbc_cache(acb); 440 break; 441 } 442 mutex_exit(&acb->acb_mutex); 443 return (DDI_SUCCESS); 444 default: 445 return (DDI_FAILURE); 446 } 447 } 448 449 static int 450 arcmsr_reset(dev_info_t *resetdev, ddi_reset_cmd_t cmd) 451 { 452 struct ACB *acb; 453 scsi_hba_tran_t *scsi_hba_transport; 454 _NOTE(ARGUNUSED(cmd)); 455 456 scsi_hba_transport = ddi_get_driver_private(resetdev); 457 if (scsi_hba_transport == NULL) 458 return (DDI_FAILURE); 459 460 acb = (struct ACB *)scsi_hba_transport->tran_hba_private; 461 if (!acb) 462 return (DDI_FAILURE); 463 464 arcmsr_pcidev_disattach(acb); 465 466 return (DDI_SUCCESS); 467 } 468 469 static int 470 arcmsr_cb_ioctl(dev_t dev, int ioctl_cmd, intptr_t arg, int mode, 471 cred_t *credp, int *rvalp) 472 { 473 struct ACB *acb; 474 struct CMD_MESSAGE_FIELD *pktioctlfld; 475 int retvalue = 0; 476 int instance = MINOR2INST(getminor(dev)); 477 478 if (instance < 0) 479 return (ENXIO); 480 481 if (secpolicy_sys_config(credp, B_FALSE) != 0) 482 return (EPERM); 483 484 acb = ddi_get_soft_state(arcmsr_soft_state, instance); 485 if (acb == NULL) 486 return (ENXIO); 487 488 pktioctlfld = kmem_zalloc(sizeof (struct CMD_MESSAGE_FIELD), KM_SLEEP); 489 490 mutex_enter(&acb->ioctl_mutex); 491 if (ddi_copyin((void *)arg, pktioctlfld, 492 sizeof (struct CMD_MESSAGE_FIELD), mode) != 0) { 493 retvalue = ENXIO; 494 goto ioctl_out; 495 } 496 497 if (memcmp(pktioctlfld->cmdmessage.Signature, "ARCMSR", 6) != 0) { 498 /* validity check */ 499 retvalue = ENXIO; 500 goto ioctl_out; 501 } 502 503 switch ((unsigned int)ioctl_cmd) { 504 case ARCMSR_MESSAGE_READ_RQBUFFER: 505 { 506 uint8_t *ver_addr; 507 uint8_t *pQbuffer, *ptmpQbuffer; 508 int32_t allxfer_len = 0; 509 510 ver_addr = kmem_zalloc(MSGDATABUFLEN, KM_SLEEP); 511 ptmpQbuffer = ver_addr; 512 while ((acb->rqbuf_firstidx != acb->rqbuf_lastidx) && 513 (allxfer_len < (MSGDATABUFLEN - 1))) { 514 /* copy READ QBUFFER to srb */ 515 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstidx]; 516 (void) memcpy(ptmpQbuffer, pQbuffer, 1); 517 acb->rqbuf_firstidx++; 518 /* if last index number set it to 0 */ 519 acb->rqbuf_firstidx %= ARCMSR_MAX_QBUFFER; 520 ptmpQbuffer++; 521 allxfer_len++; 522 } 523 524 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 525 struct QBUFFER *prbuffer; 526 uint8_t *pQbuffer; 527 uint8_t *iop_data; 528 int32_t iop_len; 529 530 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 531 prbuffer = arcmsr_get_iop_rqbuffer(acb); 532 iop_data = (uint8_t *)prbuffer->data; 533 iop_len = (int32_t)prbuffer->data_len; 534 /* 535 * this iop data does no chance to make me overflow 536 * again here, so just do it 537 */ 538 while (iop_len > 0) { 539 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastidx]; 540 (void) memcpy(pQbuffer, iop_data, 1); 541 acb->rqbuf_lastidx++; 542 /* if last index number set it to 0 */ 543 acb->rqbuf_lastidx %= ARCMSR_MAX_QBUFFER; 544 iop_data++; 545 iop_len--; 546 } 547 /* let IOP know data has been read */ 548 arcmsr_iop_message_read(acb); 549 } 550 (void) memcpy(pktioctlfld->messagedatabuffer, 551 ver_addr, allxfer_len); 552 pktioctlfld->cmdmessage.Length = allxfer_len; 553 pktioctlfld->cmdmessage.ReturnCode = 554 ARCMSR_MESSAGE_RETURNCODE_OK; 555 556 if (ddi_copyout(pktioctlfld, (void *)arg, 557 sizeof (struct CMD_MESSAGE_FIELD), mode) != 0) 558 retvalue = ENXIO; 559 560 kmem_free(ver_addr, MSGDATABUFLEN); 561 break; 562 } 563 564 case ARCMSR_MESSAGE_WRITE_WQBUFFER: 565 { 566 uint8_t *ver_addr; 567 int32_t my_empty_len, user_len; 568 int32_t wqbuf_firstidx, wqbuf_lastidx; 569 uint8_t *pQbuffer, *ptmpuserbuffer; 570 571 ver_addr = kmem_zalloc(MSGDATABUFLEN, KM_SLEEP); 572 573 ptmpuserbuffer = ver_addr; 574 user_len = min(pktioctlfld->cmdmessage.Length, 575 MSGDATABUFLEN); 576 (void) memcpy(ptmpuserbuffer, 577 pktioctlfld->messagedatabuffer, user_len); 578 /* 579 * check ifdata xfer length of this request will overflow 580 * my array qbuffer 581 */ 582 wqbuf_lastidx = acb->wqbuf_lastidx; 583 wqbuf_firstidx = acb->wqbuf_firstidx; 584 if (wqbuf_lastidx != wqbuf_firstidx) { 585 arcmsr_post_ioctldata2iop(acb); 586 pktioctlfld->cmdmessage.ReturnCode = 587 ARCMSR_MESSAGE_RETURNCODE_ERROR; 588 } else { 589 my_empty_len = (wqbuf_firstidx - wqbuf_lastidx - 1) 590 & (ARCMSR_MAX_QBUFFER - 1); 591 if (my_empty_len >= user_len) { 592 while (user_len > 0) { 593 /* copy srb data to wqbuffer */ 594 pQbuffer = 595 &acb->wqbuffer[acb->wqbuf_lastidx]; 596 (void) memcpy(pQbuffer, 597 ptmpuserbuffer, 1); 598 acb->wqbuf_lastidx++; 599 /* iflast index number set it to 0 */ 600 acb->wqbuf_lastidx %= 601 ARCMSR_MAX_QBUFFER; 602 ptmpuserbuffer++; 603 user_len--; 604 } 605 /* post first Qbuffer */ 606 if (acb->acb_flags & 607 ACB_F_MESSAGE_WQBUFFER_CLEARED) { 608 acb->acb_flags &= 609 ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 610 arcmsr_post_ioctldata2iop(acb); 611 } 612 pktioctlfld->cmdmessage.ReturnCode = 613 ARCMSR_MESSAGE_RETURNCODE_OK; 614 } else { 615 pktioctlfld->cmdmessage.ReturnCode = 616 ARCMSR_MESSAGE_RETURNCODE_ERROR; 617 } 618 } 619 if (ddi_copyout(pktioctlfld, (void *)arg, 620 sizeof (struct CMD_MESSAGE_FIELD), mode) != 0) 621 retvalue = ENXIO; 622 623 kmem_free(ver_addr, MSGDATABUFLEN); 624 break; 625 } 626 627 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: 628 { 629 uint8_t *pQbuffer = acb->rqbuffer; 630 631 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 632 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 633 arcmsr_iop_message_read(acb); 634 } 635 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 636 acb->rqbuf_firstidx = 0; 637 acb->rqbuf_lastidx = 0; 638 bzero(pQbuffer, ARCMSR_MAX_QBUFFER); 639 /* report success */ 640 pktioctlfld->cmdmessage.ReturnCode = 641 ARCMSR_MESSAGE_RETURNCODE_OK; 642 643 if (ddi_copyout(pktioctlfld, (void *)arg, 644 sizeof (struct CMD_MESSAGE_FIELD), mode) != 0) 645 retvalue = ENXIO; 646 break; 647 } 648 649 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: 650 { 651 uint8_t *pQbuffer = acb->wqbuffer; 652 653 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 654 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 655 arcmsr_iop_message_read(acb); 656 } 657 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED | 658 ACB_F_MESSAGE_WQBUFFER_READ); 659 acb->wqbuf_firstidx = 0; 660 acb->wqbuf_lastidx = 0; 661 bzero(pQbuffer, ARCMSR_MAX_QBUFFER); 662 /* report success */ 663 pktioctlfld->cmdmessage.ReturnCode = 664 ARCMSR_MESSAGE_RETURNCODE_OK; 665 666 if (ddi_copyout(pktioctlfld, (void *)arg, 667 sizeof (struct CMD_MESSAGE_FIELD), mode) != 0) 668 retvalue = ENXIO; 669 break; 670 } 671 672 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: 673 { 674 uint8_t *pQbuffer; 675 676 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 677 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 678 arcmsr_iop_message_read(acb); 679 } 680 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED | 681 ACB_F_MESSAGE_RQBUFFER_CLEARED | 682 ACB_F_MESSAGE_WQBUFFER_READ); 683 acb->rqbuf_firstidx = 0; 684 acb->rqbuf_lastidx = 0; 685 acb->wqbuf_firstidx = 0; 686 acb->wqbuf_lastidx = 0; 687 pQbuffer = acb->rqbuffer; 688 bzero(pQbuffer, sizeof (struct QBUFFER)); 689 pQbuffer = acb->wqbuffer; 690 bzero(pQbuffer, sizeof (struct QBUFFER)); 691 /* report success */ 692 pktioctlfld->cmdmessage.ReturnCode = 693 ARCMSR_MESSAGE_RETURNCODE_OK; 694 if (ddi_copyout(pktioctlfld, (void *)arg, 695 sizeof (struct CMD_MESSAGE_FIELD), mode) != 0) 696 retvalue = ENXIO; 697 break; 698 } 699 700 case ARCMSR_MESSAGE_REQUEST_RETURN_CODE_3F: 701 pktioctlfld->cmdmessage.ReturnCode = 702 ARCMSR_MESSAGE_RETURNCODE_3F; 703 if (ddi_copyout(pktioctlfld, (void *)arg, 704 sizeof (struct CMD_MESSAGE_FIELD), mode) != 0) 705 retvalue = ENXIO; 706 break; 707 708 /* Not supported: ARCMSR_MESSAGE_SAY_HELLO */ 709 case ARCMSR_MESSAGE_SAY_GOODBYE: 710 arcmsr_iop_parking(acb); 711 break; 712 713 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: 714 switch (acb->adapter_type) { 715 case ACB_ADAPTER_TYPE_A: 716 arcmsr_flush_hba_cache(acb); 717 break; 718 case ACB_ADAPTER_TYPE_B: 719 arcmsr_flush_hbb_cache(acb); 720 break; 721 case ACB_ADAPTER_TYPE_C: 722 arcmsr_flush_hbc_cache(acb); 723 break; 724 } 725 break; 726 727 default: 728 mutex_exit(&acb->ioctl_mutex); 729 kmem_free(pktioctlfld, sizeof (struct CMD_MESSAGE_FIELD)); 730 return (scsi_hba_ioctl(dev, ioctl_cmd, arg, mode, credp, 731 rvalp)); 732 } 733 734 ioctl_out: 735 kmem_free(pktioctlfld, sizeof (struct CMD_MESSAGE_FIELD)); 736 mutex_exit(&acb->ioctl_mutex); 737 738 return (retvalue); 739 } 740 741 742 /* 743 * Function: arcmsr_tran_tgt_init 744 * Description: Called when initializing a target device instance. If 745 * no per-target initialization is required, the HBA 746 * may leave tran_tgt_init to NULL 747 * Input: 748 * dev_info_t *host_dev_info, 749 * dev_info_t *target_dev_info, 750 * scsi_hba_tran_t *tran, 751 * struct scsi_device *sd 752 * 753 * Return: DDI_SUCCESS if success, else return DDI_FAILURE 754 * 755 * entry point enables the HBA to allocate and/or initialize any per- 756 * target resources. 757 * It also enables the HBA to qualify the device's address as valid and 758 * supportable for that particular HBA. 759 * By returning DDI_FAILURE, the instance of the target driver for that 760 * device will not be probed or attached. 761 * This entry point is not required, and if none is supplied, 762 * the framework will attempt to probe and attach all possible instances 763 * of the appropriate target drivers. 764 */ 765 static int 766 arcmsr_tran_tgt_init(dev_info_t *host_dev_info, dev_info_t *target_dev_info, 767 scsi_hba_tran_t *tran, struct scsi_device *sd) 768 { 769 uint16_t target; 770 uint8_t lun; 771 struct ACB *acb = tran->tran_hba_private; 772 773 _NOTE(ARGUNUSED(tran, target_dev_info, host_dev_info)) 774 775 target = sd->sd_address.a_target; 776 lun = sd->sd_address.a_lun; 777 if ((target >= ARCMSR_MAX_TARGETID) || (lun >= ARCMSR_MAX_TARGETLUN)) { 778 return (DDI_FAILURE); 779 } 780 781 782 if (ndi_dev_is_persistent_node(target_dev_info) == 0) { 783 /* 784 * If no persistent node exist, we don't allow .conf node 785 * to be created. 786 */ 787 if (arcmsr_find_child(acb, target, lun) != NULL) { 788 if ((ndi_merge_node(target_dev_info, 789 arcmsr_name_node) != DDI_SUCCESS)) { 790 return (DDI_SUCCESS); 791 } 792 } 793 return (DDI_FAILURE); 794 } 795 796 return (DDI_SUCCESS); 797 } 798 799 /* 800 * Function: arcmsr_tran_getcap(9E) 801 * Description: Get the capability named, and returnits value. 802 * Return Values: current value of capability, ifdefined 803 * -1 ifcapability is not defined 804 * ------------------------------------------------------ 805 * Common Capability Strings Array 806 * ------------------------------------------------------ 807 * #define SCSI_CAP_DMA_MAX 0 808 * #define SCSI_CAP_MSG_OUT 1 809 * #define SCSI_CAP_DISCONNECT 2 810 * #define SCSI_CAP_SYNCHRONOUS 3 811 * #define SCSI_CAP_WIDE_XFER 4 812 * #define SCSI_CAP_PARITY 5 813 * #define SCSI_CAP_INITIATOR_ID 6 814 * #define SCSI_CAP_UNTAGGED_QING 7 815 * #define SCSI_CAP_TAGGED_QING 8 816 * #define SCSI_CAP_ARQ 9 817 * #define SCSI_CAP_LINKED_CMDS 10 a 818 * #define SCSI_CAP_SECTOR_SIZE 11 b 819 * #define SCSI_CAP_TOTAL_SECTORS 12 c 820 * #define SCSI_CAP_GEOMETRY 13 d 821 * #define SCSI_CAP_RESET_NOTIFICATION 14 e 822 * #define SCSI_CAP_QFULL_RETRIES 15 f 823 * #define SCSI_CAP_QFULL_RETRY_INTERVAL 16 10 824 * #define SCSI_CAP_SCSI_VERSION 17 11 825 * #define SCSI_CAP_INTERCONNECT_TYPE 18 12 826 * #define SCSI_CAP_LUN_RESET 19 13 827 */ 828 static int 829 arcmsr_tran_getcap(struct scsi_address *ap, char *cap, int whom) 830 { 831 int capability = 0; 832 struct ACB *acb = (struct ACB *)ap->a_hba_tran->tran_hba_private; 833 834 if (cap == NULL || whom == 0) { 835 return (DDI_FAILURE); 836 } 837 838 mutex_enter(&acb->acb_mutex); 839 if (acb->devstate[ap->a_target][ap->a_lun] == ARECA_RAID_GONE) { 840 mutex_exit(&acb->acb_mutex); 841 return (-1); 842 } 843 switch (scsi_hba_lookup_capstr(cap)) { 844 case SCSI_CAP_MSG_OUT: 845 case SCSI_CAP_DISCONNECT: 846 case SCSI_CAP_WIDE_XFER: 847 case SCSI_CAP_TAGGED_QING: 848 case SCSI_CAP_UNTAGGED_QING: 849 case SCSI_CAP_PARITY: 850 case SCSI_CAP_ARQ: 851 capability = 1; 852 break; 853 case SCSI_CAP_SECTOR_SIZE: 854 capability = ARCMSR_DEV_SECTOR_SIZE; 855 break; 856 case SCSI_CAP_DMA_MAX: 857 /* Limit to 16MB max transfer */ 858 capability = ARCMSR_MAX_XFER_LEN; 859 break; 860 case SCSI_CAP_INITIATOR_ID: 861 capability = ARCMSR_SCSI_INITIATOR_ID; 862 break; 863 case SCSI_CAP_GEOMETRY: 864 /* head , track , cylinder */ 865 capability = (255 << 16) | 63; 866 break; 867 default: 868 capability = -1; 869 break; 870 } 871 mutex_exit(&acb->acb_mutex); 872 return (capability); 873 } 874 875 /* 876 * Function: arcmsr_tran_setcap(9E) 877 * Description: Set the specific capability. 878 * Return Values: 1 - capability exists and can be set to new value 879 * 0 - capability could not be set to new value 880 * -1 - no such capability 881 */ 882 static int 883 arcmsr_tran_setcap(struct scsi_address *ap, char *cap, int value, int whom) 884 { 885 _NOTE(ARGUNUSED(value)) 886 887 int supported = 0; 888 struct ACB *acb = (struct ACB *)ap->a_hba_tran->tran_hba_private; 889 890 if (cap == NULL || whom == 0) { 891 return (-1); 892 } 893 894 mutex_enter(&acb->acb_mutex); 895 if (acb->devstate[ap->a_target][ap->a_lun] == ARECA_RAID_GONE) { 896 mutex_exit(&acb->acb_mutex); 897 return (-1); 898 } 899 switch (supported = scsi_hba_lookup_capstr(cap)) { 900 case SCSI_CAP_ARQ: /* 9 auto request sense */ 901 case SCSI_CAP_UNTAGGED_QING: /* 7 */ 902 case SCSI_CAP_TAGGED_QING: /* 8 */ 903 /* these are always on, and cannot be turned off */ 904 supported = (value == 1) ? 1 : 0; 905 break; 906 case SCSI_CAP_TOTAL_SECTORS: /* c */ 907 supported = 1; 908 break; 909 case SCSI_CAP_DISCONNECT: /* 2 */ 910 case SCSI_CAP_WIDE_XFER: /* 4 */ 911 case SCSI_CAP_INITIATOR_ID: /* 6 */ 912 case SCSI_CAP_DMA_MAX: /* 0 */ 913 case SCSI_CAP_MSG_OUT: /* 1 */ 914 case SCSI_CAP_PARITY: /* 5 */ 915 case SCSI_CAP_LINKED_CMDS: /* a */ 916 case SCSI_CAP_RESET_NOTIFICATION: /* e */ 917 case SCSI_CAP_SECTOR_SIZE: /* b */ 918 /* these are not settable */ 919 supported = 0; 920 break; 921 default: 922 supported = -1; 923 break; 924 } 925 mutex_exit(&acb->acb_mutex); 926 return (supported); 927 } 928 929 930 /* 931 * Function: arcmsr_tran_init_pkt 932 * Return Values: pointer to scsi_pkt, or NULL 933 * Description: simultaneously allocate both a scsi_pkt(9S) structure and 934 * DMA resources for that pkt. 935 * Called by kernel on behalf of a target driver 936 * calling scsi_init_pkt(9F). 937 * Refer to tran_init_pkt(9E) man page 938 * Context: Can be called from different kernel process threads. 939 * Can be called by interrupt thread. 940 * Allocates SCSI packet and DMA resources 941 */ 942 static struct 943 scsi_pkt *arcmsr_tran_init_pkt(struct scsi_address *ap, 944 register struct scsi_pkt *pkt, struct buf *bp, int cmdlen, int statuslen, 945 int tgtlen, int flags, int (*callback)(), caddr_t arg) 946 { 947 struct CCB *ccb; 948 struct ARCMSR_CDB *arcmsr_cdb; 949 struct ACB *acb; 950 int old_pkt_flag; 951 952 acb = (struct ACB *)ap->a_hba_tran->tran_hba_private; 953 954 if (acb->acb_flags & ACB_F_BUS_RESET) { 955 return (NULL); 956 } 957 if (pkt == NULL) { 958 /* get free CCB */ 959 (void) ddi_dma_sync(acb->ccbs_pool_handle, 0, 0, 960 DDI_DMA_SYNC_FORKERNEL); 961 ccb = arcmsr_get_freeccb(acb); 962 if (ccb == (struct CCB *)NULL) { 963 return (NULL); 964 } 965 966 if (statuslen < sizeof (struct scsi_arq_status)) { 967 statuslen = sizeof (struct scsi_arq_status); 968 } 969 pkt = scsi_hba_pkt_alloc(acb->dev_info, ap, cmdlen, 970 statuslen, tgtlen, sizeof (void *), callback, arg); 971 if (pkt == NULL) { 972 arcmsr_warn(acb, "scsi pkt allocation failed"); 973 arcmsr_free_ccb(ccb); 974 return (NULL); 975 } 976 /* Initialize CCB */ 977 ccb->pkt = pkt; 978 ccb->pkt_dma_handle = NULL; 979 /* record how many sg are needed to xfer on this pkt */ 980 ccb->pkt_ncookies = 0; 981 /* record how many sg we got from this window */ 982 ccb->pkt_cookie = 0; 983 /* record how many windows have partial dma map set */ 984 ccb->pkt_nwin = 0; 985 /* record current sg window position */ 986 ccb->pkt_curwin = 0; 987 ccb->pkt_dma_len = 0; 988 ccb->pkt_dma_offset = 0; 989 ccb->resid_dmacookie.dmac_size = 0; 990 991 /* 992 * we will still use this point for we want to fake some 993 * information in tran_start 994 */ 995 ccb->bp = bp; 996 997 /* Initialize arcmsr_cdb */ 998 arcmsr_cdb = &ccb->arcmsr_cdb; 999 bzero(arcmsr_cdb, sizeof (struct ARCMSR_CDB)); 1000 arcmsr_cdb->Bus = 0; 1001 arcmsr_cdb->Function = 1; 1002 arcmsr_cdb->LUN = ap->a_lun; 1003 arcmsr_cdb->TargetID = ap->a_target; 1004 arcmsr_cdb->CdbLength = (uint8_t)cmdlen; 1005 arcmsr_cdb->Context = (uintptr_t)arcmsr_cdb; 1006 1007 /* Fill in the rest of the structure */ 1008 pkt->pkt_ha_private = ccb; 1009 pkt->pkt_address = *ap; 1010 pkt->pkt_comp = NULL; 1011 pkt->pkt_flags = 0; 1012 pkt->pkt_time = 0; 1013 pkt->pkt_resid = 0; 1014 pkt->pkt_statistics = 0; 1015 pkt->pkt_reason = 0; 1016 old_pkt_flag = 0; 1017 } else { 1018 ccb = pkt->pkt_ha_private; 1019 if (ccb->ccb_state & ARCMSR_ABNORMAL_MASK) { 1020 if (!(ccb->ccb_state & ARCMSR_CCB_BACK)) { 1021 return (NULL); 1022 } 1023 } 1024 1025 /* 1026 * you cannot update CdbLength with cmdlen here, it would 1027 * cause a data compare error 1028 */ 1029 ccb->ccb_state = ARCMSR_CCB_UNBUILD; 1030 old_pkt_flag = 1; 1031 } 1032 1033 /* Second step : dma allocation/move */ 1034 if (bp && bp->b_bcount != 0) { 1035 /* 1036 * system had a lot of data trunk need to xfer, from...20 byte 1037 * to 819200 byte. 1038 * arcmsr_dma_alloc will get pkt_dma_handle (not null) until 1039 * this lot of data trunk xfer done this mission will be done 1040 * by some of continue READ or WRITE scsi command, till this 1041 * lot of data trunk xfer completed. 1042 * arcmsr_dma_move do the action repeatedly, and use the same 1043 * ccb till this lot of data trunk xfer complete notice. 1044 * when after the arcmsr_tran_init_pkt returns the solaris 1045 * kernel is by your pkt_resid and its b_bcount to give you 1046 * which type of scsi command descriptor to implement the 1047 * length of folowing arcmsr_tran_start scsi cdb (data length) 1048 * 1049 * Each transfer should be aligned on a 512 byte boundary 1050 */ 1051 if (ccb->pkt_dma_handle == NULL) { 1052 if (arcmsr_dma_alloc(acb, pkt, bp, flags, callback) == 1053 DDI_FAILURE) { 1054 /* 1055 * the HBA driver is unable to allocate DMA 1056 * resources, it must free the allocated 1057 * scsi_pkt(9S) before returning 1058 */ 1059 arcmsr_warn(acb, "dma allocation failure"); 1060 if (old_pkt_flag == 0) { 1061 arcmsr_warn(acb, "dma " 1062 "allocation failed to free " 1063 "scsi hba pkt"); 1064 arcmsr_free_ccb(ccb); 1065 scsi_hba_pkt_free(ap, pkt); 1066 } 1067 return (NULL); 1068 } 1069 } else { 1070 /* DMA resources to next DMA window, for old pkt */ 1071 if (arcmsr_dma_move(acb, pkt, bp) == DDI_FAILURE) { 1072 arcmsr_warn(acb, "dma move failed"); 1073 return (NULL); 1074 } 1075 } 1076 } else { 1077 pkt->pkt_resid = 0; 1078 } 1079 return (pkt); 1080 } 1081 1082 /* 1083 * Function: arcmsr_tran_start(9E) 1084 * Description: Transport the command in pktp to the target device. 1085 * The command is not finished when this returns, only 1086 * sent to the target; arcmsr_intr_handler will call 1087 * scsi_hba_pkt_comp(pktp) when the target device has done. 1088 * 1089 * Input: struct scsi_address *ap, struct scsi_pkt *pktp 1090 * Output: TRAN_ACCEPT if pkt is OK and not driver not busy 1091 * TRAN_BUSY if driver is 1092 * TRAN_BADPKT if pkt is invalid 1093 */ 1094 static int 1095 arcmsr_tran_start(struct scsi_address *ap, struct scsi_pkt *pkt) 1096 { 1097 struct ACB *acb; 1098 struct CCB *ccb; 1099 int target = ap->a_target; 1100 int lun = ap->a_lun; 1101 1102 acb = (struct ACB *)ap->a_hba_tran->tran_hba_private; 1103 ccb = pkt->pkt_ha_private; 1104 *pkt->pkt_scbp = STATUS_GOOD; /* clear arq scsi_status */ 1105 1106 if ((ccb->ccb_flags & CCB_FLAG_DMAVALID) && 1107 (ccb->ccb_flags & DDI_DMA_CONSISTENT)) 1108 (void) ddi_dma_sync(ccb->pkt_dma_handle, 0, 0, 1109 DDI_DMA_SYNC_FORDEV); 1110 1111 if (ccb->ccb_state == ARCMSR_CCB_UNBUILD) 1112 arcmsr_build_ccb(ccb); 1113 1114 if (acb->acb_flags & ACB_F_BUS_RESET) { 1115 pkt->pkt_reason = CMD_RESET; 1116 pkt->pkt_statistics |= STAT_BUS_RESET; 1117 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | 1118 STATE_SENT_CMD | STATE_GOT_STATUS); 1119 if ((ccb->ccb_flags & CCB_FLAG_DMACONSISTENT) && 1120 (pkt->pkt_state & STATE_XFERRED_DATA)) 1121 (void) ddi_dma_sync(ccb->pkt_dma_handle, 1122 0, 0, DDI_DMA_SYNC_FORCPU); 1123 1124 scsi_hba_pkt_comp(pkt); 1125 return (TRAN_ACCEPT); 1126 } 1127 1128 /* IMPORTANT: Target 16 is a virtual device for iop message transfer */ 1129 if (target == 16) { 1130 1131 struct buf *bp = ccb->bp; 1132 uint8_t scsicmd = pkt->pkt_cdbp[0]; 1133 1134 switch (scsicmd) { 1135 case SCMD_INQUIRY: { 1136 if (lun != 0) { 1137 ccb->pkt->pkt_reason = CMD_TIMEOUT; 1138 ccb->pkt->pkt_statistics |= STAT_TIMEOUT; 1139 arcmsr_ccb_complete(ccb, 0); 1140 return (TRAN_ACCEPT); 1141 } 1142 1143 if (bp && bp->b_un.b_addr && bp->b_bcount) { 1144 uint8_t inqdata[36]; 1145 1146 /* The EVDP and pagecode is not supported */ 1147 if (pkt->pkt_cdbp[1] || pkt->pkt_cdbp[2]) { 1148 inqdata[1] = 0xFF; 1149 inqdata[2] = 0x00; 1150 } else { 1151 /* Periph Qualifier & Periph Dev Type */ 1152 inqdata[0] = DTYPE_PROCESSOR; 1153 /* rem media bit & Dev Type Modifier */ 1154 inqdata[1] = 0; 1155 /* ISO, ECMA, & ANSI versions */ 1156 inqdata[2] = 0; 1157 inqdata[3] = 0; 1158 /* length of additional data */ 1159 inqdata[4] = 31; 1160 /* Vendor Identification */ 1161 bcopy("Areca ", &inqdata[8], VIDLEN); 1162 /* Product Identification */ 1163 bcopy("RAID controller ", &inqdata[16], 1164 PIDLEN); 1165 /* Product Revision */ 1166 bcopy(&inqdata[32], "R001", REVLEN); 1167 if (bp->b_flags & (B_PHYS | B_PAGEIO)) 1168 bp_mapin(bp); 1169 1170 (void) memcpy(bp->b_un.b_addr, 1171 inqdata, sizeof (inqdata)); 1172 } 1173 ccb->pkt->pkt_state |= STATE_XFERRED_DATA; 1174 } 1175 arcmsr_ccb_complete(ccb, 0); 1176 return (TRAN_ACCEPT); 1177 } 1178 case SCMD_WRITE_BUFFER: 1179 case SCMD_READ_BUFFER: { 1180 if (arcmsr_iop_message_xfer(acb, pkt)) { 1181 /* error just for retry */ 1182 ccb->pkt->pkt_reason = CMD_TRAN_ERR; 1183 ccb->pkt->pkt_statistics |= STAT_TERMINATED; 1184 } 1185 ccb->pkt->pkt_state |= STATE_XFERRED_DATA; 1186 arcmsr_ccb_complete(ccb, 0); 1187 return (TRAN_ACCEPT); 1188 } 1189 default: 1190 ccb->pkt->pkt_state |= STATE_XFERRED_DATA; 1191 arcmsr_ccb_complete(ccb, 0); 1192 return (TRAN_ACCEPT); 1193 } 1194 } 1195 1196 if (acb->devstate[target][lun] == ARECA_RAID_GONE) { 1197 uint8_t block_cmd; 1198 1199 block_cmd = pkt->pkt_cdbp[0] & 0x0f; 1200 if (block_cmd == 0x08 || block_cmd == 0x0a) { 1201 pkt->pkt_reason = CMD_TIMEOUT; 1202 pkt->pkt_statistics |= STAT_TIMEOUT; 1203 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | 1204 STATE_SENT_CMD | STATE_GOT_STATUS); 1205 if ((ccb->ccb_flags & CCB_FLAG_DMACONSISTENT) && 1206 (pkt->pkt_state & STATE_XFERRED_DATA)) { 1207 (void) ddi_dma_sync(ccb->pkt_dma_handle, 1208 ccb->pkt_dma_offset, 1209 ccb->pkt_dma_len, DDI_DMA_SYNC_FORCPU); 1210 } 1211 scsi_hba_pkt_comp(pkt); 1212 return (TRAN_ACCEPT); 1213 } 1214 } 1215 mutex_enter(&acb->postq_mutex); 1216 if (acb->ccboutstandingcount >= ARCMSR_MAX_OUTSTANDING_CMD) { 1217 ccb->ccb_state = ARCMSR_CCB_RETRY; 1218 mutex_exit(&acb->postq_mutex); 1219 return (TRAN_BUSY); 1220 } else if (arcmsr_post_ccb(acb, ccb) == DDI_FAILURE) { 1221 arcmsr_warn(acb, "post ccb failure, ccboutstandingcount = %d", 1222 acb->ccboutstandingcount); 1223 mutex_exit(&acb->postq_mutex); 1224 return (TRAN_FATAL_ERROR); 1225 } 1226 mutex_exit(&acb->postq_mutex); 1227 return (TRAN_ACCEPT); 1228 } 1229 1230 /* 1231 * Function name: arcmsr_tran_destroy_pkt 1232 * Return Values: none 1233 * Description: Called by kernel on behalf of a target driver 1234 * calling scsi_destroy_pkt(9F). 1235 * Refer to tran_destroy_pkt(9E) man page 1236 * Context: Can be called from different kernel process threads. 1237 * Can be called by interrupt thread. 1238 */ 1239 static void 1240 arcmsr_tran_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt) 1241 { 1242 struct CCB *ccb = pkt->pkt_ha_private; 1243 ddi_dma_handle_t pkt_dma_handle = ccb->pkt_dma_handle; 1244 1245 if (ccb == NULL) { 1246 return; 1247 } 1248 if (ccb->pkt != pkt) { 1249 return; 1250 } 1251 if (ccb->ccb_flags & CCB_FLAG_DMAVALID) { 1252 ccb->ccb_flags &= ~CCB_FLAG_DMAVALID; 1253 if (pkt_dma_handle) { 1254 (void) ddi_dma_unbind_handle(ccb->pkt_dma_handle); 1255 } 1256 } 1257 if (pkt_dma_handle) { 1258 (void) ddi_dma_free_handle(&pkt_dma_handle); 1259 } 1260 pkt->pkt_ha_private = NULL; 1261 if (ccb) { 1262 if (ccb->ccb_state & ARCMSR_ABNORMAL_MASK) { 1263 if (ccb->ccb_state & ARCMSR_CCB_BACK) { 1264 arcmsr_free_ccb(ccb); 1265 } else { 1266 ccb->ccb_state |= ARCMSR_CCB_WAIT4_FREE; 1267 } 1268 } else { 1269 arcmsr_free_ccb(ccb); 1270 } 1271 } 1272 scsi_hba_pkt_free(ap, pkt); 1273 } 1274 1275 /* 1276 * Function name: arcmsr_tran_dmafree() 1277 * Return Values: none 1278 * Description: free dvma resources 1279 * Context: Can be called from different kernel process threads. 1280 * Can be called by interrupt thread. 1281 */ 1282 static void 1283 arcmsr_tran_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt) 1284 { 1285 struct CCB *ccb = pkt->pkt_ha_private; 1286 1287 if ((ccb == NULL) || (ccb->pkt != pkt)) { 1288 return; 1289 } 1290 if (ccb->ccb_flags & CCB_FLAG_DMAVALID) { 1291 ccb->ccb_flags &= ~CCB_FLAG_DMAVALID; 1292 if (ddi_dma_unbind_handle(ccb->pkt_dma_handle) != DDI_SUCCESS) { 1293 arcmsr_warn(ccb->acb, "ddi_dma_unbind_handle() failed " 1294 "(target %d lun %d)", ap->a_target, ap->a_lun); 1295 } 1296 ddi_dma_free_handle(&ccb->pkt_dma_handle); 1297 ccb->pkt_dma_handle = NULL; 1298 } 1299 } 1300 1301 /* 1302 * Function name: arcmsr_tran_sync_pkt() 1303 * Return Values: none 1304 * Description: sync dma 1305 * Context: Can be called from different kernel process threads. 1306 * Can be called by interrupt thread. 1307 */ 1308 static void 1309 arcmsr_tran_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt) 1310 { 1311 struct CCB *ccb; 1312 1313 ccb = pkt->pkt_ha_private; 1314 if ((ccb == NULL) || (ccb->pkt != pkt)) { 1315 return; 1316 } 1317 if (ccb->ccb_flags & CCB_FLAG_DMAVALID) { 1318 if (ddi_dma_sync(ccb->pkt_dma_handle, 0, 0, 1319 (ccb->ccb_flags & CCB_FLAG_DMAWRITE) ? 1320 DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU) != 1321 DDI_SUCCESS) { 1322 arcmsr_warn(ccb->acb, 1323 "sync pkt failed for target %d lun %d", 1324 ap->a_target, ap->a_lun); 1325 } 1326 } 1327 } 1328 1329 1330 /* 1331 * Function: arcmsr_tran_abort(9E) 1332 * SCSA interface routine to abort pkt(s) in progress. 1333 * Aborts the pkt specified. If NULL pkt, aborts ALL pkts. 1334 * Output: Return 1 if success 1335 * Return 0 if failure 1336 */ 1337 static int 1338 arcmsr_tran_abort(struct scsi_address *ap, struct scsi_pkt *abortpkt) 1339 { 1340 struct ACB *acb; 1341 int return_code; 1342 1343 acb = ap->a_hba_tran->tran_hba_private; 1344 1345 while (acb->ccboutstandingcount != 0) { 1346 drv_usecwait(10000); 1347 } 1348 1349 mutex_enter(&acb->isr_mutex); 1350 return_code = arcmsr_seek_cmd2abort(acb, abortpkt); 1351 mutex_exit(&acb->isr_mutex); 1352 1353 if (return_code != DDI_SUCCESS) { 1354 arcmsr_warn(acb, "abort command failed for target %d lun %d", 1355 ap->a_target, ap->a_lun); 1356 return (0); 1357 } 1358 return (1); 1359 } 1360 1361 /* 1362 * Function: arcmsr_tran_reset(9E) 1363 * SCSA interface routine to perform scsi resets on either 1364 * a specified target or the bus (default). 1365 * Output: Return 1 if success 1366 * Return 0 if failure 1367 */ 1368 static int 1369 arcmsr_tran_reset(struct scsi_address *ap, int level) 1370 { 1371 struct ACB *acb; 1372 int return_code = 1; 1373 int target = ap->a_target; 1374 int lun = ap->a_lun; 1375 1376 /* Are we in the middle of dumping core? */ 1377 if (ddi_in_panic()) 1378 return (return_code); 1379 1380 acb = (struct ACB *)ap->a_hba_tran->tran_hba_private; 1381 mutex_enter(&acb->isr_mutex); 1382 switch (level) { 1383 case RESET_ALL: /* 0 */ 1384 acb->num_resets++; 1385 acb->acb_flags |= ACB_F_BUS_RESET; 1386 if (acb->timeout_count) { 1387 if (arcmsr_iop_reset(acb) != 0) { 1388 arcmsr_handle_iop_bus_hold(acb); 1389 acb->acb_flags &= ~ACB_F_BUS_HANG_ON; 1390 } 1391 } 1392 acb->acb_flags &= ~ACB_F_BUS_RESET; 1393 break; 1394 case RESET_TARGET: /* 1 */ 1395 if (acb->devstate[target][lun] == ARECA_RAID_GONE) 1396 return_code = 0; 1397 break; 1398 case RESET_BUS: /* 2 */ 1399 return_code = 0; 1400 break; 1401 case RESET_LUN: /* 3 */ 1402 return_code = 0; 1403 break; 1404 default: 1405 return_code = 0; 1406 } 1407 mutex_exit(&acb->isr_mutex); 1408 return (return_code); 1409 } 1410 1411 static int 1412 arcmsr_tran_bus_config(dev_info_t *parent, uint_t flags, 1413 ddi_bus_config_op_t op, void *arg, dev_info_t **childp) 1414 { 1415 struct ACB *acb; 1416 int rval; 1417 int tgt, lun; 1418 1419 if ((acb = ddi_get_soft_state(arcmsr_soft_state, 1420 ddi_get_instance(parent))) == NULL) 1421 return (NDI_FAILURE); 1422 1423 ndi_devi_enter(parent); 1424 switch (op) { 1425 case BUS_CONFIG_ONE: 1426 if (arcmsr_parse_devname(arg, &tgt, &lun) != 0) { 1427 rval = NDI_FAILURE; 1428 break; 1429 } 1430 if (acb->device_map[tgt] & 1 << lun) { 1431 acb->devstate[tgt][lun] = ARECA_RAID_GOOD; 1432 rval = arcmsr_config_lun(acb, tgt, lun, childp); 1433 } 1434 break; 1435 1436 case BUS_CONFIG_DRIVER: 1437 case BUS_CONFIG_ALL: 1438 for (tgt = 0; tgt < ARCMSR_MAX_TARGETID; tgt++) 1439 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) 1440 if (acb->device_map[tgt] & 1 << lun) { 1441 acb->devstate[tgt][lun] = 1442 ARECA_RAID_GOOD; 1443 (void) arcmsr_config_lun(acb, tgt, 1444 lun, NULL); 1445 } 1446 1447 rval = NDI_SUCCESS; 1448 break; 1449 } 1450 if (rval == NDI_SUCCESS) 1451 rval = ndi_busop_bus_config(parent, flags, op, arg, childp, 0); 1452 ndi_devi_exit(parent); 1453 return (rval); 1454 } 1455 1456 /* 1457 * Function name: arcmsr_dma_alloc 1458 * Return Values: 0 if successful, -1 if failure 1459 * Description: allocate DMA resources 1460 * Context: Can only be called from arcmsr_tran_init_pkt() 1461 * register struct scsi_address *ap = &((pkt)->pkt_address); 1462 */ 1463 static int 1464 arcmsr_dma_alloc(struct ACB *acb, struct scsi_pkt *pkt, 1465 struct buf *bp, int flags, int (*callback)()) 1466 { 1467 struct CCB *ccb = pkt->pkt_ha_private; 1468 int alloc_result, map_method, dma_flags; 1469 int resid = 0; 1470 int total_ccb_xferlen = 0; 1471 int (*cb)(caddr_t); 1472 uint8_t i; 1473 1474 /* 1475 * at this point the PKT SCSI CDB is empty, and dma xfer length 1476 * is bp->b_bcount 1477 */ 1478 1479 if (bp->b_flags & B_READ) { 1480 ccb->ccb_flags &= ~CCB_FLAG_DMAWRITE; 1481 dma_flags = DDI_DMA_READ; 1482 } else { 1483 ccb->ccb_flags |= CCB_FLAG_DMAWRITE; 1484 dma_flags = DDI_DMA_WRITE; 1485 } 1486 1487 if (flags & PKT_CONSISTENT) { 1488 ccb->ccb_flags |= CCB_FLAG_DMACONSISTENT; 1489 dma_flags |= DDI_DMA_CONSISTENT; 1490 } 1491 if (flags & PKT_DMA_PARTIAL) { 1492 dma_flags |= DDI_DMA_PARTIAL; 1493 } 1494 1495 dma_flags |= DDI_DMA_REDZONE; 1496 cb = (callback == NULL_FUNC) ? DDI_DMA_DONTWAIT : DDI_DMA_SLEEP; 1497 1498 alloc_result = ddi_dma_alloc_handle(acb->dev_info, &arcmsr_dma_attr, 1499 cb, 0, &ccb->pkt_dma_handle); 1500 if (alloc_result != DDI_SUCCESS) { 1501 arcmsr_warn(acb, "dma allocate failed (%x)", alloc_result); 1502 return (DDI_FAILURE); 1503 } 1504 1505 map_method = ddi_dma_buf_bind_handle(ccb->pkt_dma_handle, 1506 bp, dma_flags, cb, 0, 1507 &ccb->pkt_dmacookies[0], /* SG List pointer */ 1508 &ccb->pkt_ncookies); /* number of sgl cookies */ 1509 1510 switch (map_method) { 1511 case DDI_DMA_PARTIAL_MAP: 1512 /* 1513 * When your main memory size larger then 4G 1514 * DDI_DMA_PARTIAL_MAP will be touched. 1515 * 1516 * We've already set DDI_DMA_PARTIAL in dma_flags, 1517 * so if it's now missing, there's something screwy 1518 * happening. We plow on.... 1519 */ 1520 1521 if ((dma_flags & DDI_DMA_PARTIAL) == 0) { 1522 arcmsr_warn(acb, 1523 "dma partial mapping lost ...impossible case!"); 1524 } 1525 if (ddi_dma_numwin(ccb->pkt_dma_handle, &ccb->pkt_nwin) == 1526 DDI_FAILURE) { 1527 arcmsr_warn(acb, "ddi_dma_numwin() failed"); 1528 } 1529 1530 if (ddi_dma_getwin(ccb->pkt_dma_handle, ccb->pkt_curwin, 1531 &ccb->pkt_dma_offset, &ccb->pkt_dma_len, 1532 &ccb->pkt_dmacookies[0], &ccb->pkt_ncookies) == 1533 DDI_FAILURE) { 1534 arcmsr_warn(acb, "ddi_dma_getwin failed"); 1535 } 1536 1537 i = 0; 1538 /* first cookie is accessed from ccb->pkt_dmacookies[0] */ 1539 total_ccb_xferlen = ccb->pkt_dmacookies[0].dmac_size; 1540 for (;;) { 1541 i++; 1542 if ((i == ARCMSR_MAX_SG_ENTRIES) || 1543 (i == ccb->pkt_ncookies) || 1544 (total_ccb_xferlen == ARCMSR_MAX_XFER_LEN)) { 1545 break; 1546 } 1547 /* 1548 * next cookie will be retrieved from 1549 * ccb->pkt_dmacookies[i] 1550 */ 1551 ddi_dma_nextcookie(ccb->pkt_dma_handle, 1552 &ccb->pkt_dmacookies[i]); 1553 total_ccb_xferlen += ccb->pkt_dmacookies[i].dmac_size; 1554 } 1555 ccb->pkt_cookie = i; 1556 ccb->arcmsr_cdb.sgcount = i; 1557 if (total_ccb_xferlen > 512) { 1558 resid = total_ccb_xferlen % 512; 1559 if (resid != 0) { 1560 i--; 1561 total_ccb_xferlen -= resid; 1562 /* modify last sg length */ 1563 ccb->pkt_dmacookies[i].dmac_size = 1564 ccb->pkt_dmacookies[i].dmac_size - resid; 1565 ccb->resid_dmacookie.dmac_size = resid; 1566 ccb->resid_dmacookie.dmac_laddress = 1567 ccb->pkt_dmacookies[i].dmac_laddress + 1568 ccb->pkt_dmacookies[i].dmac_size; 1569 } 1570 } 1571 ccb->total_dmac_size = total_ccb_xferlen; 1572 ccb->ccb_flags |= CCB_FLAG_DMAVALID; 1573 pkt->pkt_resid = bp->b_bcount - ccb->total_dmac_size; 1574 1575 return (DDI_SUCCESS); 1576 1577 case DDI_DMA_MAPPED: 1578 ccb->pkt_nwin = 1; /* all mapped, so only one window */ 1579 ccb->pkt_dma_len = 0; 1580 ccb->pkt_dma_offset = 0; 1581 i = 0; 1582 /* first cookie is accessed from ccb->pkt_dmacookies[0] */ 1583 total_ccb_xferlen = ccb->pkt_dmacookies[0].dmac_size; 1584 for (;;) { 1585 i++; 1586 if ((i == ARCMSR_MAX_SG_ENTRIES) || 1587 (i == ccb->pkt_ncookies) || 1588 (total_ccb_xferlen == ARCMSR_MAX_XFER_LEN)) { 1589 break; 1590 } 1591 /* 1592 * next cookie will be retrieved from 1593 * ccb->pkt_dmacookies[i] 1594 */ 1595 ddi_dma_nextcookie(ccb->pkt_dma_handle, 1596 &ccb->pkt_dmacookies[i]); 1597 total_ccb_xferlen += ccb->pkt_dmacookies[i].dmac_size; 1598 } 1599 ccb->pkt_cookie = i; 1600 ccb->arcmsr_cdb.sgcount = i; 1601 if (total_ccb_xferlen > 512) { 1602 resid = total_ccb_xferlen % 512; 1603 if (resid != 0) { 1604 i--; 1605 total_ccb_xferlen -= resid; 1606 /* modify last sg length */ 1607 ccb->pkt_dmacookies[i].dmac_size = 1608 ccb->pkt_dmacookies[i].dmac_size - resid; 1609 ccb->resid_dmacookie.dmac_size = resid; 1610 ccb->resid_dmacookie.dmac_laddress = 1611 ccb->pkt_dmacookies[i].dmac_laddress + 1612 ccb->pkt_dmacookies[i].dmac_size; 1613 } 1614 } 1615 ccb->total_dmac_size = total_ccb_xferlen; 1616 ccb->ccb_flags |= CCB_FLAG_DMAVALID; 1617 pkt->pkt_resid = bp->b_bcount - ccb->total_dmac_size; 1618 return (DDI_SUCCESS); 1619 1620 case DDI_DMA_NORESOURCES: 1621 arcmsr_warn(acb, "dma map got 'no resources'"); 1622 bioerror(bp, ENOMEM); 1623 break; 1624 1625 case DDI_DMA_NOMAPPING: 1626 arcmsr_warn(acb, "dma map got 'no mapping'"); 1627 bioerror(bp, EFAULT); 1628 break; 1629 1630 case DDI_DMA_TOOBIG: 1631 arcmsr_warn(acb, "dma map got 'too big'"); 1632 bioerror(bp, EINVAL); 1633 break; 1634 1635 case DDI_DMA_INUSE: 1636 arcmsr_warn(acb, "dma map got 'in use' " 1637 "(should not happen)"); 1638 break; 1639 default: 1640 arcmsr_warn(acb, "dma map failed (0x%x)", i); 1641 break; 1642 } 1643 1644 ddi_dma_free_handle(&ccb->pkt_dma_handle); 1645 ccb->pkt_dma_handle = NULL; 1646 ccb->ccb_flags &= ~CCB_FLAG_DMAVALID; 1647 return (DDI_FAILURE); 1648 } 1649 1650 1651 /* 1652 * Function name: arcmsr_dma_move 1653 * Return Values: 0 if successful, -1 if failure 1654 * Description: move DMA resources to next DMA window 1655 * Context: Can only be called from arcmsr_tran_init_pkt() 1656 */ 1657 static int 1658 arcmsr_dma_move(struct ACB *acb, struct scsi_pkt *pkt, struct buf *bp) 1659 { 1660 struct CCB *ccb = pkt->pkt_ha_private; 1661 uint8_t i = 0; 1662 int resid = 0; 1663 int total_ccb_xferlen = 0; 1664 1665 if (ccb->resid_dmacookie.dmac_size != 0) { 1666 total_ccb_xferlen += ccb->resid_dmacookie.dmac_size; 1667 ccb->pkt_dmacookies[i].dmac_size = 1668 ccb->resid_dmacookie.dmac_size; 1669 ccb->pkt_dmacookies[i].dmac_laddress = 1670 ccb->resid_dmacookie.dmac_laddress; 1671 i++; 1672 ccb->resid_dmacookie.dmac_size = 0; 1673 } 1674 /* 1675 * If there are no more cookies remaining in this window, 1676 * move to the next window. 1677 */ 1678 if (ccb->pkt_cookie == ccb->pkt_ncookies) { 1679 /* 1680 * only dma map "partial" arrive here 1681 */ 1682 if ((ccb->pkt_curwin == ccb->pkt_nwin) && 1683 (ccb->pkt_nwin == 1)) { 1684 return (DDI_SUCCESS); 1685 } 1686 1687 /* At last window, cannot move */ 1688 if (++ccb->pkt_curwin >= ccb->pkt_nwin) { 1689 arcmsr_warn(acb, "dma partial set, numwin exceeded"); 1690 return (DDI_FAILURE); 1691 } 1692 if (ddi_dma_getwin(ccb->pkt_dma_handle, ccb->pkt_curwin, 1693 &ccb->pkt_dma_offset, &ccb->pkt_dma_len, 1694 &ccb->pkt_dmacookies[i], &ccb->pkt_ncookies) == 1695 DDI_FAILURE) { 1696 arcmsr_warn(acb, "ddi_dma_getwin failed"); 1697 return (DDI_FAILURE); 1698 } 1699 /* reset cookie pointer */ 1700 ccb->pkt_cookie = 0; 1701 } else { 1702 /* 1703 * only dma map "all" arrive here 1704 * We still have more cookies in this window, 1705 * get the next one 1706 * access the pkt_dma_handle remain cookie record at 1707 * ccb->pkt_dmacookies array 1708 */ 1709 ddi_dma_nextcookie(ccb->pkt_dma_handle, 1710 &ccb->pkt_dmacookies[i]); 1711 } 1712 1713 /* Get remaining cookies in this window, up to our maximum */ 1714 total_ccb_xferlen += ccb->pkt_dmacookies[i].dmac_size; 1715 1716 /* retrieve and store cookies, start at ccb->pkt_dmacookies[0] */ 1717 for (;;) { 1718 i++; 1719 /* handled cookies count level indicator */ 1720 ccb->pkt_cookie++; 1721 if ((i == ARCMSR_MAX_SG_ENTRIES) || 1722 (ccb->pkt_cookie == ccb->pkt_ncookies) || 1723 (total_ccb_xferlen == ARCMSR_MAX_XFER_LEN)) { 1724 break; 1725 } 1726 ddi_dma_nextcookie(ccb->pkt_dma_handle, 1727 &ccb->pkt_dmacookies[i]); 1728 total_ccb_xferlen += ccb->pkt_dmacookies[i].dmac_size; 1729 } 1730 1731 ccb->arcmsr_cdb.sgcount = i; 1732 if (total_ccb_xferlen > 512) { 1733 resid = total_ccb_xferlen % 512; 1734 if (resid != 0) { 1735 i--; 1736 total_ccb_xferlen -= resid; 1737 /* modify last sg length */ 1738 ccb->pkt_dmacookies[i].dmac_size = 1739 ccb->pkt_dmacookies[i].dmac_size - resid; 1740 ccb->resid_dmacookie.dmac_size = resid; 1741 ccb->resid_dmacookie.dmac_laddress = 1742 ccb->pkt_dmacookies[i].dmac_laddress + 1743 ccb->pkt_dmacookies[i].dmac_size; 1744 } 1745 } 1746 ccb->total_dmac_size += total_ccb_xferlen; 1747 pkt->pkt_resid = bp->b_bcount - ccb->total_dmac_size; 1748 1749 return (DDI_SUCCESS); 1750 } 1751 1752 1753 /*ARGSUSED*/ 1754 static void 1755 arcmsr_build_ccb(struct CCB *ccb) 1756 { 1757 struct scsi_pkt *pkt = ccb->pkt; 1758 struct ARCMSR_CDB *arcmsr_cdb; 1759 char *psge; 1760 uint32_t address_lo, address_hi; 1761 int arccdbsize = 0x30; 1762 uint8_t sgcount; 1763 1764 arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb; 1765 psge = (char *)&arcmsr_cdb->sgu; 1766 1767 bcopy((caddr_t)pkt->pkt_cdbp, arcmsr_cdb->Cdb, arcmsr_cdb->CdbLength); 1768 sgcount = ccb->arcmsr_cdb.sgcount; 1769 1770 if (sgcount != 0) { 1771 int length, i; 1772 int cdb_sgcount = 0; 1773 int total_xfer_length = 0; 1774 1775 /* map stor port SG list to our iop SG List. */ 1776 for (i = 0; i < sgcount; i++) { 1777 /* Get physaddr of the current data pointer */ 1778 length = ccb->pkt_dmacookies[i].dmac_size; 1779 total_xfer_length += length; 1780 address_lo = 1781 dma_addr_lo32(ccb->pkt_dmacookies[i].dmac_laddress); 1782 address_hi = 1783 dma_addr_hi32(ccb->pkt_dmacookies[i].dmac_laddress); 1784 1785 if (address_hi == 0) { 1786 struct SG32ENTRY *dma_sg; 1787 1788 dma_sg = (struct SG32ENTRY *)(intptr_t)psge; 1789 dma_sg->address = address_lo; 1790 dma_sg->length = length; 1791 psge += sizeof (struct SG32ENTRY); 1792 arccdbsize += sizeof (struct SG32ENTRY); 1793 } else { 1794 struct SG64ENTRY *dma_sg; 1795 1796 dma_sg = (struct SG64ENTRY *)(intptr_t)psge; 1797 dma_sg->addresshigh = address_hi; 1798 dma_sg->address = address_lo; 1799 dma_sg->length = length | IS_SG64_ADDR; 1800 psge += sizeof (struct SG64ENTRY); 1801 arccdbsize += sizeof (struct SG64ENTRY); 1802 } 1803 cdb_sgcount++; 1804 } 1805 arcmsr_cdb->sgcount = (uint8_t)cdb_sgcount; 1806 arcmsr_cdb->DataLength = total_xfer_length; 1807 if (arccdbsize > 256) { 1808 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE; 1809 } 1810 } else { 1811 arcmsr_cdb->DataLength = 0; 1812 } 1813 1814 if (ccb->ccb_flags & CCB_FLAG_DMAWRITE) 1815 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE; 1816 ccb->arc_cdb_size = arccdbsize; 1817 } 1818 1819 /* 1820 * arcmsr_post_ccb - Send a protocol specific ARC send postcard to a AIOC. 1821 * 1822 * handle: Handle of registered ARC protocol driver 1823 * adapter_id: AIOC unique identifier(integer) 1824 * pPOSTCARD_SEND: Pointer to ARC send postcard 1825 * 1826 * This routine posts a ARC send postcard to the request post FIFO of a 1827 * specific ARC adapter. 1828 */ 1829 static int 1830 arcmsr_post_ccb(struct ACB *acb, struct CCB *ccb) 1831 { 1832 uint32_t cdb_phyaddr_pattern = ccb->cdb_phyaddr_pattern; 1833 struct scsi_pkt *pkt = ccb->pkt; 1834 struct ARCMSR_CDB *arcmsr_cdb; 1835 uint_t pkt_flags = pkt->pkt_flags; 1836 1837 arcmsr_cdb = &ccb->arcmsr_cdb; 1838 1839 /* TODO: Use correct offset and size for syncing? */ 1840 if (ddi_dma_sync(acb->ccbs_pool_handle, 0, 0, DDI_DMA_SYNC_FORDEV) == 1841 DDI_FAILURE) 1842 return (DDI_FAILURE); 1843 1844 atomic_inc_32(&acb->ccboutstandingcount); 1845 ccb->ccb_time = (time_t)(ddi_get_time() + pkt->pkt_time); 1846 1847 ccb->ccb_state = ARCMSR_CCB_START; 1848 switch (acb->adapter_type) { 1849 case ACB_ADAPTER_TYPE_A: 1850 { 1851 struct HBA_msgUnit *phbamu; 1852 1853 phbamu = (struct HBA_msgUnit *)acb->pmu; 1854 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1855 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 1856 &phbamu->inbound_queueport, 1857 cdb_phyaddr_pattern | 1858 ARCMSR_CCBPOST_FLAG_SGL_BSIZE); 1859 } else { 1860 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 1861 &phbamu->inbound_queueport, cdb_phyaddr_pattern); 1862 } 1863 if (pkt_flags & FLAG_NOINTR) 1864 arcmsr_polling_hba_ccbdone(acb, ccb); 1865 break; 1866 } 1867 1868 case ACB_ADAPTER_TYPE_B: 1869 { 1870 struct HBB_msgUnit *phbbmu; 1871 int ending_index, index; 1872 1873 phbbmu = (struct HBB_msgUnit *)acb->pmu; 1874 index = phbbmu->postq_index; 1875 ending_index = ((index+1)%ARCMSR_MAX_HBB_POSTQUEUE); 1876 phbbmu->post_qbuffer[ending_index] = 0; 1877 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1878 phbbmu->post_qbuffer[index] = 1879 (cdb_phyaddr_pattern|ARCMSR_CCBPOST_FLAG_SGL_BSIZE); 1880 } else { 1881 phbbmu->post_qbuffer[index] = cdb_phyaddr_pattern; 1882 } 1883 index++; 1884 /* if last index number set it to 0 */ 1885 index %= ARCMSR_MAX_HBB_POSTQUEUE; 1886 phbbmu->postq_index = index; 1887 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 1888 &phbbmu->hbb_doorbell->drv2iop_doorbell, 1889 ARCMSR_DRV2IOP_CDB_POSTED); 1890 1891 if (pkt_flags & FLAG_NOINTR) 1892 arcmsr_polling_hbb_ccbdone(acb, ccb); 1893 break; 1894 } 1895 1896 case ACB_ADAPTER_TYPE_C: 1897 { 1898 struct HBC_msgUnit *phbcmu; 1899 uint32_t ccb_post_stamp, arc_cdb_size; 1900 1901 phbcmu = (struct HBC_msgUnit *)acb->pmu; 1902 arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : 1903 ccb->arc_cdb_size; 1904 ccb_post_stamp = (cdb_phyaddr_pattern | 1905 ((arc_cdb_size-1) >> 6) |1); 1906 if (acb->cdb_phyaddr_hi32) { 1907 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 1908 &phbcmu->inbound_queueport_high, 1909 acb->cdb_phyaddr_hi32); 1910 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 1911 &phbcmu->inbound_queueport_low, ccb_post_stamp); 1912 } else { 1913 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 1914 &phbcmu->inbound_queueport_low, ccb_post_stamp); 1915 } 1916 if (pkt_flags & FLAG_NOINTR) 1917 arcmsr_polling_hbc_ccbdone(acb, ccb); 1918 break; 1919 } 1920 1921 } 1922 return (DDI_SUCCESS); 1923 } 1924 1925 1926 static void 1927 arcmsr_ccb_complete(struct CCB *ccb, int flag) 1928 { 1929 struct ACB *acb = ccb->acb; 1930 struct scsi_pkt *pkt = ccb->pkt; 1931 1932 if (pkt == NULL) { 1933 return; 1934 } 1935 ccb->ccb_state |= ARCMSR_CCB_DONE; 1936 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | 1937 STATE_SENT_CMD | STATE_GOT_STATUS); 1938 1939 if ((ccb->ccb_flags & CCB_FLAG_DMACONSISTENT) && 1940 (pkt->pkt_state & STATE_XFERRED_DATA)) { 1941 (void) ddi_dma_sync(ccb->pkt_dma_handle, 0, 0, 1942 DDI_DMA_SYNC_FORCPU); 1943 } 1944 /* 1945 * TODO: This represents a potential race condition, and is 1946 * ultimately a poor design decision. Revisit this code 1947 * and solve the mutex ownership issue correctly. 1948 */ 1949 if (mutex_owned(&acb->isr_mutex)) { 1950 mutex_exit(&acb->isr_mutex); 1951 scsi_hba_pkt_comp(pkt); 1952 mutex_enter(&acb->isr_mutex); 1953 } else { 1954 scsi_hba_pkt_comp(pkt); 1955 } 1956 if (flag == 1) { 1957 atomic_dec_32(&acb->ccboutstandingcount); 1958 } 1959 } 1960 1961 static void 1962 arcmsr_report_ccb_state(struct ACB *acb, struct CCB *ccb, boolean_t error) 1963 { 1964 int id, lun; 1965 1966 ccb->ccb_state |= ARCMSR_CCB_DONE; 1967 id = ccb->pkt->pkt_address.a_target; 1968 lun = ccb->pkt->pkt_address.a_lun; 1969 1970 if (!error) { 1971 if (acb->devstate[id][lun] == ARECA_RAID_GONE) { 1972 acb->devstate[id][lun] = ARECA_RAID_GOOD; 1973 } 1974 ccb->pkt->pkt_reason = CMD_CMPLT; 1975 ccb->pkt->pkt_state |= STATE_XFERRED_DATA; 1976 arcmsr_list_add_tail(&acb->ccb_complete_list_mutex, 1977 &ccb->complete_queue_pointer, &acb->ccb_complete_list); 1978 1979 } else { 1980 switch (ccb->arcmsr_cdb.DeviceStatus) { 1981 case ARCMSR_DEV_SELECT_TIMEOUT: 1982 if (acb->devstate[id][lun] == ARECA_RAID_GOOD) { 1983 arcmsr_warn(acb, 1984 "target %d lun %d selection " 1985 "timeout", id, lun); 1986 } 1987 acb->devstate[id][lun] = ARECA_RAID_GONE; 1988 ccb->pkt->pkt_reason = CMD_TIMEOUT; /* CMD_DEV_GONE; */ 1989 ccb->pkt->pkt_statistics |= STAT_TIMEOUT; 1990 arcmsr_list_add_tail(&acb->ccb_complete_list_mutex, 1991 &ccb->complete_queue_pointer, 1992 &acb->ccb_complete_list); 1993 break; 1994 case ARCMSR_DEV_ABORTED: 1995 case ARCMSR_DEV_INIT_FAIL: 1996 arcmsr_warn(acb, "isr got 'ARCMSR_DEV_ABORTED'" 1997 " 'ARCMSR_DEV_INIT_FAIL'"); 1998 arcmsr_log(acb, CE_NOTE, "raid volume was kicked out"); 1999 acb->devstate[id][lun] = ARECA_RAID_GONE; 2000 ccb->pkt->pkt_reason = CMD_DEV_GONE; 2001 ccb->pkt->pkt_statistics |= STAT_TERMINATED; 2002 arcmsr_list_add_tail(&acb->ccb_complete_list_mutex, 2003 &ccb->complete_queue_pointer, 2004 &acb->ccb_complete_list); 2005 break; 2006 case SCSISTAT_CHECK_CONDITION: 2007 acb->devstate[id][lun] = ARECA_RAID_GOOD; 2008 arcmsr_report_sense_info(ccb); 2009 arcmsr_list_add_tail(&acb->ccb_complete_list_mutex, 2010 &ccb->complete_queue_pointer, 2011 &acb->ccb_complete_list); 2012 break; 2013 default: 2014 arcmsr_warn(acb, 2015 "target %d lun %d isr received CMD_DONE" 2016 " with unknown DeviceStatus (0x%x)", 2017 id, lun, ccb->arcmsr_cdb.DeviceStatus); 2018 arcmsr_log(acb, CE_NOTE, "raid volume was kicked out"); 2019 acb->devstate[id][lun] = ARECA_RAID_GONE; 2020 /* unknown error or crc error just for retry */ 2021 ccb->pkt->pkt_reason = CMD_TRAN_ERR; 2022 ccb->pkt->pkt_statistics |= STAT_TERMINATED; 2023 arcmsr_list_add_tail(&acb->ccb_complete_list_mutex, 2024 &ccb->complete_queue_pointer, 2025 &acb->ccb_complete_list); 2026 break; 2027 } 2028 } 2029 } 2030 2031 2032 static void 2033 arcmsr_drain_donequeue(struct ACB *acb, struct CCB *ccb, boolean_t error) 2034 { 2035 uint16_t ccb_state; 2036 2037 if (ccb->acb != acb) { 2038 return; 2039 } 2040 if (ccb->ccb_state != ARCMSR_CCB_START) { 2041 switch (ccb->ccb_state & ARCMSR_ABNORMAL_MASK) { 2042 case ARCMSR_CCB_TIMEOUT: 2043 ccb_state = ccb->ccb_state; 2044 if (ccb_state & ARCMSR_CCB_WAIT4_FREE) 2045 arcmsr_free_ccb(ccb); 2046 else 2047 ccb->ccb_state |= ARCMSR_CCB_BACK; 2048 return; 2049 2050 case ARCMSR_CCB_ABORTED: 2051 ccb_state = ccb->ccb_state; 2052 if (ccb_state & ARCMSR_CCB_WAIT4_FREE) 2053 arcmsr_free_ccb(ccb); 2054 else 2055 ccb->ccb_state |= ARCMSR_CCB_BACK; 2056 return; 2057 case ARCMSR_CCB_RESET: 2058 ccb_state = ccb->ccb_state; 2059 if (ccb_state & ARCMSR_CCB_WAIT4_FREE) 2060 arcmsr_free_ccb(ccb); 2061 else 2062 ccb->ccb_state |= ARCMSR_CCB_BACK; 2063 return; 2064 default: 2065 return; 2066 } 2067 } 2068 arcmsr_report_ccb_state(acb, ccb, error); 2069 } 2070 2071 static void 2072 arcmsr_report_sense_info(struct CCB *ccb) 2073 { 2074 struct SENSE_DATA *cdb_sensedata; 2075 struct scsi_pkt *pkt = ccb->pkt; 2076 struct scsi_arq_status *arq_status; 2077 union scsi_cdb *cdbp; 2078 uint64_t err_blkno; 2079 2080 cdbp = (void *)pkt->pkt_cdbp; 2081 err_blkno = ARCMSR_GETGXADDR(ccb->arcmsr_cdb.CdbLength, cdbp); 2082 2083 arq_status = (struct scsi_arq_status *)(intptr_t)(pkt->pkt_scbp); 2084 bzero((caddr_t)arq_status, sizeof (struct scsi_arq_status)); 2085 *pkt->pkt_scbp = STATUS_CHECK; /* CHECK CONDITION */ 2086 arq_status->sts_rqpkt_reason = CMD_CMPLT; 2087 arq_status->sts_rqpkt_state = (STATE_GOT_BUS | STATE_GOT_TARGET | 2088 STATE_SENT_CMD | STATE_XFERRED_DATA | STATE_GOT_STATUS); 2089 arq_status->sts_rqpkt_statistics = 0; 2090 arq_status->sts_rqpkt_resid = 0; 2091 2092 pkt->pkt_reason = CMD_CMPLT; 2093 /* auto rqsense took place */ 2094 pkt->pkt_state |= STATE_ARQ_DONE; 2095 2096 cdb_sensedata = (struct SENSE_DATA *)ccb->arcmsr_cdb.SenseData; 2097 if (&arq_status->sts_sensedata != NULL) { 2098 if (err_blkno <= 0xfffffffful) { 2099 struct scsi_extended_sense *sts_sensedata; 2100 2101 sts_sensedata = &arq_status->sts_sensedata; 2102 sts_sensedata->es_code = cdb_sensedata->ErrorCode; 2103 /* must eq CLASS_EXTENDED_SENSE (0x07) */ 2104 sts_sensedata->es_class = cdb_sensedata->ErrorClass; 2105 sts_sensedata->es_valid = cdb_sensedata->Valid; 2106 sts_sensedata->es_segnum = cdb_sensedata->SegmentNumber; 2107 sts_sensedata->es_key = cdb_sensedata->SenseKey; 2108 sts_sensedata->es_ili = cdb_sensedata->IncorrectLength; 2109 sts_sensedata->es_eom = cdb_sensedata->EndOfMedia; 2110 sts_sensedata->es_filmk = cdb_sensedata->FileMark; 2111 sts_sensedata->es_info_1 = (err_blkno >> 24) & 0xFF; 2112 sts_sensedata->es_info_2 = (err_blkno >> 16) & 0xFF; 2113 sts_sensedata->es_info_3 = (err_blkno >> 8) & 0xFF; 2114 sts_sensedata->es_info_4 = err_blkno & 0xFF; 2115 sts_sensedata->es_add_len = 2116 cdb_sensedata->AdditionalSenseLength; 2117 sts_sensedata->es_cmd_info[0] = 2118 cdb_sensedata->CommandSpecificInformation[0]; 2119 sts_sensedata->es_cmd_info[1] = 2120 cdb_sensedata->CommandSpecificInformation[1]; 2121 sts_sensedata->es_cmd_info[2] = 2122 cdb_sensedata->CommandSpecificInformation[2]; 2123 sts_sensedata->es_cmd_info[3] = 2124 cdb_sensedata->CommandSpecificInformation[3]; 2125 sts_sensedata->es_add_code = 2126 cdb_sensedata->AdditionalSenseCode; 2127 sts_sensedata->es_qual_code = 2128 cdb_sensedata->AdditionalSenseCodeQualifier; 2129 sts_sensedata->es_fru_code = 2130 cdb_sensedata->FieldReplaceableUnitCode; 2131 } else { /* 64-bit LBA */ 2132 struct scsi_descr_sense_hdr *dsp; 2133 struct scsi_information_sense_descr *isd; 2134 2135 dsp = (struct scsi_descr_sense_hdr *) 2136 &arq_status->sts_sensedata; 2137 dsp->ds_class = CLASS_EXTENDED_SENSE; 2138 dsp->ds_code = CODE_FMT_DESCR_CURRENT; 2139 dsp->ds_key = cdb_sensedata->SenseKey; 2140 dsp->ds_add_code = cdb_sensedata->AdditionalSenseCode; 2141 dsp->ds_qual_code = 2142 cdb_sensedata->AdditionalSenseCodeQualifier; 2143 dsp->ds_addl_sense_length = 2144 sizeof (struct scsi_information_sense_descr); 2145 2146 isd = (struct scsi_information_sense_descr *)(dsp+1); 2147 isd->isd_descr_type = DESCR_INFORMATION; 2148 isd->isd_valid = 1; 2149 isd->isd_information[0] = (err_blkno >> 56) & 0xFF; 2150 isd->isd_information[1] = (err_blkno >> 48) & 0xFF; 2151 isd->isd_information[2] = (err_blkno >> 40) & 0xFF; 2152 isd->isd_information[3] = (err_blkno >> 32) & 0xFF; 2153 isd->isd_information[4] = (err_blkno >> 24) & 0xFF; 2154 isd->isd_information[5] = (err_blkno >> 16) & 0xFF; 2155 isd->isd_information[6] = (err_blkno >> 8) & 0xFF; 2156 isd->isd_information[7] = (err_blkno) & 0xFF; 2157 } 2158 } 2159 } 2160 2161 2162 static int 2163 arcmsr_seek_cmd2abort(struct ACB *acb, struct scsi_pkt *abortpkt) 2164 { 2165 struct CCB *ccb; 2166 uint32_t intmask_org = 0; 2167 int i = 0; 2168 2169 acb->num_aborts++; 2170 2171 if (abortpkt != NULL) { 2172 /* 2173 * We don't support abort of a single packet. All 2174 * callers in our kernel always do a global abort, so 2175 * there is no point in having code to support it 2176 * here. 2177 */ 2178 return (DDI_FAILURE); 2179 } 2180 2181 /* 2182 * if abortpkt is NULL, the upper layer needs us 2183 * to abort all commands 2184 */ 2185 if (acb->ccboutstandingcount != 0) { 2186 /* disable all outbound interrupt */ 2187 intmask_org = arcmsr_disable_allintr(acb); 2188 /* clear and abort all outbound posted Q */ 2189 arcmsr_done4abort_postqueue(acb); 2190 /* talk to iop 331 outstanding command aborted */ 2191 (void) arcmsr_abort_host_command(acb); 2192 2193 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) { 2194 ccb = acb->pccb_pool[i]; 2195 if (ccb->ccb_state == ARCMSR_CCB_START) { 2196 /* 2197 * this ccb will complete at 2198 * hwinterrupt 2199 */ 2200 /* ccb->ccb_state = ARCMSR_CCB_ABORTED; */ 2201 ccb->pkt->pkt_reason = CMD_ABORTED; 2202 ccb->pkt->pkt_statistics |= STAT_ABORTED; 2203 arcmsr_ccb_complete(ccb, 1); 2204 } 2205 } 2206 /* 2207 * enable outbound Post Queue, outbound 2208 * doorbell Interrupt 2209 */ 2210 arcmsr_enable_allintr(acb, intmask_org); 2211 } 2212 return (DDI_SUCCESS); 2213 } 2214 2215 2216 /* 2217 * Autoconfiguration support 2218 */ 2219 static int 2220 arcmsr_parse_devname(char *devnm, int *tgt, int *lun) 2221 { 2222 char devbuf[SCSI_MAXNAMELEN]; 2223 char *addr; 2224 char *p, *tp, *lp; 2225 long num; 2226 2227 /* Parse dev name and address */ 2228 (void) strlcpy(devbuf, devnm, sizeof (devbuf)); 2229 addr = ""; 2230 for (p = devbuf; *p != '\0'; p++) { 2231 if (*p == '@') { 2232 addr = p + 1; 2233 *p = '\0'; 2234 } else if (*p == ':') { 2235 *p = '\0'; 2236 break; 2237 } 2238 } 2239 2240 /* Parse target and lun */ 2241 for (p = tp = addr, lp = NULL; *p != '\0'; p++) { 2242 if (*p == ',') { 2243 lp = p + 1; 2244 *p = '\0'; 2245 break; 2246 } 2247 } 2248 if ((tgt != NULL) && (tp != NULL)) { 2249 if (ddi_strtol(tp, NULL, 0x10, &num) != 0) 2250 return (-1); 2251 *tgt = (int)num; 2252 } 2253 if ((lun != NULL) && (lp != NULL)) { 2254 if (ddi_strtol(lp, NULL, 0x10, &num) != 0) 2255 return (-1); 2256 *lun = (int)num; 2257 } 2258 return (0); 2259 } 2260 2261 static int 2262 arcmsr_name_node(dev_info_t *dip, char *name, int len) 2263 { 2264 int tgt, lun; 2265 2266 tgt = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "target", 2267 -1); 2268 if (tgt == -1) 2269 return (DDI_FAILURE); 2270 lun = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "lun", 2271 -1); 2272 if (lun == -1) 2273 return (DDI_FAILURE); 2274 (void) snprintf(name, len, "%x,%x", tgt, lun); 2275 return (DDI_SUCCESS); 2276 } 2277 2278 static dev_info_t * 2279 arcmsr_find_child(struct ACB *acb, uint16_t tgt, uint8_t lun) 2280 { 2281 dev_info_t *child = NULL; 2282 char addr[SCSI_MAXNAMELEN]; 2283 char tmp[SCSI_MAXNAMELEN]; 2284 2285 (void) sprintf(addr, "%x,%x", tgt, lun); 2286 2287 for (child = ddi_get_child(acb->dev_info); 2288 child; 2289 child = ddi_get_next_sibling(child)) { 2290 /* We don't care about non-persistent node */ 2291 if (ndi_dev_is_persistent_node(child) == 0) 2292 continue; 2293 if (arcmsr_name_node(child, tmp, SCSI_MAXNAMELEN) != 2294 DDI_SUCCESS) 2295 continue; 2296 if (strcmp(addr, tmp) == 0) 2297 break; 2298 } 2299 return (child); 2300 } 2301 2302 static int 2303 arcmsr_config_child(struct ACB *acb, struct scsi_device *sd, dev_info_t **dipp) 2304 { 2305 char *nodename = NULL; 2306 char **compatible = NULL; 2307 int ncompatible = 0; 2308 dev_info_t *ldip = NULL; 2309 int tgt = sd->sd_address.a_target; 2310 int lun = sd->sd_address.a_lun; 2311 int dtype = sd->sd_inq->inq_dtype & DTYPE_MASK; 2312 int rval; 2313 2314 scsi_hba_nodename_compatible_get(sd->sd_inq, NULL, dtype, 2315 NULL, &nodename, &compatible, &ncompatible); 2316 if (nodename == NULL) { 2317 arcmsr_warn(acb, "found no comptible driver for T%dL%d", 2318 tgt, lun); 2319 rval = NDI_FAILURE; 2320 goto finish; 2321 } 2322 /* Create dev node */ 2323 rval = ndi_devi_alloc(acb->dev_info, nodename, DEVI_SID_NODEID, &ldip); 2324 if (rval == NDI_SUCCESS) { 2325 if (ndi_prop_update_int(DDI_DEV_T_NONE, ldip, "target", tgt) != 2326 DDI_PROP_SUCCESS) { 2327 arcmsr_warn(acb, 2328 "unable to create target property for T%dL%d", 2329 tgt, lun); 2330 rval = NDI_FAILURE; 2331 goto finish; 2332 } 2333 if (ndi_prop_update_int(DDI_DEV_T_NONE, ldip, "lun", lun) != 2334 DDI_PROP_SUCCESS) { 2335 arcmsr_warn(acb, 2336 "unable to create lun property for T%dL%d", 2337 tgt, lun); 2338 rval = NDI_FAILURE; 2339 goto finish; 2340 } 2341 if (ndi_prop_update_string_array(DDI_DEV_T_NONE, ldip, 2342 "compatible", compatible, ncompatible) != 2343 DDI_PROP_SUCCESS) { 2344 arcmsr_warn(acb, 2345 "unable to create compatible property for T%dL%d", 2346 tgt, lun); 2347 rval = NDI_FAILURE; 2348 goto finish; 2349 } 2350 rval = ndi_devi_online(ldip, NDI_ONLINE_ATTACH); 2351 if (rval != NDI_SUCCESS) { 2352 arcmsr_warn(acb, "unable to online T%dL%d", tgt, lun); 2353 ndi_prop_remove_all(ldip); 2354 (void) ndi_devi_free(ldip); 2355 } else { 2356 arcmsr_log(acb, CE_NOTE, "T%dL%d onlined", tgt, lun); 2357 } 2358 } 2359 finish: 2360 if (dipp) 2361 *dipp = ldip; 2362 2363 scsi_hba_nodename_compatible_free(nodename, compatible); 2364 return (rval); 2365 } 2366 2367 static int 2368 arcmsr_config_lun(struct ACB *acb, uint16_t tgt, uint8_t lun, dev_info_t **ldip) 2369 { 2370 struct scsi_device sd; 2371 dev_info_t *child; 2372 int rval; 2373 2374 if ((child = arcmsr_find_child(acb, tgt, lun)) != NULL) { 2375 if (ldip) { 2376 *ldip = child; 2377 } 2378 return (NDI_SUCCESS); 2379 } 2380 bzero(&sd, sizeof (struct scsi_device)); 2381 sd.sd_address.a_hba_tran = acb->scsi_hba_transport; 2382 sd.sd_address.a_target = tgt; 2383 sd.sd_address.a_lun = lun; 2384 2385 rval = scsi_hba_probe(&sd, NULL); 2386 if (rval == SCSIPROBE_EXISTS) 2387 rval = arcmsr_config_child(acb, &sd, ldip); 2388 scsi_unprobe(&sd); 2389 return (rval); 2390 } 2391 2392 2393 static int 2394 arcmsr_add_intr(struct ACB *acb, int intr_type) 2395 { 2396 int rc, count; 2397 dev_info_t *dev_info; 2398 const char *type_str; 2399 2400 switch (intr_type) { 2401 case DDI_INTR_TYPE_MSI: 2402 type_str = "MSI"; 2403 break; 2404 case DDI_INTR_TYPE_MSIX: 2405 type_str = "MSIX"; 2406 break; 2407 case DDI_INTR_TYPE_FIXED: 2408 type_str = "FIXED"; 2409 break; 2410 default: 2411 type_str = "unknown"; 2412 break; 2413 } 2414 2415 dev_info = acb->dev_info; 2416 /* Determine number of supported interrupts */ 2417 rc = ddi_intr_get_nintrs(dev_info, intr_type, &count); 2418 if ((rc != DDI_SUCCESS) || (count == 0)) { 2419 arcmsr_warn(acb, 2420 "no interrupts of type %s, rc=0x%x, count=%d", 2421 type_str, rc, count); 2422 return (DDI_FAILURE); 2423 } 2424 acb->intr_size = sizeof (ddi_intr_handle_t) * count; 2425 acb->phandle = kmem_zalloc(acb->intr_size, KM_SLEEP); 2426 rc = ddi_intr_alloc(dev_info, acb->phandle, intr_type, 0, 2427 count, &acb->intr_count, DDI_INTR_ALLOC_NORMAL); 2428 if ((rc != DDI_SUCCESS) || (acb->intr_count == 0)) { 2429 arcmsr_warn(acb, "ddi_intr_alloc(%s) failed 0x%x", 2430 type_str, rc); 2431 return (DDI_FAILURE); 2432 } 2433 if (acb->intr_count < count) { 2434 arcmsr_log(acb, CE_NOTE, "Got %d interrupts, but requested %d", 2435 acb->intr_count, count); 2436 } 2437 /* 2438 * Get priority for first msi, assume remaining are all the same 2439 */ 2440 if (ddi_intr_get_pri(acb->phandle[0], &acb->intr_pri) != DDI_SUCCESS) { 2441 arcmsr_warn(acb, "ddi_intr_get_pri failed"); 2442 return (DDI_FAILURE); 2443 } 2444 if (acb->intr_pri >= ddi_intr_get_hilevel_pri()) { 2445 arcmsr_warn(acb, "high level interrupt not supported"); 2446 return (DDI_FAILURE); 2447 } 2448 2449 for (int x = 0; x < acb->intr_count; x++) { 2450 if (ddi_intr_add_handler(acb->phandle[x], arcmsr_intr_handler, 2451 (caddr_t)acb, NULL) != DDI_SUCCESS) { 2452 arcmsr_warn(acb, "ddi_intr_add_handler(%s) failed", 2453 type_str); 2454 return (DDI_FAILURE); 2455 } 2456 } 2457 (void) ddi_intr_get_cap(acb->phandle[0], &acb->intr_cap); 2458 if (acb->intr_cap & DDI_INTR_FLAG_BLOCK) { 2459 /* Call ddi_intr_block_enable() for MSI */ 2460 (void) ddi_intr_block_enable(acb->phandle, acb->intr_count); 2461 } else { 2462 /* Call ddi_intr_enable() for MSI non block enable */ 2463 for (int x = 0; x < acb->intr_count; x++) { 2464 (void) ddi_intr_enable(acb->phandle[x]); 2465 } 2466 } 2467 return (DDI_SUCCESS); 2468 } 2469 2470 static void 2471 arcmsr_remove_intr(struct ACB *acb) 2472 { 2473 int x; 2474 2475 if (acb->phandle == NULL) 2476 return; 2477 2478 /* Disable all interrupts */ 2479 if (acb->intr_cap & DDI_INTR_FLAG_BLOCK) { 2480 /* Call ddi_intr_block_disable() */ 2481 (void) ddi_intr_block_disable(acb->phandle, acb->intr_count); 2482 } else { 2483 for (x = 0; x < acb->intr_count; x++) { 2484 (void) ddi_intr_disable(acb->phandle[x]); 2485 } 2486 } 2487 /* Call ddi_intr_remove_handler() */ 2488 for (x = 0; x < acb->intr_count; x++) { 2489 (void) ddi_intr_remove_handler(acb->phandle[x]); 2490 (void) ddi_intr_free(acb->phandle[x]); 2491 } 2492 kmem_free(acb->phandle, acb->intr_size); 2493 acb->phandle = NULL; 2494 } 2495 2496 static void 2497 arcmsr_mutex_init(struct ACB *acb) 2498 { 2499 mutex_init(&acb->isr_mutex, NULL, MUTEX_DRIVER, NULL); 2500 mutex_init(&acb->acb_mutex, NULL, MUTEX_DRIVER, NULL); 2501 mutex_init(&acb->postq_mutex, NULL, MUTEX_DRIVER, NULL); 2502 mutex_init(&acb->workingQ_mutex, NULL, MUTEX_DRIVER, NULL); 2503 mutex_init(&acb->ioctl_mutex, NULL, MUTEX_DRIVER, NULL); 2504 } 2505 2506 static void 2507 arcmsr_mutex_destroy(struct ACB *acb) 2508 { 2509 mutex_destroy(&acb->isr_mutex); 2510 mutex_destroy(&acb->acb_mutex); 2511 mutex_destroy(&acb->postq_mutex); 2512 mutex_destroy(&acb->workingQ_mutex); 2513 mutex_destroy(&acb->ioctl_mutex); 2514 } 2515 2516 static int 2517 arcmsr_initialize(struct ACB *acb) 2518 { 2519 struct CCB *pccb_tmp; 2520 size_t allocated_length; 2521 uint16_t wval; 2522 uint_t intmask_org, count; 2523 caddr_t arcmsr_ccbs_area; 2524 uint32_t wlval, cdb_phyaddr, offset, realccb_size; 2525 int32_t dma_sync_size; 2526 int i, id, lun, instance; 2527 2528 instance = ddi_get_instance(acb->dev_info); 2529 wlval = pci_config_get32(acb->pci_acc_handle, 0); 2530 wval = (uint16_t)((wlval >> 16) & 0xffff); 2531 realccb_size = P2ROUNDUP(sizeof (struct CCB), 32); 2532 switch (wval) { 2533 case PCI_DEVICE_ID_ARECA_1880: 2534 case PCI_DEVICE_ID_ARECA_1882: 2535 { 2536 uint32_t *iop_mu_regs_map0; 2537 2538 acb->adapter_type = ACB_ADAPTER_TYPE_C; /* lsi */ 2539 dma_sync_size = ARCMSR_MAX_FREECCB_NUM * realccb_size + 0x20; 2540 if (ddi_regs_map_setup(acb->dev_info, 2, 2541 (caddr_t *)&iop_mu_regs_map0, 0, 2542 sizeof (struct HBC_msgUnit), &acb->dev_acc_attr, 2543 &acb->reg_mu_acc_handle0) != DDI_SUCCESS) { 2544 arcmsr_warn(acb, "unable to map registers"); 2545 return (DDI_FAILURE); 2546 } 2547 2548 if ((i = ddi_dma_alloc_handle(acb->dev_info, &arcmsr_ccb_attr, 2549 DDI_DMA_SLEEP, NULL, &acb->ccbs_pool_handle)) != 2550 DDI_SUCCESS) { 2551 ddi_regs_map_free(&acb->reg_mu_acc_handle0); 2552 arcmsr_warn(acb, "ddi_dma_alloc_handle failed"); 2553 return (DDI_FAILURE); 2554 } 2555 2556 if (ddi_dma_mem_alloc(acb->ccbs_pool_handle, dma_sync_size, 2557 &acb->dev_acc_attr, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 2558 DDI_DMA_SLEEP, NULL, (caddr_t *)&arcmsr_ccbs_area, 2559 &allocated_length, &acb->ccbs_acc_handle) != DDI_SUCCESS) { 2560 arcmsr_warn(acb, "ddi_dma_mem_alloc failed"); 2561 ddi_dma_free_handle(&acb->ccbs_pool_handle); 2562 ddi_regs_map_free(&acb->reg_mu_acc_handle0); 2563 return (DDI_FAILURE); 2564 } 2565 2566 if (ddi_dma_addr_bind_handle(acb->ccbs_pool_handle, NULL, 2567 (caddr_t)arcmsr_ccbs_area, dma_sync_size, DDI_DMA_RDWR | 2568 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &acb->ccb_cookie, 2569 &count) != DDI_DMA_MAPPED) { 2570 arcmsr_warn(acb, "ddi_dma_addr_bind_handle failed"); 2571 ddi_dma_mem_free(&acb->ccbs_acc_handle); 2572 ddi_dma_free_handle(&acb->ccbs_pool_handle); 2573 ddi_regs_map_free(&acb->reg_mu_acc_handle0); 2574 return (DDI_FAILURE); 2575 } 2576 bzero(arcmsr_ccbs_area, dma_sync_size); 2577 offset = (uint32_t)(P2ROUNDUP(PtrToNum(arcmsr_ccbs_area), 32) 2578 - PtrToNum(arcmsr_ccbs_area)); 2579 arcmsr_ccbs_area = arcmsr_ccbs_area + offset; 2580 /* ioport base */ 2581 acb->pmu = (struct msgUnit *)(intptr_t)iop_mu_regs_map0; 2582 break; 2583 } 2584 2585 case PCI_DEVICE_ID_ARECA_1201: 2586 { 2587 uint32_t *iop_mu_regs_map0; 2588 uint32_t *iop_mu_regs_map1; 2589 struct HBB_msgUnit *phbbmu; 2590 2591 acb->adapter_type = ACB_ADAPTER_TYPE_B; /* marvell */ 2592 dma_sync_size = 2593 (ARCMSR_MAX_FREECCB_NUM * realccb_size + 0x20) + 2594 sizeof (struct HBB_msgUnit); 2595 /* Allocate memory for the ccb */ 2596 if ((i = ddi_dma_alloc_handle(acb->dev_info, &arcmsr_ccb_attr, 2597 DDI_DMA_SLEEP, NULL, &acb->ccbs_pool_handle)) != 2598 DDI_SUCCESS) { 2599 arcmsr_warn(acb, "ddi_dma_alloc_handle failed"); 2600 return (DDI_FAILURE); 2601 } 2602 2603 if (ddi_dma_mem_alloc(acb->ccbs_pool_handle, dma_sync_size, 2604 &acb->dev_acc_attr, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 2605 DDI_DMA_SLEEP, NULL, (caddr_t *)&arcmsr_ccbs_area, 2606 &allocated_length, &acb->ccbs_acc_handle) != DDI_SUCCESS) { 2607 arcmsr_warn(acb, "ddi_dma_mem_alloc failed"); 2608 ddi_dma_free_handle(&acb->ccbs_pool_handle); 2609 return (DDI_FAILURE); 2610 } 2611 2612 if (ddi_dma_addr_bind_handle(acb->ccbs_pool_handle, NULL, 2613 (caddr_t)arcmsr_ccbs_area, dma_sync_size, 2614 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 2615 NULL, &acb->ccb_cookie, &count) != DDI_DMA_MAPPED) { 2616 arcmsr_warn(acb, "ddi_dma_addr_bind_handle failed"); 2617 ddi_dma_mem_free(&acb->ccbs_acc_handle); 2618 ddi_dma_free_handle(&acb->ccbs_pool_handle); 2619 return (DDI_FAILURE); 2620 } 2621 bzero(arcmsr_ccbs_area, dma_sync_size); 2622 offset = (uint32_t)(P2ROUNDUP(PtrToNum(arcmsr_ccbs_area), 32) 2623 - PtrToNum(arcmsr_ccbs_area)); 2624 arcmsr_ccbs_area = arcmsr_ccbs_area + offset; 2625 acb->pmu = (struct msgUnit *) 2626 NumToPtr(PtrToNum(arcmsr_ccbs_area) + 2627 (realccb_size*ARCMSR_MAX_FREECCB_NUM)); 2628 phbbmu = (struct HBB_msgUnit *)acb->pmu; 2629 2630 /* setup device register */ 2631 if (ddi_regs_map_setup(acb->dev_info, 1, 2632 (caddr_t *)&iop_mu_regs_map0, 0, 2633 sizeof (struct HBB_DOORBELL), &acb->dev_acc_attr, 2634 &acb->reg_mu_acc_handle0) != DDI_SUCCESS) { 2635 arcmsr_warn(acb, "unable to map base0 registers"); 2636 (void) ddi_dma_unbind_handle(acb->ccbs_pool_handle); 2637 ddi_dma_mem_free(&acb->ccbs_acc_handle); 2638 ddi_dma_free_handle(&acb->ccbs_pool_handle); 2639 return (DDI_FAILURE); 2640 } 2641 2642 /* ARCMSR_DRV2IOP_DOORBELL */ 2643 phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)iop_mu_regs_map0; 2644 if (ddi_regs_map_setup(acb->dev_info, 2, 2645 (caddr_t *)&iop_mu_regs_map1, 0, 2646 sizeof (struct HBB_RWBUFFER), &acb->dev_acc_attr, 2647 &acb->reg_mu_acc_handle1) != DDI_SUCCESS) { 2648 arcmsr_warn(acb, "unable to map base1 registers"); 2649 ddi_regs_map_free(&acb->reg_mu_acc_handle0); 2650 (void) ddi_dma_unbind_handle(acb->ccbs_pool_handle); 2651 ddi_dma_mem_free(&acb->ccbs_acc_handle); 2652 ddi_dma_free_handle(&acb->ccbs_pool_handle); 2653 return (DDI_FAILURE); 2654 } 2655 2656 /* ARCMSR_MSGCODE_RWBUFFER */ 2657 phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)iop_mu_regs_map1; 2658 break; 2659 } 2660 2661 case PCI_DEVICE_ID_ARECA_1110: 2662 case PCI_DEVICE_ID_ARECA_1120: 2663 case PCI_DEVICE_ID_ARECA_1130: 2664 case PCI_DEVICE_ID_ARECA_1160: 2665 case PCI_DEVICE_ID_ARECA_1170: 2666 case PCI_DEVICE_ID_ARECA_1210: 2667 case PCI_DEVICE_ID_ARECA_1220: 2668 case PCI_DEVICE_ID_ARECA_1230: 2669 case PCI_DEVICE_ID_ARECA_1231: 2670 case PCI_DEVICE_ID_ARECA_1260: 2671 case PCI_DEVICE_ID_ARECA_1261: 2672 case PCI_DEVICE_ID_ARECA_1270: 2673 case PCI_DEVICE_ID_ARECA_1280: 2674 case PCI_DEVICE_ID_ARECA_1212: 2675 case PCI_DEVICE_ID_ARECA_1222: 2676 case PCI_DEVICE_ID_ARECA_1380: 2677 case PCI_DEVICE_ID_ARECA_1381: 2678 case PCI_DEVICE_ID_ARECA_1680: 2679 case PCI_DEVICE_ID_ARECA_1681: 2680 { 2681 uint32_t *iop_mu_regs_map0; 2682 2683 acb->adapter_type = ACB_ADAPTER_TYPE_A; /* intel */ 2684 dma_sync_size = ARCMSR_MAX_FREECCB_NUM * realccb_size + 0x20; 2685 if (ddi_regs_map_setup(acb->dev_info, 1, 2686 (caddr_t *)&iop_mu_regs_map0, 0, 2687 sizeof (struct HBA_msgUnit), &acb->dev_acc_attr, 2688 &acb->reg_mu_acc_handle0) != DDI_SUCCESS) { 2689 arcmsr_warn(acb, "unable to map registers"); 2690 return (DDI_FAILURE); 2691 } 2692 2693 if ((i = ddi_dma_alloc_handle(acb->dev_info, &arcmsr_ccb_attr, 2694 DDI_DMA_SLEEP, NULL, &acb->ccbs_pool_handle)) != 2695 DDI_SUCCESS) { 2696 arcmsr_warn(acb, "ddi_dma_alloc_handle failed"); 2697 ddi_regs_map_free(&acb->reg_mu_acc_handle0); 2698 return (DDI_FAILURE); 2699 } 2700 2701 if (ddi_dma_mem_alloc(acb->ccbs_pool_handle, dma_sync_size, 2702 &acb->dev_acc_attr, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 2703 DDI_DMA_SLEEP, NULL, (caddr_t *)&arcmsr_ccbs_area, 2704 &allocated_length, &acb->ccbs_acc_handle) != DDI_SUCCESS) { 2705 arcmsr_warn(acb, "ddi_dma_mem_alloc failed", instance); 2706 ddi_dma_free_handle(&acb->ccbs_pool_handle); 2707 ddi_regs_map_free(&acb->reg_mu_acc_handle0); 2708 return (DDI_FAILURE); 2709 } 2710 2711 if (ddi_dma_addr_bind_handle(acb->ccbs_pool_handle, NULL, 2712 (caddr_t)arcmsr_ccbs_area, dma_sync_size, DDI_DMA_RDWR | 2713 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &acb->ccb_cookie, 2714 &count) != DDI_DMA_MAPPED) { 2715 arcmsr_warn(acb, "ddi_dma_addr_bind_handle failed"); 2716 ddi_dma_mem_free(&acb->ccbs_acc_handle); 2717 ddi_dma_free_handle(&acb->ccbs_pool_handle); 2718 ddi_regs_map_free(&acb->reg_mu_acc_handle0); 2719 return (DDI_FAILURE); 2720 } 2721 bzero(arcmsr_ccbs_area, dma_sync_size); 2722 offset = (uint32_t)(P2ROUNDUP(PtrToNum(arcmsr_ccbs_area), 32) 2723 - PtrToNum(arcmsr_ccbs_area)); 2724 arcmsr_ccbs_area = arcmsr_ccbs_area + offset; 2725 /* ioport base */ 2726 acb->pmu = (struct msgUnit *)(intptr_t)iop_mu_regs_map0; 2727 break; 2728 } 2729 2730 default: 2731 arcmsr_warn(acb, "Unknown RAID adapter type!"); 2732 return (DDI_FAILURE); 2733 } 2734 arcmsr_init_list_head(&acb->ccb_complete_list); 2735 /* here we can not access pci configuration again */ 2736 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2737 ACB_F_MESSAGE_RQBUFFER_CLEARED | ACB_F_MESSAGE_WQBUFFER_READ); 2738 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER; 2739 /* physical address of acb->pccb_pool */ 2740 cdb_phyaddr = acb->ccb_cookie.dmac_address + offset; 2741 2742 pccb_tmp = (struct CCB *)(intptr_t)arcmsr_ccbs_area; 2743 2744 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) { 2745 pccb_tmp->cdb_phyaddr_pattern = 2746 (acb->adapter_type == ACB_ADAPTER_TYPE_C) ? 2747 cdb_phyaddr : (cdb_phyaddr >> 5); 2748 pccb_tmp->acb = acb; 2749 acb->ccbworkingQ[i] = acb->pccb_pool[i] = pccb_tmp; 2750 cdb_phyaddr = cdb_phyaddr + realccb_size; 2751 pccb_tmp = (struct CCB *)NumToPtr(PtrToNum(pccb_tmp) + 2752 realccb_size); 2753 } 2754 acb->vir2phy_offset = PtrToNum(pccb_tmp) - cdb_phyaddr; 2755 2756 /* disable all outbound interrupt */ 2757 intmask_org = arcmsr_disable_allintr(acb); 2758 2759 if (!arcmsr_iop_confirm(acb)) { 2760 arcmsr_warn(acb, "arcmsr_iop_confirm error", instance); 2761 ddi_dma_mem_free(&acb->ccbs_acc_handle); 2762 ddi_dma_free_handle(&acb->ccbs_pool_handle); 2763 return (DDI_FAILURE); 2764 } 2765 2766 for (id = 0; id < ARCMSR_MAX_TARGETID; id++) { 2767 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) { 2768 acb->devstate[id][lun] = ARECA_RAID_GONE; 2769 } 2770 } 2771 2772 /* enable outbound Post Queue, outbound doorbell Interrupt */ 2773 arcmsr_enable_allintr(acb, intmask_org); 2774 2775 return (0); 2776 } 2777 2778 static int 2779 arcmsr_do_ddi_attach(dev_info_t *dev_info, int instance) 2780 { 2781 scsi_hba_tran_t *hba_trans; 2782 ddi_device_acc_attr_t dev_acc_attr; 2783 struct ACB *acb; 2784 uint16_t wval; 2785 int raid6 = 1; 2786 char *type; 2787 int intr_types; 2788 2789 2790 /* 2791 * Soft State Structure 2792 * The driver should allocate the per-device-instance 2793 * soft state structure, being careful to clean up properly if 2794 * an error occurs. Allocate data structure. 2795 */ 2796 if (ddi_soft_state_zalloc(arcmsr_soft_state, instance) != DDI_SUCCESS) { 2797 arcmsr_warn(NULL, "ddi_soft_state_zalloc failed"); 2798 return (DDI_FAILURE); 2799 } 2800 2801 acb = ddi_get_soft_state(arcmsr_soft_state, instance); 2802 ASSERT(acb); 2803 2804 arcmsr_mutex_init(acb); 2805 2806 /* acb is already zalloc()d so we don't need to bzero() it */ 2807 dev_acc_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 2808 dev_acc_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 2809 dev_acc_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 2810 2811 acb->dev_info = dev_info; 2812 acb->dev_acc_attr = dev_acc_attr; 2813 2814 /* 2815 * The driver, if providing DMA, should also check that its hardware is 2816 * installed in a DMA-capable slot 2817 */ 2818 if (ddi_slaveonly(dev_info) == DDI_SUCCESS) { 2819 arcmsr_warn(acb, "hardware is not installed in" 2820 " a DMA-capable slot"); 2821 goto error_level_0; 2822 } 2823 if (pci_config_setup(dev_info, &acb->pci_acc_handle) != DDI_SUCCESS) { 2824 arcmsr_warn(acb, "pci_config_setup() failed, attach failed"); 2825 goto error_level_0; 2826 } 2827 2828 wval = pci_config_get16(acb->pci_acc_handle, PCI_CONF_VENID); 2829 if (wval != PCI_VENDOR_ID_ARECA) { 2830 arcmsr_warn(acb, 2831 "'vendorid (0x%04x) does not match 0x%04x " 2832 "(PCI_VENDOR_ID_ARECA)", 2833 wval, PCI_VENDOR_ID_ARECA); 2834 goto error_level_0; 2835 } 2836 2837 wval = pci_config_get16(acb->pci_acc_handle, PCI_CONF_DEVID); 2838 switch (wval) { 2839 case PCI_DEVICE_ID_ARECA_1110: 2840 case PCI_DEVICE_ID_ARECA_1210: 2841 case PCI_DEVICE_ID_ARECA_1201: 2842 raid6 = 0; 2843 /*FALLTHRU*/ 2844 case PCI_DEVICE_ID_ARECA_1120: 2845 case PCI_DEVICE_ID_ARECA_1130: 2846 case PCI_DEVICE_ID_ARECA_1160: 2847 case PCI_DEVICE_ID_ARECA_1170: 2848 case PCI_DEVICE_ID_ARECA_1220: 2849 case PCI_DEVICE_ID_ARECA_1230: 2850 case PCI_DEVICE_ID_ARECA_1260: 2851 case PCI_DEVICE_ID_ARECA_1270: 2852 case PCI_DEVICE_ID_ARECA_1280: 2853 type = "SATA 3G"; 2854 break; 2855 case PCI_DEVICE_ID_ARECA_1380: 2856 case PCI_DEVICE_ID_ARECA_1381: 2857 case PCI_DEVICE_ID_ARECA_1680: 2858 case PCI_DEVICE_ID_ARECA_1681: 2859 type = "SAS 3G"; 2860 break; 2861 case PCI_DEVICE_ID_ARECA_1880: 2862 type = "SAS 6G"; 2863 break; 2864 default: 2865 type = "X-TYPE"; 2866 arcmsr_warn(acb, "Unknown Host Adapter RAID Controller!"); 2867 goto error_level_0; 2868 } 2869 2870 arcmsr_log(acb, CE_CONT, "Areca %s Host Adapter RAID Controller%s\n", 2871 type, raid6 ? " (RAID6 capable)" : ""); 2872 2873 /* we disable iop interrupt here */ 2874 if (arcmsr_initialize(acb) == DDI_FAILURE) { 2875 arcmsr_warn(acb, "arcmsr_initialize failed"); 2876 goto error_level_1; 2877 } 2878 2879 /* Allocate a transport structure */ 2880 hba_trans = scsi_hba_tran_alloc(dev_info, SCSI_HBA_CANSLEEP); 2881 if (hba_trans == NULL) { 2882 arcmsr_warn(acb, "scsi_hba_tran_alloc failed"); 2883 goto error_level_2; 2884 } 2885 acb->scsi_hba_transport = hba_trans; 2886 acb->dev_info = dev_info; 2887 /* init scsi host adapter transport entry */ 2888 hba_trans->tran_hba_private = acb; 2889 hba_trans->tran_tgt_private = NULL; 2890 /* 2891 * If no per-target initialization is required, the HBA can leave 2892 * tran_tgt_init set to NULL. 2893 */ 2894 hba_trans->tran_tgt_init = arcmsr_tran_tgt_init; 2895 hba_trans->tran_tgt_probe = scsi_hba_probe; 2896 hba_trans->tran_tgt_free = NULL; 2897 hba_trans->tran_start = arcmsr_tran_start; 2898 hba_trans->tran_abort = arcmsr_tran_abort; 2899 hba_trans->tran_reset = arcmsr_tran_reset; 2900 hba_trans->tran_getcap = arcmsr_tran_getcap; 2901 hba_trans->tran_setcap = arcmsr_tran_setcap; 2902 hba_trans->tran_init_pkt = arcmsr_tran_init_pkt; 2903 hba_trans->tran_destroy_pkt = arcmsr_tran_destroy_pkt; 2904 hba_trans->tran_dmafree = arcmsr_tran_dmafree; 2905 hba_trans->tran_sync_pkt = arcmsr_tran_sync_pkt; 2906 2907 hba_trans->tran_reset_notify = NULL; 2908 hba_trans->tran_get_bus_addr = NULL; 2909 hba_trans->tran_get_name = NULL; 2910 hba_trans->tran_quiesce = NULL; 2911 hba_trans->tran_unquiesce = NULL; 2912 hba_trans->tran_bus_reset = NULL; 2913 hba_trans->tran_bus_config = arcmsr_tran_bus_config; 2914 hba_trans->tran_add_eventcall = NULL; 2915 hba_trans->tran_get_eventcookie = NULL; 2916 hba_trans->tran_post_event = NULL; 2917 hba_trans->tran_remove_eventcall = NULL; 2918 2919 /* iop init and enable interrupt here */ 2920 arcmsr_iop_init(acb); 2921 2922 /* Get supported interrupt types */ 2923 if (ddi_intr_get_supported_types(dev_info, &intr_types) != 2924 DDI_SUCCESS) { 2925 arcmsr_warn(acb, "ddi_intr_get_supported_types failed"); 2926 goto error_level_3; 2927 } 2928 if (intr_types & DDI_INTR_TYPE_FIXED) { 2929 if (arcmsr_add_intr(acb, DDI_INTR_TYPE_FIXED) != DDI_SUCCESS) 2930 goto error_level_5; 2931 } else if (intr_types & DDI_INTR_TYPE_MSI) { 2932 if (arcmsr_add_intr(acb, DDI_INTR_TYPE_FIXED) != DDI_SUCCESS) 2933 goto error_level_5; 2934 } 2935 2936 /* 2937 * The driver should attach this instance of the device, and 2938 * perform error cleanup if necessary 2939 */ 2940 if (scsi_hba_attach_setup(dev_info, &arcmsr_dma_attr, 2941 hba_trans, SCSI_HBA_TRAN_CLONE) != DDI_SUCCESS) { 2942 arcmsr_warn(acb, "scsi_hba_attach_setup failed"); 2943 goto error_level_5; 2944 } 2945 2946 /* Create a taskq for dealing with dr events */ 2947 if ((acb->taskq = ddi_taskq_create(dev_info, "arcmsr_dr_taskq", 1, 2948 TASKQ_DEFAULTPRI, 0)) == NULL) { 2949 arcmsr_warn(acb, "ddi_taskq_create failed"); 2950 goto error_level_8; 2951 } 2952 2953 acb->timeout_count = 0; 2954 /* active ccbs "timeout" watchdog */ 2955 acb->timeout_id = timeout(arcmsr_ccbs_timeout, (caddr_t)acb, 2956 (ARCMSR_TIMEOUT_WATCH * drv_usectohz(1000000))); 2957 acb->timeout_sc_id = timeout(arcmsr_devMap_monitor, (caddr_t)acb, 2958 (ARCMSR_DEV_MAP_WATCH * drv_usectohz(1000000))); 2959 2960 /* report device info */ 2961 ddi_report_dev(dev_info); 2962 2963 return (DDI_SUCCESS); 2964 2965 error_level_8: 2966 2967 error_level_7: 2968 error_level_6: 2969 (void) scsi_hba_detach(dev_info); 2970 2971 error_level_5: 2972 arcmsr_remove_intr(acb); 2973 2974 error_level_3: 2975 error_level_4: 2976 if (acb->scsi_hba_transport) 2977 scsi_hba_tran_free(acb->scsi_hba_transport); 2978 2979 error_level_2: 2980 if (acb->ccbs_acc_handle) 2981 ddi_dma_mem_free(&acb->ccbs_acc_handle); 2982 if (acb->ccbs_pool_handle) 2983 ddi_dma_free_handle(&acb->ccbs_pool_handle); 2984 2985 error_level_1: 2986 if (acb->pci_acc_handle) 2987 pci_config_teardown(&acb->pci_acc_handle); 2988 arcmsr_mutex_destroy(acb); 2989 ddi_soft_state_free(arcmsr_soft_state, instance); 2990 2991 error_level_0: 2992 return (DDI_FAILURE); 2993 } 2994 2995 2996 static void 2997 arcmsr_vlog(struct ACB *acb, int level, char *fmt, va_list ap) 2998 { 2999 char buf[256]; 3000 3001 if (acb != NULL) { 3002 (void) snprintf(buf, sizeof (buf), "%s%d: %s", 3003 ddi_driver_name(acb->dev_info), 3004 ddi_get_instance(acb->dev_info), fmt); 3005 fmt = buf; 3006 } 3007 vcmn_err(level, fmt, ap); 3008 } 3009 3010 static void 3011 arcmsr_log(struct ACB *acb, int level, char *fmt, ...) 3012 { 3013 va_list ap; 3014 3015 va_start(ap, fmt); 3016 arcmsr_vlog(acb, level, fmt, ap); 3017 va_end(ap); 3018 } 3019 3020 static void 3021 arcmsr_warn(struct ACB *acb, char *fmt, ...) 3022 { 3023 va_list ap; 3024 3025 va_start(ap, fmt); 3026 arcmsr_vlog(acb, CE_WARN, fmt, ap); 3027 va_end(ap); 3028 } 3029 3030 static void 3031 arcmsr_init_list_head(struct list_head *list) 3032 { 3033 list->next = list; 3034 list->prev = list; 3035 } 3036 3037 static void 3038 arcmsr_x_list_del(struct list_head *prev, struct list_head *next) 3039 { 3040 next->prev = prev; 3041 prev->next = next; 3042 } 3043 3044 static void 3045 arcmsr_x_list_add(struct list_head *new_one, struct list_head *prev, 3046 struct list_head *next) 3047 { 3048 next->prev = new_one; 3049 new_one->next = next; 3050 new_one->prev = prev; 3051 prev->next = new_one; 3052 } 3053 3054 static void 3055 arcmsr_list_add_tail(kmutex_t *list_lock, struct list_head *new_one, 3056 struct list_head *head) 3057 { 3058 mutex_enter(list_lock); 3059 arcmsr_x_list_add(new_one, head->prev, head); 3060 mutex_exit(list_lock); 3061 } 3062 3063 static struct list_head * 3064 arcmsr_list_get_first(kmutex_t *list_lock, struct list_head *head) 3065 { 3066 struct list_head *one = NULL; 3067 3068 mutex_enter(list_lock); 3069 if (head->next == head) { 3070 mutex_exit(list_lock); 3071 return (NULL); 3072 } 3073 one = head->next; 3074 arcmsr_x_list_del(one->prev, one->next); 3075 arcmsr_init_list_head(one); 3076 mutex_exit(list_lock); 3077 return (one); 3078 } 3079 3080 static struct CCB * 3081 arcmsr_get_complete_ccb_from_list(struct ACB *acb) 3082 { 3083 struct list_head *first_complete_ccb_list = NULL; 3084 struct CCB *ccb; 3085 3086 first_complete_ccb_list = 3087 arcmsr_list_get_first(&acb->ccb_complete_list_mutex, 3088 &acb->ccb_complete_list); 3089 if (first_complete_ccb_list == NULL) { 3090 return (NULL); 3091 } 3092 ccb = (void *)((caddr_t)(first_complete_ccb_list) - 3093 offsetof(struct CCB, complete_queue_pointer)); 3094 return (ccb); 3095 } 3096 3097 static struct CCB * 3098 arcmsr_get_freeccb(struct ACB *acb) 3099 { 3100 struct CCB *ccb; 3101 int ccb_get_index, ccb_put_index; 3102 3103 mutex_enter(&acb->workingQ_mutex); 3104 ccb_put_index = acb->ccb_put_index; 3105 ccb_get_index = acb->ccb_get_index; 3106 ccb = acb->ccbworkingQ[ccb_get_index]; 3107 ccb_get_index++; 3108 if (ccb_get_index >= ARCMSR_MAX_FREECCB_NUM) 3109 ccb_get_index = ccb_get_index - ARCMSR_MAX_FREECCB_NUM; 3110 if (ccb_put_index != ccb_get_index) { 3111 acb->ccb_get_index = ccb_get_index; 3112 arcmsr_init_list_head(&ccb->complete_queue_pointer); 3113 ccb->ccb_state = ARCMSR_CCB_UNBUILD; 3114 } else { 3115 ccb = NULL; 3116 } 3117 mutex_exit(&acb->workingQ_mutex); 3118 return (ccb); 3119 } 3120 3121 3122 static void 3123 arcmsr_free_ccb(struct CCB *ccb) 3124 { 3125 struct ACB *acb = ccb->acb; 3126 3127 if (ccb->ccb_state == ARCMSR_CCB_FREE) { 3128 return; 3129 } 3130 mutex_enter(&acb->workingQ_mutex); 3131 ccb->ccb_state = ARCMSR_CCB_FREE; 3132 ccb->pkt = NULL; 3133 ccb->pkt_dma_handle = NULL; 3134 ccb->ccb_flags = 0; 3135 acb->ccbworkingQ[acb->ccb_put_index] = ccb; 3136 acb->ccb_put_index++; 3137 if (acb->ccb_put_index >= ARCMSR_MAX_FREECCB_NUM) 3138 acb->ccb_put_index = 3139 acb->ccb_put_index - ARCMSR_MAX_FREECCB_NUM; 3140 mutex_exit(&acb->workingQ_mutex); 3141 } 3142 3143 3144 static void 3145 arcmsr_ccbs_timeout(void* arg) 3146 { 3147 struct ACB *acb = (struct ACB *)arg; 3148 struct CCB *ccb; 3149 int i, instance, timeout_count = 0; 3150 uint32_t intmask_org; 3151 time_t current_time = ddi_get_time(); 3152 3153 intmask_org = arcmsr_disable_allintr(acb); 3154 mutex_enter(&acb->isr_mutex); 3155 if (acb->ccboutstandingcount != 0) { 3156 /* check each ccb */ 3157 i = ddi_dma_sync(acb->ccbs_pool_handle, 0, 0, 3158 DDI_DMA_SYNC_FORKERNEL); 3159 if (i != DDI_SUCCESS) { 3160 if ((acb->timeout_id != 0) && 3161 ((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0)) { 3162 /* do pkt timeout check each 60 secs */ 3163 acb->timeout_id = timeout(arcmsr_ccbs_timeout, 3164 (void*)acb, (ARCMSR_TIMEOUT_WATCH * 3165 drv_usectohz(1000000))); 3166 } 3167 mutex_exit(&acb->isr_mutex); 3168 arcmsr_enable_allintr(acb, intmask_org); 3169 return; 3170 } 3171 instance = ddi_get_instance(acb->dev_info); 3172 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) { 3173 ccb = acb->pccb_pool[i]; 3174 if (ccb->acb != acb) { 3175 break; 3176 } 3177 if (ccb->ccb_state == ARCMSR_CCB_FREE) { 3178 continue; 3179 } 3180 if (ccb->pkt == NULL) { 3181 continue; 3182 } 3183 if (ccb->pkt->pkt_time == 0) { 3184 continue; 3185 } 3186 if (ccb->ccb_time >= current_time) { 3187 continue; 3188 } 3189 int id = ccb->pkt->pkt_address.a_target; 3190 int lun = ccb->pkt->pkt_address.a_lun; 3191 if (ccb->ccb_state == ARCMSR_CCB_START) { 3192 uint8_t *cdb = (uint8_t *)&ccb->arcmsr_cdb.Cdb; 3193 3194 timeout_count++; 3195 arcmsr_warn(acb, 3196 "scsi target %d lun %d cmd=0x%x " 3197 "command timeout, ccb=0x%p", 3198 instance, id, lun, *cdb, (void *)ccb); 3199 ccb->ccb_state = ARCMSR_CCB_TIMEOUT; 3200 ccb->pkt->pkt_reason = CMD_TIMEOUT; 3201 ccb->pkt->pkt_statistics = STAT_TIMEOUT; 3202 /* acb->devstate[id][lun] = ARECA_RAID_GONE; */ 3203 arcmsr_ccb_complete(ccb, 1); 3204 continue; 3205 } else if ((ccb->ccb_state & ARCMSR_CCB_CAN_BE_FREE) == 3206 ARCMSR_CCB_CAN_BE_FREE) { 3207 arcmsr_free_ccb(ccb); 3208 } 3209 } 3210 } 3211 if ((acb->timeout_id != 0) && 3212 ((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0)) { 3213 /* do pkt timeout check each 60 secs */ 3214 acb->timeout_id = timeout(arcmsr_ccbs_timeout, 3215 (void*)acb, (ARCMSR_TIMEOUT_WATCH * drv_usectohz(1000000))); 3216 } 3217 mutex_exit(&acb->isr_mutex); 3218 arcmsr_enable_allintr(acb, intmask_org); 3219 } 3220 3221 static void 3222 arcmsr_abort_dr_ccbs(struct ACB *acb, uint16_t target, uint8_t lun) 3223 { 3224 struct CCB *ccb; 3225 uint32_t intmask_org; 3226 int i; 3227 3228 /* disable all outbound interrupts */ 3229 intmask_org = arcmsr_disable_allintr(acb); 3230 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) { 3231 ccb = acb->pccb_pool[i]; 3232 if (ccb->ccb_state == ARCMSR_CCB_START) { 3233 if ((target == ccb->pkt->pkt_address.a_target) && 3234 (lun == ccb->pkt->pkt_address.a_lun)) { 3235 ccb->ccb_state = ARCMSR_CCB_ABORTED; 3236 ccb->pkt->pkt_reason = CMD_ABORTED; 3237 ccb->pkt->pkt_statistics |= STAT_ABORTED; 3238 arcmsr_ccb_complete(ccb, 1); 3239 arcmsr_log(acb, CE_NOTE, 3240 "abort T%dL%d ccb", target, lun); 3241 } 3242 } 3243 } 3244 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3245 arcmsr_enable_allintr(acb, intmask_org); 3246 } 3247 3248 static int 3249 arcmsr_scsi_device_probe(struct ACB *acb, uint16_t tgt, uint8_t lun) 3250 { 3251 struct scsi_device sd; 3252 dev_info_t *child; 3253 int rval; 3254 3255 bzero(&sd, sizeof (struct scsi_device)); 3256 sd.sd_address.a_hba_tran = acb->scsi_hba_transport; 3257 sd.sd_address.a_target = (uint16_t)tgt; 3258 sd.sd_address.a_lun = (uint8_t)lun; 3259 if ((child = arcmsr_find_child(acb, tgt, lun)) != NULL) { 3260 rval = scsi_hba_probe(&sd, NULL); 3261 if (rval == SCSIPROBE_EXISTS) { 3262 rval = ndi_devi_online(child, NDI_ONLINE_ATTACH); 3263 if (rval != NDI_SUCCESS) { 3264 arcmsr_warn(acb, "unable to online T%dL%d", 3265 tgt, lun); 3266 } else { 3267 arcmsr_log(acb, CE_NOTE, "T%dL%d onlined", 3268 tgt, lun); 3269 } 3270 } 3271 } else { 3272 rval = scsi_hba_probe(&sd, NULL); 3273 if (rval == SCSIPROBE_EXISTS) 3274 rval = arcmsr_config_child(acb, &sd, NULL); 3275 } 3276 scsi_unprobe(&sd); 3277 return (rval); 3278 } 3279 3280 static void 3281 arcmsr_dr_handle(struct ACB *acb) 3282 { 3283 char *acb_dev_map = (char *)acb->device_map; 3284 char *devicemap; 3285 char temp; 3286 uint16_t target; 3287 uint8_t lun; 3288 char diff; 3289 dev_info_t *dip; 3290 ddi_acc_handle_t reg; 3291 3292 switch (acb->adapter_type) { 3293 case ACB_ADAPTER_TYPE_A: 3294 { 3295 struct HBA_msgUnit *phbamu; 3296 3297 phbamu = (struct HBA_msgUnit *)acb->pmu; 3298 devicemap = (char *)&phbamu->msgcode_rwbuffer[21]; 3299 reg = acb->reg_mu_acc_handle0; 3300 break; 3301 } 3302 3303 case ACB_ADAPTER_TYPE_B: 3304 { 3305 struct HBB_msgUnit *phbbmu; 3306 3307 phbbmu = (struct HBB_msgUnit *)acb->pmu; 3308 devicemap = (char *) 3309 &phbbmu->hbb_rwbuffer->msgcode_rwbuffer[21]; 3310 reg = acb->reg_mu_acc_handle1; 3311 break; 3312 } 3313 3314 case ACB_ADAPTER_TYPE_C: 3315 { 3316 struct HBC_msgUnit *phbcmu; 3317 3318 phbcmu = (struct HBC_msgUnit *)acb->pmu; 3319 devicemap = (char *)&phbcmu->msgcode_rwbuffer[21]; 3320 reg = acb->reg_mu_acc_handle0; 3321 break; 3322 } 3323 3324 } 3325 3326 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++) { 3327 temp = CHIP_REG_READ8(reg, devicemap); 3328 diff = (*acb_dev_map)^ temp; 3329 if (diff != 0) { 3330 *acb_dev_map = temp; 3331 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) { 3332 if ((temp & 0x01) == 1 && (diff & 0x01) == 1) { 3333 ndi_devi_enter(acb->dev_info); 3334 acb->devstate[target][lun] = 3335 ARECA_RAID_GOOD; 3336 (void) arcmsr_scsi_device_probe(acb, 3337 target, lun); 3338 ndi_devi_exit(acb->dev_info); 3339 arcmsr_log(acb, CE_NOTE, 3340 "T%dL%d on-line", target, lun); 3341 } else if ((temp & 0x01) == 0 && 3342 (diff & 0x01) == 1) { 3343 dip = arcmsr_find_child(acb, target, 3344 lun); 3345 if (dip != NULL) { 3346 acb->devstate[target][lun] = 3347 ARECA_RAID_GONE; 3348 if (mutex_owned(&acb-> 3349 isr_mutex)) { 3350 arcmsr_abort_dr_ccbs( 3351 acb, target, lun); 3352 (void) 3353 ndi_devi_offline( 3354 dip, 3355 NDI_DEVI_REMOVE | 3356 NDI_DEVI_OFFLINE); 3357 } else { 3358 mutex_enter(&acb-> 3359 isr_mutex); 3360 arcmsr_abort_dr_ccbs( 3361 acb, target, lun); 3362 (void) 3363 ndi_devi_offline( 3364 dip, 3365 NDI_DEVI_REMOVE | 3366 NDI_DEVI_OFFLINE); 3367 mutex_exit(&acb-> 3368 isr_mutex); 3369 } 3370 } 3371 arcmsr_log(acb, CE_NOTE, 3372 "T%dL%d off-line", target, lun); 3373 } 3374 temp >>= 1; 3375 diff >>= 1; 3376 } 3377 } 3378 devicemap++; 3379 acb_dev_map++; 3380 } 3381 } 3382 3383 3384 static void 3385 arcmsr_devMap_monitor(void* arg) 3386 { 3387 3388 struct ACB *acb = (struct ACB *)arg; 3389 switch (acb->adapter_type) { 3390 case ACB_ADAPTER_TYPE_A: 3391 { 3392 struct HBA_msgUnit *phbamu; 3393 3394 phbamu = (struct HBA_msgUnit *)acb->pmu; 3395 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 3396 &phbamu->inbound_msgaddr0, 3397 ARCMSR_INBOUND_MESG0_GET_CONFIG); 3398 break; 3399 } 3400 3401 case ACB_ADAPTER_TYPE_B: 3402 { 3403 struct HBB_msgUnit *phbbmu; 3404 3405 phbbmu = (struct HBB_msgUnit *)acb->pmu; 3406 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 3407 &phbbmu->hbb_doorbell->drv2iop_doorbell, 3408 ARCMSR_MESSAGE_GET_CONFIG); 3409 break; 3410 } 3411 3412 case ACB_ADAPTER_TYPE_C: 3413 { 3414 struct HBC_msgUnit *phbcmu; 3415 3416 phbcmu = (struct HBC_msgUnit *)acb->pmu; 3417 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 3418 &phbcmu->inbound_msgaddr0, 3419 ARCMSR_INBOUND_MESG0_GET_CONFIG); 3420 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 3421 &phbcmu->inbound_doorbell, 3422 ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3423 break; 3424 } 3425 3426 } 3427 3428 if ((acb->timeout_id != 0) && 3429 ((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0)) { 3430 /* do pkt timeout check each 5 secs */ 3431 acb->timeout_id = timeout(arcmsr_devMap_monitor, (void*)acb, 3432 (ARCMSR_DEV_MAP_WATCH * drv_usectohz(1000000))); 3433 } 3434 } 3435 3436 3437 static uint32_t 3438 arcmsr_disable_allintr(struct ACB *acb) 3439 { 3440 uint32_t intmask_org; 3441 3442 switch (acb->adapter_type) { 3443 case ACB_ADAPTER_TYPE_A: 3444 { 3445 struct HBA_msgUnit *phbamu; 3446 3447 phbamu = (struct HBA_msgUnit *)acb->pmu; 3448 /* disable all outbound interrupt */ 3449 intmask_org = CHIP_REG_READ32(acb->reg_mu_acc_handle0, 3450 &phbamu->outbound_intmask); 3451 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 3452 &phbamu->outbound_intmask, 3453 intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE); 3454 break; 3455 } 3456 3457 case ACB_ADAPTER_TYPE_B: 3458 { 3459 struct HBB_msgUnit *phbbmu; 3460 3461 phbbmu = (struct HBB_msgUnit *)acb->pmu; 3462 /* disable all outbound interrupt */ 3463 intmask_org = CHIP_REG_READ32(acb->reg_mu_acc_handle0, 3464 &phbbmu->hbb_doorbell->iop2drv_doorbell_mask); 3465 /* disable all interrupts */ 3466 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 3467 &phbbmu->hbb_doorbell->iop2drv_doorbell_mask, 0); 3468 break; 3469 } 3470 3471 case ACB_ADAPTER_TYPE_C: 3472 { 3473 struct HBC_msgUnit *phbcmu; 3474 3475 phbcmu = (struct HBC_msgUnit *)acb->pmu; 3476 /* disable all outbound interrupt */ 3477 intmask_org = CHIP_REG_READ32(acb->reg_mu_acc_handle0, 3478 &phbcmu->host_int_mask); /* disable outbound message0 int */ 3479 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 3480 &phbcmu->host_int_mask, 3481 intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE); 3482 break; 3483 } 3484 3485 } 3486 return (intmask_org); 3487 } 3488 3489 3490 static void 3491 arcmsr_enable_allintr(struct ACB *acb, uint32_t intmask_org) 3492 { 3493 int mask; 3494 3495 switch (acb->adapter_type) { 3496 case ACB_ADAPTER_TYPE_A: 3497 { 3498 struct HBA_msgUnit *phbamu; 3499 3500 phbamu = (struct HBA_msgUnit *)acb->pmu; 3501 /* 3502 * enable outbound Post Queue, outbound doorbell message0 3503 * Interrupt 3504 */ 3505 mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE | 3506 ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE | 3507 ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE); 3508 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 3509 &phbamu->outbound_intmask, intmask_org & mask); 3510 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff; 3511 break; 3512 } 3513 3514 case ACB_ADAPTER_TYPE_B: 3515 { 3516 struct HBB_msgUnit *phbbmu; 3517 3518 phbbmu = (struct HBB_msgUnit *)acb->pmu; 3519 mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK | 3520 ARCMSR_IOP2DRV_DATA_READ_OK | ARCMSR_IOP2DRV_CDB_DONE | 3521 ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); 3522 /* 1=interrupt enable, 0=interrupt disable */ 3523 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 3524 &phbbmu->hbb_doorbell->iop2drv_doorbell_mask, 3525 intmask_org | mask); 3526 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f; 3527 break; 3528 } 3529 3530 case ACB_ADAPTER_TYPE_C: 3531 { 3532 struct HBC_msgUnit *phbcmu; 3533 3534 phbcmu = (struct HBC_msgUnit *)acb->pmu; 3535 /* enable outbound Post Queue,outbound doorbell Interrupt */ 3536 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | 3537 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | 3538 ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK); 3539 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 3540 &phbcmu->host_int_mask, intmask_org & mask); 3541 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 3542 break; 3543 } 3544 3545 } 3546 } 3547 3548 3549 static void 3550 arcmsr_iop_parking(struct ACB *acb) 3551 { 3552 /* stop adapter background rebuild */ 3553 if (acb->acb_flags & ACB_F_MSG_START_BGRB) { 3554 uint32_t intmask_org; 3555 3556 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 3557 /* disable all outbound interrupt */ 3558 intmask_org = arcmsr_disable_allintr(acb); 3559 switch (acb->adapter_type) { 3560 case ACB_ADAPTER_TYPE_A: 3561 arcmsr_stop_hba_bgrb(acb); 3562 arcmsr_flush_hba_cache(acb); 3563 break; 3564 3565 case ACB_ADAPTER_TYPE_B: 3566 arcmsr_stop_hbb_bgrb(acb); 3567 arcmsr_flush_hbb_cache(acb); 3568 break; 3569 3570 case ACB_ADAPTER_TYPE_C: 3571 arcmsr_stop_hbc_bgrb(acb); 3572 arcmsr_flush_hbc_cache(acb); 3573 break; 3574 } 3575 /* 3576 * enable outbound Post Queue 3577 * enable outbound doorbell Interrupt 3578 */ 3579 arcmsr_enable_allintr(acb, intmask_org); 3580 } 3581 } 3582 3583 3584 static uint8_t 3585 arcmsr_hba_wait_msgint_ready(struct ACB *acb) 3586 { 3587 uint32_t i; 3588 uint8_t retries = 0x00; 3589 struct HBA_msgUnit *phbamu; 3590 3591 3592 phbamu = (struct HBA_msgUnit *)acb->pmu; 3593 3594 do { 3595 for (i = 0; i < 100; i++) { 3596 if (CHIP_REG_READ32(acb->reg_mu_acc_handle0, 3597 &phbamu->outbound_intstatus) & 3598 ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 3599 /* clear interrupt */ 3600 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 3601 &phbamu->outbound_intstatus, 3602 ARCMSR_MU_OUTBOUND_MESSAGE0_INT); 3603 return (TRUE); 3604 } 3605 drv_usecwait(10000); 3606 if (ddi_in_panic()) { 3607 /* clear interrupts */ 3608 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 3609 &phbamu->outbound_intstatus, 3610 ARCMSR_MU_OUTBOUND_MESSAGE0_INT); 3611 return (TRUE); 3612 } 3613 } /* max 1 second */ 3614 } while (retries++ < 20); /* max 20 seconds */ 3615 return (FALSE); 3616 } 3617 3618 3619 static uint8_t 3620 arcmsr_hbb_wait_msgint_ready(struct ACB *acb) 3621 { 3622 struct HBB_msgUnit *phbbmu; 3623 uint32_t i; 3624 uint8_t retries = 0x00; 3625 3626 phbbmu = (struct HBB_msgUnit *)acb->pmu; 3627 3628 do { 3629 for (i = 0; i < 100; i++) { 3630 if (CHIP_REG_READ32(acb->reg_mu_acc_handle0, 3631 &phbbmu->hbb_doorbell->iop2drv_doorbell) & 3632 ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 3633 /* clear interrupt */ 3634 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 3635 &phbbmu->hbb_doorbell->iop2drv_doorbell, 3636 ARCMSR_MESSAGE_INT_CLEAR_PATTERN); 3637 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 3638 &phbbmu->hbb_doorbell->drv2iop_doorbell, 3639 ARCMSR_DRV2IOP_END_OF_INTERRUPT); 3640 return (TRUE); 3641 } 3642 drv_usecwait(10000); 3643 if (ddi_in_panic()) { 3644 /* clear interrupts */ 3645 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 3646 &phbbmu->hbb_doorbell->iop2drv_doorbell, 3647 ARCMSR_MESSAGE_INT_CLEAR_PATTERN); 3648 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 3649 &phbbmu->hbb_doorbell->drv2iop_doorbell, 3650 ARCMSR_DRV2IOP_END_OF_INTERRUPT); 3651 return (TRUE); 3652 } 3653 } /* max 1 second */ 3654 } while (retries++ < 20); /* max 20 seconds */ 3655 3656 return (FALSE); 3657 } 3658 3659 3660 static uint8_t 3661 arcmsr_hbc_wait_msgint_ready(struct ACB *acb) 3662 { 3663 uint32_t i; 3664 uint8_t retries = 0x00; 3665 struct HBC_msgUnit *phbcmu; 3666 uint32_t c = ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR; 3667 3668 3669 phbcmu = (struct HBC_msgUnit *)acb->pmu; 3670 3671 do { 3672 for (i = 0; i < 100; i++) { 3673 if (CHIP_REG_READ32(acb->reg_mu_acc_handle0, 3674 &phbcmu->outbound_doorbell) & 3675 ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 3676 /* clear interrupt */ 3677 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 3678 &phbcmu->outbound_doorbell_clear, c); 3679 return (TRUE); 3680 } 3681 drv_usecwait(10000); 3682 if (ddi_in_panic()) { 3683 /* clear interrupts */ 3684 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 3685 &phbcmu->outbound_doorbell_clear, c); 3686 return (TRUE); 3687 } 3688 } /* max 1 second */ 3689 } while (retries++ < 20); /* max 20 seconds */ 3690 return (FALSE); 3691 } 3692 3693 3694 static void 3695 arcmsr_flush_hba_cache(struct ACB *acb) 3696 { 3697 struct HBA_msgUnit *phbamu; 3698 int retry_count = 30; 3699 3700 /* enlarge wait flush adapter cache time: 10 minutes */ 3701 3702 phbamu = (struct HBA_msgUnit *)acb->pmu; 3703 3704 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, &phbamu->inbound_msgaddr0, 3705 ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 3706 do { 3707 if (arcmsr_hba_wait_msgint_ready(acb)) { 3708 break; 3709 } else { 3710 retry_count--; 3711 } 3712 } while (retry_count != 0); 3713 } 3714 3715 static void 3716 arcmsr_flush_hbb_cache(struct ACB *acb) 3717 { 3718 struct HBB_msgUnit *phbbmu; 3719 int retry_count = 30; 3720 3721 /* enlarge wait flush adapter cache time: 10 minutes */ 3722 3723 phbbmu = (struct HBB_msgUnit *)acb->pmu; 3724 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 3725 &phbbmu->hbb_doorbell->drv2iop_doorbell, 3726 ARCMSR_MESSAGE_FLUSH_CACHE); 3727 do { 3728 if (arcmsr_hbb_wait_msgint_ready(acb)) { 3729 break; 3730 } else { 3731 retry_count--; 3732 } 3733 } while (retry_count != 0); 3734 } 3735 3736 3737 static void 3738 arcmsr_flush_hbc_cache(struct ACB *acb) 3739 { 3740 struct HBC_msgUnit *phbcmu; 3741 int retry_count = 30; 3742 3743 /* enlarge wait flush adapter cache time: 10 minutes */ 3744 3745 phbcmu = (struct HBC_msgUnit *)acb->pmu; 3746 3747 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, &phbcmu->inbound_msgaddr0, 3748 ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 3749 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, &phbcmu->inbound_doorbell, 3750 ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3751 do { 3752 if (arcmsr_hbc_wait_msgint_ready(acb)) { 3753 break; 3754 } else { 3755 retry_count--; 3756 } 3757 } while (retry_count != 0); 3758 } 3759 3760 3761 3762 static uint8_t 3763 arcmsr_abort_hba_allcmd(struct ACB *acb) 3764 { 3765 struct HBA_msgUnit *phbamu = (struct HBA_msgUnit *)acb->pmu; 3766 3767 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, &phbamu->inbound_msgaddr0, 3768 ARCMSR_INBOUND_MESG0_ABORT_CMD); 3769 3770 if (!arcmsr_hba_wait_msgint_ready(acb)) { 3771 arcmsr_warn(acb, 3772 "timeout while waiting for 'abort all " 3773 "outstanding commands'"); 3774 return (0xff); 3775 } 3776 return (0x00); 3777 } 3778 3779 3780 3781 static uint8_t 3782 arcmsr_abort_hbb_allcmd(struct ACB *acb) 3783 { 3784 struct HBB_msgUnit *phbbmu = (struct HBB_msgUnit *)acb->pmu; 3785 3786 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 3787 &phbbmu->hbb_doorbell->drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD); 3788 3789 if (!arcmsr_hbb_wait_msgint_ready(acb)) { 3790 arcmsr_warn(acb, 3791 "timeout while waiting for 'abort all " 3792 "outstanding commands'"); 3793 return (0x00); 3794 } 3795 return (0x00); 3796 } 3797 3798 3799 static uint8_t 3800 arcmsr_abort_hbc_allcmd(struct ACB *acb) 3801 { 3802 struct HBC_msgUnit *phbcmu = (struct HBC_msgUnit *)acb->pmu; 3803 3804 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, &phbcmu->inbound_msgaddr0, 3805 ARCMSR_INBOUND_MESG0_ABORT_CMD); 3806 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, &phbcmu->inbound_doorbell, 3807 ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3808 3809 if (!arcmsr_hbc_wait_msgint_ready(acb)) { 3810 arcmsr_warn(acb, 3811 "timeout while waiting for 'abort all " 3812 "outstanding commands'"); 3813 return (0xff); 3814 } 3815 return (0x00); 3816 } 3817 3818 3819 static void 3820 arcmsr_done4abort_postqueue(struct ACB *acb) 3821 { 3822 3823 struct CCB *ccb; 3824 uint32_t flag_ccb; 3825 int i = 0; 3826 boolean_t error; 3827 3828 switch (acb->adapter_type) { 3829 case ACB_ADAPTER_TYPE_A: 3830 { 3831 struct HBA_msgUnit *phbamu; 3832 uint32_t outbound_intstatus; 3833 3834 phbamu = (struct HBA_msgUnit *)acb->pmu; 3835 /* clear and abort all outbound posted Q */ 3836 outbound_intstatus = CHIP_REG_READ32(acb->reg_mu_acc_handle0, 3837 &phbamu->outbound_intstatus) & acb->outbound_int_enable; 3838 /* clear interrupt */ 3839 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 3840 &phbamu->outbound_intstatus, outbound_intstatus); 3841 while (((flag_ccb = CHIP_REG_READ32(acb->reg_mu_acc_handle0, 3842 &phbamu->outbound_queueport)) != 0xFFFFFFFF) && 3843 (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 3844 /* frame must be 32 bytes aligned */ 3845 /* the CDB is the first field of the CCB */ 3846 ccb = NumToPtr((acb->vir2phy_offset + (flag_ccb << 5))); 3847 /* check if command done with no error */ 3848 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? 3849 B_TRUE : B_FALSE; 3850 arcmsr_drain_donequeue(acb, ccb, error); 3851 } 3852 break; 3853 } 3854 3855 case ACB_ADAPTER_TYPE_B: 3856 { 3857 struct HBB_msgUnit *phbbmu; 3858 3859 phbbmu = (struct HBB_msgUnit *)acb->pmu; 3860 /* clear all outbound posted Q */ 3861 /* clear doorbell interrupt */ 3862 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 3863 &phbbmu->hbb_doorbell->iop2drv_doorbell, 3864 ARCMSR_DOORBELL_INT_CLEAR_PATTERN); 3865 for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) { 3866 if ((flag_ccb = phbbmu->done_qbuffer[i]) != 0) { 3867 phbbmu->done_qbuffer[i] = 0; 3868 /* frame must be 32 bytes aligned */ 3869 ccb = NumToPtr((acb->vir2phy_offset + 3870 (flag_ccb << 5))); 3871 /* check if command done with no error */ 3872 error = 3873 (flag_ccb & 3874 ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? 3875 B_TRUE : B_FALSE; 3876 arcmsr_drain_donequeue(acb, ccb, error); 3877 } 3878 phbbmu->post_qbuffer[i] = 0; 3879 } /* drain reply FIFO */ 3880 phbbmu->doneq_index = 0; 3881 phbbmu->postq_index = 0; 3882 break; 3883 } 3884 3885 case ACB_ADAPTER_TYPE_C: 3886 { 3887 struct HBC_msgUnit *phbcmu; 3888 uint32_t ccb_cdb_phy; 3889 3890 phbcmu = (struct HBC_msgUnit *)acb->pmu; 3891 while ((CHIP_REG_READ32(acb->reg_mu_acc_handle0, 3892 &phbcmu->host_int_status) & 3893 ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && 3894 (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 3895 /* need to do */ 3896 flag_ccb = CHIP_REG_READ32(acb->reg_mu_acc_handle0, 3897 &phbcmu->outbound_queueport_low); 3898 /* frame must be 32 bytes aligned */ 3899 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0); 3900 ccb = NumToPtr((acb->vir2phy_offset + ccb_cdb_phy)); 3901 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)? 3902 B_TRUE : B_FALSE; 3903 arcmsr_drain_donequeue(acb, ccb, error); 3904 } 3905 break; 3906 } 3907 3908 } 3909 } 3910 /* 3911 * Routine Description: try to get echo from iop. 3912 * Arguments: 3913 * Return Value: Nothing. 3914 */ 3915 static uint8_t 3916 arcmsr_get_echo_from_iop(struct ACB *acb) 3917 { 3918 uint32_t intmask_org; 3919 uint8_t rtnval = 0; 3920 3921 if (acb->adapter_type == ACB_ADAPTER_TYPE_A) { 3922 struct HBA_msgUnit *phbamu; 3923 3924 phbamu = (struct HBA_msgUnit *)acb->pmu; 3925 intmask_org = arcmsr_disable_allintr(acb); 3926 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 3927 &phbamu->inbound_msgaddr0, 3928 ARCMSR_INBOUND_MESG0_GET_CONFIG); 3929 if (!arcmsr_hba_wait_msgint_ready(acb)) { 3930 arcmsr_warn(acb, "try to get echo from iop," 3931 "... timeout ..."); 3932 acb->acb_flags |= ACB_F_BUS_HANG_ON; 3933 rtnval = 0xFF; 3934 } 3935 /* enable all outbound interrupt */ 3936 arcmsr_enable_allintr(acb, intmask_org); 3937 } 3938 return (rtnval); 3939 } 3940 3941 /* 3942 * Routine Description: Reset 80331 iop. 3943 * Arguments: 3944 * Return Value: Nothing. 3945 */ 3946 static uint8_t 3947 arcmsr_iop_reset(struct ACB *acb) 3948 { 3949 struct CCB *ccb; 3950 uint32_t intmask_org; 3951 uint8_t rtnval = 0; 3952 int i = 0; 3953 3954 if (acb->ccboutstandingcount > 0) { 3955 /* disable all outbound interrupt */ 3956 intmask_org = arcmsr_disable_allintr(acb); 3957 /* clear and abort all outbound posted Q */ 3958 arcmsr_done4abort_postqueue(acb); 3959 /* talk to iop 331 outstanding command aborted */ 3960 rtnval = (acb->acb_flags & ACB_F_BUS_HANG_ON) ? 3961 0xFF : arcmsr_abort_host_command(acb); 3962 3963 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) { 3964 ccb = acb->pccb_pool[i]; 3965 if (ccb->ccb_state == ARCMSR_CCB_START) { 3966 /* ccb->ccb_state = ARCMSR_CCB_RESET; */ 3967 ccb->pkt->pkt_reason = CMD_RESET; 3968 ccb->pkt->pkt_statistics |= STAT_BUS_RESET; 3969 arcmsr_ccb_complete(ccb, 1); 3970 } 3971 } 3972 atomic_and_32(&acb->ccboutstandingcount, 0); 3973 /* enable all outbound interrupt */ 3974 arcmsr_enable_allintr(acb, intmask_org); 3975 } else { 3976 rtnval = arcmsr_get_echo_from_iop(acb); 3977 } 3978 return (rtnval); 3979 } 3980 3981 3982 static struct QBUFFER * 3983 arcmsr_get_iop_rqbuffer(struct ACB *acb) 3984 { 3985 struct QBUFFER *qb; 3986 3987 switch (acb->adapter_type) { 3988 case ACB_ADAPTER_TYPE_A: 3989 { 3990 struct HBA_msgUnit *phbamu; 3991 3992 phbamu = (struct HBA_msgUnit *)acb->pmu; 3993 qb = (struct QBUFFER *)&phbamu->message_rbuffer; 3994 break; 3995 } 3996 3997 case ACB_ADAPTER_TYPE_B: 3998 { 3999 struct HBB_msgUnit *phbbmu; 4000 4001 phbbmu = (struct HBB_msgUnit *)acb->pmu; 4002 qb = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer; 4003 break; 4004 } 4005 4006 case ACB_ADAPTER_TYPE_C: 4007 { 4008 struct HBC_msgUnit *phbcmu; 4009 4010 phbcmu = (struct HBC_msgUnit *)acb->pmu; 4011 qb = (struct QBUFFER *)&phbcmu->message_rbuffer; 4012 break; 4013 } 4014 4015 } 4016 return (qb); 4017 } 4018 4019 4020 static struct QBUFFER * 4021 arcmsr_get_iop_wqbuffer(struct ACB *acb) 4022 { 4023 struct QBUFFER *qbuffer = NULL; 4024 4025 switch (acb->adapter_type) { 4026 case ACB_ADAPTER_TYPE_A: 4027 { 4028 struct HBA_msgUnit *phbamu; 4029 4030 phbamu = (struct HBA_msgUnit *)acb->pmu; 4031 qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer; 4032 break; 4033 } 4034 4035 case ACB_ADAPTER_TYPE_B: 4036 { 4037 struct HBB_msgUnit *phbbmu; 4038 4039 phbbmu = (struct HBB_msgUnit *)acb->pmu; 4040 qbuffer = (struct QBUFFER *) 4041 &phbbmu->hbb_rwbuffer->message_wbuffer; 4042 break; 4043 } 4044 4045 case ACB_ADAPTER_TYPE_C: 4046 { 4047 struct HBC_msgUnit *phbcmu; 4048 4049 phbcmu = (struct HBC_msgUnit *)acb->pmu; 4050 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer; 4051 break; 4052 } 4053 4054 } 4055 return (qbuffer); 4056 } 4057 4058 4059 4060 static void 4061 arcmsr_iop_message_read(struct ACB *acb) 4062 { 4063 switch (acb->adapter_type) { 4064 case ACB_ADAPTER_TYPE_A: 4065 { 4066 struct HBA_msgUnit *phbamu; 4067 4068 phbamu = (struct HBA_msgUnit *)acb->pmu; 4069 /* let IOP know the data has been read */ 4070 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 4071 &phbamu->inbound_doorbell, 4072 ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 4073 break; 4074 } 4075 4076 case ACB_ADAPTER_TYPE_B: 4077 { 4078 struct HBB_msgUnit *phbbmu; 4079 4080 phbbmu = (struct HBB_msgUnit *)acb->pmu; 4081 /* let IOP know the data has been read */ 4082 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 4083 &phbbmu->hbb_doorbell->drv2iop_doorbell, 4084 ARCMSR_DRV2IOP_DATA_READ_OK); 4085 break; 4086 } 4087 4088 case ACB_ADAPTER_TYPE_C: 4089 { 4090 struct HBC_msgUnit *phbcmu; 4091 4092 phbcmu = (struct HBC_msgUnit *)acb->pmu; 4093 /* let IOP know data has been read */ 4094 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 4095 &phbcmu->inbound_doorbell, 4096 ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 4097 break; 4098 } 4099 4100 } 4101 } 4102 4103 4104 4105 static void 4106 arcmsr_iop_message_wrote(struct ACB *acb) 4107 { 4108 switch (acb->adapter_type) { 4109 case ACB_ADAPTER_TYPE_A: { 4110 struct HBA_msgUnit *phbamu; 4111 4112 phbamu = (struct HBA_msgUnit *)acb->pmu; 4113 /* 4114 * push inbound doorbell tell iop, driver data write ok 4115 * and wait reply on next hwinterrupt for next Qbuffer post 4116 */ 4117 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 4118 &phbamu->inbound_doorbell, 4119 ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK); 4120 break; 4121 } 4122 4123 case ACB_ADAPTER_TYPE_B: 4124 { 4125 struct HBB_msgUnit *phbbmu; 4126 4127 phbbmu = (struct HBB_msgUnit *)acb->pmu; 4128 /* 4129 * push inbound doorbell tell iop, driver data was writen 4130 * successfully, then await reply on next hwinterrupt for 4131 * next Qbuffer post 4132 */ 4133 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 4134 &phbbmu->hbb_doorbell->drv2iop_doorbell, 4135 ARCMSR_DRV2IOP_DATA_WRITE_OK); 4136 break; 4137 } 4138 4139 case ACB_ADAPTER_TYPE_C: 4140 { 4141 struct HBC_msgUnit *phbcmu; 4142 4143 phbcmu = (struct HBC_msgUnit *)acb->pmu; 4144 /* 4145 * push inbound doorbell tell iop, driver data write ok 4146 * and wait reply on next hwinterrupt for next Qbuffer post 4147 */ 4148 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 4149 &phbcmu->inbound_doorbell, 4150 ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK); 4151 break; 4152 } 4153 4154 } 4155 } 4156 4157 4158 4159 static void 4160 arcmsr_post_ioctldata2iop(struct ACB *acb) 4161 { 4162 uint8_t *pQbuffer; 4163 struct QBUFFER *pwbuffer; 4164 uint8_t *iop_data; 4165 int32_t allxfer_len = 0; 4166 4167 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 4168 iop_data = (uint8_t *)pwbuffer->data; 4169 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 4170 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 4171 while ((acb->wqbuf_firstidx != acb->wqbuf_lastidx) && 4172 (allxfer_len < 124)) { 4173 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstidx]; 4174 (void) memcpy(iop_data, pQbuffer, 1); 4175 acb->wqbuf_firstidx++; 4176 /* if last index number set it to 0 */ 4177 acb->wqbuf_firstidx %= ARCMSR_MAX_QBUFFER; 4178 iop_data++; 4179 allxfer_len++; 4180 } 4181 pwbuffer->data_len = allxfer_len; 4182 /* 4183 * push inbound doorbell and wait reply at hwinterrupt 4184 * routine for next Qbuffer post 4185 */ 4186 arcmsr_iop_message_wrote(acb); 4187 } 4188 } 4189 4190 4191 4192 static void 4193 arcmsr_stop_hba_bgrb(struct ACB *acb) 4194 { 4195 struct HBA_msgUnit *phbamu; 4196 4197 phbamu = (struct HBA_msgUnit *)acb->pmu; 4198 4199 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 4200 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 4201 &phbamu->inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 4202 if (!arcmsr_hba_wait_msgint_ready(acb)) 4203 arcmsr_warn(acb, 4204 "timeout while waiting for background rebuild completion"); 4205 } 4206 4207 4208 static void 4209 arcmsr_stop_hbb_bgrb(struct ACB *acb) 4210 { 4211 struct HBB_msgUnit *phbbmu; 4212 4213 phbbmu = (struct HBB_msgUnit *)acb->pmu; 4214 4215 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 4216 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 4217 &phbbmu->hbb_doorbell->drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB); 4218 4219 if (!arcmsr_hbb_wait_msgint_ready(acb)) 4220 arcmsr_warn(acb, 4221 "timeout while waiting for background rebuild completion"); 4222 } 4223 4224 4225 static void 4226 arcmsr_stop_hbc_bgrb(struct ACB *acb) 4227 { 4228 struct HBC_msgUnit *phbcmu; 4229 4230 phbcmu = (struct HBC_msgUnit *)acb->pmu; 4231 4232 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 4233 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 4234 &phbcmu->inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 4235 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 4236 &phbcmu->inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 4237 if (!arcmsr_hbc_wait_msgint_ready(acb)) 4238 arcmsr_warn(acb, 4239 "timeout while waiting for background rebuild completion"); 4240 } 4241 4242 4243 static int 4244 arcmsr_iop_message_xfer(struct ACB *acb, struct scsi_pkt *pkt) 4245 { 4246 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 4247 struct CCB *ccb = pkt->pkt_ha_private; 4248 struct buf *bp = ccb->bp; 4249 uint8_t *pQbuffer; 4250 int retvalue = 0, transfer_len = 0; 4251 char *buffer; 4252 uint32_t controlcode; 4253 4254 4255 /* 4 bytes: Areca io control code */ 4256 controlcode = 4257 (uint32_t)pkt->pkt_cdbp[5] << 24 | 4258 (uint32_t)pkt->pkt_cdbp[6] << 16 | 4259 (uint32_t)pkt->pkt_cdbp[7] << 8 | 4260 (uint32_t)pkt->pkt_cdbp[8]; 4261 4262 if (bp->b_flags & (B_PHYS | B_PAGEIO)) 4263 bp_mapin(bp); 4264 4265 buffer = bp->b_un.b_addr; 4266 transfer_len = bp->b_bcount; 4267 if (transfer_len > sizeof (struct CMD_MESSAGE_FIELD)) { 4268 retvalue = ARCMSR_MESSAGE_FAIL; 4269 goto message_out; 4270 } 4271 4272 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *)(intptr_t)buffer; 4273 switch (controlcode) { 4274 case ARCMSR_MESSAGE_READ_RQBUFFER: 4275 { 4276 unsigned long *ver_addr; 4277 uint8_t *ptmpQbuffer; 4278 int32_t allxfer_len = 0; 4279 4280 ver_addr = kmem_zalloc(MSGDATABUFLEN, KM_SLEEP); 4281 4282 ptmpQbuffer = (uint8_t *)ver_addr; 4283 while ((acb->rqbuf_firstidx != acb->rqbuf_lastidx) && 4284 (allxfer_len < (MSGDATABUFLEN - 1))) { 4285 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstidx]; 4286 (void) memcpy(ptmpQbuffer, pQbuffer, 1); 4287 acb->rqbuf_firstidx++; 4288 acb->rqbuf_firstidx %= ARCMSR_MAX_QBUFFER; 4289 ptmpQbuffer++; 4290 allxfer_len++; 4291 } 4292 4293 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 4294 struct QBUFFER *prbuffer; 4295 uint8_t *iop_data; 4296 int32_t iop_len; 4297 4298 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 4299 prbuffer = arcmsr_get_iop_rqbuffer(acb); 4300 iop_data = (uint8_t *)prbuffer->data; 4301 iop_len = (int32_t)prbuffer->data_len; 4302 4303 while (iop_len > 0) { 4304 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastidx]; 4305 (void) memcpy(pQbuffer, iop_data, 1); 4306 acb->rqbuf_lastidx++; 4307 acb->rqbuf_lastidx %= ARCMSR_MAX_QBUFFER; 4308 iop_data++; 4309 iop_len--; 4310 } 4311 arcmsr_iop_message_read(acb); 4312 } 4313 4314 (void) memcpy(pcmdmessagefld->messagedatabuffer, 4315 (uint8_t *)ver_addr, allxfer_len); 4316 pcmdmessagefld->cmdmessage.Length = allxfer_len; 4317 pcmdmessagefld->cmdmessage.ReturnCode = 4318 ARCMSR_MESSAGE_RETURNCODE_OK; 4319 kmem_free(ver_addr, MSGDATABUFLEN); 4320 break; 4321 } 4322 4323 case ARCMSR_MESSAGE_WRITE_WQBUFFER: 4324 { 4325 uint8_t *ver_addr; 4326 int32_t my_empty_len, user_len, wqbuf_firstidx, 4327 wqbuf_lastidx; 4328 uint8_t *ptmpuserbuffer; 4329 4330 ver_addr = kmem_zalloc(MSGDATABUFLEN, KM_SLEEP); 4331 4332 ptmpuserbuffer = ver_addr; 4333 user_len = min(pcmdmessagefld->cmdmessage.Length, 4334 MSGDATABUFLEN); 4335 (void) memcpy(ptmpuserbuffer, 4336 pcmdmessagefld->messagedatabuffer, user_len); 4337 wqbuf_lastidx = acb->wqbuf_lastidx; 4338 wqbuf_firstidx = acb->wqbuf_firstidx; 4339 if (wqbuf_lastidx != wqbuf_firstidx) { 4340 struct scsi_arq_status *arq_status; 4341 4342 arcmsr_post_ioctldata2iop(acb); 4343 arq_status = (struct scsi_arq_status *) 4344 (intptr_t)(pkt->pkt_scbp); 4345 bzero((caddr_t)arq_status, 4346 sizeof (struct scsi_arq_status)); 4347 arq_status->sts_rqpkt_reason = CMD_CMPLT; 4348 arq_status->sts_rqpkt_state = (STATE_GOT_BUS | 4349 STATE_GOT_TARGET | STATE_SENT_CMD | 4350 STATE_XFERRED_DATA | STATE_GOT_STATUS); 4351 4352 arq_status->sts_rqpkt_statistics = 4353 pkt->pkt_statistics; 4354 arq_status->sts_rqpkt_resid = 0; 4355 if (&arq_status->sts_sensedata != NULL) { 4356 struct scsi_extended_sense *sts_sensedata; 4357 4358 sts_sensedata = &arq_status->sts_sensedata; 4359 4360 /* has error report sensedata */ 4361 sts_sensedata->es_code = 0x0; 4362 sts_sensedata->es_valid = 0x01; 4363 sts_sensedata->es_key = KEY_ILLEGAL_REQUEST; 4364 /* AdditionalSenseLength */ 4365 sts_sensedata->es_add_len = 0x0A; 4366 /* AdditionalSenseCode */ 4367 sts_sensedata->es_add_code = 0x20; 4368 } 4369 retvalue = ARCMSR_MESSAGE_FAIL; 4370 } else { 4371 my_empty_len = (wqbuf_firstidx-wqbuf_lastidx - 1) & 4372 (ARCMSR_MAX_QBUFFER - 1); 4373 if (my_empty_len >= user_len) { 4374 while (user_len > 0) { 4375 pQbuffer = &acb->wqbuffer[ 4376 acb->wqbuf_lastidx]; 4377 (void) memcpy(pQbuffer, 4378 ptmpuserbuffer, 1); 4379 acb->wqbuf_lastidx++; 4380 acb->wqbuf_lastidx %= 4381 ARCMSR_MAX_QBUFFER; 4382 ptmpuserbuffer++; 4383 user_len--; 4384 } 4385 if (acb->acb_flags & 4386 ACB_F_MESSAGE_WQBUFFER_CLEARED) { 4387 acb->acb_flags &= 4388 ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 4389 arcmsr_post_ioctldata2iop(acb); 4390 } 4391 } else { 4392 struct scsi_arq_status *arq_status; 4393 4394 /* has error report sensedata */ 4395 arq_status = (struct scsi_arq_status *) 4396 (intptr_t)(pkt->pkt_scbp); 4397 bzero((caddr_t)arq_status, 4398 sizeof (struct scsi_arq_status)); 4399 arq_status->sts_rqpkt_reason = CMD_CMPLT; 4400 arq_status->sts_rqpkt_state = 4401 (STATE_GOT_BUS | 4402 STATE_GOT_TARGET |STATE_SENT_CMD | 4403 STATE_XFERRED_DATA | STATE_GOT_STATUS); 4404 arq_status->sts_rqpkt_statistics = 4405 pkt->pkt_statistics; 4406 arq_status->sts_rqpkt_resid = 0; 4407 if (&arq_status->sts_sensedata != NULL) { 4408 struct scsi_extended_sense * 4409 sts_sensedata; 4410 4411 sts_sensedata = 4412 &arq_status->sts_sensedata; 4413 4414 /* has error report sensedata */ 4415 sts_sensedata->es_code = 0x0; 4416 sts_sensedata->es_valid = 0x01; 4417 sts_sensedata->es_key = 4418 KEY_ILLEGAL_REQUEST; 4419 /* AdditionalSenseLength */ 4420 sts_sensedata->es_add_len = 0x0A; 4421 /* AdditionalSenseCode */ 4422 sts_sensedata->es_add_code = 0x20; 4423 } 4424 retvalue = ARCMSR_MESSAGE_FAIL; 4425 } 4426 } 4427 kmem_free(ver_addr, MSGDATABUFLEN); 4428 break; 4429 } 4430 4431 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: 4432 pQbuffer = acb->rqbuffer; 4433 4434 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 4435 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 4436 arcmsr_iop_message_read(acb); 4437 } 4438 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 4439 acb->rqbuf_firstidx = 0; 4440 acb->rqbuf_lastidx = 0; 4441 (void) memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 4442 pcmdmessagefld->cmdmessage.ReturnCode = 4443 ARCMSR_MESSAGE_RETURNCODE_OK; 4444 break; 4445 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: 4446 pQbuffer = acb->wqbuffer; 4447 4448 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 4449 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 4450 arcmsr_iop_message_read(acb); 4451 } 4452 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED | 4453 ACB_F_MESSAGE_WQBUFFER_READ); 4454 acb->wqbuf_firstidx = 0; 4455 acb->wqbuf_lastidx = 0; 4456 (void) memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 4457 pcmdmessagefld->cmdmessage.ReturnCode = 4458 ARCMSR_MESSAGE_RETURNCODE_OK; 4459 break; 4460 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: 4461 4462 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 4463 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 4464 arcmsr_iop_message_read(acb); 4465 } 4466 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED | 4467 ACB_F_MESSAGE_RQBUFFER_CLEARED | 4468 ACB_F_MESSAGE_WQBUFFER_READ); 4469 acb->rqbuf_firstidx = 0; 4470 acb->rqbuf_lastidx = 0; 4471 acb->wqbuf_firstidx = 0; 4472 acb->wqbuf_lastidx = 0; 4473 pQbuffer = acb->rqbuffer; 4474 (void) memset(pQbuffer, 0, sizeof (struct QBUFFER)); 4475 pQbuffer = acb->wqbuffer; 4476 (void) memset(pQbuffer, 0, sizeof (struct QBUFFER)); 4477 pcmdmessagefld->cmdmessage.ReturnCode = 4478 ARCMSR_MESSAGE_RETURNCODE_OK; 4479 break; 4480 4481 case ARCMSR_MESSAGE_REQUEST_RETURN_CODE_3F: 4482 pcmdmessagefld->cmdmessage.ReturnCode = 4483 ARCMSR_MESSAGE_RETURNCODE_3F; 4484 break; 4485 /* 4486 * Not supported - ARCMSR_MESSAGE_SAY_HELLO 4487 */ 4488 case ARCMSR_MESSAGE_SAY_GOODBYE: 4489 arcmsr_iop_parking(acb); 4490 break; 4491 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: 4492 switch (acb->adapter_type) { 4493 case ACB_ADAPTER_TYPE_A: 4494 arcmsr_flush_hba_cache(acb); 4495 break; 4496 case ACB_ADAPTER_TYPE_B: 4497 arcmsr_flush_hbb_cache(acb); 4498 break; 4499 case ACB_ADAPTER_TYPE_C: 4500 arcmsr_flush_hbc_cache(acb); 4501 break; 4502 } 4503 break; 4504 default: 4505 retvalue = ARCMSR_MESSAGE_FAIL; 4506 } 4507 4508 message_out: 4509 4510 return (retvalue); 4511 } 4512 4513 4514 4515 4516 static void 4517 arcmsr_pcidev_disattach(struct ACB *acb) 4518 { 4519 struct CCB *ccb; 4520 int i = 0; 4521 4522 /* disable all outbound interrupts */ 4523 (void) arcmsr_disable_allintr(acb); 4524 /* stop adapter background rebuild */ 4525 switch (acb->adapter_type) { 4526 case ACB_ADAPTER_TYPE_A: 4527 arcmsr_stop_hba_bgrb(acb); 4528 arcmsr_flush_hba_cache(acb); 4529 break; 4530 case ACB_ADAPTER_TYPE_B: 4531 arcmsr_stop_hbb_bgrb(acb); 4532 arcmsr_flush_hbb_cache(acb); 4533 break; 4534 case ACB_ADAPTER_TYPE_C: 4535 arcmsr_stop_hbc_bgrb(acb); 4536 arcmsr_flush_hbc_cache(acb); 4537 break; 4538 } 4539 /* abort all outstanding commands */ 4540 acb->acb_flags |= ACB_F_SCSISTOPADAPTER; 4541 acb->acb_flags &= ~ACB_F_IOP_INITED; 4542 4543 if (acb->ccboutstandingcount != 0) { 4544 /* clear and abort all outbound posted Q */ 4545 arcmsr_done4abort_postqueue(acb); 4546 /* talk to iop outstanding command aborted */ 4547 (void) arcmsr_abort_host_command(acb); 4548 4549 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) { 4550 ccb = acb->pccb_pool[i]; 4551 if (ccb->ccb_state == ARCMSR_CCB_START) { 4552 /* ccb->ccb_state = ARCMSR_CCB_ABORTED; */ 4553 ccb->pkt->pkt_reason = CMD_ABORTED; 4554 ccb->pkt->pkt_statistics |= STAT_ABORTED; 4555 arcmsr_ccb_complete(ccb, 1); 4556 } 4557 } 4558 } 4559 } 4560 4561 /* get firmware miscellaneous data */ 4562 static void 4563 arcmsr_get_hba_config(struct ACB *acb) 4564 { 4565 struct HBA_msgUnit *phbamu; 4566 4567 char *acb_firm_model; 4568 char *acb_firm_version; 4569 char *acb_device_map; 4570 char *iop_firm_model; 4571 char *iop_firm_version; 4572 char *iop_device_map; 4573 int count; 4574 4575 phbamu = (struct HBA_msgUnit *)acb->pmu; 4576 acb_firm_model = acb->firm_model; 4577 acb_firm_version = acb->firm_version; 4578 acb_device_map = acb->device_map; 4579 /* firm_model, 15 */ 4580 iop_firm_model = 4581 (char *)(&phbamu->msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); 4582 /* firm_version, 17 */ 4583 iop_firm_version = 4584 (char *)(&phbamu->msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); 4585 4586 /* device_map, 21 */ 4587 iop_device_map = 4588 (char *)(&phbamu->msgcode_rwbuffer[ARCMSR_FW_MAP_OFFSET]); 4589 4590 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 4591 &phbamu->inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 4592 4593 if (!arcmsr_hba_wait_msgint_ready(acb)) 4594 arcmsr_warn(acb, 4595 "timeout while waiting for adapter firmware " 4596 "miscellaneous data"); 4597 4598 count = 8; 4599 while (count) { 4600 *acb_firm_model = CHIP_REG_READ8(acb->reg_mu_acc_handle0, 4601 iop_firm_model); 4602 acb_firm_model++; 4603 iop_firm_model++; 4604 count--; 4605 } 4606 4607 count = 16; 4608 while (count) { 4609 *acb_firm_version = 4610 CHIP_REG_READ8(acb->reg_mu_acc_handle0, iop_firm_version); 4611 acb_firm_version++; 4612 iop_firm_version++; 4613 count--; 4614 } 4615 4616 count = 16; 4617 while (count) { 4618 *acb_device_map = 4619 CHIP_REG_READ8(acb->reg_mu_acc_handle0, iop_device_map); 4620 acb_device_map++; 4621 iop_device_map++; 4622 count--; 4623 } 4624 4625 arcmsr_log(acb, CE_CONT, "ARECA RAID FIRMWARE VERSION %s\n", 4626 acb->firm_version); 4627 4628 /* firm_request_len, 1 */ 4629 acb->firm_request_len = CHIP_REG_READ32(acb->reg_mu_acc_handle0, 4630 &phbamu->msgcode_rwbuffer[1]); 4631 /* firm_numbers_queue, 2 */ 4632 acb->firm_numbers_queue = CHIP_REG_READ32(acb->reg_mu_acc_handle0, 4633 &phbamu->msgcode_rwbuffer[2]); 4634 /* firm_sdram_size, 3 */ 4635 acb->firm_sdram_size = CHIP_REG_READ32(acb->reg_mu_acc_handle0, 4636 &phbamu->msgcode_rwbuffer[3]); 4637 /* firm_ide_channels, 4 */ 4638 acb->firm_ide_channels = CHIP_REG_READ32(acb->reg_mu_acc_handle0, 4639 &phbamu->msgcode_rwbuffer[4]); 4640 } 4641 4642 /* get firmware miscellaneous data */ 4643 static void 4644 arcmsr_get_hbb_config(struct ACB *acb) 4645 { 4646 struct HBB_msgUnit *phbbmu; 4647 char *acb_firm_model; 4648 char *acb_firm_version; 4649 char *acb_device_map; 4650 char *iop_firm_model; 4651 char *iop_firm_version; 4652 char *iop_device_map; 4653 int count; 4654 4655 phbbmu = (struct HBB_msgUnit *)acb->pmu; 4656 acb_firm_model = acb->firm_model; 4657 acb_firm_version = acb->firm_version; 4658 acb_device_map = acb->device_map; 4659 /* firm_model, 15 */ 4660 iop_firm_model = (char *) 4661 (&phbbmu->hbb_rwbuffer->msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); 4662 /* firm_version, 17 */ 4663 iop_firm_version = (char *) 4664 (&phbbmu->hbb_rwbuffer->msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); 4665 /* device_map, 21 */ 4666 iop_device_map = (char *) 4667 (&phbbmu->hbb_rwbuffer->msgcode_rwbuffer[ARCMSR_FW_MAP_OFFSET]); 4668 4669 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 4670 &phbbmu->hbb_doorbell->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 4671 4672 if (!arcmsr_hbb_wait_msgint_ready(acb)) 4673 arcmsr_warn(acb, 4674 "timeout while waiting for adapter firmware " 4675 "miscellaneous data"); 4676 4677 count = 8; 4678 while (count) { 4679 *acb_firm_model = 4680 CHIP_REG_READ8(acb->reg_mu_acc_handle1, iop_firm_model); 4681 acb_firm_model++; 4682 iop_firm_model++; 4683 count--; 4684 } 4685 count = 16; 4686 while (count) { 4687 *acb_firm_version = 4688 CHIP_REG_READ8(acb->reg_mu_acc_handle1, iop_firm_version); 4689 acb_firm_version++; 4690 iop_firm_version++; 4691 count--; 4692 } 4693 count = 16; 4694 while (count) { 4695 *acb_device_map = 4696 CHIP_REG_READ8(acb->reg_mu_acc_handle1, iop_device_map); 4697 acb_device_map++; 4698 iop_device_map++; 4699 count--; 4700 } 4701 4702 arcmsr_log(acb, CE_CONT, "ARECA RAID FIRMWARE VERSION %s\n", 4703 acb->firm_version); 4704 4705 /* firm_request_len, 1 */ 4706 acb->firm_request_len = CHIP_REG_READ32(acb->reg_mu_acc_handle1, 4707 &phbbmu->hbb_rwbuffer->msgcode_rwbuffer[1]); 4708 /* firm_numbers_queue, 2 */ 4709 acb->firm_numbers_queue = CHIP_REG_READ32(acb->reg_mu_acc_handle1, 4710 &phbbmu->hbb_rwbuffer->msgcode_rwbuffer[2]); 4711 /* firm_sdram_size, 3 */ 4712 acb->firm_sdram_size = CHIP_REG_READ32(acb->reg_mu_acc_handle1, 4713 &phbbmu->hbb_rwbuffer->msgcode_rwbuffer[3]); 4714 /* firm_ide_channels, 4 */ 4715 acb->firm_ide_channels = CHIP_REG_READ32(acb->reg_mu_acc_handle1, 4716 &phbbmu->hbb_rwbuffer->msgcode_rwbuffer[4]); 4717 } 4718 4719 4720 /* get firmware miscellaneous data */ 4721 static void 4722 arcmsr_get_hbc_config(struct ACB *acb) 4723 { 4724 struct HBC_msgUnit *phbcmu; 4725 4726 char *acb_firm_model; 4727 char *acb_firm_version; 4728 char *acb_device_map; 4729 char *iop_firm_model; 4730 char *iop_firm_version; 4731 char *iop_device_map; 4732 int count; 4733 4734 phbcmu = (struct HBC_msgUnit *)acb->pmu; 4735 acb_firm_model = acb->firm_model; 4736 acb_firm_version = acb->firm_version; 4737 acb_device_map = acb->device_map; 4738 /* firm_model, 15 */ 4739 iop_firm_model = 4740 (char *)(&phbcmu->msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); 4741 /* firm_version, 17 */ 4742 iop_firm_version = 4743 (char *)(&phbcmu->msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); 4744 /* device_map, 21 */ 4745 iop_device_map = 4746 (char *)(&phbcmu->msgcode_rwbuffer[ARCMSR_FW_MAP_OFFSET]); 4747 /* post "get config" instruction */ 4748 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 4749 &phbcmu->inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 4750 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 4751 &phbcmu->inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 4752 if (!arcmsr_hbc_wait_msgint_ready(acb)) 4753 arcmsr_warn(acb, 4754 "timeout while waiting for adapter firmware " 4755 "miscellaneous data"); 4756 count = 8; 4757 while (count) { 4758 *acb_firm_model = 4759 CHIP_REG_READ8(acb->reg_mu_acc_handle0, iop_firm_model); 4760 acb_firm_model++; 4761 iop_firm_model++; 4762 count--; 4763 } 4764 4765 count = 16; 4766 while (count) { 4767 *acb_firm_version = 4768 CHIP_REG_READ8(acb->reg_mu_acc_handle0, iop_firm_version); 4769 acb_firm_version++; 4770 iop_firm_version++; 4771 count--; 4772 } 4773 4774 count = 16; 4775 while (count) { 4776 *acb_device_map = 4777 CHIP_REG_READ8(acb->reg_mu_acc_handle0, iop_device_map); 4778 acb_device_map++; 4779 iop_device_map++; 4780 count--; 4781 } 4782 4783 arcmsr_log(acb, CE_CONT, "ARECA RAID FIRMWARE VERSION %s\n", 4784 acb->firm_version); 4785 4786 /* firm_request_len, 1, 04-07 */ 4787 acb->firm_request_len = CHIP_REG_READ32(acb->reg_mu_acc_handle0, 4788 &phbcmu->msgcode_rwbuffer[1]); 4789 /* firm_numbers_queue, 2, 08-11 */ 4790 acb->firm_numbers_queue = CHIP_REG_READ32(acb->reg_mu_acc_handle0, 4791 &phbcmu->msgcode_rwbuffer[2]); 4792 /* firm_sdram_size, 3, 12-15 */ 4793 acb->firm_sdram_size = CHIP_REG_READ32(acb->reg_mu_acc_handle0, 4794 &phbcmu->msgcode_rwbuffer[3]); 4795 /* firm_ide_channels, 4, 16-19 */ 4796 acb->firm_ide_channels = CHIP_REG_READ32(acb->reg_mu_acc_handle0, 4797 &phbcmu->msgcode_rwbuffer[4]); 4798 /* firm_cfg_version, 25, 100-103 */ 4799 acb->firm_cfg_version = CHIP_REG_READ32(acb->reg_mu_acc_handle0, 4800 &phbcmu->msgcode_rwbuffer[25]); 4801 } 4802 4803 4804 /* start background rebuild */ 4805 static void 4806 arcmsr_start_hba_bgrb(struct ACB *acb) 4807 { 4808 struct HBA_msgUnit *phbamu; 4809 4810 phbamu = (struct HBA_msgUnit *)acb->pmu; 4811 4812 acb->acb_flags |= ACB_F_MSG_START_BGRB; 4813 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 4814 &phbamu->inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 4815 4816 if (!arcmsr_hba_wait_msgint_ready(acb)) 4817 arcmsr_warn(acb, 4818 "timeout while waiting for background rebuild to start"); 4819 } 4820 4821 4822 static void 4823 arcmsr_start_hbb_bgrb(struct ACB *acb) 4824 { 4825 struct HBB_msgUnit *phbbmu; 4826 4827 phbbmu = (struct HBB_msgUnit *)acb->pmu; 4828 4829 acb->acb_flags |= ACB_F_MSG_START_BGRB; 4830 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 4831 &phbbmu->hbb_doorbell->drv2iop_doorbell, 4832 ARCMSR_MESSAGE_START_BGRB); 4833 4834 if (!arcmsr_hbb_wait_msgint_ready(acb)) 4835 arcmsr_warn(acb, 4836 "timeout while waiting for background rebuild to start"); 4837 } 4838 4839 4840 static void 4841 arcmsr_start_hbc_bgrb(struct ACB *acb) 4842 { 4843 struct HBC_msgUnit *phbcmu; 4844 4845 phbcmu = (struct HBC_msgUnit *)acb->pmu; 4846 4847 acb->acb_flags |= ACB_F_MSG_START_BGRB; 4848 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 4849 &phbcmu->inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 4850 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 4851 &phbcmu->inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 4852 if (!arcmsr_hbc_wait_msgint_ready(acb)) 4853 arcmsr_warn(acb, 4854 "timeout while waiting for background rebuild to start"); 4855 } 4856 4857 static void 4858 arcmsr_polling_hba_ccbdone(struct ACB *acb, struct CCB *poll_ccb) 4859 { 4860 struct HBA_msgUnit *phbamu; 4861 struct CCB *ccb; 4862 boolean_t error; 4863 uint32_t flag_ccb, outbound_intstatus, intmask_org; 4864 boolean_t poll_ccb_done = B_FALSE; 4865 uint32_t poll_count = 0; 4866 4867 4868 phbamu = (struct HBA_msgUnit *)acb->pmu; 4869 4870 polling_ccb_retry: 4871 /* TODO: Use correct offset and size for syncing? */ 4872 if (ddi_dma_sync(acb->ccbs_pool_handle, 0, 0, 4873 DDI_DMA_SYNC_FORKERNEL) != DDI_SUCCESS) 4874 return; 4875 intmask_org = arcmsr_disable_allintr(acb); 4876 4877 for (;;) { 4878 if ((flag_ccb = CHIP_REG_READ32(acb->reg_mu_acc_handle0, 4879 &phbamu->outbound_queueport)) == 0xFFFFFFFF) { 4880 if (poll_ccb_done) { 4881 /* chip FIFO no ccb for completion already */ 4882 break; 4883 } else { 4884 drv_usecwait(25000); 4885 if ((poll_count > 100) && (poll_ccb != NULL)) { 4886 break; 4887 } 4888 if (acb->ccboutstandingcount == 0) { 4889 break; 4890 } 4891 poll_count++; 4892 outbound_intstatus = 4893 CHIP_REG_READ32(acb->reg_mu_acc_handle0, 4894 &phbamu->outbound_intstatus) & 4895 acb->outbound_int_enable; 4896 4897 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 4898 &phbamu->outbound_intstatus, 4899 outbound_intstatus); /* clear interrupt */ 4900 } 4901 } 4902 4903 /* frame must be 32 bytes aligned */ 4904 ccb = NumToPtr((acb->vir2phy_offset + (flag_ccb << 5))); 4905 4906 /* check if command done with no error */ 4907 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? 4908 B_TRUE : B_FALSE; 4909 if (poll_ccb != NULL) 4910 poll_ccb_done = (ccb == poll_ccb) ? B_TRUE : B_FALSE; 4911 4912 if (ccb->acb != acb) { 4913 arcmsr_warn(acb, "ccb got a wrong acb!"); 4914 continue; 4915 } 4916 if (ccb->ccb_state != ARCMSR_CCB_START) { 4917 if (ccb->ccb_state & ARCMSR_ABNORMAL_MASK) { 4918 ccb->ccb_state |= ARCMSR_CCB_BACK; 4919 ccb->pkt->pkt_reason = CMD_ABORTED; 4920 ccb->pkt->pkt_statistics |= STAT_ABORTED; 4921 arcmsr_ccb_complete(ccb, 1); 4922 continue; 4923 } 4924 arcmsr_report_ccb_state(acb, ccb, error); 4925 arcmsr_warn(acb, 4926 "polling op got unexpected ccb command done"); 4927 continue; 4928 } 4929 arcmsr_report_ccb_state(acb, ccb, error); 4930 } /* drain reply FIFO */ 4931 arcmsr_enable_allintr(acb, intmask_org); 4932 } 4933 4934 4935 static void 4936 arcmsr_polling_hbb_ccbdone(struct ACB *acb, struct CCB *poll_ccb) 4937 { 4938 struct HBB_msgUnit *phbbmu; 4939 struct CCB *ccb; 4940 uint32_t flag_ccb, intmask_org; 4941 boolean_t error; 4942 uint32_t poll_count = 0; 4943 int index; 4944 boolean_t poll_ccb_done = B_FALSE; 4945 4946 4947 phbbmu = (struct HBB_msgUnit *)acb->pmu; 4948 4949 4950 polling_ccb_retry: 4951 /* Use correct offset and size for syncing */ 4952 if (ddi_dma_sync(acb->ccbs_pool_handle, 0, 0, 4953 DDI_DMA_SYNC_FORKERNEL) != DDI_SUCCESS) 4954 return; 4955 4956 intmask_org = arcmsr_disable_allintr(acb); 4957 4958 for (;;) { 4959 index = phbbmu->doneq_index; 4960 if ((flag_ccb = phbbmu->done_qbuffer[index]) == 0) { 4961 if (poll_ccb_done) { 4962 /* chip FIFO no ccb for completion already */ 4963 break; 4964 } else { 4965 drv_usecwait(25000); 4966 if ((poll_count > 100) && (poll_ccb != NULL)) 4967 break; 4968 if (acb->ccboutstandingcount == 0) 4969 break; 4970 poll_count++; 4971 /* clear doorbell interrupt */ 4972 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 4973 &phbbmu->hbb_doorbell->iop2drv_doorbell, 4974 ARCMSR_DOORBELL_INT_CLEAR_PATTERN); 4975 } 4976 } 4977 4978 phbbmu->done_qbuffer[index] = 0; 4979 index++; 4980 /* if last index number set it to 0 */ 4981 index %= ARCMSR_MAX_HBB_POSTQUEUE; 4982 phbbmu->doneq_index = index; 4983 /* check if command done with no error */ 4984 /* frame must be 32 bytes aligned */ 4985 ccb = NumToPtr((acb->vir2phy_offset + (flag_ccb << 5))); 4986 4987 /* check if command done with no error */ 4988 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? 4989 B_TRUE : B_FALSE; 4990 4991 if (poll_ccb != NULL) 4992 poll_ccb_done = (ccb == poll_ccb) ? B_TRUE : B_FALSE; 4993 if (ccb->acb != acb) { 4994 arcmsr_warn(acb, "ccb got a wrong acb!"); 4995 continue; 4996 } 4997 if (ccb->ccb_state != ARCMSR_CCB_START) { 4998 if (ccb->ccb_state & ARCMSR_ABNORMAL_MASK) { 4999 ccb->ccb_state |= ARCMSR_CCB_BACK; 5000 ccb->pkt->pkt_reason = CMD_ABORTED; 5001 ccb->pkt->pkt_statistics |= STAT_ABORTED; 5002 arcmsr_ccb_complete(ccb, 1); 5003 continue; 5004 } 5005 arcmsr_report_ccb_state(acb, ccb, error); 5006 arcmsr_warn(acb, 5007 "polling op got unexpect ccb command done"); 5008 continue; 5009 } 5010 arcmsr_report_ccb_state(acb, ccb, error); 5011 } /* drain reply FIFO */ 5012 arcmsr_enable_allintr(acb, intmask_org); 5013 } 5014 5015 5016 static void 5017 arcmsr_polling_hbc_ccbdone(struct ACB *acb, struct CCB *poll_ccb) 5018 { 5019 5020 struct HBC_msgUnit *phbcmu; 5021 struct CCB *ccb; 5022 boolean_t error; 5023 uint32_t ccb_cdb_phy; 5024 uint32_t flag_ccb, intmask_org; 5025 boolean_t poll_ccb_done = B_FALSE; 5026 uint32_t poll_count = 0; 5027 5028 5029 phbcmu = (struct HBC_msgUnit *)acb->pmu; 5030 5031 polling_ccb_retry: 5032 5033 /* Use correct offset and size for syncing */ 5034 if (ddi_dma_sync(acb->ccbs_pool_handle, 0, 0, 5035 DDI_DMA_SYNC_FORKERNEL) != DDI_SUCCESS) 5036 return; 5037 5038 intmask_org = arcmsr_disable_allintr(acb); 5039 5040 for (;;) { 5041 if (!(CHIP_REG_READ32(acb->reg_mu_acc_handle0, 5042 &phbcmu->host_int_status) & 5043 ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) { 5044 5045 if (poll_ccb_done) { 5046 /* chip FIFO no ccb for completion already */ 5047 break; 5048 } else { 5049 drv_usecwait(25000); 5050 if ((poll_count > 100) && (poll_ccb != NULL)) { 5051 break; 5052 } 5053 if (acb->ccboutstandingcount == 0) { 5054 break; 5055 } 5056 poll_count++; 5057 } 5058 } 5059 flag_ccb = CHIP_REG_READ32(acb->reg_mu_acc_handle0, 5060 &phbcmu->outbound_queueport_low); 5061 /* frame must be 32 bytes aligned */ 5062 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0); 5063 /* the CDB is the first field of the CCB */ 5064 ccb = NumToPtr((acb->vir2phy_offset + ccb_cdb_phy)); 5065 5066 /* check if command done with no error */ 5067 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? 5068 B_TRUE : B_FALSE; 5069 if (poll_ccb != NULL) 5070 poll_ccb_done = (ccb == poll_ccb) ? B_TRUE : B_FALSE; 5071 5072 if (ccb->acb != acb) { 5073 arcmsr_warn(acb, "ccb got a wrong acb!"); 5074 continue; 5075 } 5076 if (ccb->ccb_state != ARCMSR_CCB_START) { 5077 if (ccb->ccb_state & ARCMSR_ABNORMAL_MASK) { 5078 ccb->ccb_state |= ARCMSR_CCB_BACK; 5079 ccb->pkt->pkt_reason = CMD_ABORTED; 5080 ccb->pkt->pkt_statistics |= STAT_ABORTED; 5081 arcmsr_ccb_complete(ccb, 1); 5082 continue; 5083 } 5084 arcmsr_report_ccb_state(acb, ccb, error); 5085 arcmsr_warn(acb, 5086 "polling op got unexpected ccb command done"); 5087 continue; 5088 } 5089 arcmsr_report_ccb_state(acb, ccb, error); 5090 } /* drain reply FIFO */ 5091 arcmsr_enable_allintr(acb, intmask_org); 5092 } 5093 5094 5095 /* 5096 * Function: arcmsr_hba_hardware_reset() 5097 * Bug Fix for Intel IOP cause firmware hang on. 5098 * and kernel panic 5099 */ 5100 static void 5101 arcmsr_hba_hardware_reset(struct ACB *acb) 5102 { 5103 struct HBA_msgUnit *phbamu; 5104 uint8_t value[64]; 5105 int i; 5106 5107 phbamu = (struct HBA_msgUnit *)acb->pmu; 5108 /* backup pci config data */ 5109 for (i = 0; i < 64; i++) { 5110 value[i] = pci_config_get8(acb->pci_acc_handle, i); 5111 } 5112 /* hardware reset signal */ 5113 if ((PCI_DEVICE_ID_ARECA_1680 == 5114 pci_config_get16(acb->pci_acc_handle, PCI_CONF_DEVID))) { 5115 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5116 &phbamu->reserved1[0], 0x00000003); 5117 } else { 5118 pci_config_put8(acb->pci_acc_handle, 0x84, 0x20); 5119 } 5120 drv_usecwait(1000000); 5121 /* write back pci config data */ 5122 for (i = 0; i < 64; i++) { 5123 pci_config_put8(acb->pci_acc_handle, i, value[i]); 5124 } 5125 drv_usecwait(1000000); 5126 } 5127 5128 /* 5129 * Function: arcmsr_abort_host_command 5130 */ 5131 static uint8_t 5132 arcmsr_abort_host_command(struct ACB *acb) 5133 { 5134 uint8_t rtnval = 0; 5135 5136 switch (acb->adapter_type) { 5137 case ACB_ADAPTER_TYPE_A: 5138 rtnval = arcmsr_abort_hba_allcmd(acb); 5139 break; 5140 case ACB_ADAPTER_TYPE_B: 5141 rtnval = arcmsr_abort_hbb_allcmd(acb); 5142 break; 5143 case ACB_ADAPTER_TYPE_C: 5144 rtnval = arcmsr_abort_hbc_allcmd(acb); 5145 break; 5146 } 5147 return (rtnval); 5148 } 5149 5150 /* 5151 * Function: arcmsr_handle_iop_bus_hold 5152 */ 5153 static void 5154 arcmsr_handle_iop_bus_hold(struct ACB *acb) 5155 { 5156 5157 switch (acb->adapter_type) { 5158 case ACB_ADAPTER_TYPE_A: 5159 { 5160 struct HBA_msgUnit *phbamu; 5161 int retry_count = 0; 5162 5163 acb->timeout_count = 0; 5164 phbamu = (struct HBA_msgUnit *)acb->pmu; 5165 arcmsr_hba_hardware_reset(acb); 5166 acb->acb_flags &= ~ACB_F_IOP_INITED; 5167 sleep_again: 5168 drv_usecwait(1000000); 5169 if ((CHIP_REG_READ32(acb->reg_mu_acc_handle0, 5170 &phbamu->outbound_msgaddr1) & 5171 ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) { 5172 if (retry_count > 60) { 5173 arcmsr_warn(acb, 5174 "waiting for hardware" 5175 "bus reset return, RETRY TERMINATED!!"); 5176 return; 5177 } 5178 retry_count++; 5179 goto sleep_again; 5180 } 5181 arcmsr_iop_init(acb); 5182 break; 5183 } 5184 5185 } 5186 } 5187 5188 static void 5189 arcmsr_iop2drv_data_wrote_handle(struct ACB *acb) 5190 { 5191 struct QBUFFER *prbuffer; 5192 uint8_t *pQbuffer; 5193 uint8_t *iop_data; 5194 int my_empty_len, iop_len; 5195 int rqbuf_firstidx, rqbuf_lastidx; 5196 5197 /* check this iop data if overflow my rqbuffer */ 5198 rqbuf_lastidx = acb->rqbuf_lastidx; 5199 rqbuf_firstidx = acb->rqbuf_firstidx; 5200 prbuffer = arcmsr_get_iop_rqbuffer(acb); 5201 iop_data = (uint8_t *)prbuffer->data; 5202 iop_len = prbuffer->data_len; 5203 my_empty_len = (rqbuf_firstidx-rqbuf_lastidx - 1) & 5204 (ARCMSR_MAX_QBUFFER - 1); 5205 5206 if (my_empty_len >= iop_len) { 5207 while (iop_len > 0) { 5208 pQbuffer = &acb->rqbuffer[rqbuf_lastidx]; 5209 (void) memcpy(pQbuffer, iop_data, 1); 5210 rqbuf_lastidx++; 5211 /* if last index number set it to 0 */ 5212 rqbuf_lastidx %= ARCMSR_MAX_QBUFFER; 5213 iop_data++; 5214 iop_len--; 5215 } 5216 acb->rqbuf_lastidx = rqbuf_lastidx; 5217 arcmsr_iop_message_read(acb); 5218 /* signature, let IOP know data has been read */ 5219 } else { 5220 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 5221 } 5222 } 5223 5224 5225 5226 static void 5227 arcmsr_iop2drv_data_read_handle(struct ACB *acb) 5228 { 5229 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ; 5230 /* 5231 * check if there are any mail packages from user space program 5232 * in my post bag, now is the time to send them into Areca's firmware 5233 */ 5234 5235 if (acb->wqbuf_firstidx != acb->wqbuf_lastidx) { 5236 5237 uint8_t *pQbuffer; 5238 struct QBUFFER *pwbuffer; 5239 uint8_t *iop_data; 5240 int allxfer_len = 0; 5241 5242 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 5243 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 5244 iop_data = (uint8_t *)pwbuffer->data; 5245 5246 while ((acb->wqbuf_firstidx != acb->wqbuf_lastidx) && 5247 (allxfer_len < 124)) { 5248 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstidx]; 5249 (void) memcpy(iop_data, pQbuffer, 1); 5250 acb->wqbuf_firstidx++; 5251 /* if last index number set it to 0 */ 5252 acb->wqbuf_firstidx %= ARCMSR_MAX_QBUFFER; 5253 iop_data++; 5254 allxfer_len++; 5255 } 5256 pwbuffer->data_len = allxfer_len; 5257 /* 5258 * push inbound doorbell, tell iop driver data write ok 5259 * await reply on next hwinterrupt for next Qbuffer post 5260 */ 5261 arcmsr_iop_message_wrote(acb); 5262 } 5263 5264 if (acb->wqbuf_firstidx == acb->wqbuf_lastidx) 5265 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED; 5266 } 5267 5268 5269 static void 5270 arcmsr_hba_doorbell_isr(struct ACB *acb) 5271 { 5272 uint32_t outbound_doorbell; 5273 struct HBA_msgUnit *phbamu; 5274 5275 phbamu = (struct HBA_msgUnit *)acb->pmu; 5276 5277 /* 5278 * Maybe here we need to check wrqbuffer_lock is locked or not 5279 * DOORBELL: ding! dong! 5280 * check if there are any mail need to pack from firmware 5281 */ 5282 5283 outbound_doorbell = CHIP_REG_READ32(acb->reg_mu_acc_handle0, 5284 &phbamu->outbound_doorbell); 5285 /* clear doorbell interrupt */ 5286 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5287 &phbamu->outbound_doorbell, outbound_doorbell); 5288 5289 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) 5290 arcmsr_iop2drv_data_wrote_handle(acb); 5291 5292 5293 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) 5294 arcmsr_iop2drv_data_read_handle(acb); 5295 } 5296 5297 5298 5299 static void 5300 arcmsr_hbc_doorbell_isr(struct ACB *acb) 5301 { 5302 uint32_t outbound_doorbell; 5303 struct HBC_msgUnit *phbcmu; 5304 5305 phbcmu = (struct HBC_msgUnit *)acb->pmu; 5306 5307 /* 5308 * Maybe here we need to check wrqbuffer_lock is locked or not 5309 * DOORBELL: ding! dong! 5310 * check if there are any mail need to pick from firmware 5311 */ 5312 5313 outbound_doorbell = CHIP_REG_READ32(acb->reg_mu_acc_handle0, 5314 &phbcmu->outbound_doorbell); 5315 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5316 &phbcmu->outbound_doorbell_clear, 5317 outbound_doorbell); /* clear interrupt */ 5318 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) { 5319 arcmsr_iop2drv_data_wrote_handle(acb); 5320 } 5321 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) { 5322 arcmsr_iop2drv_data_read_handle(acb); 5323 } 5324 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 5325 /* messenger of "driver to iop commands" */ 5326 arcmsr_hbc_message_isr(acb); 5327 } 5328 } 5329 5330 5331 static void 5332 arcmsr_hba_message_isr(struct ACB *acb) 5333 { 5334 struct HBA_msgUnit *phbamu = (struct HBA_msgUnit *)acb->pmu; 5335 uint32_t *signature = (&phbamu->msgcode_rwbuffer[0]); 5336 uint32_t outbound_message; 5337 5338 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5339 &phbamu->outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT); 5340 5341 outbound_message = CHIP_REG_READ32(acb->reg_mu_acc_handle0, signature); 5342 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 5343 if ((ddi_taskq_dispatch(acb->taskq, 5344 (void (*)(void *))arcmsr_dr_handle, 5345 acb, DDI_NOSLEEP)) != DDI_SUCCESS) { 5346 arcmsr_warn(acb, "DR task start failed"); 5347 } 5348 } 5349 5350 static void 5351 arcmsr_hbb_message_isr(struct ACB *acb) 5352 { 5353 struct HBB_msgUnit *phbbmu = (struct HBB_msgUnit *)acb->pmu; 5354 uint32_t *signature = (&phbbmu->hbb_rwbuffer->msgcode_rwbuffer[0]); 5355 uint32_t outbound_message; 5356 5357 /* clear interrupts */ 5358 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5359 &phbbmu->hbb_doorbell->iop2drv_doorbell, 5360 ARCMSR_MESSAGE_INT_CLEAR_PATTERN); 5361 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5362 &phbbmu->hbb_doorbell->drv2iop_doorbell, 5363 ARCMSR_DRV2IOP_END_OF_INTERRUPT); 5364 5365 outbound_message = CHIP_REG_READ32(acb->reg_mu_acc_handle0, signature); 5366 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 5367 if ((ddi_taskq_dispatch(acb->taskq, 5368 (void (*)(void *))arcmsr_dr_handle, 5369 acb, DDI_NOSLEEP)) != DDI_SUCCESS) { 5370 arcmsr_warn(acb, "DR task start failed"); 5371 } 5372 } 5373 5374 static void 5375 arcmsr_hbc_message_isr(struct ACB *acb) 5376 { 5377 struct HBC_msgUnit *phbcmu = (struct HBC_msgUnit *)acb->pmu; 5378 uint32_t *signature = (&phbcmu->msgcode_rwbuffer[0]); 5379 uint32_t outbound_message; 5380 5381 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5382 &phbcmu->outbound_doorbell_clear, 5383 ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR); 5384 5385 outbound_message = CHIP_REG_READ32(acb->reg_mu_acc_handle0, signature); 5386 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 5387 if ((ddi_taskq_dispatch(acb->taskq, 5388 (void (*)(void *))arcmsr_dr_handle, 5389 acb, DDI_NOSLEEP)) != DDI_SUCCESS) { 5390 arcmsr_warn(acb, "DR task start failed"); 5391 } 5392 } 5393 5394 5395 static void 5396 arcmsr_hba_postqueue_isr(struct ACB *acb) 5397 { 5398 5399 struct HBA_msgUnit *phbamu; 5400 struct CCB *ccb; 5401 uint32_t flag_ccb; 5402 boolean_t error; 5403 5404 phbamu = (struct HBA_msgUnit *)acb->pmu; 5405 5406 /* areca cdb command done */ 5407 /* Use correct offset and size for syncing */ 5408 (void) ddi_dma_sync(acb->ccbs_pool_handle, 0, 0, 5409 DDI_DMA_SYNC_FORKERNEL); 5410 5411 while ((flag_ccb = CHIP_REG_READ32(acb->reg_mu_acc_handle0, 5412 &phbamu->outbound_queueport)) != 0xFFFFFFFF) { 5413 /* frame must be 32 bytes aligned */ 5414 ccb = NumToPtr((acb->vir2phy_offset+(flag_ccb << 5))); 5415 /* check if command done with no error */ 5416 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? 5417 B_TRUE : B_FALSE; 5418 arcmsr_drain_donequeue(acb, ccb, error); 5419 } /* drain reply FIFO */ 5420 } 5421 5422 5423 static void 5424 arcmsr_hbb_postqueue_isr(struct ACB *acb) 5425 { 5426 struct HBB_msgUnit *phbbmu; 5427 struct CCB *ccb; 5428 uint32_t flag_ccb; 5429 boolean_t error; 5430 int index; 5431 5432 phbbmu = (struct HBB_msgUnit *)acb->pmu; 5433 5434 /* areca cdb command done */ 5435 index = phbbmu->doneq_index; 5436 if (ddi_dma_sync(acb->ccbs_pool_handle, 0, 0, 5437 DDI_DMA_SYNC_FORKERNEL) != DDI_SUCCESS) 5438 return; 5439 while ((flag_ccb = phbbmu->done_qbuffer[index]) != 0) { 5440 phbbmu->done_qbuffer[index] = 0; 5441 /* frame must be 32 bytes aligned */ 5442 5443 /* the CDB is the first field of the CCB */ 5444 ccb = NumToPtr((acb->vir2phy_offset + (flag_ccb << 5))); 5445 5446 /* check if command done with no error */ 5447 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? 5448 B_TRUE : B_FALSE; 5449 arcmsr_drain_donequeue(acb, ccb, error); 5450 index++; 5451 /* if last index number set it to 0 */ 5452 index %= ARCMSR_MAX_HBB_POSTQUEUE; 5453 phbbmu->doneq_index = index; 5454 } /* drain reply FIFO */ 5455 } 5456 5457 5458 static void 5459 arcmsr_hbc_postqueue_isr(struct ACB *acb) 5460 { 5461 5462 struct HBC_msgUnit *phbcmu; 5463 struct CCB *ccb; 5464 uint32_t flag_ccb, ccb_cdb_phy, throttling = 0; 5465 boolean_t error; 5466 5467 phbcmu = (struct HBC_msgUnit *)acb->pmu; 5468 /* areca cdb command done */ 5469 /* Use correct offset and size for syncing */ 5470 (void) ddi_dma_sync(acb->ccbs_pool_handle, 0, 0, 5471 DDI_DMA_SYNC_FORKERNEL); 5472 5473 while (CHIP_REG_READ32(acb->reg_mu_acc_handle0, 5474 &phbcmu->host_int_status) & 5475 ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) { 5476 /* check if command done with no error */ 5477 flag_ccb = CHIP_REG_READ32(acb->reg_mu_acc_handle0, 5478 &phbcmu->outbound_queueport_low); 5479 /* frame must be 32 bytes aligned */ 5480 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0); 5481 5482 /* the CDB is the first field of the CCB */ 5483 ccb = NumToPtr((acb->vir2phy_offset + ccb_cdb_phy)); 5484 5485 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? 5486 B_TRUE : B_FALSE; 5487 /* check if command done with no error */ 5488 arcmsr_drain_donequeue(acb, ccb, error); 5489 if (throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) { 5490 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5491 &phbcmu->inbound_doorbell, 5492 ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING); 5493 break; 5494 } 5495 throttling++; 5496 } /* drain reply FIFO */ 5497 } 5498 5499 5500 static uint_t 5501 arcmsr_handle_hba_isr(struct ACB *acb) 5502 { 5503 uint32_t outbound_intstatus; 5504 struct HBA_msgUnit *phbamu; 5505 5506 phbamu = (struct HBA_msgUnit *)acb->pmu; 5507 5508 outbound_intstatus = CHIP_REG_READ32(acb->reg_mu_acc_handle0, 5509 &phbamu->outbound_intstatus) & acb->outbound_int_enable; 5510 5511 if (outbound_intstatus == 0) /* it must be a shared irq */ 5512 return (DDI_INTR_UNCLAIMED); 5513 5514 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, &phbamu->outbound_intstatus, 5515 outbound_intstatus); /* clear interrupt */ 5516 5517 /* MU doorbell interrupts */ 5518 5519 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) 5520 arcmsr_hba_doorbell_isr(acb); 5521 5522 /* MU post queue interrupts */ 5523 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) 5524 arcmsr_hba_postqueue_isr(acb); 5525 5526 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 5527 arcmsr_hba_message_isr(acb); 5528 } 5529 5530 return (DDI_INTR_CLAIMED); 5531 } 5532 5533 5534 static uint_t 5535 arcmsr_handle_hbb_isr(struct ACB *acb) 5536 { 5537 uint32_t outbound_doorbell; 5538 struct HBB_msgUnit *phbbmu; 5539 5540 5541 phbbmu = (struct HBB_msgUnit *)acb->pmu; 5542 5543 outbound_doorbell = CHIP_REG_READ32(acb->reg_mu_acc_handle0, 5544 &phbbmu->hbb_doorbell->iop2drv_doorbell) & acb->outbound_int_enable; 5545 5546 if (outbound_doorbell == 0) /* it must be a shared irq */ 5547 return (DDI_INTR_UNCLAIMED); 5548 5549 /* clear doorbell interrupt */ 5550 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5551 &phbbmu->hbb_doorbell->iop2drv_doorbell, ~outbound_doorbell); 5552 /* wait a cycle */ 5553 (void) CHIP_REG_READ32(acb->reg_mu_acc_handle0, 5554 &phbbmu->hbb_doorbell->iop2drv_doorbell); 5555 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5556 &phbbmu->hbb_doorbell->drv2iop_doorbell, 5557 ARCMSR_DRV2IOP_END_OF_INTERRUPT); 5558 5559 /* MU ioctl transfer doorbell interrupts */ 5560 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) 5561 arcmsr_iop2drv_data_wrote_handle(acb); 5562 5563 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) 5564 arcmsr_iop2drv_data_read_handle(acb); 5565 5566 /* MU post queue interrupts */ 5567 if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) 5568 arcmsr_hbb_postqueue_isr(acb); 5569 5570 /* MU message interrupt */ 5571 5572 if (outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 5573 arcmsr_hbb_message_isr(acb); 5574 } 5575 5576 return (DDI_INTR_CLAIMED); 5577 } 5578 5579 static uint_t 5580 arcmsr_handle_hbc_isr(struct ACB *acb) 5581 { 5582 uint32_t host_interrupt_status; 5583 struct HBC_msgUnit *phbcmu; 5584 5585 phbcmu = (struct HBC_msgUnit *)acb->pmu; 5586 /* check outbound intstatus */ 5587 host_interrupt_status= 5588 CHIP_REG_READ32(acb->reg_mu_acc_handle0, &phbcmu->host_int_status); 5589 if (host_interrupt_status == 0) /* it must be share irq */ 5590 return (DDI_INTR_UNCLAIMED); 5591 /* MU ioctl transfer doorbell interrupts */ 5592 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) { 5593 /* messenger of "ioctl message read write" */ 5594 arcmsr_hbc_doorbell_isr(acb); 5595 } 5596 /* MU post queue interrupts */ 5597 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) { 5598 /* messenger of "scsi commands" */ 5599 arcmsr_hbc_postqueue_isr(acb); 5600 } 5601 return (DDI_INTR_CLAIMED); 5602 } 5603 5604 static uint_t 5605 arcmsr_intr_handler(caddr_t arg, caddr_t arg2) 5606 { 5607 struct ACB *acb = (void *)arg; 5608 struct CCB *ccb; 5609 uint_t retrn = DDI_INTR_UNCLAIMED; 5610 _NOTE(ARGUNUSED(arg2)) 5611 5612 mutex_enter(&acb->isr_mutex); 5613 switch (acb->adapter_type) { 5614 case ACB_ADAPTER_TYPE_A: 5615 retrn = arcmsr_handle_hba_isr(acb); 5616 break; 5617 5618 case ACB_ADAPTER_TYPE_B: 5619 retrn = arcmsr_handle_hbb_isr(acb); 5620 break; 5621 5622 case ACB_ADAPTER_TYPE_C: 5623 retrn = arcmsr_handle_hbc_isr(acb); 5624 break; 5625 5626 default: 5627 /* We should never be here */ 5628 ASSERT(0); 5629 break; 5630 } 5631 mutex_exit(&acb->isr_mutex); 5632 while ((ccb = arcmsr_get_complete_ccb_from_list(acb)) != NULL) { 5633 arcmsr_ccb_complete(ccb, 1); 5634 } 5635 return (retrn); 5636 } 5637 5638 5639 static void 5640 arcmsr_wait_firmware_ready(struct ACB *acb) 5641 { 5642 uint32_t firmware_state; 5643 5644 firmware_state = 0; 5645 5646 switch (acb->adapter_type) { 5647 case ACB_ADAPTER_TYPE_A: 5648 { 5649 struct HBA_msgUnit *phbamu; 5650 phbamu = (struct HBA_msgUnit *)acb->pmu; 5651 do { 5652 firmware_state = 5653 CHIP_REG_READ32(acb->reg_mu_acc_handle0, 5654 &phbamu->outbound_msgaddr1); 5655 } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) 5656 == 0); 5657 break; 5658 } 5659 5660 case ACB_ADAPTER_TYPE_B: 5661 { 5662 struct HBB_msgUnit *phbbmu; 5663 phbbmu = (struct HBB_msgUnit *)acb->pmu; 5664 do { 5665 firmware_state = 5666 CHIP_REG_READ32(acb->reg_mu_acc_handle0, 5667 &phbbmu->hbb_doorbell->iop2drv_doorbell); 5668 } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0); 5669 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5670 &phbbmu->hbb_doorbell->drv2iop_doorbell, 5671 ARCMSR_DRV2IOP_END_OF_INTERRUPT); 5672 break; 5673 } 5674 5675 case ACB_ADAPTER_TYPE_C: 5676 { 5677 struct HBC_msgUnit *phbcmu; 5678 phbcmu = (struct HBC_msgUnit *)acb->pmu; 5679 do { 5680 firmware_state = 5681 CHIP_REG_READ32(acb->reg_mu_acc_handle0, 5682 &phbcmu->outbound_msgaddr1); 5683 } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) 5684 == 0); 5685 break; 5686 } 5687 5688 } 5689 } 5690 5691 static void 5692 arcmsr_clear_doorbell_queue_buffer(struct ACB *acb) 5693 { 5694 switch (acb->adapter_type) { 5695 case ACB_ADAPTER_TYPE_A: { 5696 struct HBA_msgUnit *phbamu; 5697 uint32_t outbound_doorbell; 5698 5699 phbamu = (struct HBA_msgUnit *)acb->pmu; 5700 /* empty doorbell Qbuffer if door bell rung */ 5701 outbound_doorbell = CHIP_REG_READ32(acb->reg_mu_acc_handle0, 5702 &phbamu->outbound_doorbell); 5703 /* clear doorbell interrupt */ 5704 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5705 &phbamu->outbound_doorbell, outbound_doorbell); 5706 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5707 &phbamu->inbound_doorbell, 5708 ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 5709 break; 5710 } 5711 5712 case ACB_ADAPTER_TYPE_B: { 5713 struct HBB_msgUnit *phbbmu; 5714 5715 phbbmu = (struct HBB_msgUnit *)acb->pmu; 5716 /* clear interrupt and message state */ 5717 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5718 &phbbmu->hbb_doorbell->iop2drv_doorbell, 5719 ARCMSR_MESSAGE_INT_CLEAR_PATTERN); 5720 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5721 &phbbmu->hbb_doorbell->drv2iop_doorbell, 5722 ARCMSR_DRV2IOP_DATA_READ_OK); 5723 /* let IOP know data has been read */ 5724 break; 5725 } 5726 5727 case ACB_ADAPTER_TYPE_C: { 5728 struct HBC_msgUnit *phbcmu; 5729 uint32_t outbound_doorbell; 5730 5731 phbcmu = (struct HBC_msgUnit *)acb->pmu; 5732 /* empty doorbell Qbuffer if door bell ringed */ 5733 outbound_doorbell = CHIP_REG_READ32(acb->reg_mu_acc_handle0, 5734 &phbcmu->outbound_doorbell); 5735 /* clear outbound doobell isr */ 5736 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5737 &phbcmu->outbound_doorbell_clear, outbound_doorbell); 5738 /* let IOP know data has been read */ 5739 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5740 &phbcmu->inbound_doorbell, 5741 ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 5742 break; 5743 } 5744 5745 } 5746 } 5747 5748 5749 static uint32_t 5750 arcmsr_iop_confirm(struct ACB *acb) 5751 { 5752 uint64_t cdb_phyaddr; 5753 uint32_t cdb_phyaddr_hi32; 5754 5755 /* 5756 * here we need to tell iop 331 about our freeccb.HighPart 5757 * if freeccb.HighPart is non-zero 5758 */ 5759 cdb_phyaddr = acb->ccb_cookie.dmac_laddress; 5760 cdb_phyaddr_hi32 = (uint32_t)((cdb_phyaddr >> 16) >> 16); 5761 acb->cdb_phyaddr_hi32 = cdb_phyaddr_hi32; 5762 switch (acb->adapter_type) { 5763 case ACB_ADAPTER_TYPE_A: 5764 if (cdb_phyaddr_hi32 != 0) { 5765 struct HBA_msgUnit *phbamu; 5766 5767 phbamu = (struct HBA_msgUnit *)acb->pmu; 5768 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5769 &phbamu->msgcode_rwbuffer[0], 5770 ARCMSR_SIGNATURE_SET_CONFIG); 5771 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5772 &phbamu->msgcode_rwbuffer[1], cdb_phyaddr_hi32); 5773 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5774 &phbamu->inbound_msgaddr0, 5775 ARCMSR_INBOUND_MESG0_SET_CONFIG); 5776 if (!arcmsr_hba_wait_msgint_ready(acb)) { 5777 arcmsr_warn(acb, 5778 "timeout setting ccb " 5779 "high physical address"); 5780 return (FALSE); 5781 } 5782 } 5783 break; 5784 5785 /* if adapter is type B, set window of "post command queue" */ 5786 case ACB_ADAPTER_TYPE_B: { 5787 uint32_t post_queue_phyaddr; 5788 struct HBB_msgUnit *phbbmu; 5789 5790 phbbmu = (struct HBB_msgUnit *)acb->pmu; 5791 phbbmu->postq_index = 0; 5792 phbbmu->doneq_index = 0; 5793 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5794 &phbbmu->hbb_doorbell->drv2iop_doorbell, 5795 ARCMSR_MESSAGE_SET_POST_WINDOW); 5796 5797 if (!arcmsr_hbb_wait_msgint_ready(acb)) { 5798 arcmsr_warn(acb, "timeout setting post command " 5799 "queue window"); 5800 return (FALSE); 5801 } 5802 5803 post_queue_phyaddr = (uint32_t)cdb_phyaddr + 5804 ARCMSR_MAX_FREECCB_NUM * P2ROUNDUP(sizeof (struct CCB), 32) 5805 + offsetof(struct HBB_msgUnit, post_qbuffer); 5806 /* driver "set config" signature */ 5807 CHIP_REG_WRITE32(acb->reg_mu_acc_handle1, 5808 &phbbmu->hbb_rwbuffer->msgcode_rwbuffer[0], 5809 ARCMSR_SIGNATURE_SET_CONFIG); 5810 /* normal should be zero */ 5811 CHIP_REG_WRITE32(acb->reg_mu_acc_handle1, 5812 &phbbmu->hbb_rwbuffer->msgcode_rwbuffer[1], 5813 cdb_phyaddr_hi32); 5814 /* postQ size (256+8)*4 */ 5815 CHIP_REG_WRITE32(acb->reg_mu_acc_handle1, 5816 &phbbmu->hbb_rwbuffer->msgcode_rwbuffer[2], 5817 post_queue_phyaddr); 5818 /* doneQ size (256+8)*4 */ 5819 CHIP_REG_WRITE32(acb->reg_mu_acc_handle1, 5820 &phbbmu->hbb_rwbuffer->msgcode_rwbuffer[3], 5821 post_queue_phyaddr+1056); 5822 /* ccb maxQ size must be --> [(256+8)*4] */ 5823 CHIP_REG_WRITE32(acb->reg_mu_acc_handle1, 5824 &phbbmu->hbb_rwbuffer->msgcode_rwbuffer[4], 1056); 5825 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5826 &phbbmu->hbb_doorbell->drv2iop_doorbell, 5827 ARCMSR_MESSAGE_SET_CONFIG); 5828 5829 if (!arcmsr_hbb_wait_msgint_ready(acb)) { 5830 arcmsr_warn(acb, 5831 "timeout setting command queue window"); 5832 return (FALSE); 5833 } 5834 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5835 &phbbmu->hbb_doorbell->drv2iop_doorbell, 5836 ARCMSR_MESSAGE_START_DRIVER_MODE); 5837 5838 if (!arcmsr_hbb_wait_msgint_ready(acb)) { 5839 arcmsr_warn(acb, "timeout in 'start driver mode'"); 5840 return (FALSE); 5841 } 5842 break; 5843 } 5844 5845 case ACB_ADAPTER_TYPE_C: 5846 if (cdb_phyaddr_hi32 != 0) { 5847 struct HBC_msgUnit *phbcmu; 5848 5849 phbcmu = (struct HBC_msgUnit *)acb->pmu; 5850 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5851 &phbcmu->msgcode_rwbuffer[0], 5852 ARCMSR_SIGNATURE_SET_CONFIG); 5853 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5854 &phbcmu->msgcode_rwbuffer[1], cdb_phyaddr_hi32); 5855 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5856 &phbcmu->inbound_msgaddr0, 5857 ARCMSR_INBOUND_MESG0_SET_CONFIG); 5858 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5859 &phbcmu->inbound_doorbell, 5860 ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 5861 if (!arcmsr_hbc_wait_msgint_ready(acb)) { 5862 arcmsr_warn(acb, "'set ccb " 5863 "high part physical address' timeout"); 5864 return (FALSE); 5865 } 5866 } 5867 break; 5868 } 5869 return (TRUE); 5870 } 5871 5872 5873 /* 5874 * ONLY used for Adapter type B 5875 */ 5876 static void 5877 arcmsr_enable_eoi_mode(struct ACB *acb) 5878 { 5879 struct HBB_msgUnit *phbbmu; 5880 5881 phbbmu = (struct HBB_msgUnit *)acb->pmu; 5882 5883 CHIP_REG_WRITE32(acb->reg_mu_acc_handle0, 5884 &phbbmu->hbb_doorbell->drv2iop_doorbell, 5885 ARCMSR_MESSAGE_ACTIVE_EOI_MODE); 5886 5887 if (!arcmsr_hbb_wait_msgint_ready(acb)) 5888 arcmsr_warn(acb, "'iop enable eoi mode' timeout"); 5889 } 5890 5891 /* start background rebuild */ 5892 static void 5893 arcmsr_iop_init(struct ACB *acb) 5894 { 5895 uint32_t intmask_org; 5896 5897 /* disable all outbound interrupt */ 5898 intmask_org = arcmsr_disable_allintr(acb); 5899 arcmsr_wait_firmware_ready(acb); 5900 (void) arcmsr_iop_confirm(acb); 5901 5902 /* start background rebuild */ 5903 switch (acb->adapter_type) { 5904 case ACB_ADAPTER_TYPE_A: 5905 arcmsr_get_hba_config(acb); 5906 arcmsr_start_hba_bgrb(acb); 5907 break; 5908 case ACB_ADAPTER_TYPE_B: 5909 arcmsr_get_hbb_config(acb); 5910 arcmsr_start_hbb_bgrb(acb); 5911 break; 5912 case ACB_ADAPTER_TYPE_C: 5913 arcmsr_get_hbc_config(acb); 5914 arcmsr_start_hbc_bgrb(acb); 5915 break; 5916 } 5917 /* empty doorbell Qbuffer if door bell rang */ 5918 arcmsr_clear_doorbell_queue_buffer(acb); 5919 5920 if (acb->adapter_type == ACB_ADAPTER_TYPE_B) 5921 arcmsr_enable_eoi_mode(acb); 5922 5923 /* enable outbound Post Queue, outbound doorbell Interrupt */ 5924 arcmsr_enable_allintr(acb, intmask_org); 5925 acb->acb_flags |= ACB_F_IOP_INITED; 5926 } 5927