1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/types.h> 27 #include <sys/stat.h> 28 #include <sys/sunndi.h> 29 #include <sys/pci.h> 30 #include <sys/pci_impl.h> 31 #include <sys/pci_cfgspace.h> 32 #include <sys/memlist.h> 33 #include <sys/bootconf.h> 34 #include <io/pci/mps_table.h> 35 #include <sys/pci_cfgspace.h> 36 #include <sys/pci_cfgspace_impl.h> 37 #include <sys/psw.h> 38 #include "../../../../common/pci/pci_strings.h" 39 #include <sys/apic.h> 40 #include <io/pciex/pcie_nvidia.h> 41 #include <io/hotplug/pciehpc/pciehpc_acpi.h> 42 #include <sys/acpi/acpi.h> 43 #include <sys/acpica.h> 44 #include <sys/intel_iommu.h> 45 46 #define pci_getb (*pci_getb_func) 47 #define pci_getw (*pci_getw_func) 48 #define pci_getl (*pci_getl_func) 49 #define pci_putb (*pci_putb_func) 50 #define pci_putw (*pci_putw_func) 51 #define pci_putl (*pci_putl_func) 52 #define dcmn_err if (pci_boot_debug) cmn_err 53 54 #define CONFIG_INFO 0 55 #define CONFIG_UPDATE 1 56 #define CONFIG_NEW 2 57 #define CONFIG_FIX 3 58 #define COMPAT_BUFSIZE 512 59 60 #define PPB_IO_ALIGNMENT 0x1000 /* 4K aligned */ 61 #define PPB_MEM_ALIGNMENT 0x100000 /* 1M aligned */ 62 63 /* See AMD-8111 Datasheet Rev 3.03, Page 149: */ 64 #define LPC_IO_CONTROL_REG_1 0x40 65 #define AMD8111_ENABLENMI (uint8_t)0x80 66 #define DEVID_AMD8111_LPC 0x7468 67 68 struct pci_fixundo { 69 uint8_t bus; 70 uint8_t dev; 71 uint8_t fn; 72 void (*undofn)(uint8_t, uint8_t, uint8_t); 73 struct pci_fixundo *next; 74 }; 75 76 struct pci_devfunc { 77 struct pci_devfunc *next; 78 dev_info_t *dip; 79 uchar_t dev; 80 uchar_t func; 81 boolean_t reprogram; /* this device needs to be reprogrammed */ 82 }; 83 84 extern int pci_bios_nbus; 85 static uchar_t max_dev_pci = 32; /* PCI standard */ 86 int pci_boot_debug = 0; 87 extern struct memlist *find_bus_res(int, int); 88 static struct pci_fixundo *undolist = NULL; 89 static int num_root_bus = 0; /* count of root buses */ 90 91 /* 92 * Module prototypes 93 */ 94 static void enumerate_bus_devs(uchar_t bus, int config_op); 95 static void create_root_bus_dip(uchar_t bus); 96 static void process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t, 97 ushort_t, int); 98 static void add_compatible(dev_info_t *, ushort_t, ushort_t, 99 ushort_t, ushort_t, uchar_t, uint_t, int); 100 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 101 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, 102 ushort_t); 103 static void add_model_prop(dev_info_t *, uint_t); 104 static void add_bus_range_prop(int); 105 static void add_bus_slot_names_prop(int); 106 static void add_ppb_ranges_prop(int); 107 static void add_bus_available_prop(int); 108 static int get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id); 109 static void fix_ppb_res(uchar_t, boolean_t); 110 static void alloc_res_array(); 111 static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 112 ushort_t deviceid); 113 static void pciex_slot_names_prop(dev_info_t *, ushort_t); 114 115 extern int pci_slot_names_prop(int, char *, int); 116 117 /* set non-zero to force PCI peer-bus renumbering */ 118 int pci_bus_always_renumber = 0; 119 120 /* get the subordinate bus # for a root/peer bus */ 121 static int 122 pci_root_subbus(int bus, uchar_t *subbus) 123 { 124 ACPI_HANDLE hdl; 125 ACPI_BUFFER rb; 126 ACPI_RESOURCE *rp; 127 int rv; 128 129 if (pci_bus_res[bus].dip == NULL) { 130 /* non-used bus # */ 131 return (AE_ERROR); 132 } 133 if (acpica_get_handle(pci_bus_res[bus].dip, &hdl) != AE_OK) { 134 cmn_err(CE_WARN, "!No ACPI obj for bus%d, ACPI OFF?\n", bus); 135 return (AE_ERROR); 136 } 137 138 rb.Length = ACPI_ALLOCATE_BUFFER; 139 if (AcpiGetCurrentResources(hdl, &rb) != AE_OK) { 140 cmn_err(CE_WARN, "!_CRS failed on pci%d\n", bus); 141 return (AE_ERROR); 142 } 143 144 rv = AE_ERROR; 145 146 for (rp = rb.Pointer; rp->Type != ACPI_RESOURCE_TYPE_END_TAG; 147 rp = ACPI_NEXT_RESOURCE(rp)) { 148 149 switch (rp->Type) { 150 case ACPI_RESOURCE_TYPE_ADDRESS16: 151 if (rp->Data.Address.ResourceType != 152 ACPI_BUS_NUMBER_RANGE) 153 continue; 154 *subbus = (uchar_t)rp->Data.Address16.Maximum; 155 dcmn_err(CE_NOTE, "Address16,subbus=%d\n", *subbus); 156 break; 157 case ACPI_RESOURCE_TYPE_ADDRESS32: 158 if (rp->Data.Address.ResourceType != 159 ACPI_BUS_NUMBER_RANGE) 160 continue; 161 *subbus = (uchar_t)rp->Data.Address32.Maximum; 162 dcmn_err(CE_NOTE, "Address32,subbus=%d\n", *subbus); 163 break; 164 case ACPI_RESOURCE_TYPE_ADDRESS64: 165 if (rp->Data.Address.ResourceType != 166 ACPI_BUS_NUMBER_RANGE) 167 continue; 168 *subbus = (uchar_t)rp->Data.Address64.Maximum; 169 dcmn_err(CE_NOTE, "Address64,subbus=%d\n", *subbus); 170 break; 171 case ACPI_RESOURCE_TYPE_EXTENDED_ADDRESS64: 172 if (rp->Data.Address.ResourceType != 173 ACPI_BUS_NUMBER_RANGE) 174 continue; 175 *subbus = (uchar_t)rp->Data.ExtAddress64.Maximum; 176 dcmn_err(CE_NOTE, "ExtAdr64,subbus=%d\n", *subbus); 177 break; 178 default: 179 dcmn_err(CE_NOTE, "rp->Type=%d\n", rp->Type); 180 continue; 181 } 182 183 /* found the bus-range resource */ 184 dcmn_err(CE_NOTE, "pci%d, subbus=%d\n", bus, *subbus); 185 rv = AE_OK; 186 187 /* This breaks out of the resource scanning loop */ 188 break; 189 } 190 191 AcpiOsFree(rb.Pointer); 192 if (rv != AE_OK) 193 cmn_err(CE_NOTE, "!No bus-range resource for pci%d\n", bus); 194 195 return (rv); 196 197 } 198 199 /* 200 * Enumerate all PCI devices 201 */ 202 void 203 pci_setup_tree() 204 { 205 uchar_t i, root_bus_addr = 0; 206 207 alloc_res_array(); 208 for (i = 0; i <= pci_bios_nbus; i++) { 209 pci_bus_res[i].par_bus = (uchar_t)-1; 210 pci_bus_res[i].root_addr = (uchar_t)-1; 211 pci_bus_res[i].sub_bus = i; 212 } 213 214 pci_bus_res[0].root_addr = root_bus_addr++; 215 create_root_bus_dip(0); 216 enumerate_bus_devs(0, CONFIG_INFO); 217 218 /* 219 * Now enumerate peer busses 220 * 221 * We loop till pci_bios_nbus. On most systems, there is 222 * one more bus at the high end, which implements the ISA 223 * compatibility bus. We don't care about that. 224 * 225 * Note: In the old (bootconf) enumeration, the peer bus 226 * address did not use the bus number, and there were 227 * too many peer busses created. The root_bus_addr is 228 * used to maintain the old peer bus address assignment. 229 * However, we stop enumerating phantom peers with no 230 * device below. 231 */ 232 for (i = 1; i <= pci_bios_nbus; i++) { 233 if (pci_bus_res[i].dip == NULL) { 234 pci_bus_res[i].root_addr = root_bus_addr++; 235 } 236 enumerate_bus_devs(i, CONFIG_INFO); 237 238 /* add slot-names property for named pci hot-plug slots */ 239 add_bus_slot_names_prop(i); 240 } 241 242 } 243 244 /* 245 * >0 = present, 0 = not present, <0 = error 246 */ 247 static int 248 pci_bbn_present(int bus) 249 { 250 ACPI_HANDLE hdl; 251 int rv; 252 253 /* no dip means no _BBN */ 254 if (pci_bus_res[bus].dip == NULL) 255 return (0); 256 257 rv = -1; /* default return value in case of error below */ 258 if (ACPI_SUCCESS(acpica_get_handle(pci_bus_res[bus].dip, &hdl))) { 259 switch (AcpiEvaluateObject(hdl, "_BBN", NULL, NULL)) { 260 case AE_OK: 261 rv = 1; 262 break; 263 case AE_NOT_FOUND: 264 rv = 0; 265 break; 266 default: 267 break; 268 } 269 } 270 271 return (rv); 272 } 273 274 /* 275 * Return non-zero if any PCI bus in the system has an associated 276 * _BBN object, 0 otherwise. 277 */ 278 static int 279 pci_roots_have_bbn(void) 280 { 281 int i; 282 283 /* 284 * Scan the PCI busses and look for at least 1 _BBN 285 */ 286 for (i = 0; i <= pci_bios_nbus; i++) { 287 /* skip non-root (peer) PCI busses */ 288 if (pci_bus_res[i].par_bus != (uchar_t)-1) 289 continue; 290 291 if (pci_bbn_present(i) > 0) 292 return (1); 293 } 294 return (0); 295 296 } 297 298 /* 299 * return non-zero if the machine is one on which we renumber 300 * the internal pci unit-addresses 301 */ 302 static int 303 pci_bus_renumber() 304 { 305 ACPI_TABLE_HEADER *fadt; 306 307 if (pci_bus_always_renumber) 308 return (1); 309 310 /* get the FADT */ 311 if (AcpiGetTable(ACPI_SIG_FADT, 1, (ACPI_TABLE_HEADER **)&fadt) != 312 AE_OK) 313 return (0); 314 315 /* compare OEM Table ID to "SUNm31" */ 316 if (strncmp("SUNm31", fadt->OemId, 6)) 317 return (0); 318 else 319 return (1); 320 } 321 322 /* 323 * Initial enumeration of the physical PCI bus hierarchy can 324 * leave 'gaps' in the order of peer PCI bus unit-addresses. 325 * Systems with more than one peer PCI bus *must* have an ACPI 326 * _BBN object associated with each peer bus; use the presence 327 * of this object to remove gaps in the numbering of the peer 328 * PCI bus unit-addresses - only peer busses with an associated 329 * _BBN are counted. 330 */ 331 static void 332 pci_renumber_root_busses(void) 333 { 334 int pci_regs[] = {0, 0, 0}; 335 int i, root_addr = 0; 336 337 /* 338 * Currently, we only enable the re-numbering on specific 339 * Sun machines; this is a work-around for the more complicated 340 * issue of upgrade changing physical device paths 341 */ 342 if (!pci_bus_renumber()) 343 return; 344 345 /* 346 * If we find no _BBN objects at all, we either don't need 347 * to do anything or can't do anything anyway 348 */ 349 if (!pci_roots_have_bbn()) 350 return; 351 352 for (i = 0; i <= pci_bios_nbus; i++) { 353 /* skip non-root (peer) PCI busses */ 354 if (pci_bus_res[i].par_bus != (uchar_t)-1) 355 continue; 356 357 if (pci_bbn_present(i) < 1) { 358 pci_bus_res[i].root_addr = (uchar_t)-1; 359 continue; 360 } 361 362 ASSERT(pci_bus_res[i].dip != NULL); 363 if (pci_bus_res[i].root_addr != root_addr) { 364 /* update reg property for node */ 365 pci_bus_res[i].root_addr = root_addr; 366 pci_regs[0] = pci_bus_res[i].root_addr; 367 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 368 pci_bus_res[i].dip, "reg", (int *)pci_regs, 3); 369 } 370 root_addr++; 371 } 372 } 373 374 static void 375 remove_resource_range(struct memlist **list, int *ranges, int range_count) 376 { 377 struct range { 378 uint32_t base; 379 uint32_t len; 380 }; 381 int index; 382 383 for (index = 0; index < range_count; index++) { 384 /* all done if list is or has become empty */ 385 if (*list == NULL) 386 break; 387 (void) memlist_remove(list, 388 (uint64_t)((struct range *)ranges)[index].base, 389 (uint64_t)((struct range *)ranges)[index].len); 390 } 391 } 392 393 static void 394 remove_used_resources() 395 { 396 dev_info_t *used; 397 int *narray; 398 uint_t ncount; 399 int status; 400 int bus; 401 402 used = ddi_find_devinfo("used-resources", -1, 0); 403 if (used == NULL) 404 return; 405 406 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used, 407 DDI_PROP_DONTPASS, "io-space", &narray, &ncount); 408 if (status == DDI_PROP_SUCCESS) { 409 for (bus = 0; bus <= pci_bios_nbus; bus++) 410 remove_resource_range(&pci_bus_res[bus].io_ports, 411 narray, ncount / 2); 412 ddi_prop_free(narray); 413 } 414 415 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used, 416 DDI_PROP_DONTPASS, "device-memory", &narray, &ncount); 417 if (status == DDI_PROP_SUCCESS) { 418 for (bus = 0; bus <= pci_bios_nbus; bus++) 419 remove_resource_range(&pci_bus_res[bus].mem_space, 420 narray, ncount / 2); 421 ddi_prop_free(narray); 422 } 423 } 424 425 /* 426 * Remove the resources which are already used by devices under a subtractive 427 * bridge from the bus's resources lists, because they're not available, and 428 * shouldn't be allocated to other buses. This is necessary because tracking 429 * resources for subtractive bridges is not complete. (Subtractive bridges only 430 * track some of their claimed resources, not "the rest of the address space" as 431 * they should, so that allocation to peer non-subtractive PPBs is easier. We 432 * need a fully-capable global resource allocator). 433 */ 434 static void 435 remove_subtractive_res() 436 { 437 int i, j; 438 struct memlist *list; 439 440 for (i = 0; i <= pci_bios_nbus; i++) { 441 if (pci_bus_res[i].subtractive) { 442 /* remove used io ports */ 443 list = pci_bus_res[i].io_ports_used; 444 while (list) { 445 for (j = 0; j <= pci_bios_nbus; j++) { 446 if (pci_bus_res[j].io_ports) 447 (void) memlist_remove( 448 &pci_bus_res[j].io_ports, 449 list->address, list->size); 450 } 451 list = list->next; 452 } 453 /* remove used mem resource */ 454 list = pci_bus_res[i].mem_space_used; 455 while (list) { 456 for (j = 0; j <= pci_bios_nbus; j++) { 457 if (pci_bus_res[j].mem_space) 458 (void) memlist_remove( 459 &pci_bus_res[j].mem_space, 460 list->address, list->size); 461 } 462 list = list->next; 463 } 464 /* remove used prefetchable mem resource */ 465 list = pci_bus_res[i].pmem_space_used; 466 while (list) { 467 for (j = 0; j <= pci_bios_nbus; j++) { 468 if (pci_bus_res[j].pmem_space) 469 (void) memlist_remove( 470 &pci_bus_res[j].pmem_space, 471 list->address, list->size); 472 } 473 list = list->next; 474 } 475 } 476 } 477 } 478 479 /* Set up this bus's "bus_space" resource list */ 480 static void 481 setup_bus_res(int bus) 482 { 483 uchar_t par_bus; 484 uchar_t sub_bus; 485 486 if (pci_bus_res[bus].dip == NULL) /* unused bus */ 487 return; 488 489 sub_bus = pci_bus_res[bus].sub_bus; 490 ASSERT(sub_bus >= bus); 491 ASSERT(pci_bus_res[bus].bus_space == NULL); 492 if (sub_bus > bus) { 493 /* 494 * Keep the remaining available bus range in bus_space. 495 * ('bus' is already allocated) 496 */ 497 memlist_insert(&pci_bus_res[bus].bus_space, bus + 1, 498 sub_bus - bus); 499 } 500 501 /* 502 * Remove resources from parent bus node if this is not a 503 * root bus. 504 */ 505 par_bus = pci_bus_res[bus].par_bus; 506 if (par_bus != (uchar_t)-1) { 507 ASSERT(pci_bus_res[par_bus].bus_space != NULL); 508 (void) memlist_remove(&pci_bus_res[par_bus].bus_space, 509 bus, sub_bus - bus + 1); 510 } 511 } 512 513 static uint64_t 514 get_parbus_io_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 515 { 516 uint64_t addr = 0; 517 uchar_t res_bus; 518 519 /* 520 * Skip root(peer) buses in multiple-root-bus systems, as currently 521 * the initial resources set on each root bus might not be correctly 522 * accounted for. (We need to read resources from ACPI as well as 523 * the MP tables and hotplug tables.) 524 */ 525 if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 526 (num_root_bus > 1)) 527 return (0); 528 529 res_bus = parbus; 530 while (pci_bus_res[res_bus].subtractive) { 531 if (pci_bus_res[res_bus].io_ports) 532 break; 533 res_bus = pci_bus_res[res_bus].par_bus; 534 if (res_bus == (uchar_t)-1) 535 break; /* root bus already */ 536 } 537 538 if (pci_bus_res[res_bus].io_ports) { 539 addr = memlist_find(&pci_bus_res[res_bus].io_ports, 540 size, align); 541 if (addr) { 542 memlist_insert(&pci_bus_res[res_bus].io_ports_used, 543 addr, size); 544 /* free the old resource */ 545 memlist_free_all(&pci_bus_res[bus].io_ports); 546 /* add the new resource */ 547 memlist_insert(&pci_bus_res[bus].io_ports, addr, size); 548 } 549 } 550 551 return (addr); 552 } 553 554 static uint64_t 555 get_parbus_mem_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 556 { 557 uint64_t addr = 0; 558 uchar_t res_bus; 559 560 /* 561 * Skip root(peer) buses in multiple-root-bus systems, as currently 562 * the initial resources set on each root bus might not be correctly 563 * accounted for. (We need to read resources from ACPI as well as 564 * the MP tables and hotplug tables.) 565 */ 566 if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 567 (num_root_bus > 1)) 568 return (0); 569 570 res_bus = parbus; 571 while (pci_bus_res[res_bus].subtractive) { 572 if (pci_bus_res[res_bus].mem_space) 573 break; 574 res_bus = pci_bus_res[res_bus].par_bus; 575 if (res_bus == (uchar_t)-1) 576 break; /* root bus already */ 577 } 578 579 if (pci_bus_res[res_bus].mem_space) { 580 addr = memlist_find(&pci_bus_res[res_bus].mem_space, 581 size, align); 582 if (addr) { 583 memlist_insert(&pci_bus_res[res_bus].mem_space_used, 584 addr, size); 585 /* free the old resource */ 586 memlist_free_all(&pci_bus_res[bus].mem_space); 587 /* add the new resource */ 588 memlist_insert(&pci_bus_res[bus].mem_space, addr, size); 589 } 590 } 591 592 return (addr); 593 } 594 595 /* 596 * given a cap_id, return its cap_id location in config space 597 */ 598 static int 599 get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id) 600 { 601 uint8_t curcap, cap_id_loc; 602 uint16_t status; 603 int location = -1; 604 605 /* 606 * Need to check the Status register for ECP support first. 607 * Also please note that for type 1 devices, the 608 * offset could change. Should support type 1 next. 609 */ 610 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 611 if (!(status & PCI_STAT_CAP)) { 612 return (-1); 613 } 614 cap_id_loc = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 615 616 /* Walk the list of capabilities */ 617 while (cap_id_loc && cap_id_loc != (uint8_t)-1) { 618 curcap = pci_getb(bus, dev, func, cap_id_loc); 619 620 if (curcap == cap_id) { 621 location = cap_id_loc; 622 break; 623 } 624 cap_id_loc = pci_getb(bus, dev, func, cap_id_loc + 1); 625 } 626 return (location); 627 } 628 629 /* 630 * Assign valid resources to unconfigured pci(e) bridges. We are trying 631 * to reprogram the bridge when its 632 * i) SECBUS == SUBBUS || 633 * ii) IOBASE > IOLIM || 634 * iii) MEMBASE > MEMLIM 635 * This must be done after one full pass through the PCI tree to collect 636 * all BIOS-configured resources, so that we know what resources are 637 * free and available to assign to the unconfigured PPBs. 638 */ 639 static void 640 fix_ppb_res(uchar_t secbus, boolean_t prog_sub) 641 { 642 uchar_t bus, dev, func; 643 uchar_t parbus, subbus; 644 uint_t io_base, io_limit, mem_base, mem_limit; 645 uint_t io_size, mem_size; 646 uint64_t addr = 0; 647 int *regp = NULL; 648 uint_t reglen; 649 int rv, cap_ptr, physhi; 650 dev_info_t *dip; 651 uint16_t cmd_reg; 652 struct memlist *list; 653 654 /* skip root (peer) PCI busses */ 655 if (pci_bus_res[secbus].par_bus == (uchar_t)-1) 656 return; 657 658 /* skip subtractive PPB when prog_sub is not TRUE */ 659 if (pci_bus_res[secbus].subtractive && !prog_sub) 660 return; 661 662 /* some entries may be empty due to discontiguous bus numbering */ 663 dip = pci_bus_res[secbus].dip; 664 if (dip == NULL) 665 return; 666 667 rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 668 "reg", ®p, ®len); 669 ASSERT(rv == DDI_PROP_SUCCESS && reglen > 0); 670 physhi = regp[0]; 671 ddi_prop_free(regp); 672 673 func = (uchar_t)PCI_REG_FUNC_G(physhi); 674 dev = (uchar_t)PCI_REG_DEV_G(physhi); 675 bus = (uchar_t)PCI_REG_BUS_G(physhi); 676 677 /* 678 * If pcie bridge, check to see if link is enabled 679 */ 680 cap_ptr = get_pci_cap(bus, dev, func, PCI_CAP_ID_PCI_E); 681 if (cap_ptr != -1) { 682 cmd_reg = pci_getw(bus, dev, func, 683 (uint16_t)cap_ptr + PCIE_LINKCTL); 684 if (cmd_reg & PCIE_LINKCTL_LINK_DISABLE) { 685 dcmn_err(CE_NOTE, 686 "!fix_ppb_res: ppb[%x/%x/%x] link is disabled.\n", 687 bus, dev, func); 688 return; 689 } 690 } 691 692 subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 693 parbus = pci_bus_res[secbus].par_bus; 694 ASSERT(parbus == bus); 695 cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 696 697 /* 698 * If we have a Cardbus bridge, but no bus space 699 */ 700 if (pci_bus_res[secbus].num_cbb != 0 && 701 pci_bus_res[secbus].bus_space == NULL) { 702 uchar_t range; 703 704 /* normally there are 2 buses under a cardbus bridge */ 705 range = pci_bus_res[secbus].num_cbb * 2; 706 707 /* 708 * Try to find and allocate a bus-range starting at subbus+1 709 * from the parent of the PPB. 710 */ 711 for (; range != 0; range--) { 712 if (memlist_find_with_startaddr( 713 &pci_bus_res[parbus].bus_space, 714 subbus + 1, range, 1) != NULL) 715 break; /* find bus range resource at parent */ 716 } 717 if (range != 0) { 718 memlist_insert(&pci_bus_res[secbus].bus_space, 719 subbus + 1, range); 720 subbus = subbus + range; 721 pci_bus_res[secbus].sub_bus = subbus; 722 pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus); 723 add_bus_range_prop(secbus); 724 725 cmn_err(CE_NOTE, "!reprogram bus-range on ppb" 726 "[%x/%x/%x]: %x ~ %x\n", bus, dev, func, 727 secbus, subbus); 728 } 729 } 730 731 /* 732 * Calculate required IO size 733 * We are going to assign 512 bytes per bus. The size needs to be 734 * 4K aligned and the maximum size is 16K. 735 */ 736 io_size = (subbus - secbus + 1) * 0x200; 737 io_size = (io_size + PPB_IO_ALIGNMENT) & (~(PPB_IO_ALIGNMENT - 1)); 738 if (io_size > 0x4 * PPB_IO_ALIGNMENT) 739 io_size = 0x4 * PPB_IO_ALIGNMENT; 740 /* 741 * Calculate required MEM size 742 * We are going to assign 1M bytes per bus. The size needs to be 743 * 1M aligned and the maximum size is 8M. 744 */ 745 mem_size = (subbus - secbus + 1) * PPB_MEM_ALIGNMENT; 746 if (mem_size > 0x8 * PPB_MEM_ALIGNMENT) 747 mem_size = 0x8 * PPB_MEM_ALIGNMENT; 748 749 /* Subtractive bridge */ 750 if (pci_bus_res[secbus].subtractive && prog_sub) { 751 /* 752 * We program an arbitrary amount of I/O and memory resource 753 * for the subtractive bridge so that child dynamic-resource- 754 * allocating devices (such as Cardbus bridges) have a chance 755 * of success. Until we have full-tree resource rebalancing, 756 * dynamic resource allocation (thru busra) only looks at the 757 * parent bridge, so all PPBs must have some allocatable 758 * resource. For non-subtractive bridges, the resources come 759 * from the base/limit register "windows", but subtractive 760 * bridges often don't program those (since they don't need to). 761 * If we put all the remaining resources on the subtractive 762 * bridge, then peer non-subtractive bridges can't allocate 763 * more space (even though this is probably most correct). 764 * If we put the resources only on the parent, then allocations 765 * from children of subtractive bridges will fail without 766 * special-case code for bypassing the subtractive bridge. 767 * This solution is the middle-ground temporary solution until 768 * we have fully-capable resource allocation. 769 */ 770 771 /* 772 * Add an arbitrary I/O resource to the subtractive PPB 773 */ 774 if (pci_bus_res[secbus].io_ports == NULL) { 775 addr = get_parbus_io_res(parbus, secbus, io_size, 776 PPB_IO_ALIGNMENT); 777 if (addr) { 778 add_ppb_ranges_prop(secbus); 779 pci_bus_res[secbus].io_reprogram = 780 pci_bus_res[parbus].io_reprogram; 781 782 cmn_err(CE_NOTE, "!add io-range on subtractive" 783 " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 784 bus, dev, func, (uint32_t)addr, 785 (uint32_t)addr + io_size - 1); 786 } 787 } 788 /* 789 * Add an arbitrary memory resource to the subtractive PPB 790 */ 791 if (pci_bus_res[secbus].mem_space == NULL) { 792 addr = get_parbus_mem_res(parbus, secbus, mem_size, 793 PPB_MEM_ALIGNMENT); 794 if (addr) { 795 add_ppb_ranges_prop(secbus); 796 pci_bus_res[secbus].mem_reprogram = 797 pci_bus_res[parbus].mem_reprogram; 798 799 cmn_err(CE_NOTE, "!add mem-range on " 800 "subtractive ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 801 bus, dev, func, (uint32_t)addr, 802 (uint32_t)addr + mem_size - 1); 803 } 804 } 805 806 goto cmd_enable; 807 } 808 809 /* 810 * Check to see if we need to reprogram I/O space, either because the 811 * parent bus needed reprogramming and so do we, or because I/O space is 812 * disabled in base/limit or command register. 813 */ 814 io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 815 io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 816 io_base = (io_base & 0xf0) << 8; 817 io_limit = ((io_limit & 0xf0) << 8) | 0xfff; 818 819 if (pci_bus_res[parbus].io_reprogram || (io_base > io_limit) || 820 (!(cmd_reg & PCI_COMM_IO))) { 821 if (pci_bus_res[secbus].io_ports_used) { 822 memlist_merge(&pci_bus_res[secbus].io_ports_used, 823 &pci_bus_res[secbus].io_ports); 824 } 825 if (pci_bus_res[secbus].io_ports && 826 (!pci_bus_res[parbus].io_reprogram) && 827 (!pci_bus_res[parbus].subtractive)) { 828 /* rechoose old io ports info */ 829 list = pci_bus_res[secbus].io_ports; 830 io_base = (uint_t)list->address; 831 /* 4K aligned */ 832 io_base = io_base & (~(PPB_IO_ALIGNMENT - 1)); 833 io_limit = (uint_t)(list->address + list->size); 834 while (list->next) { 835 list = list->next; 836 if ((list->address + list->size) > io_limit) 837 io_limit = (uint_t) 838 (list->address + list->size); 839 } 840 io_limit = io_limit - 1; 841 /* 4K aligned */ 842 io_limit = (io_limit + PPB_IO_ALIGNMENT) & 843 (~(PPB_IO_ALIGNMENT - 1)); 844 io_size = io_limit - io_base; 845 io_limit = io_limit - 1; 846 ASSERT(io_base <= io_limit); 847 memlist_free_all(&pci_bus_res[secbus].io_ports); 848 memlist_insert(&pci_bus_res[secbus].io_ports, 849 io_base, io_size); 850 memlist_insert(&pci_bus_res[parbus].io_ports_used, 851 io_base, io_size); 852 if (pci_bus_res[parbus].io_ports) 853 (void) memlist_remove( 854 &pci_bus_res[parbus].io_ports, 855 io_base, io_size); 856 pci_bus_res[secbus].io_reprogram = B_TRUE; 857 } else { 858 /* get new io ports from parent bus */ 859 addr = get_parbus_io_res(parbus, secbus, io_size, 860 PPB_IO_ALIGNMENT); 861 if (addr) { 862 io_base = addr; 863 io_limit = addr + io_size - 1; 864 pci_bus_res[secbus].io_reprogram = B_TRUE; 865 } 866 } 867 if (pci_bus_res[secbus].io_reprogram) { 868 /* reprogram PPB regs */ 869 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 870 (uchar_t)((io_base>>8) & 0xf0)); 871 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 872 (uchar_t)((io_limit>>8) & 0xf0)); 873 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 874 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 875 add_ppb_ranges_prop(secbus); 876 877 cmn_err(CE_NOTE, "!reprogram io-range on" 878 " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 879 bus, dev, func, io_base, io_limit); 880 } 881 } 882 883 /* 884 * Check memory space as we did I/O space. 885 */ 886 mem_base = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 887 mem_base = (mem_base & 0xfff0) << 16; 888 mem_limit = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 889 mem_limit = ((mem_limit & 0xfff0) << 16) | 0xfffff; 890 891 if (pci_bus_res[parbus].mem_reprogram || (mem_base > mem_limit) || 892 (!(cmd_reg & PCI_COMM_MAE))) { 893 if (pci_bus_res[secbus].mem_space_used) { 894 memlist_merge(&pci_bus_res[secbus].mem_space_used, 895 &pci_bus_res[secbus].mem_space); 896 } 897 if (pci_bus_res[secbus].mem_space && 898 (!pci_bus_res[parbus].mem_reprogram) && 899 (!pci_bus_res[parbus].subtractive)) { 900 /* rechoose old mem resource */ 901 list = pci_bus_res[secbus].mem_space; 902 mem_base = (uint_t)list->address; 903 /* 1M aligned */ 904 mem_base = mem_base & (~0xfffff); 905 mem_limit = (uint_t)(list->address + list->size); 906 while (list->next) { 907 list = list->next; 908 if ((list->address + list->size) > mem_limit) 909 mem_limit = (uint_t) 910 (list->address + list->size); 911 } 912 mem_limit = mem_limit - 1; 913 /* 1M aligned */ 914 mem_limit = (mem_limit + PPB_MEM_ALIGNMENT) & 915 (~(PPB_MEM_ALIGNMENT - 1)); 916 mem_size = mem_limit - mem_base; 917 mem_limit = mem_limit - 1; 918 ASSERT(mem_base <= mem_limit); 919 memlist_free_all(&pci_bus_res[secbus].mem_space); 920 memlist_insert(&pci_bus_res[secbus].mem_space, 921 mem_base, mem_size); 922 memlist_insert(&pci_bus_res[parbus].mem_space_used, 923 mem_base, mem_size); 924 if (pci_bus_res[parbus].mem_space) 925 (void) memlist_remove( 926 &pci_bus_res[parbus].mem_space, 927 mem_base, mem_size); 928 pci_bus_res[secbus].mem_reprogram = B_TRUE; 929 } else { 930 /* get new mem resource from parent bus */ 931 addr = get_parbus_mem_res(parbus, secbus, mem_size, 932 PPB_MEM_ALIGNMENT); 933 if (addr) { 934 mem_base = addr; 935 mem_limit = addr + mem_size - 1; 936 pci_bus_res[secbus].mem_reprogram = B_TRUE; 937 } 938 } 939 940 if (pci_bus_res[secbus].mem_reprogram) { 941 /* reprogram PPB regs */ 942 pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE, 943 (uint16_t)((mem_base>>16) & 0xfff0)); 944 pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT, 945 (uint16_t)((mem_limit>>16) & 0xfff0)); 946 add_ppb_ranges_prop(secbus); 947 948 cmn_err(CE_NOTE, "!reprogram mem-range on" 949 " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 950 bus, dev, func, mem_base, mem_limit); 951 } 952 } 953 954 cmd_enable: 955 if (pci_bus_res[secbus].io_ports) 956 cmd_reg |= PCI_COMM_IO | PCI_COMM_ME; 957 if (pci_bus_res[secbus].mem_space) 958 cmd_reg |= PCI_COMM_MAE | PCI_COMM_ME; 959 pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 960 } 961 962 void 963 pci_reprogram(void) 964 { 965 int i, pci_reconfig = 1; 966 char *onoff; 967 968 /* 969 * Excise phantom roots if possible 970 */ 971 pci_renumber_root_busses(); 972 973 /* add bus-range property for root/peer bus nodes */ 974 for (i = 0; i <= pci_bios_nbus; i++) { 975 if (pci_bus_res[i].par_bus == (uchar_t)-1) { 976 uchar_t subbus; 977 if (pci_root_subbus(i, &subbus) == AE_OK) 978 pci_bus_res[i].sub_bus = subbus; 979 add_bus_range_prop(i); 980 } 981 /* setup bus range resource on each bus */ 982 setup_bus_res(i); 983 } 984 985 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 986 DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 987 if (strcmp(onoff, "off") == 0) { 988 pci_reconfig = 0; 989 cmn_err(CE_NOTE, "pci device reprogramming disabled"); 990 } 991 ddi_prop_free(onoff); 992 } 993 994 /* remove used-resources from PCI resource maps */ 995 remove_used_resources(); 996 remove_subtractive_res(); 997 998 /* reprogram the non-subtractive PPB */ 999 if (pci_reconfig) 1000 for (i = 0; i <= pci_bios_nbus; i++) 1001 fix_ppb_res(i, B_FALSE); 1002 1003 for (i = 0; i <= pci_bios_nbus; i++) { 1004 /* configure devices not configured by BIOS */ 1005 if (pci_reconfig) { 1006 /* 1007 * Reprogram the subtractive PPB. At this time, all its 1008 * siblings should have got their resources already. 1009 */ 1010 if (pci_bus_res[i].subtractive) 1011 fix_ppb_res(i, B_TRUE); 1012 enumerate_bus_devs(i, CONFIG_NEW); 1013 } 1014 /* All dev programmed, so we can create available prop */ 1015 add_bus_available_prop(i); 1016 } 1017 } 1018 1019 /* 1020 * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 1021 */ 1022 static void 1023 create_root_bus_dip(uchar_t bus) 1024 { 1025 int pci_regs[] = {0, 0, 0}; 1026 dev_info_t *dip; 1027 1028 ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 1029 1030 num_root_bus++; 1031 ndi_devi_alloc_sleep(ddi_root_node(), "pci", 1032 (pnode_t)DEVI_SID_NODEID, &dip); 1033 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1034 "#address-cells", 3); 1035 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1036 "#size-cells", 2); 1037 pci_regs[0] = pci_bus_res[bus].root_addr; 1038 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1039 "reg", (int *)pci_regs, 3); 1040 1041 /* 1042 * If system has PCIe bus, then create different properties 1043 */ 1044 if (create_pcie_root_bus(bus, dip) == B_FALSE) 1045 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1046 "device_type", "pci"); 1047 1048 (void) ndi_devi_bind_driver(dip, 0); 1049 pci_bus_res[bus].dip = dip; 1050 pci_bus_res[bus].pmem_space = find_bus_res(bus, PREFETCH_TYPE); 1051 pci_bus_res[bus].mem_space = find_bus_res(bus, MEM_TYPE); 1052 pci_bus_res[bus].io_ports = find_bus_res(bus, IO_TYPE); 1053 1054 if (bus != 0) 1055 return; 1056 1057 /* 1058 * Special treatment of bus 0: 1059 * If no resource from MPSPEC/HRT, copy pcimem from boot 1060 * and make I/O space the entire range starting at 0x100. There 1061 * is no difference between prefetchable memory or not. 1062 */ 1063 if (pci_bus_res[0].mem_space == NULL) 1064 pci_bus_res[0].mem_space = 1065 memlist_dup(bootops->boot_mem->pcimem); 1066 /* Exclude 0x00 to 0xff of the I/O space, used by all PCs */ 1067 if (pci_bus_res[0].io_ports == NULL) 1068 memlist_insert(&pci_bus_res[0].io_ports, 0x100, 0xffff); 1069 } 1070 1071 /* 1072 * For any fixed configuration (often compatability) pci devices 1073 * and those with their own expansion rom, create device nodes 1074 * to hold the already configured device details. 1075 */ 1076 void 1077 enumerate_bus_devs(uchar_t bus, int config_op) 1078 { 1079 uchar_t dev, func, nfunc, header; 1080 ushort_t venid; 1081 struct pci_devfunc *devlist = NULL, *entry; 1082 1083 if (config_op == CONFIG_NEW) { 1084 dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 1085 } else if (config_op == CONFIG_FIX) { 1086 dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus); 1087 } else 1088 dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 1089 1090 for (dev = 0; dev < max_dev_pci; dev++) { 1091 nfunc = 1; 1092 for (func = 0; func < nfunc; func++) { 1093 1094 dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", 1095 dev, func); 1096 1097 venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 1098 1099 if ((venid == 0xffff) || (venid == 0)) { 1100 /* no function at this address */ 1101 continue; 1102 } 1103 1104 header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 1105 if (header == 0xff) { 1106 continue; /* illegal value */ 1107 } 1108 1109 /* 1110 * according to some mail from Microsoft posted 1111 * to the pci-drivers alias, their only requirement 1112 * for a multifunction device is for the 1st 1113 * function to have to PCI_HEADER_MULTI bit set. 1114 */ 1115 if ((func == 0) && (header & PCI_HEADER_MULTI)) { 1116 nfunc = 8; 1117 } 1118 1119 if (config_op == CONFIG_FIX || 1120 config_op == CONFIG_INFO) { 1121 /* 1122 * Create the node, unconditionally, on the 1123 * first pass only. It may still need 1124 * resource assignment, which will be 1125 * done on the second, CONFIG_NEW, pass. 1126 */ 1127 process_devfunc(bus, dev, func, header, 1128 venid, config_op); 1129 1130 } 1131 } 1132 } 1133 1134 if (config_op == CONFIG_NEW) { 1135 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 1136 while (devlist) { 1137 entry = devlist; 1138 devlist = entry->next; 1139 if (entry->reprogram || 1140 pci_bus_res[bus].io_reprogram || 1141 pci_bus_res[bus].mem_reprogram) { 1142 /* reprogram device(s) */ 1143 (void) add_reg_props(entry->dip, bus, 1144 entry->dev, entry->func, CONFIG_NEW, 0); 1145 } 1146 kmem_free(entry, sizeof (*entry)); 1147 } 1148 pci_bus_res[bus].privdata = NULL; 1149 } 1150 } 1151 1152 static int 1153 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 1154 ushort_t subvenid, ushort_t subdevid) 1155 { 1156 static int prop_exist = -1; 1157 static char *pciide_str; 1158 char compat[32]; 1159 1160 if (prop_exist == -1) { 1161 prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 1162 ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 1163 &pciide_str) == DDI_SUCCESS); 1164 } 1165 1166 if (!prop_exist) 1167 return (0); 1168 1169 /* compare property value against various forms of compatible */ 1170 if (subvenid) { 1171 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 1172 venid, devid, subvenid, subdevid, revid); 1173 if (strcmp(pciide_str, compat) == 0) 1174 return (1); 1175 1176 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 1177 venid, devid, subvenid, subdevid); 1178 if (strcmp(pciide_str, compat) == 0) 1179 return (1); 1180 1181 (void) snprintf(compat, sizeof (compat), "pci%x,%x", 1182 subvenid, subdevid); 1183 if (strcmp(pciide_str, compat) == 0) 1184 return (1); 1185 } 1186 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 1187 venid, devid, revid); 1188 if (strcmp(pciide_str, compat) == 0) 1189 return (1); 1190 1191 (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 1192 if (strcmp(pciide_str, compat) == 0) 1193 return (1); 1194 1195 return (0); 1196 } 1197 1198 static int 1199 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 1200 ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 1201 { 1202 struct ide_table { /* table for PCI_MASS_OTHER */ 1203 ushort_t venid; 1204 ushort_t devid; 1205 } *entry; 1206 1207 /* XXX SATA and other devices: need a way to add dynamically */ 1208 static struct ide_table ide_other[] = { 1209 {0x1095, 0x3112}, 1210 {0x1095, 0x3114}, 1211 {0x1095, 0x3512}, 1212 {0x1095, 0x680}, /* Sil0680 */ 1213 {0x1283, 0x8211}, /* ITE 8211F is subcl PCI_MASS_OTHER */ 1214 {0, 0} 1215 }; 1216 1217 if (basecl != PCI_CLASS_MASS) 1218 return (0); 1219 1220 if (subcl == PCI_MASS_IDE) { 1221 return (1); 1222 } 1223 1224 if (check_pciide_prop(revid, venid, devid, subvenid, subdevid)) 1225 return (1); 1226 1227 if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 1228 return (0); 1229 } 1230 1231 entry = &ide_other[0]; 1232 while (entry->venid) { 1233 if (entry->venid == venid && entry->devid == devid) 1234 return (1); 1235 entry++; 1236 } 1237 return (0); 1238 } 1239 1240 static int 1241 is_display(uint_t classcode) 1242 { 1243 static uint_t disp_classes[] = { 1244 0x000100, 1245 0x030000, 1246 0x030001 1247 }; 1248 int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 1249 1250 for (i = 0; i < nclasses; i++) { 1251 if (classcode == disp_classes[i]) 1252 return (1); 1253 } 1254 return (0); 1255 } 1256 1257 static void 1258 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn, 1259 void (*undofn)(uint8_t, uint8_t, uint8_t)) 1260 { 1261 struct pci_fixundo *newundo; 1262 1263 newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP); 1264 1265 /* 1266 * Adding an item to this list means that we must turn its NMIENABLE 1267 * bit back on at a later time. 1268 */ 1269 newundo->bus = bus; 1270 newundo->dev = dev; 1271 newundo->fn = fn; 1272 newundo->undofn = undofn; 1273 newundo->next = undolist; 1274 1275 /* add to the undo list in LIFO order */ 1276 undolist = newundo; 1277 } 1278 1279 void 1280 add_pci_fixes(void) 1281 { 1282 int i; 1283 1284 for (i = 0; i <= pci_bios_nbus; i++) { 1285 /* 1286 * For each bus, apply needed fixes to the appropriate devices. 1287 * This must be done before the main enumeration loop because 1288 * some fixes must be applied to devices normally encountered 1289 * later in the pci scan (e.g. if a fix to device 7 must be 1290 * applied before scanning device 6, applying fixes in the 1291 * normal enumeration loop would obviously be too late). 1292 */ 1293 enumerate_bus_devs(i, CONFIG_FIX); 1294 } 1295 } 1296 1297 void 1298 undo_pci_fixes(void) 1299 { 1300 struct pci_fixundo *nextundo; 1301 uint8_t bus, dev, fn; 1302 1303 /* 1304 * All fixes in the undo list are performed unconditionally. Future 1305 * fixes may require selective undo. 1306 */ 1307 while (undolist != NULL) { 1308 1309 bus = undolist->bus; 1310 dev = undolist->dev; 1311 fn = undolist->fn; 1312 1313 (*(undolist->undofn))(bus, dev, fn); 1314 1315 nextundo = undolist->next; 1316 kmem_free(undolist, sizeof (struct pci_fixundo)); 1317 undolist = nextundo; 1318 } 1319 } 1320 1321 static void 1322 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn) 1323 { 1324 uint8_t val8; 1325 1326 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1327 /* 1328 * The NMIONERR bit is turned back on to allow the SMM BIOS 1329 * to handle more critical PCI errors (e.g. PERR#). 1330 */ 1331 val8 |= AMD8111_ENABLENMI; 1332 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1333 } 1334 1335 static void 1336 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn) 1337 { 1338 uint8_t val8; 1339 1340 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1341 1342 if ((val8 & AMD8111_ENABLENMI) == 0) 1343 return; 1344 1345 /* 1346 * We reset NMIONERR in the LPC because master-abort on the PCI 1347 * bridge side of the 8111 will cause NMI, which might cause SMI, 1348 * which sometimes prevents all devices from being enumerated. 1349 */ 1350 val8 &= ~AMD8111_ENABLENMI; 1351 1352 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1353 1354 add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix); 1355 } 1356 1357 static void 1358 set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func) 1359 { 1360 uint16_t status; 1361 uint8_t header; 1362 uint8_t cap_ptr; 1363 uint8_t cap_id; 1364 uint16_t pmcsr; 1365 1366 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 1367 if (!(status & PCI_STAT_CAP)) 1368 return; /* No capabilities list */ 1369 1370 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1371 if (header == PCI_HEADER_CARDBUS) 1372 cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_RESERVED1); 1373 else 1374 cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 1375 /* 1376 * Walk the capabilities list searching for a PM entry. 1377 */ 1378 while (cap_ptr != PCI_CAP_NEXT_PTR_NULL && cap_ptr >= PCI_CAP_PTR_OFF) { 1379 cap_ptr &= PCI_CAP_PTR_MASK; 1380 cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID); 1381 if (cap_id == PCI_CAP_ID_PM) { 1382 pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR); 1383 pmcsr &= ~(PCI_PMCSR_STATE_MASK); 1384 pmcsr |= PCI_PMCSR_D0; /* D0 state */ 1385 pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr); 1386 break; 1387 } 1388 cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR); 1389 } 1390 1391 } 1392 1393 static void 1394 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 1395 ushort_t vendorid, int config_op) 1396 { 1397 char nodename[32], unitaddr[5]; 1398 dev_info_t *dip; 1399 uchar_t basecl, subcl, progcl, intr, revid; 1400 ushort_t subvenid, subdevid, status; 1401 ushort_t slot_num; 1402 uint_t classcode, revclass; 1403 int reprogram = 0, pciide = 0; 1404 int power[2] = {1, 1}; 1405 int pciex = 0; 1406 ushort_t is_pci_bridge = 0; 1407 struct pci_devfunc *devlist = NULL, *entry = NULL; 1408 iommu_private_t *private; 1409 1410 ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 1411 1412 switch (header & PCI_HEADER_TYPE_M) { 1413 case PCI_HEADER_ZERO: 1414 subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 1415 subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 1416 break; 1417 case PCI_HEADER_CARDBUS: 1418 subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 1419 subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 1420 /* Record the # of cardbus bridges found on the bus */ 1421 if (config_op == CONFIG_INFO) 1422 pci_bus_res[bus].num_cbb++; 1423 break; 1424 default: 1425 subvenid = 0; 1426 subdevid = 0; 1427 break; 1428 } 1429 1430 if (config_op == CONFIG_FIX) { 1431 if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) { 1432 pci_fix_amd8111(bus, dev, func); 1433 } 1434 return; 1435 } 1436 1437 /* XXX should be use generic names? derive from class? */ 1438 revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 1439 classcode = revclass >> 8; 1440 revid = revclass & 0xff; 1441 1442 /* figure out if this is pci-ide */ 1443 basecl = classcode >> 16; 1444 subcl = (classcode >> 8) & 0xff; 1445 progcl = classcode & 0xff; 1446 1447 1448 if (is_display(classcode)) 1449 (void) snprintf(nodename, sizeof (nodename), "display"); 1450 else if (subvenid != 0) 1451 (void) snprintf(nodename, sizeof (nodename), 1452 "pci%x,%x", subvenid, subdevid); 1453 else 1454 (void) snprintf(nodename, sizeof (nodename), 1455 "pci%x,%x", vendorid, deviceid); 1456 1457 /* make sure parent bus dip has been created */ 1458 if (pci_bus_res[bus].dip == NULL) { 1459 create_root_bus_dip(bus); 1460 } 1461 1462 ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 1463 DEVI_SID_NODEID, &dip); 1464 1465 if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num, 1466 &is_pci_bridge) == B_TRUE) 1467 pciex = 1; 1468 1469 /* add properties */ 1470 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 1471 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 1472 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 1473 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1474 "class-code", classcode); 1475 if (func == 0) 1476 (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 1477 else 1478 (void) snprintf(unitaddr, sizeof (unitaddr), 1479 "%x,%x", dev, func); 1480 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1481 "unit-address", unitaddr); 1482 1483 /* add device_type for display nodes */ 1484 if (is_display(classcode)) { 1485 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1486 "device_type", "display"); 1487 } 1488 /* add special stuff for header type */ 1489 if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 1490 uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 1491 uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 1492 1493 if (subvenid != 0) { 1494 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1495 "subsystem-id", subdevid); 1496 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1497 "subsystem-vendor-id", subvenid); 1498 } 1499 if (!pciex) 1500 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1501 "min-grant", mingrant); 1502 if (!pciex) 1503 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1504 "max-latency", maxlatency); 1505 } 1506 1507 /* interrupt, record if not 0 */ 1508 intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 1509 if (intr != 0) 1510 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1511 "interrupts", intr); 1512 1513 /* 1514 * Add support for 133 mhz pci eventually 1515 */ 1516 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 1517 1518 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1519 "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 1520 if (!pciex && (status & PCI_STAT_FBBC)) 1521 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1522 "fast-back-to-back"); 1523 if (!pciex && (status & PCI_STAT_66MHZ)) 1524 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1525 "66mhz-capable"); 1526 if (status & PCI_STAT_UDF) 1527 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1528 "udf-supported"); 1529 if (pciex && slot_num) { 1530 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1531 "physical-slot#", slot_num); 1532 if (!is_pci_bridge) 1533 pciex_slot_names_prop(dip, slot_num); 1534 } 1535 1536 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1537 "power-consumption", power, 2); 1538 1539 /* Set the device PM state to D0 */ 1540 set_devpm_d0(bus, dev, func); 1541 1542 if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) 1543 add_ppb_props(dip, bus, dev, func, pciex, is_pci_bridge); 1544 else { 1545 /* 1546 * Record the non-PPB devices on the bus for possible 1547 * reprogramming at 2nd bus enumeration. 1548 * Note: PPB reprogramming is done in fix_ppb_res() 1549 */ 1550 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 1551 entry = kmem_zalloc(sizeof (*entry), KM_SLEEP); 1552 entry->dip = dip; 1553 entry->dev = dev; 1554 entry->func = func; 1555 entry->next = devlist; 1556 pci_bus_res[bus].privdata = entry; 1557 } 1558 1559 if (config_op == CONFIG_INFO && 1560 IS_CLASS_IOAPIC(basecl, subcl, progcl)) { 1561 create_ioapic_node(bus, dev, func, vendorid, deviceid); 1562 } 1563 1564 /* check for ck8-04 based PCI ISA bridge only */ 1565 if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) && 1566 (func == 0)) 1567 add_nvidia_isa_bridge_props(dip, bus, dev, func); 1568 1569 if (pciex && is_pci_bridge) 1570 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 1571 (char *)"PCIe-PCI bridge"); 1572 else 1573 add_model_prop(dip, classcode); 1574 1575 add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 1576 revid, classcode, pciex); 1577 1578 /* 1579 * See if this device is a controller that advertises 1580 * itself to be a standard ATA task file controller, or one that 1581 * has been hard coded. 1582 * 1583 * If it is, check if any other higher precedence driver listed in 1584 * driver_aliases will claim the node by calling 1585 * ddi_compatibile_driver_major. If so, clear pciide and do not 1586 * create a pci-ide node or any other special handling. 1587 * 1588 * If another driver does not bind, set the node name to pci-ide 1589 * and then let the special pci-ide handling for registers and 1590 * child pci-ide nodes proceed below. 1591 */ 1592 if (is_pciide(basecl, subcl, revid, vendorid, deviceid, 1593 subvenid, subdevid) == 1) { 1594 if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) { 1595 (void) ndi_devi_set_nodename(dip, "pci-ide", 0); 1596 pciide = 1; 1597 } 1598 } 1599 1600 reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 1601 (void) ndi_devi_bind_driver(dip, 0); 1602 1603 /* special handling for pci-ide */ 1604 if (pciide) { 1605 dev_info_t *cdip; 1606 1607 /* 1608 * Create properties specified by P1275 Working Group 1609 * Proposal #414 Version 1 1610 */ 1611 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1612 "device_type", "pci-ide"); 1613 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1614 "#address-cells", 1); 1615 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1616 "#size-cells", 0); 1617 1618 /* allocate two child nodes */ 1619 ndi_devi_alloc_sleep(dip, "ide", 1620 (pnode_t)DEVI_SID_NODEID, &cdip); 1621 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 1622 "reg", 0); 1623 (void) ndi_devi_bind_driver(cdip, 0); 1624 ndi_devi_alloc_sleep(dip, "ide", 1625 (pnode_t)DEVI_SID_NODEID, &cdip); 1626 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 1627 "reg", 1); 1628 (void) ndi_devi_bind_driver(cdip, 0); 1629 1630 reprogram = 0; /* don't reprogram pci-ide bridge */ 1631 } 1632 1633 /* allocate and set up iommu private */ 1634 private = kmem_alloc(sizeof (iommu_private_t), KM_SLEEP); 1635 private->idp_seg = 0; 1636 private->idp_bus = bus; 1637 private->idp_devfn = (dev << 3) | func; 1638 private->idp_sec = 0; 1639 private->idp_sub = 0; 1640 private->idp_bbp_type = IOMMU_PPB_NONE; 1641 /* record the bridge */ 1642 private->idp_is_bridge = ((basecl == PCI_CLASS_BRIDGE) && 1643 (subcl == PCI_BRIDGE_PCI)); 1644 if (private->idp_is_bridge) { 1645 private->idp_sec = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 1646 private->idp_sub = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 1647 if (pciex && is_pci_bridge) 1648 private->idp_bbp_type = IOMMU_PPB_PCIE_PCI; 1649 else if (pciex) 1650 private->idp_bbp_type = IOMMU_PPB_PCIE_PCIE; 1651 else 1652 private->idp_bbp_type = IOMMU_PPB_PCI_PCI; 1653 } 1654 /* record the special devices */ 1655 private->idp_is_display = (is_display(classcode) ? B_TRUE : B_FALSE); 1656 private->idp_is_lpc = ((basecl == PCI_CLASS_BRIDGE) && 1657 (subcl == PCI_BRIDGE_ISA)); 1658 private->idp_domain = NULL; 1659 /* hook the private to dip */ 1660 DEVI(dip)->devi_iommu_private = private; 1661 1662 if (reprogram && (entry != NULL)) 1663 entry->reprogram = B_TRUE; 1664 } 1665 1666 /* 1667 * Set the compatible property to a value compliant with 1668 * rev 2.1 of the IEEE1275 PCI binding. 1669 * (Also used for PCI-Express devices). 1670 * 1671 * pciVVVV,DDDD.SSSS.ssss.RR (0) 1672 * pciVVVV,DDDD.SSSS.ssss (1) 1673 * pciSSSS,ssss (2) 1674 * pciVVVV,DDDD.RR (3) 1675 * pciVVVV,DDDD (4) 1676 * pciclass,CCSSPP (5) 1677 * pciclass,CCSS (6) 1678 * 1679 * The Subsystem (SSSS) forms are not inserted if 1680 * subsystem-vendor-id is 0. 1681 * 1682 * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above 1683 * property 2 is not created as per "1275 bindings for PCI Express Interconnect" 1684 * 1685 * Set with setprop and \x00 between each 1686 * to generate the encoded string array form. 1687 */ 1688 void 1689 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 1690 ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode, 1691 int pciex) 1692 { 1693 int i = 0; 1694 int size = COMPAT_BUFSIZE; 1695 char *compat[13]; 1696 char *buf, *curr; 1697 1698 curr = buf = kmem_alloc(size, KM_SLEEP); 1699 1700 if (pciex) { 1701 if (subvenid) { 1702 compat[i++] = curr; /* form 0 */ 1703 (void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x", 1704 vendorid, deviceid, subvenid, subdevid, revid); 1705 size -= strlen(curr) + 1; 1706 curr += strlen(curr) + 1; 1707 1708 compat[i++] = curr; /* form 1 */ 1709 (void) snprintf(curr, size, "pciex%x,%x.%x.%x", 1710 vendorid, deviceid, subvenid, subdevid); 1711 size -= strlen(curr) + 1; 1712 curr += strlen(curr) + 1; 1713 1714 } 1715 compat[i++] = curr; /* form 3 */ 1716 (void) snprintf(curr, size, "pciex%x,%x.%x", 1717 vendorid, deviceid, revid); 1718 size -= strlen(curr) + 1; 1719 curr += strlen(curr) + 1; 1720 1721 compat[i++] = curr; /* form 4 */ 1722 (void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid); 1723 size -= strlen(curr) + 1; 1724 curr += strlen(curr) + 1; 1725 1726 compat[i++] = curr; /* form 5 */ 1727 (void) snprintf(curr, size, "pciexclass,%06x", classcode); 1728 size -= strlen(curr) + 1; 1729 curr += strlen(curr) + 1; 1730 1731 compat[i++] = curr; /* form 6 */ 1732 (void) snprintf(curr, size, "pciexclass,%04x", 1733 (classcode >> 8)); 1734 size -= strlen(curr) + 1; 1735 curr += strlen(curr) + 1; 1736 } 1737 1738 if (subvenid) { 1739 compat[i++] = curr; /* form 0 */ 1740 (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 1741 vendorid, deviceid, subvenid, subdevid, revid); 1742 size -= strlen(curr) + 1; 1743 curr += strlen(curr) + 1; 1744 1745 compat[i++] = curr; /* form 1 */ 1746 (void) snprintf(curr, size, "pci%x,%x.%x.%x", 1747 vendorid, deviceid, subvenid, subdevid); 1748 size -= strlen(curr) + 1; 1749 curr += strlen(curr) + 1; 1750 1751 compat[i++] = curr; /* form 2 */ 1752 (void) snprintf(curr, size, "pci%x,%x", subvenid, subdevid); 1753 size -= strlen(curr) + 1; 1754 curr += strlen(curr) + 1; 1755 } 1756 compat[i++] = curr; /* form 3 */ 1757 (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 1758 size -= strlen(curr) + 1; 1759 curr += strlen(curr) + 1; 1760 1761 compat[i++] = curr; /* form 4 */ 1762 (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 1763 size -= strlen(curr) + 1; 1764 curr += strlen(curr) + 1; 1765 1766 compat[i++] = curr; /* form 5 */ 1767 (void) snprintf(curr, size, "pciclass,%06x", classcode); 1768 size -= strlen(curr) + 1; 1769 curr += strlen(curr) + 1; 1770 1771 compat[i++] = curr; /* form 6 */ 1772 (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 1773 size -= strlen(curr) + 1; 1774 curr += strlen(curr) + 1; 1775 1776 (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 1777 "compatible", compat, i); 1778 kmem_free(buf, COMPAT_BUFSIZE); 1779 } 1780 1781 /* 1782 * Adjust the reg properties for a dual channel PCI-IDE device. 1783 * 1784 * NOTE: don't do anything that changes the order of the hard-decodes 1785 * and programmed BARs. The kernel driver depends on these values 1786 * being in this order regardless of whether they're for a 'native' 1787 * mode BAR or not. 1788 */ 1789 /* 1790 * config info for pci-ide devices 1791 */ 1792 static struct { 1793 uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 1794 uchar_t bar_offset; /* offset for alt status register */ 1795 ushort_t addr; /* compatibility mode base address */ 1796 ushort_t length; /* number of ports for this BAR */ 1797 } pciide_bar[] = { 1798 { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 1799 { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 1800 { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 1801 { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 1802 }; 1803 1804 static int 1805 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 1806 { 1807 int hard_decode = 0; 1808 1809 /* 1810 * Adjust the base and len for the BARs of the PCI-IDE 1811 * device's primary and secondary controllers. The first 1812 * two BARs are for the primary controller and the next 1813 * two BARs are for the secondary controller. The fifth 1814 * and sixth bars are never adjusted. 1815 */ 1816 if (index >= 0 && index <= 3) { 1817 *lenp = pciide_bar[index].length; 1818 1819 if (progcl & pciide_bar[index].native_mask) { 1820 *basep += pciide_bar[index].bar_offset; 1821 } else { 1822 *basep = pciide_bar[index].addr; 1823 hard_decode = 1; 1824 } 1825 } 1826 1827 /* 1828 * if either base or len is zero make certain both are zero 1829 */ 1830 if (*basep == 0 || *lenp == 0) { 1831 *basep = 0; 1832 *lenp = 0; 1833 hard_decode = 0; 1834 } 1835 1836 return (hard_decode); 1837 } 1838 1839 1840 /* 1841 * Add the "reg" and "assigned-addresses" property 1842 */ 1843 static int 1844 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 1845 int config_op, int pciide) 1846 { 1847 uchar_t baseclass, subclass, progclass, header; 1848 ushort_t bar_sz; 1849 uint_t value = 0, len, devloc; 1850 uint_t base, base_hi, type; 1851 ushort_t offset, end; 1852 int max_basereg, j, reprogram = 0; 1853 uint_t phys_hi; 1854 struct memlist **io_res, **mres, **mem_res, **pmem_res; 1855 struct memlist **io_res_used, **mres_used; 1856 struct memlist **mem_res_used, **pmem_res_used; 1857 uchar_t res_bus; 1858 1859 pci_regspec_t regs[16] = {{0}}; 1860 pci_regspec_t assigned[15] = {{0}}; 1861 int nreg, nasgn; 1862 1863 io_res = &pci_bus_res[bus].io_ports; 1864 io_res_used = &pci_bus_res[bus].io_ports_used; 1865 mem_res = &pci_bus_res[bus].mem_space; 1866 mem_res_used = &pci_bus_res[bus].mem_space_used; 1867 if (bus == 0) { /* for bus 0, there is only mem_space */ 1868 pmem_res = mem_res; 1869 pmem_res_used = mem_res_used; 1870 } else { 1871 pmem_res = &pci_bus_res[bus].pmem_space; 1872 pmem_res_used = &pci_bus_res[bus].pmem_space_used; 1873 } 1874 1875 devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 1876 regs[0].pci_phys_hi = devloc; 1877 nreg = 1; /* rest of regs[0] is all zero */ 1878 nasgn = 0; 1879 1880 baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 1881 subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 1882 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 1883 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1884 1885 switch (header) { 1886 case PCI_HEADER_ZERO: 1887 max_basereg = PCI_BASE_NUM; 1888 break; 1889 case PCI_HEADER_PPB: 1890 max_basereg = PCI_BCNF_BASE_NUM; 1891 break; 1892 case PCI_HEADER_CARDBUS: 1893 max_basereg = PCI_CBUS_BASE_NUM; 1894 break; 1895 default: 1896 max_basereg = 0; 1897 break; 1898 } 1899 1900 /* 1901 * Create the register property by saving the current 1902 * value of the base register. Write 0xffffffff to the 1903 * base register. Read the value back to determine the 1904 * required size of the address space. Restore the base 1905 * register contents. 1906 * 1907 * Do not disable I/O and memory access; this isn't necessary 1908 * since no driver is yet attached to this device, and disabling 1909 * I/O and memory access has the side-effect of disabling PCI-PCI 1910 * bridge mappings, which makes the bridge transparent to secondary- 1911 * bus activity (see sections 4.1-4.3 of the PCI-PCI Bridge 1912 * Spec V1.2). 1913 */ 1914 end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 1915 for (j = 0, offset = PCI_CONF_BASE0; offset < end; 1916 j++, offset += bar_sz) { 1917 int hard_decode = 0; 1918 1919 /* determine the size of the address space */ 1920 base = pci_getl(bus, dev, func, offset); 1921 pci_putl(bus, dev, func, offset, 0xffffffff); 1922 value = pci_getl(bus, dev, func, offset); 1923 pci_putl(bus, dev, func, offset, base); 1924 1925 /* construct phys hi,med.lo, size hi, lo */ 1926 if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 1927 /* i/o space */ 1928 bar_sz = PCI_BAR_SZ_32; 1929 value &= PCI_BASE_IO_ADDR_M; 1930 len = ((value ^ (value-1)) + 1) >> 1; 1931 1932 /* XXX Adjust first 4 IDE registers */ 1933 if (pciide) { 1934 if (subclass != PCI_MASS_IDE) 1935 progclass = (PCI_IDE_IF_NATIVE_PRI | 1936 PCI_IDE_IF_NATIVE_SEC); 1937 hard_decode = pciIdeAdjustBAR(progclass, j, 1938 &base, &len); 1939 } else if (value == 0) { 1940 /* skip base regs with size of 0 */ 1941 continue; 1942 } 1943 1944 regs[nreg].pci_size_low = 1945 assigned[nasgn].pci_size_low = len; 1946 if (!hard_decode) { 1947 regs[nreg].pci_phys_hi = 1948 (PCI_ADDR_IO | devloc) + offset; 1949 } else { 1950 regs[nreg].pci_phys_hi = 1951 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + 1952 offset; 1953 regs[nreg].pci_phys_low = 1954 base & PCI_BASE_IO_ADDR_M; 1955 } 1956 assigned[nasgn].pci_phys_hi = 1957 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + offset; 1958 type = base & (~PCI_BASE_IO_ADDR_M); 1959 base &= PCI_BASE_IO_ADDR_M; 1960 /* 1961 * A device under a subtractive PPB can allocate 1962 * resources from its parent bus if there is no resource 1963 * available on its own bus. 1964 */ 1965 if ((config_op == CONFIG_NEW) && (*io_res == NULL)) { 1966 res_bus = bus; 1967 while (pci_bus_res[res_bus].subtractive) { 1968 res_bus = pci_bus_res[res_bus].par_bus; 1969 if (res_bus == (uchar_t)-1) 1970 break; /* root bus already */ 1971 if (pci_bus_res[res_bus].io_ports) { 1972 io_res = &pci_bus_res 1973 [res_bus].io_ports; 1974 break; 1975 } 1976 } 1977 } 1978 1979 /* 1980 * first pass - gather what's there 1981 * update/second pass - adjust/allocate regions 1982 * config - allocate regions 1983 */ 1984 if (config_op == CONFIG_INFO) { /* first pass */ 1985 /* take out of the resource map of the bus */ 1986 if (base != 0) { 1987 if (*io_res) 1988 (void) memlist_remove(io_res, 1989 base, len); 1990 memlist_insert(io_res_used, base, len); 1991 } else 1992 reprogram = 1; 1993 } else if ((*io_res && base == 0) || 1994 pci_bus_res[bus].io_reprogram) { 1995 base = (uint_t)memlist_find(io_res, len, len); 1996 if (base != 0) { 1997 memlist_insert(io_res_used, base, len); 1998 /* XXX need to worry about 64-bit? */ 1999 pci_putl(bus, dev, func, offset, 2000 base | type); 2001 base = pci_getl(bus, dev, func, offset); 2002 base &= PCI_BASE_IO_ADDR_M; 2003 } 2004 if (base == 0) { 2005 cmn_err(CE_WARN, "failed to program" 2006 " IO space [%d/%d/%d] BAR@0x%x" 2007 " length 0x%x", 2008 bus, dev, func, offset, len); 2009 } 2010 } 2011 assigned[nasgn].pci_phys_low = base; 2012 nreg++, nasgn++; 2013 2014 } else { 2015 /* memory space */ 2016 if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 2017 bar_sz = PCI_BAR_SZ_64; 2018 base_hi = pci_getl(bus, dev, func, offset + 4); 2019 phys_hi = PCI_ADDR_MEM64; 2020 } else { 2021 bar_sz = PCI_BAR_SZ_32; 2022 base_hi = 0; 2023 phys_hi = PCI_ADDR_MEM32; 2024 } 2025 2026 /* skip base regs with size of 0 */ 2027 value &= PCI_BASE_M_ADDR_M; 2028 2029 if (value == 0) { 2030 continue; 2031 } 2032 len = ((value ^ (value-1)) + 1) >> 1; 2033 regs[nreg].pci_size_low = 2034 assigned[nasgn].pci_size_low = len; 2035 2036 phys_hi |= (devloc | offset); 2037 if (base & PCI_BASE_PREF_M) { 2038 mres = pmem_res; 2039 mres_used = pmem_res_used; 2040 phys_hi |= PCI_PREFETCH_B; 2041 } else { 2042 mres = mem_res; 2043 mres_used = mem_res_used; 2044 } 2045 /* 2046 * A device under a subtractive PPB can allocate 2047 * resources from its parent bus if there is no resource 2048 * available on its own bus. 2049 */ 2050 if ((config_op == CONFIG_NEW) && (*mres == NULL)) { 2051 res_bus = bus; 2052 while (pci_bus_res[res_bus].subtractive) { 2053 res_bus = pci_bus_res[res_bus].par_bus; 2054 if (res_bus == (uchar_t)-1) 2055 break; /* root bus already */ 2056 if ((phys_hi & PCI_PREFETCH_B) && 2057 (res_bus != 0)) 2058 mres = &pci_bus_res 2059 [res_bus].pmem_space; 2060 else 2061 mres = &pci_bus_res 2062 [res_bus].mem_space; 2063 if (*mres) 2064 break; 2065 } 2066 } 2067 2068 regs[nreg].pci_phys_hi = 2069 assigned[nasgn].pci_phys_hi = phys_hi; 2070 assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 2071 assigned[nasgn].pci_phys_mid = base_hi; 2072 type = base & ~PCI_BASE_M_ADDR_M; 2073 base &= PCI_BASE_M_ADDR_M; 2074 2075 if (config_op == CONFIG_INFO) { 2076 /* take out of the resource map of the bus */ 2077 if (base != 0) { 2078 if (*mres) 2079 (void) memlist_remove(mres, 2080 base, len); 2081 memlist_insert(mres_used, base, len); 2082 } else 2083 reprogram = 1; 2084 } else if ((*mres && base == 0) || 2085 pci_bus_res[bus].mem_reprogram) { 2086 base = (uint_t)memlist_find(mres, len, len); 2087 if (base != NULL) { 2088 memlist_insert(mres_used, base, len); 2089 pci_putl(bus, dev, func, offset, 2090 base | type); 2091 base = pci_getl(bus, dev, func, offset); 2092 base &= PCI_BASE_M_ADDR_M; 2093 } 2094 2095 if (base == 0) { 2096 cmn_err(CE_WARN, "failed to program " 2097 "mem space [%d/%d/%d] BAR@0x%x" 2098 " length 0x%x", 2099 bus, dev, func, offset, len); 2100 } 2101 } 2102 assigned[nasgn].pci_phys_low = base; 2103 nreg++, nasgn++; 2104 } 2105 } 2106 switch (header) { 2107 case PCI_HEADER_ZERO: 2108 offset = PCI_CONF_ROM; 2109 break; 2110 case PCI_HEADER_PPB: 2111 offset = PCI_BCNF_ROM; 2112 break; 2113 default: /* including PCI_HEADER_CARDBUS */ 2114 goto done; 2115 } 2116 2117 /* 2118 * Add the expansion rom memory space 2119 * Determine the size of the ROM base reg; don't write reserved bits 2120 * ROM isn't in the PCI memory space. 2121 */ 2122 base = pci_getl(bus, dev, func, offset); 2123 pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 2124 value = pci_getl(bus, dev, func, offset); 2125 pci_putl(bus, dev, func, offset, base); 2126 if (value & PCI_BASE_ROM_ENABLE) 2127 value &= PCI_BASE_ROM_ADDR_M; 2128 else 2129 value = 0; 2130 2131 if (value != 0) { 2132 regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 2133 assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 2134 PCI_ADDR_MEM32 | devloc) + offset; 2135 base &= PCI_BASE_ROM_ADDR_M; 2136 assigned[nasgn].pci_phys_low = base; 2137 len = ((value ^ (value-1)) + 1) >> 1; 2138 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 2139 nreg++, nasgn++; 2140 /* take it out of the memory resource */ 2141 if (*mem_res && base != 0) 2142 (void) memlist_remove(mem_res, base, len); 2143 if (base != 0) 2144 memlist_insert(mem_res, base, len); 2145 } 2146 2147 /* 2148 * The following are ISA resources. There are not part 2149 * of the PCI local bus resources. So don't attempt to 2150 * do resource accounting against PCI. 2151 */ 2152 2153 /* add the three hard-decode, aliased address spaces for VGA */ 2154 if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 2155 (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 2156 2157 /* VGA hard decode 0x3b0-0x3bb */ 2158 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2159 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2160 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 2161 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 2162 nreg++, nasgn++; 2163 2164 /* VGA hard decode 0x3c0-0x3df */ 2165 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2166 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2167 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 2168 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 2169 nreg++, nasgn++; 2170 2171 /* Video memory */ 2172 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2173 (PCI_RELOCAT_B | PCI_ADDR_MEM32 | devloc); 2174 regs[nreg].pci_phys_low = 2175 assigned[nasgn].pci_phys_low = 0xa0000; 2176 regs[nreg].pci_size_low = 2177 assigned[nasgn].pci_size_low = 0x20000; 2178 nreg++, nasgn++; 2179 } 2180 2181 /* add the hard-decode, aliased address spaces for 8514 */ 2182 if ((baseclass == PCI_CLASS_DISPLAY) && 2183 (subclass == PCI_DISPLAY_VGA) && 2184 (progclass & PCI_DISPLAY_IF_8514)) { 2185 2186 /* hard decode 0x2e8 */ 2187 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2188 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2189 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 2190 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 2191 nreg++, nasgn++; 2192 2193 /* hard decode 0x2ea-0x2ef */ 2194 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2195 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2196 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 2197 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 2198 nreg++, nasgn++; 2199 } 2200 2201 done: 2202 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 2203 (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 2204 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 2205 "assigned-addresses", 2206 (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 2207 2208 return (reprogram); 2209 } 2210 2211 static void 2212 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 2213 int pciex, ushort_t is_pci_bridge) 2214 { 2215 char *dev_type; 2216 int i; 2217 uint_t val, io_range[2], mem_range[2], pmem_range[2]; 2218 uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 2219 uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 2220 uchar_t progclass; 2221 2222 ASSERT(secbus <= subbus); 2223 2224 /* 2225 * Check if it's a subtractive PPB. 2226 */ 2227 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 2228 if (progclass == PCI_BRIDGE_PCI_IF_SUBDECODE) 2229 pci_bus_res[secbus].subtractive = B_TRUE; 2230 2231 /* 2232 * Some BIOSes lie about max pci busses, we allow for 2233 * such mistakes here 2234 */ 2235 if (subbus > pci_bios_nbus) { 2236 pci_bios_nbus = subbus; 2237 alloc_res_array(); 2238 } 2239 2240 ASSERT(pci_bus_res[secbus].dip == NULL); 2241 pci_bus_res[secbus].dip = dip; 2242 pci_bus_res[secbus].par_bus = bus; 2243 2244 dev_type = (pciex && !is_pci_bridge) ? "pciex" : "pci"; 2245 2246 /* setup bus number hierarchy */ 2247 pci_bus_res[secbus].sub_bus = subbus; 2248 /* 2249 * Keep track of the largest subordinate bus number (this is essential 2250 * for peer busses because there is no other way of determining its 2251 * subordinate bus number). 2252 */ 2253 if (subbus > pci_bus_res[bus].sub_bus) 2254 pci_bus_res[bus].sub_bus = subbus; 2255 /* 2256 * Loop through subordinate busses, initializing their parent bus 2257 * field to this bridge's parent. The subordinate busses' parent 2258 * fields may very well be further refined later, as child bridges 2259 * are enumerated. (The value is to note that the subordinate busses 2260 * are not peer busses by changing their par_bus fields to anything 2261 * other than -1.) 2262 */ 2263 for (i = secbus + 1; i <= subbus; i++) 2264 pci_bus_res[i].par_bus = bus; 2265 2266 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 2267 "device_type", dev_type); 2268 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2269 "#address-cells", 3); 2270 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2271 "#size-cells", 2); 2272 2273 /* 2274 * According to PPB spec, the base register should be programmed 2275 * with a value bigger than the limit register when there are 2276 * no resources available. This applies to io, memory, and 2277 * prefetchable memory. 2278 */ 2279 2280 /* 2281 * io range 2282 * We determine i/o windows that are left unconfigured by BIOS 2283 * through its i/o enable bit as Microsoft recommends OEMs to do. 2284 * If it is unset, we disable i/o and mark it for reconfiguration in 2285 * later passes by setting the base > limit 2286 */ 2287 val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM); 2288 if (val & PCI_COMM_IO) { 2289 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 2290 io_range[0] = ((val & 0xf0) << 8); 2291 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 2292 io_range[1] = ((val & 0xf0) << 8) | 0xFFF; 2293 } else { 2294 io_range[0] = 0x9fff; 2295 io_range[1] = 0x1000; 2296 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 2297 (uint8_t)((io_range[0] >> 8) & 0xf0)); 2298 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 2299 (uint8_t)((io_range[1] >> 8) & 0xf0)); 2300 pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 2301 pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 2302 } 2303 2304 if (io_range[0] != 0 && io_range[0] < io_range[1]) { 2305 memlist_insert(&pci_bus_res[secbus].io_ports, 2306 (uint64_t)io_range[0], 2307 (uint64_t)(io_range[1] - io_range[0] + 1)); 2308 memlist_insert(&pci_bus_res[bus].io_ports_used, 2309 (uint64_t)io_range[0], 2310 (uint64_t)(io_range[1] - io_range[0] + 1)); 2311 if (pci_bus_res[bus].io_ports != NULL) { 2312 (void) memlist_remove(&pci_bus_res[bus].io_ports, 2313 (uint64_t)io_range[0], 2314 (uint64_t)(io_range[1] - io_range[0] + 1)); 2315 } 2316 dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x", 2317 secbus, io_range[0], io_range[1]); 2318 /* if 32-bit supported, make sure upper bits are not set */ 2319 if ((val & 0xf) == 1 && 2320 pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) { 2321 cmn_err(CE_NOTE, "unsupported 32-bit IO address on" 2322 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 2323 } 2324 } 2325 2326 /* mem range */ 2327 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 2328 mem_range[0] = ((val & 0xFFF0) << 16); 2329 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 2330 mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 2331 if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 2332 memlist_insert(&pci_bus_res[secbus].mem_space, 2333 (uint64_t)mem_range[0], 2334 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2335 memlist_insert(&pci_bus_res[bus].mem_space_used, 2336 (uint64_t)mem_range[0], 2337 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2338 /* remove from parent resouce list */ 2339 if (pci_bus_res[bus].mem_space != NULL) { 2340 (void) memlist_remove(&pci_bus_res[bus].mem_space, 2341 (uint64_t)mem_range[0], 2342 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2343 } 2344 dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x", 2345 secbus, mem_range[0], mem_range[1]); 2346 } 2347 2348 /* prefetchable memory range */ 2349 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 2350 pmem_range[0] = ((val & 0xFFF0) << 16); 2351 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 2352 pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 2353 if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 2354 memlist_insert(&pci_bus_res[secbus].pmem_space, 2355 (uint64_t)pmem_range[0], 2356 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2357 memlist_insert(&pci_bus_res[bus].pmem_space_used, 2358 (uint64_t)pmem_range[0], 2359 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2360 if (pci_bus_res[bus].pmem_space != NULL) { 2361 (void) memlist_remove(&pci_bus_res[bus].pmem_space, 2362 (uint64_t)pmem_range[0], 2363 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2364 } 2365 dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x", 2366 secbus, pmem_range[0], pmem_range[1]); 2367 /* if 64-bit supported, make sure upper bits are not set */ 2368 if ((val & 0xf) == 1 && 2369 pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) { 2370 cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on" 2371 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 2372 } 2373 } 2374 2375 add_bus_range_prop(secbus); 2376 add_ppb_ranges_prop(secbus); 2377 } 2378 2379 extern const struct pci_class_strings_s class_pci[]; 2380 extern int class_pci_items; 2381 2382 static void 2383 add_model_prop(dev_info_t *dip, uint_t classcode) 2384 { 2385 const char *desc; 2386 int i; 2387 uchar_t baseclass = classcode >> 16; 2388 uchar_t subclass = (classcode >> 8) & 0xff; 2389 uchar_t progclass = classcode & 0xff; 2390 2391 if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 2392 desc = "IDE controller"; 2393 } else { 2394 for (desc = 0, i = 0; i < class_pci_items; i++) { 2395 if ((baseclass == class_pci[i].base_class) && 2396 (subclass == class_pci[i].sub_class) && 2397 (progclass == class_pci[i].prog_class)) { 2398 desc = class_pci[i].actual_desc; 2399 break; 2400 } 2401 } 2402 if (i == class_pci_items) 2403 desc = "Unknown class of pci/pnpbios device"; 2404 } 2405 2406 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 2407 (char *)desc); 2408 } 2409 2410 static void 2411 add_bus_range_prop(int bus) 2412 { 2413 int bus_range[2]; 2414 2415 if (pci_bus_res[bus].dip == NULL) 2416 return; 2417 bus_range[0] = bus; 2418 bus_range[1] = pci_bus_res[bus].sub_bus; 2419 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 2420 "bus-range", (int *)bus_range, 2); 2421 } 2422 2423 /* 2424 * Add slot-names property for any named pci hot-plug slots 2425 */ 2426 static void 2427 add_bus_slot_names_prop(int bus) 2428 { 2429 char slotprop[256]; 2430 int len; 2431 2432 if (pci_bus_res[bus].dip != NULL) { 2433 /* simply return if the property is already defined */ 2434 if (ddi_prop_exists(DDI_DEV_T_ANY, pci_bus_res[bus].dip, 2435 DDI_PROP_DONTPASS, "slot-names")) 2436 return; 2437 } 2438 2439 len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); 2440 if (len > 0) { 2441 /* 2442 * Only create a peer bus node if this bus may be a peer bus. 2443 * It may be a peer bus if the dip is NULL and if par_bus is 2444 * -1 (par_bus is -1 if this bus was not found to be 2445 * subordinate to any PCI-PCI bridge). 2446 * If it's not a peer bus, then the ACPI BBN-handling code 2447 * will remove it later. 2448 */ 2449 if (pci_bus_res[bus].par_bus == (uchar_t)-1 && 2450 pci_bus_res[bus].dip == NULL) { 2451 2452 create_root_bus_dip(bus); 2453 } 2454 if (pci_bus_res[bus].dip != NULL) { 2455 ASSERT((len % sizeof (int)) == 0); 2456 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 2457 pci_bus_res[bus].dip, "slot-names", 2458 (int *)slotprop, len / sizeof (int)); 2459 } else { 2460 cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI " 2461 "IRQ routing table; Not adding slot-names " 2462 "property for incorrect bus %d", bus); 2463 } 2464 } 2465 } 2466 2467 static int 2468 memlist_to_range(ppb_ranges_t *rp, struct memlist *entry, int type) 2469 { 2470 if (entry == NULL) 2471 return (0); 2472 2473 /* assume 32-bit addresses */ 2474 rp->child_high = rp->parent_high = type; 2475 rp->child_mid = rp->parent_mid = 0; 2476 rp->child_low = rp->parent_low = (uint32_t)entry->address; 2477 rp->size_high = 0; 2478 rp->size_low = (uint32_t)entry->size; 2479 return (1); 2480 } 2481 2482 static void 2483 add_ppb_ranges_prop(int bus) 2484 { 2485 int i = 0; 2486 ppb_ranges_t *rp; 2487 2488 rp = kmem_alloc(3 * sizeof (*rp), KM_SLEEP); 2489 2490 i = memlist_to_range(&rp[0], pci_bus_res[bus].io_ports, 2491 PCI_ADDR_IO | PCI_REG_REL_M); 2492 i += memlist_to_range(&rp[i], pci_bus_res[bus].mem_space, 2493 PCI_ADDR_MEM32 | PCI_REG_REL_M); 2494 i += memlist_to_range(&rp[i], pci_bus_res[bus].pmem_space, 2495 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 2496 2497 if (i != 0) 2498 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 2499 pci_bus_res[bus].dip, "ranges", (int *)rp, 2500 i * sizeof (ppb_ranges_t) / sizeof (int)); 2501 kmem_free(rp, 3 * sizeof (*rp)); 2502 } 2503 2504 static int 2505 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 2506 { 2507 int i = 0; 2508 2509 while (list) { 2510 /* assume 32-bit addresses */ 2511 sp->pci_phys_hi = type; 2512 sp->pci_phys_mid = 0; 2513 sp->pci_phys_low = (uint32_t)list->address; 2514 sp->pci_size_hi = 0; 2515 sp->pci_size_low = (uint32_t)list->size; 2516 2517 list = list->next; 2518 sp++, i++; 2519 } 2520 return (i); 2521 } 2522 2523 static void 2524 add_bus_available_prop(int bus) 2525 { 2526 int i, count; 2527 struct pci_phys_spec *sp; 2528 2529 count = memlist_count(pci_bus_res[bus].io_ports) + 2530 memlist_count(pci_bus_res[bus].mem_space) + 2531 memlist_count(pci_bus_res[bus].pmem_space); 2532 2533 if (count == 0) /* nothing available */ 2534 return; 2535 2536 sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 2537 i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_ports, 2538 PCI_ADDR_IO | PCI_REG_REL_M); 2539 i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_space, 2540 PCI_ADDR_MEM32 | PCI_REG_REL_M); 2541 i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_space, 2542 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 2543 ASSERT(i == count); 2544 2545 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 2546 "available", (int *)sp, 2547 i * sizeof (struct pci_phys_spec) / sizeof (int)); 2548 kmem_free(sp, count * sizeof (*sp)); 2549 } 2550 2551 static void 2552 alloc_res_array(void) 2553 { 2554 static int array_max = 0; 2555 int old_max; 2556 void *old_res; 2557 2558 if (array_max > pci_bios_nbus + 1) 2559 return; /* array is big enough */ 2560 2561 old_max = array_max; 2562 old_res = pci_bus_res; 2563 2564 if (array_max == 0) 2565 array_max = 16; /* start with a reasonable number */ 2566 2567 while (array_max < pci_bios_nbus + 1) 2568 array_max <<= 1; 2569 pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 2570 array_max * sizeof (struct pci_bus_resource), KM_SLEEP); 2571 2572 if (old_res) { /* copy content and free old array */ 2573 bcopy(old_res, pci_bus_res, 2574 old_max * sizeof (struct pci_bus_resource)); 2575 kmem_free(old_res, old_max * sizeof (struct pci_bus_resource)); 2576 } 2577 } 2578 2579 static void 2580 create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 2581 ushort_t deviceid) 2582 { 2583 static dev_info_t *ioapicsnode = NULL; 2584 static int numioapics = 0; 2585 dev_info_t *ioapic_node; 2586 uint64_t physaddr; 2587 uint32_t lobase, hibase = 0; 2588 2589 /* BAR 0 contains the IOAPIC's memory-mapped I/O address */ 2590 lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0); 2591 2592 /* We (and the rest of the world) only support memory-mapped IOAPICs */ 2593 if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM) 2594 return; 2595 2596 if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) 2597 hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4); 2598 2599 lobase &= PCI_BASE_M_ADDR_M; 2600 2601 physaddr = (((uint64_t)hibase) << 32) | lobase; 2602 2603 /* 2604 * Create a nexus node for all IOAPICs under the root node. 2605 */ 2606 if (ioapicsnode == NULL) { 2607 if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME, 2608 (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) { 2609 return; 2610 } 2611 (void) ndi_devi_online(ioapicsnode, 0); 2612 } 2613 2614 /* 2615 * Create a child node for this IOAPIC 2616 */ 2617 ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME, 2618 DEVI_SID_NODEID, numioapics++); 2619 if (ioapic_node == NULL) { 2620 return; 2621 } 2622 2623 /* Vendor and Device ID */ 2624 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 2625 IOAPICS_PROP_VENID, vendorid); 2626 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 2627 IOAPICS_PROP_DEVID, deviceid); 2628 2629 /* device_type */ 2630 (void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node, 2631 "device_type", IOAPICS_DEV_TYPE); 2632 2633 /* reg */ 2634 (void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node, 2635 "reg", physaddr); 2636 } 2637 2638 /* 2639 * NOTE: For PCIe slots, the name is generated from the slot number 2640 * information obtained from Slot Capabilities register. 2641 * For non-PCIe slots, it is generated based on the slot number 2642 * information in the PCI IRQ table. 2643 */ 2644 static void 2645 pciex_slot_names_prop(dev_info_t *dip, ushort_t slot_num) 2646 { 2647 char slotprop[256]; 2648 int len; 2649 2650 bzero(slotprop, sizeof (slotprop)); 2651 2652 /* set mask to 1 as there is only one slot (i.e dev 0) */ 2653 *(uint32_t *)slotprop = 1; 2654 len = 4; 2655 (void) snprintf(slotprop + len, sizeof (slotprop) - len, "pcie%d", 2656 slot_num); 2657 len += strlen(slotprop + len) + 1; 2658 len += len % 4; 2659 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "slot-names", 2660 (int *)slotprop, len / sizeof (int)); 2661 } 2662