1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright 2019 Joyent, Inc. 24 * Copyright 2019 Western Digital Corporation 25 * Copyright 2020 OmniOS Community Edition (OmniOSce) Association. 26 * Copyright 2022 Oxide Computer Company 27 */ 28 29 /* 30 * PCI bus enumeration and device programming are done in several passes. The 31 * following is a high level overview of this process. 32 * 33 * pci_enumerate(reprogram=0) 34 * The main entry point to PCI bus enumeration is 35 * pci_enumerate(). This function is invoked 36 * twice, once to set up the PCI portion of the 37 * device tree, and then a second time to 38 * reprogram any devices which were not set up by 39 * the system firmware. On this first call, the 40 * reprogram parameter is set to 0. 41 * add_pci_fixes() 42 * enumerate_bus_devs(CONFIG_FIX) 43 * <foreach bus> 44 * process_devfunc(CONFIG_FIX) 45 * Some devices need a specific action taking in 46 * order for subsequent enumeration to be 47 * successful. add_pci_fixes() retrieves the 48 * vendor and device IDs for each item on the bus 49 * and applies fixes as required. It also creates 50 * a list which is used by undo_pci_fixes() to 51 * reverse the process later. 52 * pci_setup_tree() 53 * enumerate_bus_devs(CONFIG_INFO) 54 * <foreach bus> 55 * process_devfunc(CONFIG_INFO) 56 * <set up most device properties> 57 * The next stage is to enumerate the bus and set 58 * up the bulk of the properties for each device. 59 * This is where the generic properties such as 60 * 'device-id' are created. 61 * <if PPB device> 62 * add_ppb_props() 63 * For a PCI-to-PCI bridge (ppb) device, any 64 * memory ranges for IO, memory or pre-fetchable 65 * memory that have been programmed by the system 66 * firmware (BIOS/EFI) are retrieved and stored in 67 * bus-specific lists (pci_bus_res[bus].io_avail, 68 * mem_avail and pmem_avail). The contents of 69 * these lists are used to set the initial 'ranges' 70 * property on the ppb device. Later, as children 71 * are found for this bridge, resources will be 72 * removed from these avail lists as necessary. 73 * This is an initial pass so the ppb devices can 74 * still be reprogrammed later in fix_ppb_res(). 75 * <else> 76 * <add to list of non-PPB devices for the bus> 77 * Any non-PPB device on the bus is recorded in a 78 * bus-specific list, to be set up (and possibly 79 * reprogrammed) later. 80 * add_reg_props(CONFIG_INFO) 81 * The final step in this phase is to add the 82 * initial 'reg' and 'assigned-addresses' 83 * properties to all devices. At the same time, 84 * any IO or memory ranges which have been 85 * assigned to the bus are moved from the avail 86 * list to the corresponding used one. If no 87 * resources have been assigned to a device at 88 * this stage, then it is flagged for subsequent 89 * reprogramming. 90 * undo_pci_fixes() 91 * Any fixes which were applied in add_pci_fixes() 92 * are now undone before returning, using the 93 * undo list which was created earier. 94 * 95 * pci_enumerate(reprogram=1) 96 * The second bus enumeration pass is to take care 97 * of any devices that were not set up by the 98 * system firmware. These devices were flagged 99 * during the first pass. This pass is bracketed 100 * by the same pci fix application and removal as 101 * the first. 102 * add_pci_fixes() 103 * As for first pass. 104 * pci_reprogram() 105 * pci_prd_root_complex_iter() 106 * The platform is asked to tell us of all root 107 * complexes that it knows about (e.g. using the 108 * _BBN method via ACPI). This will include buses 109 * that we've already discovered and those that we 110 * potentially haven't. Anything that has not been 111 * previously discovered (or inferred to exist) is 112 * then added to the system. 113 * <foreach ROOT bus> 114 * populate_bus_res() 115 * Find resources associated with this root bus 116 * based on what the platform provideds through the 117 * pci platform interfaces defined in 118 * sys/plat/pci_prd.h. On i86pc this is driven by 119 * ACPI and BIOS tables. 120 * <foreach bus> 121 * fix_ppb_res() 122 * Reprogram pci(e) bridges which have not already 123 * had resources assigned, or which are under a 124 * bus that has been flagged for reprogramming. 125 * If the parent bus has not been flagged, then IO 126 * space is reprogrammed only if there are no 127 * assigned IO resources. Memory space is 128 * reprogrammed only if there is both no assigned 129 * ordinary memory AND no assigned pre-fetchable 130 * memory. However, if memory reprogramming is 131 * necessary then both ordinary and prefetch are 132 * done together so that both memory ranges end up 133 * in the avail lists for add_reg_props() to find 134 * later. 135 * enumerate_bus_devs(CONFIG_NEW) 136 * <foreach non-PPB device on the bus> 137 * add_reg_props(CONFIG_NEW) 138 * Using the list of non-PPB devices on the bus 139 * which was assembled during the first pass, add 140 * or update the 'reg' and 'assigned-address' 141 * properties for these devices. For devices which 142 * have been flagged for reprogramming or have no 143 * assigned resources, this is where resources are 144 * finally assigned and programmed into the 145 * device. This can result in these properties 146 * changing from their previous values. 147 * <foreach bus> 148 * add_bus_available_prop() 149 * Finally, the 'available' properties is set on 150 * each device, representing that device's final 151 * unallocated (available) IO and memory ranges. 152 * undo_pci_fixes() 153 * As for first pass. 154 */ 155 156 #include <sys/types.h> 157 #include <sys/stat.h> 158 #include <sys/sysmacros.h> 159 #include <sys/sunndi.h> 160 #include <sys/pci.h> 161 #include <sys/pci_impl.h> 162 #include <sys/pcie_impl.h> 163 #include <sys/memlist.h> 164 #include <sys/bootconf.h> 165 #include <sys/pci_cfgacc.h> 166 #include <sys/pci_cfgspace.h> 167 #include <sys/pci_cfgspace_impl.h> 168 #include <sys/psw.h> 169 #include "../../../../common/pci/pci_strings.h" 170 #include <sys/apic.h> 171 #include <io/pciex/pcie_nvidia.h> 172 #include <sys/hotplug/pci/pciehpc_acpi.h> 173 #include <sys/acpi/acpi.h> 174 #include <sys/acpica.h> 175 #include <sys/iommulib.h> 176 #include <sys/devcache.h> 177 #include <sys/pci_cfgacc_x86.h> 178 #include <sys/plat/pci_prd.h> 179 180 #define pci_getb (*pci_getb_func) 181 #define pci_getw (*pci_getw_func) 182 #define pci_getl (*pci_getl_func) 183 #define pci_putb (*pci_putb_func) 184 #define pci_putw (*pci_putw_func) 185 #define pci_putl (*pci_putl_func) 186 #define dcmn_err if (pci_boot_debug != 0) cmn_err 187 #define bus_debug(bus) (pci_boot_debug != 0 && pci_debug_bus_start != -1 && \ 188 pci_debug_bus_end != -1 && (bus) >= pci_debug_bus_start && \ 189 (bus) <= pci_debug_bus_end) 190 #define dump_memlists(tag, bus) \ 191 if (bus_debug((bus))) dump_memlists_impl((tag), (bus)) 192 193 #define CONFIG_INFO 0 194 #define CONFIG_UPDATE 1 195 #define CONFIG_NEW 2 196 #define CONFIG_FIX 3 197 #define COMPAT_BUFSIZE 512 198 199 #define PPB_IO_ALIGNMENT 0x1000 /* 4K aligned */ 200 #define PPB_MEM_ALIGNMENT 0x100000 /* 1M aligned */ 201 /* round down to nearest power of two */ 202 #define P2LE(align) \ 203 { \ 204 int i = 0; \ 205 while (align >>= 1) \ 206 i ++; \ 207 align = 1 << i; \ 208 } \ 209 210 /* for is_vga and list_is_vga_only */ 211 212 enum io_mem { 213 IO, 214 MEM 215 }; 216 217 /* for get_parbus_res */ 218 219 enum parbus_mem { 220 PB_IO, 221 PB_MEM, 222 PB_PMEM 223 }; 224 225 226 /* See AMD-8111 Datasheet Rev 3.03, Page 149: */ 227 #define LPC_IO_CONTROL_REG_1 0x40 228 #define AMD8111_ENABLENMI (uint8_t)0x80 229 #define DEVID_AMD8111_LPC 0x7468 230 231 struct pci_fixundo { 232 uint8_t bus; 233 uint8_t dev; 234 uint8_t fn; 235 void (*undofn)(uint8_t, uint8_t, uint8_t); 236 struct pci_fixundo *next; 237 }; 238 239 struct pci_devfunc { 240 struct pci_devfunc *next; 241 dev_info_t *dip; 242 uchar_t dev; 243 uchar_t func; 244 boolean_t reprogram; /* this device needs to be reprogrammed */ 245 }; 246 247 extern int apic_nvidia_io_max; 248 extern int pseudo_isa; 249 static uchar_t max_dev_pci = 32; /* PCI standard */ 250 int pci_boot_maxbus; 251 int pci_boot_debug = 0; 252 int pci_debug_bus_start = -1; 253 int pci_debug_bus_end = -1; 254 static struct pci_fixundo *undolist = NULL; 255 static int num_root_bus = 0; /* count of root buses */ 256 extern void pci_cfgacc_add_workaround(uint16_t, uchar_t, uchar_t); 257 extern dev_info_t *pcie_get_rc_dip(dev_info_t *); 258 259 /* 260 * Module prototypes 261 */ 262 static void enumerate_bus_devs(uchar_t bus, int config_op); 263 static void create_root_bus_dip(uchar_t bus); 264 static void process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t, 265 ushort_t, int); 266 static void add_compatible(dev_info_t *, ushort_t, ushort_t, 267 ushort_t, ushort_t, uchar_t, uint_t, int); 268 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 269 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, 270 ushort_t); 271 static void add_model_prop(dev_info_t *, uint_t); 272 static void add_bus_range_prop(int); 273 static void add_ranges_prop(int, int); 274 static void add_bus_available_prop(int); 275 static int get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id); 276 static void fix_ppb_res(uchar_t, boolean_t); 277 static void alloc_res_array(void); 278 static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 279 ushort_t deviceid); 280 static void pciex_slot_names_prop(dev_info_t *, ushort_t); 281 static void populate_bus_res(uchar_t bus); 282 static void memlist_remove_list(struct memlist **list, 283 struct memlist *remove_list); 284 static void ck804_fix_aer_ptr(dev_info_t *, pcie_req_id_t); 285 286 static int pci_unitaddr_cache_valid(void); 287 static int pci_bus_unitaddr(int); 288 static void pci_unitaddr_cache_create(void); 289 290 static int pci_cache_unpack_nvlist(nvf_handle_t, nvlist_t *, char *); 291 static int pci_cache_pack_nvlist(nvf_handle_t, nvlist_t **); 292 static void pci_cache_free_list(nvf_handle_t); 293 294 /* set non-zero to force PCI peer-bus renumbering */ 295 int pci_bus_always_renumber = 0; 296 297 /* 298 * used to register ISA resource usage which must not be made 299 * "available" from other PCI node' resource maps 300 */ 301 static struct { 302 struct memlist *io_used; 303 struct memlist *mem_used; 304 } isa_res; 305 306 /* 307 * PCI unit-address cache management 308 */ 309 static nvf_ops_t pci_unitaddr_cache_ops = { 310 "/etc/devices/pci_unitaddr_persistent", /* path to cache */ 311 pci_cache_unpack_nvlist, /* read in nvlist form */ 312 pci_cache_pack_nvlist, /* convert to nvlist form */ 313 pci_cache_free_list, /* free data list */ 314 NULL /* write complete callback */ 315 }; 316 317 typedef struct { 318 list_node_t pua_nodes; 319 int pua_index; 320 int pua_addr; 321 } pua_node_t; 322 323 nvf_handle_t puafd_handle; 324 int pua_cache_valid = 0; 325 326 dev_info_t * 327 pci_boot_bus_to_dip(uint32_t busno) 328 { 329 ASSERT3U(busno, <=, pci_boot_maxbus); 330 return (pci_bus_res[busno].dip); 331 } 332 333 static void 334 dump_memlists_impl(const char *tag, int bus) 335 { 336 printf("Memlist dump at %s - bus %x\n", tag, bus); 337 if (pci_bus_res[bus].io_used != NULL) { 338 printf(" io_used "); 339 memlist_dump(pci_bus_res[bus].io_used); 340 } 341 if (pci_bus_res[bus].io_avail != NULL) { 342 printf(" io_avail "); 343 memlist_dump(pci_bus_res[bus].io_avail); 344 } 345 if (pci_bus_res[bus].mem_used != NULL) { 346 printf(" mem_used "); 347 memlist_dump(pci_bus_res[bus].mem_used); 348 } 349 if (pci_bus_res[bus].mem_avail != NULL) { 350 printf(" mem_avail "); 351 memlist_dump(pci_bus_res[bus].mem_avail); 352 } 353 if (pci_bus_res[bus].pmem_used != NULL) { 354 printf(" pmem_used "); 355 memlist_dump(pci_bus_res[bus].pmem_used); 356 } 357 if (pci_bus_res[bus].pmem_avail != NULL) { 358 printf(" pmem_avail "); 359 memlist_dump(pci_bus_res[bus].pmem_avail); 360 } 361 } 362 363 static boolean_t 364 pci_rc_scan_cb(uint32_t busno, void *arg) 365 { 366 if (busno > pci_boot_maxbus) { 367 dcmn_err(CE_NOTE, "platform root complex scan returned bus " 368 "with invalid bus id: 0x%x", busno); 369 return (B_TRUE); 370 } 371 372 if (pci_bus_res[busno].par_bus == (uchar_t)-1 && 373 pci_bus_res[busno].dip == NULL) { 374 create_root_bus_dip((uchar_t)busno); 375 } 376 377 return (B_TRUE); 378 } 379 380 static void 381 pci_unitaddr_cache_init(void) 382 { 383 384 puafd_handle = nvf_register_file(&pci_unitaddr_cache_ops); 385 ASSERT(puafd_handle); 386 387 list_create(nvf_list(puafd_handle), sizeof (pua_node_t), 388 offsetof(pua_node_t, pua_nodes)); 389 390 rw_enter(nvf_lock(puafd_handle), RW_WRITER); 391 (void) nvf_read_file(puafd_handle); 392 rw_exit(nvf_lock(puafd_handle)); 393 } 394 395 /* 396 * Format of /etc/devices/pci_unitaddr_persistent: 397 * 398 * The persistent record of unit-address assignments contains 399 * a list of name/value pairs, where name is a string representation 400 * of the "index value" of the PCI root-bus and the value is 401 * the assigned unit-address. 402 * 403 * The "index value" is simply the zero-based index of the PCI 404 * root-buses ordered by physical bus number; first PCI bus is 0, 405 * second is 1, and so on. 406 */ 407 408 /*ARGSUSED*/ 409 static int 410 pci_cache_unpack_nvlist(nvf_handle_t hdl, nvlist_t *nvl, char *name) 411 { 412 long index; 413 int32_t value; 414 nvpair_t *np; 415 pua_node_t *node; 416 417 np = NULL; 418 while ((np = nvlist_next_nvpair(nvl, np)) != NULL) { 419 /* name of nvpair is index value */ 420 if (ddi_strtol(nvpair_name(np), NULL, 10, &index) != 0) 421 continue; 422 423 if (nvpair_value_int32(np, &value) != 0) 424 continue; 425 426 node = kmem_zalloc(sizeof (pua_node_t), KM_SLEEP); 427 node->pua_index = index; 428 node->pua_addr = value; 429 list_insert_tail(nvf_list(hdl), node); 430 } 431 432 pua_cache_valid = 1; 433 return (DDI_SUCCESS); 434 } 435 436 static int 437 pci_cache_pack_nvlist(nvf_handle_t hdl, nvlist_t **ret_nvl) 438 { 439 int rval; 440 nvlist_t *nvl, *sub_nvl; 441 list_t *listp; 442 pua_node_t *pua; 443 char buf[13]; 444 445 ASSERT(RW_WRITE_HELD(nvf_lock(hdl))); 446 447 rval = nvlist_alloc(&nvl, NV_UNIQUE_NAME, KM_SLEEP); 448 if (rval != DDI_SUCCESS) { 449 nvf_error("%s: nvlist alloc error %d\n", 450 nvf_cache_name(hdl), rval); 451 return (DDI_FAILURE); 452 } 453 454 sub_nvl = NULL; 455 rval = nvlist_alloc(&sub_nvl, NV_UNIQUE_NAME, KM_SLEEP); 456 if (rval != DDI_SUCCESS) 457 goto error; 458 459 listp = nvf_list(hdl); 460 for (pua = list_head(listp); pua != NULL; 461 pua = list_next(listp, pua)) { 462 (void) snprintf(buf, sizeof (buf), "%d", pua->pua_index); 463 rval = nvlist_add_int32(sub_nvl, buf, pua->pua_addr); 464 if (rval != DDI_SUCCESS) 465 goto error; 466 } 467 468 rval = nvlist_add_nvlist(nvl, "table", sub_nvl); 469 if (rval != DDI_SUCCESS) 470 goto error; 471 nvlist_free(sub_nvl); 472 473 *ret_nvl = nvl; 474 return (DDI_SUCCESS); 475 476 error: 477 nvlist_free(sub_nvl); 478 ASSERT(nvl); 479 nvlist_free(nvl); 480 *ret_nvl = NULL; 481 return (DDI_FAILURE); 482 } 483 484 static void 485 pci_cache_free_list(nvf_handle_t hdl) 486 { 487 list_t *listp; 488 pua_node_t *pua; 489 490 ASSERT(RW_WRITE_HELD(nvf_lock(hdl))); 491 492 listp = nvf_list(hdl); 493 for (pua = list_head(listp); pua != NULL; 494 pua = list_next(listp, pua)) { 495 list_remove(listp, pua); 496 kmem_free(pua, sizeof (pua_node_t)); 497 } 498 } 499 500 501 static int 502 pci_unitaddr_cache_valid(void) 503 { 504 505 /* read only, no need for rw lock */ 506 return (pua_cache_valid); 507 } 508 509 510 static int 511 pci_bus_unitaddr(int index) 512 { 513 pua_node_t *pua; 514 list_t *listp; 515 int addr; 516 517 rw_enter(nvf_lock(puafd_handle), RW_READER); 518 519 addr = -1; /* default return if no match */ 520 listp = nvf_list(puafd_handle); 521 for (pua = list_head(listp); pua != NULL; 522 pua = list_next(listp, pua)) { 523 if (pua->pua_index == index) { 524 addr = pua->pua_addr; 525 break; 526 } 527 } 528 529 rw_exit(nvf_lock(puafd_handle)); 530 return (addr); 531 } 532 533 static void 534 pci_unitaddr_cache_create(void) 535 { 536 int i, index; 537 pua_node_t *node; 538 list_t *listp; 539 540 rw_enter(nvf_lock(puafd_handle), RW_WRITER); 541 542 index = 0; 543 listp = nvf_list(puafd_handle); 544 for (i = 0; i <= pci_boot_maxbus; i++) { 545 /* skip non-root (peer) PCI busses */ 546 if ((pci_bus_res[i].par_bus != (uchar_t)-1) || 547 (pci_bus_res[i].dip == NULL)) 548 continue; 549 node = kmem_zalloc(sizeof (pua_node_t), KM_SLEEP); 550 node->pua_index = index++; 551 node->pua_addr = pci_bus_res[i].root_addr; 552 list_insert_tail(listp, node); 553 } 554 555 (void) nvf_mark_dirty(puafd_handle); 556 rw_exit(nvf_lock(puafd_handle)); 557 nvf_wake_daemon(); 558 } 559 560 561 /* 562 * Enumerate all PCI devices 563 */ 564 void 565 pci_setup_tree(void) 566 { 567 uint_t i, root_bus_addr = 0; 568 569 alloc_res_array(); 570 for (i = 0; i <= pci_boot_maxbus; i++) { 571 pci_bus_res[i].par_bus = (uchar_t)-1; 572 pci_bus_res[i].root_addr = (uchar_t)-1; 573 pci_bus_res[i].sub_bus = i; 574 } 575 576 pci_bus_res[0].root_addr = root_bus_addr++; 577 create_root_bus_dip(0); 578 enumerate_bus_devs(0, CONFIG_INFO); 579 580 /* 581 * Now enumerate peer busses 582 * 583 * We loop till pci_boot_maxbus. On most systems, there is 584 * one more bus at the high end, which implements the ISA 585 * compatibility bus. We don't care about that. 586 * 587 * Note: In the old (bootconf) enumeration, the peer bus 588 * address did not use the bus number, and there were 589 * too many peer busses created. The root_bus_addr is 590 * used to maintain the old peer bus address assignment. 591 * However, we stop enumerating phantom peers with no 592 * device below. 593 */ 594 for (i = 1; i <= pci_boot_maxbus; i++) { 595 if (pci_bus_res[i].dip == NULL) { 596 pci_bus_res[i].root_addr = root_bus_addr++; 597 } 598 enumerate_bus_devs(i, CONFIG_INFO); 599 } 600 } 601 602 void 603 pci_register_isa_resources(int type, uint32_t base, uint32_t size) 604 { 605 (void) memlist_insert( 606 (type == 1) ? &isa_res.io_used : &isa_res.mem_used, 607 base, size); 608 } 609 610 /* 611 * Remove the resources which are already used by devices under a subtractive 612 * bridge from the bus's resources lists, because they're not available, and 613 * shouldn't be allocated to other buses. This is necessary because tracking 614 * resources for subtractive bridges is not complete. (Subtractive bridges only 615 * track some of their claimed resources, not "the rest of the address space" as 616 * they should, so that allocation to peer non-subtractive PPBs is easier. We 617 * need a fully-capable global resource allocator). 618 */ 619 static void 620 remove_subtractive_res() 621 { 622 int i, j; 623 struct memlist *list; 624 625 for (i = 0; i <= pci_boot_maxbus; i++) { 626 if (pci_bus_res[i].subtractive) { 627 /* remove used io ports */ 628 list = pci_bus_res[i].io_used; 629 while (list) { 630 for (j = 0; j <= pci_boot_maxbus; j++) 631 (void) memlist_remove( 632 &pci_bus_res[j].io_avail, 633 list->ml_address, list->ml_size); 634 list = list->ml_next; 635 } 636 /* remove used mem resource */ 637 list = pci_bus_res[i].mem_used; 638 while (list) { 639 for (j = 0; j <= pci_boot_maxbus; j++) { 640 (void) memlist_remove( 641 &pci_bus_res[j].mem_avail, 642 list->ml_address, list->ml_size); 643 (void) memlist_remove( 644 &pci_bus_res[j].pmem_avail, 645 list->ml_address, list->ml_size); 646 } 647 list = list->ml_next; 648 } 649 /* remove used prefetchable mem resource */ 650 list = pci_bus_res[i].pmem_used; 651 while (list) { 652 for (j = 0; j <= pci_boot_maxbus; j++) { 653 (void) memlist_remove( 654 &pci_bus_res[j].pmem_avail, 655 list->ml_address, list->ml_size); 656 (void) memlist_remove( 657 &pci_bus_res[j].mem_avail, 658 list->ml_address, list->ml_size); 659 } 660 list = list->ml_next; 661 } 662 } 663 } 664 } 665 666 /* 667 * Set up (or complete the setup of) the bus_avail resource list 668 */ 669 static void 670 setup_bus_res(int bus) 671 { 672 uchar_t par_bus; 673 674 if (pci_bus_res[bus].dip == NULL) /* unused bus */ 675 return; 676 677 /* 678 * Set up bus_avail if not already filled in by populate_bus_res() 679 */ 680 if (pci_bus_res[bus].bus_avail == NULL) { 681 ASSERT(pci_bus_res[bus].sub_bus >= bus); 682 memlist_insert(&pci_bus_res[bus].bus_avail, bus, 683 pci_bus_res[bus].sub_bus - bus + 1); 684 } 685 686 ASSERT(pci_bus_res[bus].bus_avail != NULL); 687 688 /* 689 * Remove resources from parent bus node if this is not a 690 * root bus. 691 */ 692 par_bus = pci_bus_res[bus].par_bus; 693 if (par_bus != (uchar_t)-1) { 694 ASSERT(pci_bus_res[par_bus].bus_avail != NULL); 695 memlist_remove_list(&pci_bus_res[par_bus].bus_avail, 696 pci_bus_res[bus].bus_avail); 697 } 698 699 /* remove self from bus_avail */; 700 (void) memlist_remove(&pci_bus_res[bus].bus_avail, bus, 1); 701 } 702 703 /* 704 * Allocate a resource from the parent bus 705 */ 706 static uint64_t 707 get_parbus_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align, 708 enum parbus_mem mem) 709 { 710 uint64_t addr = 0; 711 uchar_t res_bus; 712 713 /* 714 * Skip root(peer) buses in multiple-root-bus systems when 715 * ACPI resource discovery was not successfully done; the 716 * initial resources set on each root bus might not be correctly 717 * accounted for in this case. 718 */ 719 if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 720 (num_root_bus > 1) && !pci_prd_multi_root_ok()) { 721 return (0); 722 } 723 724 /* 725 * Set res_bus to the bus from which resources should be allocated. 726 * A device under a subtractive PPB can allocate resources from its 727 * parent bus if there are no resources available on its own bus, so 728 * iterate up the chain until resources are found or the root is 729 * reached. 730 */ 731 res_bus = parbus; 732 while (pci_bus_res[res_bus].subtractive) { 733 if (mem == PB_IO && pci_bus_res[res_bus].io_avail != NULL) 734 break; 735 if (mem == PB_MEM && pci_bus_res[res_bus].mem_avail != NULL) 736 break; 737 if (mem == PB_PMEM && pci_bus_res[res_bus].pmem_avail != NULL) 738 break; 739 res_bus = pci_bus_res[res_bus].par_bus; 740 /* Has the root bus been reached? */ 741 if (res_bus == (uchar_t)-1) 742 break; 743 } 744 745 switch (mem) { 746 case PB_IO: 747 if (pci_bus_res[res_bus].io_avail == NULL) 748 break; 749 addr = memlist_find(&pci_bus_res[res_bus].io_avail, 750 size, align); 751 if (addr > 0) { 752 memlist_insert(&pci_bus_res[res_bus].io_used, 753 addr, size); 754 755 /* free the old resource */ 756 memlist_free_all(&pci_bus_res[bus].io_avail); 757 memlist_free_all(&pci_bus_res[bus].io_used); 758 759 /* add the new resource */ 760 memlist_insert(&pci_bus_res[bus].io_avail, addr, size); 761 } 762 break; 763 case PB_MEM: 764 if (pci_bus_res[res_bus].mem_avail == NULL) 765 break; 766 addr = memlist_find(&pci_bus_res[res_bus].mem_avail, 767 size, align); 768 if (addr > 0) { 769 memlist_insert(&pci_bus_res[res_bus].mem_used, 770 addr, size); 771 (void) memlist_remove(&pci_bus_res[res_bus].pmem_avail, 772 addr, size); 773 774 /* free the old resource */ 775 memlist_free_all(&pci_bus_res[bus].mem_avail); 776 memlist_free_all(&pci_bus_res[bus].mem_used); 777 778 /* add the new resource */ 779 memlist_insert(&pci_bus_res[bus].mem_avail, addr, size); 780 } 781 break; 782 case PB_PMEM: 783 if (pci_bus_res[res_bus].pmem_avail == NULL) 784 break; 785 addr = memlist_find(&pci_bus_res[res_bus].pmem_avail, 786 size, align); 787 if (addr > 0) { 788 memlist_insert(&pci_bus_res[res_bus].pmem_used, 789 addr, size); 790 (void) memlist_remove(&pci_bus_res[res_bus].mem_avail, 791 addr, size); 792 793 /* free the old resource */ 794 memlist_free_all(&pci_bus_res[bus].pmem_avail); 795 memlist_free_all(&pci_bus_res[bus].pmem_used); 796 797 /* add the new resource */ 798 memlist_insert(&pci_bus_res[bus].pmem_avail, 799 addr, size); 800 } 801 break; 802 } 803 804 return (addr); 805 } 806 807 /* 808 * given a cap_id, return its cap_id location in config space 809 */ 810 static int 811 get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id) 812 { 813 uint8_t curcap, cap_id_loc; 814 uint16_t status; 815 int location = -1; 816 817 /* 818 * Need to check the Status register for ECP support first. 819 * Also please note that for type 1 devices, the 820 * offset could change. Should support type 1 next. 821 */ 822 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 823 if (!(status & PCI_STAT_CAP)) { 824 return (-1); 825 } 826 cap_id_loc = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 827 828 /* Walk the list of capabilities */ 829 while (cap_id_loc && cap_id_loc != (uint8_t)-1) { 830 curcap = pci_getb(bus, dev, func, cap_id_loc); 831 832 if (curcap == cap_id) { 833 location = cap_id_loc; 834 break; 835 } 836 cap_id_loc = pci_getb(bus, dev, func, cap_id_loc + 1); 837 } 838 return (location); 839 } 840 841 /* 842 * Does this resource element live in the legacy VGA range? 843 */ 844 845 static boolean_t 846 is_vga(struct memlist *elem, enum io_mem io) 847 { 848 if (io == IO) { 849 if ((elem->ml_address == 0x3b0 && elem->ml_size == 0xc) || 850 (elem->ml_address == 0x3c0 && elem->ml_size == 0x20)) 851 return (B_TRUE); 852 } else { 853 if (elem->ml_address == 0xa0000 && elem->ml_size == 0x20000) 854 return (B_TRUE); 855 } 856 return (B_FALSE); 857 } 858 859 /* 860 * Does this entire resource list consist only of legacy VGA resources? 861 */ 862 863 static boolean_t 864 list_is_vga_only(struct memlist *l, enum io_mem io) 865 { 866 if (l == NULL) { 867 return (B_FALSE); 868 } 869 870 do { 871 if (!is_vga(l, io)) 872 return (B_FALSE); 873 } while ((l = l->ml_next) != NULL); 874 return (B_TRUE); 875 } 876 877 /* 878 * Find the start and end addresses that cover the range for all list entries, 879 * excluding legacy VGA addresses. Relies on the list being sorted. 880 */ 881 static void 882 pci_memlist_range(struct memlist *list, enum io_mem iomem, uint64_t *basep, 883 uint64_t *limitp) 884 { 885 *limitp = *basep = 0; 886 887 for (; list != NULL; list = list->ml_next) { 888 if (is_vga(list, iomem)) 889 continue; 890 891 if (*basep == 0) 892 *basep = list->ml_address; 893 894 if (list->ml_address + list->ml_size >= *limitp) 895 *limitp = list->ml_address + list->ml_size - 1; 896 } 897 } 898 899 /* 900 * Assign valid resources to unconfigured pci(e) bridges. We are trying 901 * to reprogram the bridge when its 902 * i) SECBUS == SUBBUS || 903 * ii) IOBASE > IOLIM || 904 * iii) MEMBASE > MEMLIM && PMEMBASE > PMEMLIM 905 * This must be done after one full pass through the PCI tree to collect 906 * all BIOS-configured resources, so that we know what resources are 907 * free and available to assign to the unconfigured PPBs. 908 */ 909 static void 910 fix_ppb_res(uchar_t secbus, boolean_t prog_sub) 911 { 912 uchar_t bus, dev, func; 913 uchar_t parbus, subbus; 914 uint_t io_base, io_limit, mem_base; 915 uint_t io_size, io_align; 916 uint64_t mem_size, mem_align, mem_limit; 917 uint64_t pmem_size, pmem_base, pmem_limit; 918 uint64_t addr = 0; 919 int *regp = NULL; 920 uint_t val, reglen; 921 int rv, cap_ptr, physhi; 922 dev_info_t *dip; 923 uint16_t cmd_reg; 924 struct memlist *scratch_list; 925 boolean_t reprogram_mem; 926 927 /* skip root (peer) PCI busses */ 928 if (pci_bus_res[secbus].par_bus == (uchar_t)-1) 929 return; 930 931 /* skip subtractive PPB when prog_sub is not TRUE */ 932 if (pci_bus_res[secbus].subtractive && !prog_sub) 933 return; 934 935 /* some entries may be empty due to discontiguous bus numbering */ 936 dip = pci_bus_res[secbus].dip; 937 if (dip == NULL) 938 return; 939 940 rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 941 "reg", ®p, ®len); 942 if (rv != DDI_PROP_SUCCESS || reglen == 0) 943 return; 944 physhi = regp[0]; 945 ddi_prop_free(regp); 946 947 func = (uchar_t)PCI_REG_FUNC_G(physhi); 948 dev = (uchar_t)PCI_REG_DEV_G(physhi); 949 bus = (uchar_t)PCI_REG_BUS_G(physhi); 950 951 dump_memlists("fix_ppb_res start bus", bus); 952 dump_memlists("fix_ppb_res start secbus", secbus); 953 954 /* 955 * If pcie bridge, check to see if link is enabled 956 */ 957 cap_ptr = get_pci_cap(bus, dev, func, PCI_CAP_ID_PCI_E); 958 if (cap_ptr != -1) { 959 cmd_reg = pci_getw(bus, dev, func, 960 (uint16_t)cap_ptr + PCIE_LINKCTL); 961 if (cmd_reg & PCIE_LINKCTL_LINK_DISABLE) { 962 dcmn_err(CE_NOTE, 963 "!fix_ppb_res: ppb[%x/%x/%x] link is disabled.", 964 bus, dev, func); 965 return; 966 } 967 } 968 969 subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 970 parbus = pci_bus_res[secbus].par_bus; 971 ASSERT(parbus == bus); 972 cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 973 974 /* 975 * If we have a Cardbus bridge, but no bus space 976 */ 977 if (pci_bus_res[secbus].num_cbb != 0 && 978 pci_bus_res[secbus].bus_avail == NULL) { 979 uchar_t range; 980 981 /* normally there are 2 buses under a cardbus bridge */ 982 range = pci_bus_res[secbus].num_cbb * 2; 983 984 /* 985 * Try to find and allocate a bus-range starting at subbus+1 986 * from the parent of the PPB. 987 */ 988 for (; range != 0; range--) { 989 if (memlist_find_with_startaddr( 990 &pci_bus_res[parbus].bus_avail, 991 subbus + 1, range, 1) != 0) 992 break; /* find bus range resource at parent */ 993 } 994 if (range != 0) { 995 memlist_insert(&pci_bus_res[secbus].bus_avail, 996 subbus + 1, range); 997 subbus = subbus + range; 998 pci_bus_res[secbus].sub_bus = subbus; 999 pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus); 1000 add_bus_range_prop(secbus); 1001 1002 cmn_err(CE_NOTE, "!reprogram bus-range on ppb" 1003 "[%x/%x/%x]: %x ~ %x", bus, dev, func, 1004 secbus, subbus); 1005 } 1006 } 1007 1008 /* 1009 * Calculate required IO size and alignment 1010 * If bus io_size is zero, we are going to assign 512 bytes per bus, 1011 * otherwise, we'll choose the maximum value of such calculation and 1012 * bus io_size. The size needs to be 4K aligned. 1013 * 1014 * We calculate alignment as the largest power of two less than the 1015 * the sum of all children's IO size requirements, because this will 1016 * align to the size of the largest child request within that size 1017 * (which is always a power of two). 1018 */ 1019 io_size = (subbus - secbus + 1) * 0x200; 1020 if (io_size < pci_bus_res[secbus].io_size) 1021 io_size = pci_bus_res[secbus].io_size; 1022 io_size = P2ROUNDUP(io_size, PPB_IO_ALIGNMENT); 1023 io_align = io_size; 1024 P2LE(io_align); 1025 1026 /* 1027 * Calculate required MEM size and alignment 1028 * If bus mem_size is zero, we are going to assign 1M bytes per bus, 1029 * otherwise, we'll choose the maximum value of such calculation and 1030 * bus mem_size. The size needs to be 1M aligned. 1031 * 1032 * For the alignment, refer to the I/O comment above. 1033 */ 1034 mem_size = (subbus - secbus + 1) * PPB_MEM_ALIGNMENT; 1035 if (mem_size < pci_bus_res[secbus].mem_size) { 1036 mem_size = pci_bus_res[secbus].mem_size; 1037 mem_size = P2ROUNDUP(mem_size, PPB_MEM_ALIGNMENT); 1038 } 1039 mem_align = mem_size; 1040 P2LE(mem_align); 1041 1042 /* Subtractive bridge */ 1043 if (pci_bus_res[secbus].subtractive && prog_sub) { 1044 /* 1045 * We program an arbitrary amount of I/O and memory resource 1046 * for the subtractive bridge so that child dynamic-resource- 1047 * allocating devices (such as Cardbus bridges) have a chance 1048 * of success. Until we have full-tree resource rebalancing, 1049 * dynamic resource allocation (thru busra) only looks at the 1050 * parent bridge, so all PPBs must have some allocatable 1051 * resource. For non-subtractive bridges, the resources come 1052 * from the base/limit register "windows", but subtractive 1053 * bridges often don't program those (since they don't need to). 1054 * If we put all the remaining resources on the subtractive 1055 * bridge, then peer non-subtractive bridges can't allocate 1056 * more space (even though this is probably most correct). 1057 * If we put the resources only on the parent, then allocations 1058 * from children of subtractive bridges will fail without 1059 * special-case code for bypassing the subtractive bridge. 1060 * This solution is the middle-ground temporary solution until 1061 * we have fully-capable resource allocation. 1062 */ 1063 1064 /* 1065 * Add an arbitrary I/O resource to the subtractive PPB 1066 */ 1067 if (pci_bus_res[secbus].io_avail == NULL) { 1068 addr = get_parbus_res(parbus, secbus, io_size, 1069 io_align, PB_IO); 1070 if (addr) { 1071 add_ranges_prop(secbus, 1); 1072 pci_bus_res[secbus].io_reprogram = 1073 pci_bus_res[parbus].io_reprogram; 1074 1075 cmn_err(CE_NOTE, "!add io-range on subtractive" 1076 " ppb[%x/%x/%x]: " 1077 "0x%"PRIx64" ~ 0x%"PRIx64"", 1078 bus, dev, func, addr, addr + io_size - 1); 1079 } 1080 } 1081 /* 1082 * Add an arbitrary memory resource to the subtractive PPB 1083 */ 1084 if (pci_bus_res[secbus].mem_avail == NULL) { 1085 addr = get_parbus_res(parbus, secbus, mem_size, 1086 mem_align, PB_MEM); 1087 if (addr) { 1088 add_ranges_prop(secbus, 1); 1089 pci_bus_res[secbus].mem_reprogram = 1090 pci_bus_res[parbus].mem_reprogram; 1091 1092 cmn_err(CE_NOTE, "!add mem-range on " 1093 "subtractive ppb[%x/%x/%x]: " 1094 "0x%"PRIx64" ~ 0x%"PRIx64"", 1095 bus, dev, func, 1096 addr, addr + mem_size - 1); 1097 } 1098 } 1099 1100 goto cmd_enable; 1101 } 1102 1103 /* 1104 * Check to see if we need to reprogram I/O space, either because the 1105 * parent bus needed reprogramming and so do we, or because I/O space is 1106 * disabled in base/limit or command register. 1107 */ 1108 val = io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 1109 io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 1110 io_base = (io_base & PCI_BCNF_IO_MASK) << PCI_BCNF_IO_SHIFT; 1111 io_limit = ((io_limit & PCI_BCNF_IO_MASK) << PCI_BCNF_IO_SHIFT) | 0xfff; 1112 if ((val & PCI_BCNF_ADDR_MASK) == PCI_BCNF_IO_32BIT) { 1113 uint16_t io_base_hi, io_limit_hi; 1114 io_base_hi = pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI); 1115 io_limit_hi = pci_getw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI); 1116 1117 io_base |= (uint_t)io_base_hi << 16; 1118 io_limit |= (uint_t)io_limit_hi << 16; 1119 } 1120 1121 /* Form list of all resources passed (avail + used) */ 1122 scratch_list = memlist_dup(pci_bus_res[secbus].io_avail); 1123 memlist_merge(&pci_bus_res[secbus].io_used, &scratch_list); 1124 1125 if ((pci_bus_res[parbus].io_reprogram || 1126 (io_base > io_limit) || 1127 (!(cmd_reg & PCI_COMM_IO))) && 1128 !list_is_vga_only(scratch_list, IO)) { 1129 1130 if (pci_bus_res[secbus].io_used) { 1131 memlist_subsume(&pci_bus_res[secbus].io_used, 1132 &pci_bus_res[secbus].io_avail); 1133 } 1134 1135 if (pci_bus_res[secbus].io_avail && 1136 !pci_bus_res[parbus].io_reprogram && 1137 !pci_bus_res[parbus].subtractive) { 1138 /* re-choose old io ports info */ 1139 1140 uint64_t base, limit; 1141 1142 pci_memlist_range(pci_bus_res[secbus].io_avail, 1143 IO, &base, &limit); 1144 io_base = (uint_t)base; 1145 io_limit = (uint_t)limit; 1146 1147 /* 4K aligned */ 1148 io_base = P2ALIGN(base, PPB_IO_ALIGNMENT); 1149 io_limit = P2ROUNDUP(io_limit, PPB_IO_ALIGNMENT) - 1; 1150 io_size = io_limit - io_base + 1; 1151 ASSERT(io_base <= io_limit); 1152 memlist_free_all(&pci_bus_res[secbus].io_avail); 1153 memlist_insert(&pci_bus_res[secbus].io_avail, 1154 io_base, io_size); 1155 memlist_insert(&pci_bus_res[parbus].io_used, 1156 io_base, io_size); 1157 (void) memlist_remove(&pci_bus_res[parbus].io_avail, 1158 io_base, io_size); 1159 pci_bus_res[secbus].io_reprogram = B_TRUE; 1160 } else { 1161 /* get new io ports from parent bus */ 1162 addr = get_parbus_res(parbus, secbus, io_size, 1163 io_align, PB_IO); 1164 if (addr) { 1165 io_base = addr; 1166 io_limit = addr + io_size - 1; 1167 pci_bus_res[secbus].io_reprogram = B_TRUE; 1168 } 1169 } 1170 if (pci_bus_res[secbus].io_reprogram) { 1171 /* reprogram PPB regs */ 1172 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 1173 (uchar_t)((io_base>>8) & 0xf0)); 1174 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 1175 (uchar_t)((io_limit>>8) & 0xf0)); 1176 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 1177 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 1178 add_ranges_prop(secbus, 1); 1179 1180 cmn_err(CE_NOTE, "!reprogram io-range on" 1181 " ppb[%x/%x/%x]: 0x%x ~ 0x%x", 1182 bus, dev, func, io_base, io_limit); 1183 } 1184 } 1185 memlist_free_all(&scratch_list); 1186 1187 /* 1188 * Check memory space as we did I/O space. 1189 */ 1190 1191 mem_base = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 1192 mem_base = (mem_base & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT; 1193 mem_limit = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 1194 mem_limit = ((mem_limit & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT) 1195 | 0xfffff; 1196 1197 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 1198 pmem_limit = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT) | 1199 0xfffff; 1200 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 1201 pmem_base = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT); 1202 1203 if ((val & PCI_BCNF_ADDR_MASK) == PCI_BCNF_PF_MEM_64BIT) { 1204 uint32_t pf_addr_hi, pf_limit_hi; 1205 1206 pf_addr_hi = pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH); 1207 pf_limit_hi = pci_getl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH); 1208 pmem_base |= (uint64_t)pf_addr_hi << 32; 1209 pmem_limit |= (uint64_t)pf_limit_hi << 32; 1210 } 1211 1212 /* 1213 * Reprogram memory if any of: 1214 * 1215 * - The parent bus is flagged for reprogramming; 1216 * - Mem space is currently disabled in the command register; 1217 * - Both mem and pmem space are disabled via base/limit. 1218 * 1219 * Always reprogram both mem and pmem together since this leaves 1220 * resources in the 'avail' list for add_reg_props() to subsequently 1221 * find and assign. 1222 */ 1223 reprogram_mem = pci_bus_res[parbus].mem_reprogram || 1224 !(cmd_reg & PCI_COMM_MAE) || 1225 (mem_base > mem_limit && pmem_base > pmem_limit); 1226 1227 scratch_list = memlist_dup(pci_bus_res[secbus].mem_avail); 1228 memlist_merge(&pci_bus_res[secbus].mem_used, &scratch_list); 1229 1230 if (reprogram_mem && !list_is_vga_only(scratch_list, MEM)) { 1231 1232 if (pci_bus_res[secbus].mem_used) { 1233 memlist_subsume(&pci_bus_res[secbus].mem_used, 1234 &pci_bus_res[secbus].mem_avail); 1235 } 1236 1237 /* 1238 * At this point, if the parent bus has not been 1239 * reprogrammed and there is memory in this bus' available 1240 * pool, then it can just be re-used. Otherwise a new range 1241 * is requested from the parent bus - note that 1242 * get_parbus_res() also takes care of constructing new 1243 * avail and used lists for the bus. 1244 * 1245 * For a subtractive parent bus, always request a fresh 1246 * memory range. 1247 */ 1248 if (pci_bus_res[secbus].mem_avail && 1249 !pci_bus_res[parbus].mem_reprogram && 1250 !pci_bus_res[parbus].subtractive) { 1251 /* re-choose old mem resource */ 1252 1253 uint64_t base; 1254 1255 pci_memlist_range(pci_bus_res[secbus].mem_avail, 1256 MEM, &base, &mem_limit); 1257 mem_base = (uint_t)base; 1258 1259 mem_base = P2ALIGN(mem_base, PPB_MEM_ALIGNMENT); 1260 mem_limit = P2ROUNDUP(mem_limit, PPB_MEM_ALIGNMENT) - 1; 1261 mem_size = mem_limit + 1 - mem_base; 1262 ASSERT(mem_base <= mem_limit); 1263 memlist_free_all(&pci_bus_res[secbus].mem_avail); 1264 memlist_insert(&pci_bus_res[secbus].mem_avail, 1265 mem_base, mem_size); 1266 memlist_insert(&pci_bus_res[parbus].mem_used, 1267 mem_base, mem_size); 1268 (void) memlist_remove(&pci_bus_res[parbus].mem_avail, 1269 mem_base, mem_size); 1270 pci_bus_res[secbus].mem_reprogram = B_TRUE; 1271 } else { 1272 /* get new mem resource from parent bus */ 1273 addr = get_parbus_res(parbus, secbus, mem_size, 1274 mem_align, PB_MEM); 1275 if (addr) { 1276 mem_base = addr; 1277 mem_limit = addr + mem_size - 1; 1278 pci_bus_res[secbus].mem_reprogram = B_TRUE; 1279 } 1280 } 1281 } 1282 memlist_free_all(&scratch_list); 1283 1284 /* Prefetch memory */ 1285 1286 scratch_list = memlist_dup(pci_bus_res[secbus].pmem_avail); 1287 memlist_merge(&pci_bus_res[secbus].pmem_used, &scratch_list); 1288 1289 /* 1290 * Only reprogram prefetchable memory If the MEM access bit is 1291 * currently enabled. If it is not, then prefetchable memory will be 1292 * disabled anyway via base/limit below. 1293 */ 1294 if (reprogram_mem && !list_is_vga_only(scratch_list, MEM) && 1295 (cmd_reg & PCI_COMM_MAE)) { 1296 1297 if (pci_bus_res[secbus].pmem_used) { 1298 memlist_subsume(&pci_bus_res[secbus].pmem_used, 1299 &pci_bus_res[secbus].pmem_avail); 1300 } 1301 1302 /* Same logic as for non-prefetch memory, see above */ 1303 if (pci_bus_res[secbus].pmem_avail && 1304 !pci_bus_res[parbus].mem_reprogram && 1305 !pci_bus_res[parbus].subtractive) { 1306 /* re-choose old mem resource */ 1307 1308 pci_memlist_range(pci_bus_res[secbus].pmem_avail, 1309 MEM, &pmem_base, &pmem_limit); 1310 1311 pmem_base = P2ALIGN(pmem_base, PPB_MEM_ALIGNMENT); 1312 pmem_limit = P2ROUNDUP(pmem_limit, 1313 PPB_MEM_ALIGNMENT) - 1; 1314 pmem_size = pmem_limit + 1 - pmem_base; 1315 ASSERT(pmem_base <= pmem_limit); 1316 memlist_free_all(&pci_bus_res[secbus].pmem_avail); 1317 memlist_insert(&pci_bus_res[secbus].pmem_avail, 1318 pmem_base, pmem_size); 1319 memlist_insert(&pci_bus_res[parbus].pmem_used, 1320 pmem_base, pmem_size); 1321 (void) memlist_remove(&pci_bus_res[parbus].pmem_avail, 1322 pmem_base, pmem_size); 1323 pci_bus_res[secbus].mem_reprogram = B_TRUE; 1324 } else { 1325 /* get new mem resource from parent bus */ 1326 addr = get_parbus_res(parbus, secbus, mem_size, 1327 mem_align, PB_PMEM); 1328 if (addr) { 1329 pmem_base = addr; 1330 pmem_limit = addr + mem_size - 1; 1331 pci_bus_res[secbus].mem_reprogram = B_TRUE; 1332 } 1333 } 1334 } 1335 1336 memlist_free_all(&scratch_list); 1337 1338 if (pci_bus_res[secbus].mem_reprogram) { 1339 /* reprogram PPB MEM regs */ 1340 1341 pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE, 1342 (uint16_t)((mem_base >> PCI_BCNF_MEM_SHIFT) & 1343 PCI_BCNF_MEM_MASK)); 1344 pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT, 1345 (uint16_t)((mem_limit >> PCI_BCNF_MEM_SHIFT) & 1346 PCI_BCNF_MEM_MASK)); 1347 1348 cmn_err(CE_NOTE, "!reprogram mem-range on" 1349 " ppb[%x/%x/%x]: 0x%x ~ 0x%"PRIx64"", 1350 bus, dev, func, mem_base, mem_limit); 1351 1352 if (!(cmd_reg & PCI_COMM_MAE)) { 1353 /* 1354 * If the MEM access bit is initially disabled by BIOS, 1355 * we disable the PMEM window manually by setting PMEM 1356 * base > PMEM limit here, in case there are incorrect 1357 * values in them from BIOS, so that we won't get in 1358 * trouble once the MEM access bit is enabled at the 1359 * end of this function. 1360 */ 1361 pci_putw(bus, dev, func, PCI_BCNF_PF_BASE_LOW, 0xfff0); 1362 pci_putw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW, 0x0); 1363 pci_putl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH, 1364 0xffffffff); 1365 pci_putl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH, 0x0); 1366 1367 } else { 1368 1369 pci_putw(bus, dev, func, PCI_BCNF_PF_BASE_LOW, 1370 ((pmem_base & 0xffffffff) >> PCI_BCNF_MEM_SHIFT) & 1371 PCI_BCNF_MEM_MASK); 1372 pci_putl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH, 1373 pmem_base >> 32); 1374 1375 pci_putw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW, 1376 ((pmem_limit & 0xffffffff) >> PCI_BCNF_MEM_SHIFT) & 1377 PCI_BCNF_MEM_MASK); 1378 pci_putl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH, 1379 pmem_limit >> 32); 1380 1381 cmn_err(CE_NOTE, "!reprogram pmem-range on" 1382 " ppb[%x/%x/%x]: 0x%"PRIx64" ~ 0x%"PRIx64"", 1383 bus, dev, func, pmem_base, pmem_limit); 1384 } 1385 1386 add_ranges_prop(secbus, 1); 1387 } 1388 1389 cmd_enable: 1390 dump_memlists("fix_ppb_res end bus", bus); 1391 dump_memlists("fix_ppb_res end secbus", secbus); 1392 1393 if (pci_bus_res[secbus].io_avail) 1394 cmd_reg |= PCI_COMM_IO | PCI_COMM_ME; 1395 if (pci_bus_res[secbus].mem_avail) 1396 cmd_reg |= PCI_COMM_MAE | PCI_COMM_ME; 1397 pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 1398 } 1399 1400 void 1401 pci_reprogram(void) 1402 { 1403 int i, pci_reconfig = 1; 1404 char *onoff; 1405 int bus; 1406 1407 /* 1408 * Ask platform code for all of the root complexes it knows about in 1409 * case we have missed anything in the scan. This is to ensure that we 1410 * have them show up in the devinfo tree. This scan should find any 1411 * existing entries as well. After this, go through each bus and 1412 * ask the platform if it wants to change the name of the slot. 1413 */ 1414 pci_prd_root_complex_iter(pci_rc_scan_cb, NULL); 1415 for (bus = 0; bus <= pci_boot_maxbus; bus++) { 1416 pci_prd_slot_name(bus, pci_bus_res[bus].dip); 1417 } 1418 pci_unitaddr_cache_init(); 1419 1420 /* 1421 * Fix-up unit-address assignments if cache is available 1422 */ 1423 if (pci_unitaddr_cache_valid()) { 1424 int pci_regs[] = {0, 0, 0}; 1425 int new_addr; 1426 int index = 0; 1427 1428 for (bus = 0; bus <= pci_boot_maxbus; bus++) { 1429 /* skip non-root (peer) PCI busses */ 1430 if ((pci_bus_res[bus].par_bus != (uchar_t)-1) || 1431 (pci_bus_res[bus].dip == NULL)) 1432 continue; 1433 1434 new_addr = pci_bus_unitaddr(index); 1435 if (pci_bus_res[bus].root_addr != new_addr) { 1436 /* update reg property for node */ 1437 pci_regs[0] = pci_bus_res[bus].root_addr = 1438 new_addr; 1439 (void) ndi_prop_update_int_array( 1440 DDI_DEV_T_NONE, pci_bus_res[bus].dip, 1441 "reg", (int *)pci_regs, 3); 1442 } 1443 index++; 1444 } 1445 } else { 1446 /* perform legacy processing */ 1447 pci_unitaddr_cache_create(); 1448 } 1449 1450 /* 1451 * Do root-bus resource discovery 1452 */ 1453 for (bus = 0; bus <= pci_boot_maxbus; bus++) { 1454 /* skip non-root (peer) PCI busses */ 1455 if (pci_bus_res[bus].par_bus != (uchar_t)-1) 1456 continue; 1457 1458 /* 1459 * 1. find resources associated with this root bus 1460 */ 1461 populate_bus_res(bus); 1462 1463 1464 /* 1465 * 2. Remove used PCI and ISA resources from bus resource map 1466 */ 1467 1468 memlist_remove_list(&pci_bus_res[bus].io_avail, 1469 pci_bus_res[bus].io_used); 1470 memlist_remove_list(&pci_bus_res[bus].mem_avail, 1471 pci_bus_res[bus].mem_used); 1472 memlist_remove_list(&pci_bus_res[bus].pmem_avail, 1473 pci_bus_res[bus].pmem_used); 1474 memlist_remove_list(&pci_bus_res[bus].mem_avail, 1475 pci_bus_res[bus].pmem_used); 1476 memlist_remove_list(&pci_bus_res[bus].pmem_avail, 1477 pci_bus_res[bus].mem_used); 1478 1479 memlist_remove_list(&pci_bus_res[bus].io_avail, 1480 isa_res.io_used); 1481 memlist_remove_list(&pci_bus_res[bus].mem_avail, 1482 isa_res.mem_used); 1483 1484 /* 1485 * 3. Exclude <1M address range here in case below reserved 1486 * ranges for BIOS data area, ROM area etc are wrongly reported 1487 * in ACPI resource producer entries for PCI root bus. 1488 * 00000000 - 000003FF RAM 1489 * 00000400 - 000004FF BIOS data area 1490 * 00000500 - 0009FFFF RAM 1491 * 000A0000 - 000BFFFF VGA RAM 1492 * 000C0000 - 000FFFFF ROM area 1493 */ 1494 (void) memlist_remove(&pci_bus_res[bus].mem_avail, 0, 0x100000); 1495 (void) memlist_remove(&pci_bus_res[bus].pmem_avail, 1496 0, 0x100000); 1497 } 1498 1499 memlist_free_all(&isa_res.io_used); 1500 memlist_free_all(&isa_res.mem_used); 1501 1502 /* add bus-range property for root/peer bus nodes */ 1503 for (i = 0; i <= pci_boot_maxbus; i++) { 1504 /* create bus-range property on root/peer buses */ 1505 if (pci_bus_res[i].par_bus == (uchar_t)-1) 1506 add_bus_range_prop(i); 1507 1508 /* setup bus range resource on each bus */ 1509 setup_bus_res(i); 1510 } 1511 1512 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 1513 DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 1514 if (strcmp(onoff, "off") == 0) { 1515 pci_reconfig = 0; 1516 cmn_err(CE_NOTE, "pci device reprogramming disabled"); 1517 } 1518 ddi_prop_free(onoff); 1519 } 1520 1521 remove_subtractive_res(); 1522 1523 /* reprogram the non-subtractive PPB */ 1524 if (pci_reconfig) 1525 for (i = 0; i <= pci_boot_maxbus; i++) 1526 fix_ppb_res(i, B_FALSE); 1527 1528 for (i = 0; i <= pci_boot_maxbus; i++) { 1529 /* configure devices not configured by BIOS */ 1530 if (pci_reconfig) { 1531 /* 1532 * Reprogram the subtractive PPB. At this time, all its 1533 * siblings should have got their resources already. 1534 */ 1535 if (pci_bus_res[i].subtractive) 1536 fix_ppb_res(i, B_TRUE); 1537 enumerate_bus_devs(i, CONFIG_NEW); 1538 } 1539 } 1540 1541 /* All dev programmed, so we can create available prop */ 1542 for (i = 0; i <= pci_boot_maxbus; i++) 1543 add_bus_available_prop(i); 1544 } 1545 1546 /* 1547 * populate bus resources 1548 */ 1549 static void 1550 populate_bus_res(uchar_t bus) 1551 { 1552 1553 /* scan BIOS structures */ 1554 pci_bus_res[bus].pmem_avail = pci_prd_find_resource(bus, 1555 PCI_PRD_R_PREFETCH); 1556 pci_bus_res[bus].mem_avail = pci_prd_find_resource(bus, PCI_PRD_R_MMIO); 1557 pci_bus_res[bus].io_avail = pci_prd_find_resource(bus, PCI_PRD_R_IO); 1558 pci_bus_res[bus].bus_avail = pci_prd_find_resource(bus, PCI_PRD_R_BUS); 1559 1560 /* 1561 * attempt to initialize sub_bus from the largest range-end 1562 * in the bus_avail list 1563 */ 1564 if (pci_bus_res[bus].bus_avail != NULL) { 1565 struct memlist *entry; 1566 int current; 1567 1568 entry = pci_bus_res[bus].bus_avail; 1569 while (entry != NULL) { 1570 current = entry->ml_address + entry->ml_size - 1; 1571 if (current > pci_bus_res[bus].sub_bus) 1572 pci_bus_res[bus].sub_bus = current; 1573 entry = entry->ml_next; 1574 } 1575 } 1576 1577 if (bus == 0) { 1578 /* 1579 * Special treatment of bus 0: 1580 * If no IO/MEM resource from ACPI/MPSPEC/HRT, copy 1581 * pcimem from boot and make I/O space the entire range 1582 * starting at 0x100. 1583 */ 1584 if (pci_bus_res[0].mem_avail == NULL) 1585 pci_bus_res[0].mem_avail = 1586 memlist_dup(bootops->boot_mem->pcimem); 1587 /* Exclude 0x00 to 0xff of the I/O space, used by all PCs */ 1588 if (pci_bus_res[0].io_avail == NULL) 1589 memlist_insert(&pci_bus_res[0].io_avail, 0x100, 0xffff); 1590 } 1591 1592 /* 1593 * Create 'ranges' property here before any resources are 1594 * removed from the resource lists 1595 */ 1596 add_ranges_prop(bus, 0); 1597 } 1598 1599 /* 1600 * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 1601 */ 1602 static void 1603 create_root_bus_dip(uchar_t bus) 1604 { 1605 int pci_regs[] = {0, 0, 0}; 1606 dev_info_t *dip; 1607 1608 ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 1609 1610 num_root_bus++; 1611 ndi_devi_alloc_sleep(ddi_root_node(), "pci", 1612 (pnode_t)DEVI_SID_NODEID, &dip); 1613 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1614 "#address-cells", 3); 1615 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1616 "#size-cells", 2); 1617 pci_regs[0] = pci_bus_res[bus].root_addr; 1618 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1619 "reg", (int *)pci_regs, 3); 1620 1621 /* 1622 * If system has PCIe bus, then create different properties 1623 */ 1624 if (create_pcie_root_bus(bus, dip) == B_FALSE) 1625 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1626 "device_type", "pci"); 1627 1628 (void) ndi_devi_bind_driver(dip, 0); 1629 pci_bus_res[bus].dip = dip; 1630 } 1631 1632 /* 1633 * For any fixed configuration (often compatability) pci devices 1634 * and those with their own expansion rom, create device nodes 1635 * to hold the already configured device details. 1636 */ 1637 void 1638 enumerate_bus_devs(uchar_t bus, int config_op) 1639 { 1640 uchar_t dev, func, nfunc, header; 1641 ushort_t venid; 1642 struct pci_devfunc *devlist = NULL, *entry; 1643 1644 if (pci_debug_bus_start == -1 || bus_debug(bus)) { 1645 if (config_op == CONFIG_NEW) { 1646 dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 1647 } else if (config_op == CONFIG_FIX) { 1648 dcmn_err(CE_NOTE, 1649 "fixing devices on pci bus 0x%x", bus); 1650 } else { 1651 dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 1652 } 1653 } 1654 1655 if (config_op == CONFIG_NEW) { 1656 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 1657 while (devlist) { 1658 entry = devlist; 1659 devlist = entry->next; 1660 if (entry->reprogram || 1661 pci_bus_res[bus].io_reprogram || 1662 pci_bus_res[bus].mem_reprogram) { 1663 /* reprogram device(s) */ 1664 (void) add_reg_props(entry->dip, bus, 1665 entry->dev, entry->func, CONFIG_NEW, 0); 1666 } 1667 kmem_free(entry, sizeof (*entry)); 1668 } 1669 pci_bus_res[bus].privdata = NULL; 1670 return; 1671 } 1672 1673 for (dev = 0; dev < max_dev_pci; dev++) { 1674 nfunc = 1; 1675 for (func = 0; func < nfunc; func++) { 1676 1677 venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 1678 1679 if ((venid == 0xffff) || (venid == 0)) { 1680 /* no function at this address */ 1681 continue; 1682 } 1683 1684 header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 1685 if (header == 0xff) { 1686 continue; /* illegal value */ 1687 } 1688 1689 /* 1690 * according to some mail from Microsoft posted 1691 * to the pci-drivers alias, their only requirement 1692 * for a multifunction device is for the 1st 1693 * function to have to PCI_HEADER_MULTI bit set. 1694 */ 1695 if ((func == 0) && (header & PCI_HEADER_MULTI)) { 1696 nfunc = 8; 1697 } 1698 1699 if (config_op == CONFIG_FIX || 1700 config_op == CONFIG_INFO) { 1701 /* 1702 * Create the node, unconditionally, on the 1703 * first pass only. It may still need 1704 * resource assignment, which will be 1705 * done on the second, CONFIG_NEW, pass. 1706 */ 1707 process_devfunc(bus, dev, func, header, 1708 venid, config_op); 1709 1710 } 1711 } 1712 } 1713 1714 /* percolate bus used resources up through parents to root */ 1715 if (config_op == CONFIG_INFO) { 1716 int par_bus; 1717 1718 par_bus = pci_bus_res[bus].par_bus; 1719 while (par_bus != (uchar_t)-1) { 1720 pci_bus_res[par_bus].io_size += 1721 pci_bus_res[bus].io_size; 1722 pci_bus_res[par_bus].mem_size += 1723 pci_bus_res[bus].mem_size; 1724 1725 if (pci_bus_res[bus].io_used) 1726 memlist_merge(&pci_bus_res[bus].io_used, 1727 &pci_bus_res[par_bus].io_used); 1728 1729 if (pci_bus_res[bus].mem_used) 1730 memlist_merge(&pci_bus_res[bus].mem_used, 1731 &pci_bus_res[par_bus].mem_used); 1732 1733 if (pci_bus_res[bus].pmem_used) 1734 memlist_merge(&pci_bus_res[bus].pmem_used, 1735 &pci_bus_res[par_bus].pmem_used); 1736 1737 bus = par_bus; 1738 par_bus = pci_bus_res[par_bus].par_bus; 1739 } 1740 } 1741 } 1742 1743 static int 1744 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 1745 ushort_t subvenid, ushort_t subdevid) 1746 { 1747 static int prop_exist = -1; 1748 static char *pciide_str; 1749 char compat[32]; 1750 1751 if (prop_exist == -1) { 1752 prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 1753 ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 1754 &pciide_str) == DDI_SUCCESS); 1755 } 1756 1757 if (!prop_exist) 1758 return (0); 1759 1760 /* compare property value against various forms of compatible */ 1761 if (subvenid) { 1762 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 1763 venid, devid, subvenid, subdevid, revid); 1764 if (strcmp(pciide_str, compat) == 0) 1765 return (1); 1766 1767 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 1768 venid, devid, subvenid, subdevid); 1769 if (strcmp(pciide_str, compat) == 0) 1770 return (1); 1771 1772 (void) snprintf(compat, sizeof (compat), "pci%x,%x", 1773 subvenid, subdevid); 1774 if (strcmp(pciide_str, compat) == 0) 1775 return (1); 1776 } 1777 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 1778 venid, devid, revid); 1779 if (strcmp(pciide_str, compat) == 0) 1780 return (1); 1781 1782 (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 1783 if (strcmp(pciide_str, compat) == 0) 1784 return (1); 1785 1786 return (0); 1787 } 1788 1789 static int 1790 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 1791 ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 1792 { 1793 struct ide_table { /* table for PCI_MASS_OTHER */ 1794 ushort_t venid; 1795 ushort_t devid; 1796 } *entry; 1797 1798 /* XXX SATA and other devices: need a way to add dynamically */ 1799 static struct ide_table ide_other[] = { 1800 {0x1095, 0x3112}, 1801 {0x1095, 0x3114}, 1802 {0x1095, 0x3512}, 1803 {0x1095, 0x680}, /* Sil0680 */ 1804 {0x1283, 0x8211}, /* ITE 8211F is subcl PCI_MASS_OTHER */ 1805 {0, 0} 1806 }; 1807 1808 if (basecl != PCI_CLASS_MASS) 1809 return (0); 1810 1811 if (subcl == PCI_MASS_IDE) { 1812 return (1); 1813 } 1814 1815 if (check_pciide_prop(revid, venid, devid, subvenid, subdevid)) 1816 return (1); 1817 1818 if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 1819 return (0); 1820 } 1821 1822 entry = &ide_other[0]; 1823 while (entry->venid) { 1824 if (entry->venid == venid && entry->devid == devid) 1825 return (1); 1826 entry++; 1827 } 1828 return (0); 1829 } 1830 1831 static int 1832 is_display(uint_t classcode) 1833 { 1834 static uint_t disp_classes[] = { 1835 0x000100, 1836 0x030000, 1837 0x030001 1838 }; 1839 int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 1840 1841 for (i = 0; i < nclasses; i++) { 1842 if (classcode == disp_classes[i]) 1843 return (1); 1844 } 1845 return (0); 1846 } 1847 1848 static void 1849 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn, 1850 void (*undofn)(uint8_t, uint8_t, uint8_t)) 1851 { 1852 struct pci_fixundo *newundo; 1853 1854 newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP); 1855 1856 /* 1857 * Adding an item to this list means that we must turn its NMIENABLE 1858 * bit back on at a later time. 1859 */ 1860 newundo->bus = bus; 1861 newundo->dev = dev; 1862 newundo->fn = fn; 1863 newundo->undofn = undofn; 1864 newundo->next = undolist; 1865 1866 /* add to the undo list in LIFO order */ 1867 undolist = newundo; 1868 } 1869 1870 void 1871 add_pci_fixes(void) 1872 { 1873 int i; 1874 1875 for (i = 0; i <= pci_boot_maxbus; i++) { 1876 /* 1877 * For each bus, apply needed fixes to the appropriate devices. 1878 * This must be done before the main enumeration loop because 1879 * some fixes must be applied to devices normally encountered 1880 * later in the pci scan (e.g. if a fix to device 7 must be 1881 * applied before scanning device 6, applying fixes in the 1882 * normal enumeration loop would obviously be too late). 1883 */ 1884 enumerate_bus_devs(i, CONFIG_FIX); 1885 } 1886 } 1887 1888 void 1889 undo_pci_fixes(void) 1890 { 1891 struct pci_fixundo *nextundo; 1892 uint8_t bus, dev, fn; 1893 1894 /* 1895 * All fixes in the undo list are performed unconditionally. Future 1896 * fixes may require selective undo. 1897 */ 1898 while (undolist != NULL) { 1899 1900 bus = undolist->bus; 1901 dev = undolist->dev; 1902 fn = undolist->fn; 1903 1904 (*(undolist->undofn))(bus, dev, fn); 1905 1906 nextundo = undolist->next; 1907 kmem_free(undolist, sizeof (struct pci_fixundo)); 1908 undolist = nextundo; 1909 } 1910 } 1911 1912 static void 1913 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn) 1914 { 1915 uint8_t val8; 1916 1917 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1918 /* 1919 * The NMIONERR bit is turned back on to allow the SMM BIOS 1920 * to handle more critical PCI errors (e.g. PERR#). 1921 */ 1922 val8 |= AMD8111_ENABLENMI; 1923 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1924 } 1925 1926 static void 1927 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn) 1928 { 1929 uint8_t val8; 1930 1931 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1932 1933 if ((val8 & AMD8111_ENABLENMI) == 0) 1934 return; 1935 1936 /* 1937 * We reset NMIONERR in the LPC because master-abort on the PCI 1938 * bridge side of the 8111 will cause NMI, which might cause SMI, 1939 * which sometimes prevents all devices from being enumerated. 1940 */ 1941 val8 &= ~AMD8111_ENABLENMI; 1942 1943 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1944 1945 add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix); 1946 } 1947 1948 static void 1949 set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func) 1950 { 1951 uint16_t status; 1952 uint8_t header; 1953 uint8_t cap_ptr; 1954 uint8_t cap_id; 1955 uint16_t pmcsr; 1956 1957 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 1958 if (!(status & PCI_STAT_CAP)) 1959 return; /* No capabilities list */ 1960 1961 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1962 if (header == PCI_HEADER_CARDBUS) 1963 cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_CAP_PTR); 1964 else 1965 cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 1966 /* 1967 * Walk the capabilities list searching for a PM entry. 1968 */ 1969 while (cap_ptr != PCI_CAP_NEXT_PTR_NULL && cap_ptr >= PCI_CAP_PTR_OFF) { 1970 cap_ptr &= PCI_CAP_PTR_MASK; 1971 cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID); 1972 if (cap_id == PCI_CAP_ID_PM) { 1973 pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR); 1974 pmcsr &= ~(PCI_PMCSR_STATE_MASK); 1975 pmcsr |= PCI_PMCSR_D0; /* D0 state */ 1976 pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr); 1977 break; 1978 } 1979 cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR); 1980 } 1981 1982 } 1983 1984 #define is_isa(bc, sc) \ 1985 (((bc) == PCI_CLASS_BRIDGE) && ((sc) == PCI_BRIDGE_ISA)) 1986 1987 static void 1988 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 1989 ushort_t vendorid, int config_op) 1990 { 1991 char nodename[32], unitaddr[5]; 1992 dev_info_t *dip; 1993 uchar_t basecl, subcl, progcl, intr, revid; 1994 ushort_t subvenid, subdevid, status; 1995 ushort_t slot_num; 1996 uint_t classcode, revclass; 1997 int reprogram = 0, pciide = 0; 1998 int power[2] = {1, 1}; 1999 int pciex = 0; 2000 ushort_t is_pci_bridge = 0; 2001 struct pci_devfunc *devlist = NULL, *entry = NULL; 2002 boolean_t slot_valid; 2003 gfx_entry_t *gfxp; 2004 pcie_req_id_t bdf; 2005 2006 ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 2007 2008 switch (header & PCI_HEADER_TYPE_M) { 2009 case PCI_HEADER_ZERO: 2010 subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 2011 subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 2012 break; 2013 case PCI_HEADER_CARDBUS: 2014 subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 2015 subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 2016 /* Record the # of cardbus bridges found on the bus */ 2017 if (config_op == CONFIG_INFO) 2018 pci_bus_res[bus].num_cbb++; 2019 break; 2020 default: 2021 subvenid = 0; 2022 subdevid = 0; 2023 break; 2024 } 2025 2026 if (config_op == CONFIG_FIX) { 2027 if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) { 2028 pci_fix_amd8111(bus, dev, func); 2029 } 2030 return; 2031 } 2032 2033 /* XXX should be use generic names? derive from class? */ 2034 revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 2035 classcode = revclass >> 8; 2036 revid = revclass & 0xff; 2037 2038 /* figure out if this is pci-ide */ 2039 basecl = classcode >> 16; 2040 subcl = (classcode >> 8) & 0xff; 2041 progcl = classcode & 0xff; 2042 2043 2044 if (is_display(classcode)) 2045 (void) snprintf(nodename, sizeof (nodename), "display"); 2046 else if (!pseudo_isa && is_isa(basecl, subcl)) 2047 (void) snprintf(nodename, sizeof (nodename), "isa"); 2048 else if (subvenid != 0) 2049 (void) snprintf(nodename, sizeof (nodename), 2050 "pci%x,%x", subvenid, subdevid); 2051 else 2052 (void) snprintf(nodename, sizeof (nodename), 2053 "pci%x,%x", vendorid, deviceid); 2054 2055 /* make sure parent bus dip has been created */ 2056 if (pci_bus_res[bus].dip == NULL) 2057 create_root_bus_dip(bus); 2058 2059 ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 2060 DEVI_SID_NODEID, &dip); 2061 2062 if (check_if_device_is_pciex(dip, bus, dev, func, &slot_valid, 2063 &slot_num, &is_pci_bridge) == B_TRUE) 2064 pciex = 1; 2065 2066 bdf = PCI_GETBDF(bus, dev, func); 2067 /* 2068 * Record BAD AMD bridges which don't support MMIO config access. 2069 */ 2070 if (IS_BAD_AMD_NTBRIDGE(vendorid, deviceid) || 2071 IS_AMD_8132_CHIP(vendorid, deviceid)) { 2072 uchar_t secbus = 0; 2073 uchar_t subbus = 0; 2074 2075 if ((basecl == PCI_CLASS_BRIDGE) && 2076 (subcl == PCI_BRIDGE_PCI)) { 2077 secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 2078 subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 2079 } 2080 pci_cfgacc_add_workaround(bdf, secbus, subbus); 2081 } 2082 2083 /* 2084 * Only populate bus_t if this device is sitting under a PCIE root 2085 * complex. Some particular machines have both a PCIE root complex and 2086 * a PCI hostbridge, in which case only devices under the PCIE root 2087 * complex will have their bus_t populated. 2088 */ 2089 if (pcie_get_rc_dip(dip) != NULL) { 2090 ck804_fix_aer_ptr(dip, bdf); 2091 (void) pcie_init_bus(dip, bdf, PCIE_BUS_INITIAL); 2092 } 2093 2094 /* add properties */ 2095 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 2096 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 2097 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 2098 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2099 "class-code", classcode); 2100 if (func == 0) 2101 (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 2102 else 2103 (void) snprintf(unitaddr, sizeof (unitaddr), 2104 "%x,%x", dev, func); 2105 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 2106 "unit-address", unitaddr); 2107 2108 /* add device_type for display nodes */ 2109 if (is_display(classcode)) { 2110 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 2111 "device_type", "display"); 2112 } 2113 /* add special stuff for header type */ 2114 if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 2115 uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 2116 uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 2117 2118 if (subvenid != 0) { 2119 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2120 "subsystem-id", subdevid); 2121 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2122 "subsystem-vendor-id", subvenid); 2123 } 2124 if (!pciex) 2125 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2126 "min-grant", mingrant); 2127 if (!pciex) 2128 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2129 "max-latency", maxlatency); 2130 } 2131 2132 /* interrupt, record if not 0 */ 2133 intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 2134 if (intr != 0) 2135 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2136 "interrupts", intr); 2137 2138 /* 2139 * Add support for 133 mhz pci eventually 2140 */ 2141 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 2142 2143 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2144 "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 2145 if (!pciex && (status & PCI_STAT_FBBC)) 2146 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 2147 "fast-back-to-back"); 2148 if (!pciex && (status & PCI_STAT_66MHZ)) 2149 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 2150 "66mhz-capable"); 2151 if (status & PCI_STAT_UDF) 2152 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 2153 "udf-supported"); 2154 if (pciex && slot_valid) { 2155 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2156 "physical-slot#", slot_num); 2157 if (!is_pci_bridge) 2158 pciex_slot_names_prop(dip, slot_num); 2159 } 2160 2161 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 2162 "power-consumption", power, 2); 2163 2164 /* Set the device PM state to D0 */ 2165 set_devpm_d0(bus, dev, func); 2166 2167 if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) 2168 add_ppb_props(dip, bus, dev, func, pciex, is_pci_bridge); 2169 else { 2170 /* 2171 * Record the non-PPB devices on the bus for possible 2172 * reprogramming at 2nd bus enumeration. 2173 * Note: PPB reprogramming is done in fix_ppb_res() 2174 */ 2175 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 2176 entry = kmem_zalloc(sizeof (*entry), KM_SLEEP); 2177 entry->dip = dip; 2178 entry->dev = dev; 2179 entry->func = func; 2180 entry->next = devlist; 2181 pci_bus_res[bus].privdata = entry; 2182 } 2183 2184 if (IS_CLASS_IOAPIC(basecl, subcl, progcl)) { 2185 create_ioapic_node(bus, dev, func, vendorid, deviceid); 2186 } 2187 2188 /* check for NVIDIA CK8-04/MCP55 based LPC bridge */ 2189 if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) && 2190 (func == 0)) { 2191 add_nvidia_isa_bridge_props(dip, bus, dev, func); 2192 /* each LPC bridge has an integrated IOAPIC */ 2193 apic_nvidia_io_max++; 2194 } 2195 2196 if (pciex && is_pci_bridge) 2197 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 2198 (char *)"PCIe-PCI bridge"); 2199 else 2200 add_model_prop(dip, classcode); 2201 2202 add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 2203 revid, classcode, pciex); 2204 2205 /* 2206 * See if this device is a controller that advertises 2207 * itself to be a standard ATA task file controller, or one that 2208 * has been hard coded. 2209 * 2210 * If it is, check if any other higher precedence driver listed in 2211 * driver_aliases will claim the node by calling 2212 * ddi_compatibile_driver_major. If so, clear pciide and do not 2213 * create a pci-ide node or any other special handling. 2214 * 2215 * If another driver does not bind, set the node name to pci-ide 2216 * and then let the special pci-ide handling for registers and 2217 * child pci-ide nodes proceed below. 2218 */ 2219 if (is_pciide(basecl, subcl, revid, vendorid, deviceid, 2220 subvenid, subdevid) == 1) { 2221 if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) { 2222 (void) ndi_devi_set_nodename(dip, "pci-ide", 0); 2223 pciide = 1; 2224 } 2225 } 2226 2227 DEVI_SET_PCI(dip); 2228 reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 2229 (void) ndi_devi_bind_driver(dip, 0); 2230 2231 /* special handling for pci-ide */ 2232 if (pciide) { 2233 dev_info_t *cdip; 2234 2235 /* 2236 * Create properties specified by P1275 Working Group 2237 * Proposal #414 Version 1 2238 */ 2239 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 2240 "device_type", "pci-ide"); 2241 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2242 "#address-cells", 1); 2243 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2244 "#size-cells", 0); 2245 2246 /* allocate two child nodes */ 2247 ndi_devi_alloc_sleep(dip, "ide", 2248 (pnode_t)DEVI_SID_NODEID, &cdip); 2249 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 2250 "reg", 0); 2251 (void) ndi_devi_bind_driver(cdip, 0); 2252 ndi_devi_alloc_sleep(dip, "ide", 2253 (pnode_t)DEVI_SID_NODEID, &cdip); 2254 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 2255 "reg", 1); 2256 (void) ndi_devi_bind_driver(cdip, 0); 2257 2258 reprogram = 0; /* don't reprogram pci-ide bridge */ 2259 } 2260 2261 if (is_display(classcode)) { 2262 gfxp = kmem_zalloc(sizeof (*gfxp), KM_SLEEP); 2263 gfxp->g_dip = dip; 2264 gfxp->g_prev = NULL; 2265 gfxp->g_next = gfx_devinfo_list; 2266 gfx_devinfo_list = gfxp; 2267 if (gfxp->g_next) 2268 gfxp->g_next->g_prev = gfxp; 2269 } 2270 2271 /* special handling for isa */ 2272 if (!pseudo_isa && is_isa(basecl, subcl)) { 2273 /* add device_type */ 2274 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 2275 "device_type", "isa"); 2276 } 2277 2278 if (reprogram && (entry != NULL)) 2279 entry->reprogram = B_TRUE; 2280 2281 } 2282 2283 /* 2284 * Some vendors do not use unique subsystem IDs in their products, which 2285 * makes the use of form 2 compatible names (pciSSSS,ssss) inappropriate. 2286 * Allow for these compatible forms to be excluded on a per-device basis. 2287 */ 2288 /*ARGSUSED*/ 2289 static boolean_t 2290 subsys_compat_exclude(ushort_t venid, ushort_t devid, ushort_t subvenid, 2291 ushort_t subdevid, uchar_t revid, uint_t classcode) 2292 { 2293 /* Nvidia display adapters */ 2294 if ((venid == 0x10de) && (is_display(classcode))) 2295 return (B_TRUE); 2296 2297 /* 2298 * 8086,166 is the Ivy Bridge built-in graphics controller on some 2299 * models. Unfortunately 8086,2044 is the Skylake Server processor 2300 * memory channel device. The Ivy Bridge device uses the Skylake 2301 * ID as its sub-device ID. The GPU is not a memory controller DIMM 2302 * channel. 2303 */ 2304 if (venid == 0x8086 && devid == 0x166 && subvenid == 0x8086 && 2305 subdevid == 0x2044) { 2306 return (B_TRUE); 2307 } 2308 2309 return (B_FALSE); 2310 } 2311 2312 /* 2313 * Set the compatible property to a value compliant with rev 2.1 of the IEEE1275 2314 * PCI binding. This is also used for PCI express devices and we have our own 2315 * minor additions. 2316 * 2317 * pciVVVV,DDDD.SSSS.ssss.RR (0) 2318 * pciVVVV,DDDD.SSSS.ssss (1) 2319 * pciSSSS,ssss,s (2+) 2320 * pciSSSS,ssss (2) 2321 * pciVVVV,DDDD.RR (3) 2322 * pciVVVV,DDDD,p (4+) 2323 * pciVVVV,DDDD (4) 2324 * pciclass,CCSSPP (5) 2325 * pciclass,CCSS (6) 2326 * 2327 * The Subsystem (SSSS) forms are not inserted if subsystem-vendor-id is 0 or if 2328 * it is a case where we know that the IDs overlap. 2329 * 2330 * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above and 2331 * property 2 is not created as per "1275 bindings for PCI Express 2332 * Interconnect". 2333 * 2334 * Unlike on SPARC, we generate both the "pciex" and "pci" versions of the 2335 * above. The problem with property 2 is that it has an ambiguity with 2336 * property 4. To make sure that drivers can specify either form of 2 or 4 2337 * without ambiguity we add a suffix. The 'p' suffix represents the primary ID, 2338 * meaning that it is guaranteed to be form 4. The 's' suffix means that it is 2339 * sub-vendor and sub-device form, meaning it is guaranteed to be form 2. 2340 * 2341 * Set with setprop and \x00 between each to generate the encoded string array 2342 * form. 2343 */ 2344 void 2345 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 2346 ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode, 2347 int pciex) 2348 { 2349 int i = 0; 2350 int size = COMPAT_BUFSIZE; 2351 char *compat[15]; 2352 char *buf, *curr; 2353 2354 curr = buf = kmem_alloc(size, KM_SLEEP); 2355 2356 if (pciex) { 2357 if (subvenid) { 2358 compat[i++] = curr; /* form 0 */ 2359 (void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x", 2360 vendorid, deviceid, subvenid, subdevid, revid); 2361 size -= strlen(curr) + 1; 2362 curr += strlen(curr) + 1; 2363 2364 compat[i++] = curr; /* form 1 */ 2365 (void) snprintf(curr, size, "pciex%x,%x.%x.%x", 2366 vendorid, deviceid, subvenid, subdevid); 2367 size -= strlen(curr) + 1; 2368 curr += strlen(curr) + 1; 2369 2370 } 2371 compat[i++] = curr; /* form 3 */ 2372 (void) snprintf(curr, size, "pciex%x,%x.%x", 2373 vendorid, deviceid, revid); 2374 size -= strlen(curr) + 1; 2375 curr += strlen(curr) + 1; 2376 2377 compat[i++] = curr; /* form 4 */ 2378 (void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid); 2379 size -= strlen(curr) + 1; 2380 curr += strlen(curr) + 1; 2381 2382 compat[i++] = curr; /* form 5 */ 2383 (void) snprintf(curr, size, "pciexclass,%06x", classcode); 2384 size -= strlen(curr) + 1; 2385 curr += strlen(curr) + 1; 2386 2387 compat[i++] = curr; /* form 6 */ 2388 (void) snprintf(curr, size, "pciexclass,%04x", 2389 (classcode >> 8)); 2390 size -= strlen(curr) + 1; 2391 curr += strlen(curr) + 1; 2392 } 2393 2394 if (subvenid) { 2395 compat[i++] = curr; /* form 0 */ 2396 (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 2397 vendorid, deviceid, subvenid, subdevid, revid); 2398 size -= strlen(curr) + 1; 2399 curr += strlen(curr) + 1; 2400 2401 compat[i++] = curr; /* form 1 */ 2402 (void) snprintf(curr, size, "pci%x,%x.%x.%x", 2403 vendorid, deviceid, subvenid, subdevid); 2404 size -= strlen(curr) + 1; 2405 curr += strlen(curr) + 1; 2406 2407 if (subsys_compat_exclude(vendorid, deviceid, subvenid, 2408 subdevid, revid, classcode) == B_FALSE) { 2409 compat[i++] = curr; /* form 2+ */ 2410 (void) snprintf(curr, size, "pci%x,%x,s", subvenid, 2411 subdevid); 2412 size -= strlen(curr) + 1; 2413 curr += strlen(curr) + 1; 2414 2415 compat[i++] = curr; /* form 2 */ 2416 (void) snprintf(curr, size, "pci%x,%x", subvenid, 2417 subdevid); 2418 size -= strlen(curr) + 1; 2419 curr += strlen(curr) + 1; 2420 } 2421 } 2422 compat[i++] = curr; /* form 3 */ 2423 (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 2424 size -= strlen(curr) + 1; 2425 curr += strlen(curr) + 1; 2426 2427 compat[i++] = curr; /* form 4+ */ 2428 (void) snprintf(curr, size, "pci%x,%x,p", vendorid, deviceid); 2429 size -= strlen(curr) + 1; 2430 curr += strlen(curr) + 1; 2431 2432 compat[i++] = curr; /* form 4 */ 2433 (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 2434 size -= strlen(curr) + 1; 2435 curr += strlen(curr) + 1; 2436 2437 compat[i++] = curr; /* form 5 */ 2438 (void) snprintf(curr, size, "pciclass,%06x", classcode); 2439 size -= strlen(curr) + 1; 2440 curr += strlen(curr) + 1; 2441 2442 compat[i++] = curr; /* form 6 */ 2443 (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 2444 size -= strlen(curr) + 1; 2445 curr += strlen(curr) + 1; 2446 2447 (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 2448 "compatible", compat, i); 2449 kmem_free(buf, COMPAT_BUFSIZE); 2450 } 2451 2452 /* 2453 * Adjust the reg properties for a dual channel PCI-IDE device. 2454 * 2455 * NOTE: don't do anything that changes the order of the hard-decodes 2456 * and programmed BARs. The kernel driver depends on these values 2457 * being in this order regardless of whether they're for a 'native' 2458 * mode BAR or not. 2459 */ 2460 /* 2461 * config info for pci-ide devices 2462 */ 2463 static struct { 2464 uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 2465 uchar_t bar_offset; /* offset for alt status register */ 2466 ushort_t addr; /* compatibility mode base address */ 2467 ushort_t length; /* number of ports for this BAR */ 2468 } pciide_bar[] = { 2469 { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 2470 { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 2471 { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 2472 { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 2473 }; 2474 2475 static int 2476 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 2477 { 2478 int hard_decode = 0; 2479 2480 /* 2481 * Adjust the base and len for the BARs of the PCI-IDE 2482 * device's primary and secondary controllers. The first 2483 * two BARs are for the primary controller and the next 2484 * two BARs are for the secondary controller. The fifth 2485 * and sixth bars are never adjusted. 2486 */ 2487 if (index >= 0 && index <= 3) { 2488 *lenp = pciide_bar[index].length; 2489 2490 if (progcl & pciide_bar[index].native_mask) { 2491 *basep += pciide_bar[index].bar_offset; 2492 } else { 2493 *basep = pciide_bar[index].addr; 2494 hard_decode = 1; 2495 } 2496 } 2497 2498 /* 2499 * if either base or len is zero make certain both are zero 2500 */ 2501 if (*basep == 0 || *lenp == 0) { 2502 *basep = 0; 2503 *lenp = 0; 2504 hard_decode = 0; 2505 } 2506 2507 return (hard_decode); 2508 } 2509 2510 2511 /* 2512 * Add the "reg" and "assigned-addresses" property 2513 */ 2514 static int 2515 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 2516 int config_op, int pciide) 2517 { 2518 uchar_t baseclass, subclass, progclass, header; 2519 ushort_t bar_sz; 2520 uint64_t value = 0, fbase; 2521 uint_t devloc; 2522 uint_t base, base_hi, type; 2523 ushort_t offset, end; 2524 int max_basereg, j, reprogram = 0; 2525 uint_t phys_hi; 2526 struct memlist **io_avail, **io_used; 2527 struct memlist **mem_avail, **mem_used; 2528 struct memlist **pmem_avail, **pmem_used; 2529 uchar_t res_bus; 2530 2531 pci_regspec_t regs[16] = {{0}}; 2532 pci_regspec_t assigned[15] = {{0}}; 2533 int nreg, nasgn; 2534 2535 io_avail = &pci_bus_res[bus].io_avail; 2536 io_used = &pci_bus_res[bus].io_used; 2537 mem_avail = &pci_bus_res[bus].mem_avail; 2538 mem_used = &pci_bus_res[bus].mem_used; 2539 pmem_avail = &pci_bus_res[bus].pmem_avail; 2540 pmem_used = &pci_bus_res[bus].pmem_used; 2541 2542 dump_memlists("add_reg_props start", bus); 2543 2544 devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 2545 regs[0].pci_phys_hi = devloc; 2546 nreg = 1; /* rest of regs[0] is all zero */ 2547 nasgn = 0; 2548 2549 baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 2550 subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 2551 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 2552 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 2553 2554 switch (header) { 2555 case PCI_HEADER_ZERO: 2556 max_basereg = PCI_BASE_NUM; 2557 break; 2558 case PCI_HEADER_PPB: 2559 max_basereg = PCI_BCNF_BASE_NUM; 2560 break; 2561 case PCI_HEADER_CARDBUS: 2562 max_basereg = PCI_CBUS_BASE_NUM; 2563 reprogram = 1; 2564 break; 2565 default: 2566 max_basereg = 0; 2567 break; 2568 } 2569 2570 /* 2571 * Create the register property by saving the current 2572 * value of the base register. Write 0xffffffff to the 2573 * base register. Read the value back to determine the 2574 * required size of the address space. Restore the base 2575 * register contents. 2576 * 2577 * Do not disable I/O and memory access for bridges; this 2578 * has the side-effect of making the bridge transparent to 2579 * secondary-bus activity (see sections 4.1-4.3 of the 2580 * PCI-PCI Bridge Spec V1.2). For non-bridges, disable 2581 * I/O and memory access to avoid difficulty with USB 2582 * emulation (see OHCI spec1.0a appendix B 2583 * "Host Controller Mapping") 2584 */ 2585 end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 2586 for (j = 0, offset = PCI_CONF_BASE0; offset < end; 2587 j++, offset += bar_sz) { 2588 uint_t command = 0; 2589 2590 /* determine the size of the address space */ 2591 base = pci_getl(bus, dev, func, offset); 2592 if (baseclass != PCI_CLASS_BRIDGE) { 2593 command = (uint_t)pci_getw(bus, dev, func, 2594 PCI_CONF_COMM); 2595 pci_putw(bus, dev, func, PCI_CONF_COMM, 2596 command & ~(PCI_COMM_MAE | PCI_COMM_IO)); 2597 } 2598 pci_putl(bus, dev, func, offset, 0xffffffff); 2599 value = pci_getl(bus, dev, func, offset); 2600 pci_putl(bus, dev, func, offset, base); 2601 if (baseclass != PCI_CLASS_BRIDGE) 2602 pci_putw(bus, dev, func, PCI_CONF_COMM, command); 2603 2604 /* construct phys hi,med.lo, size hi, lo */ 2605 if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 2606 int hard_decode = 0; 2607 uint_t len; 2608 2609 /* i/o space */ 2610 bar_sz = PCI_BAR_SZ_32; 2611 value &= PCI_BASE_IO_ADDR_M; 2612 len = ((value ^ (value-1)) + 1) >> 1; 2613 2614 /* XXX Adjust first 4 IDE registers */ 2615 if (pciide) { 2616 if (subclass != PCI_MASS_IDE) 2617 progclass = (PCI_IDE_IF_NATIVE_PRI | 2618 PCI_IDE_IF_NATIVE_SEC); 2619 hard_decode = pciIdeAdjustBAR(progclass, j, 2620 &base, &len); 2621 } else if (value == 0) { 2622 /* skip base regs with size of 0 */ 2623 continue; 2624 } 2625 2626 regs[nreg].pci_phys_hi = PCI_ADDR_IO | devloc | 2627 (hard_decode ? PCI_RELOCAT_B : offset); 2628 regs[nreg].pci_phys_low = hard_decode ? 2629 base & PCI_BASE_IO_ADDR_M : 0; 2630 assigned[nasgn].pci_phys_hi = 2631 PCI_RELOCAT_B | regs[nreg].pci_phys_hi; 2632 regs[nreg].pci_size_low = 2633 assigned[nasgn].pci_size_low = len; 2634 type = base & (~PCI_BASE_IO_ADDR_M); 2635 base &= PCI_BASE_IO_ADDR_M; 2636 /* 2637 * A device under a subtractive PPB can allocate 2638 * resources from its parent bus if there is no resource 2639 * available on its own bus. 2640 */ 2641 if ((config_op == CONFIG_NEW) && (*io_avail == NULL)) { 2642 res_bus = bus; 2643 while (pci_bus_res[res_bus].subtractive) { 2644 res_bus = pci_bus_res[res_bus].par_bus; 2645 if (res_bus == (uchar_t)-1) 2646 break; /* root bus already */ 2647 if (pci_bus_res[res_bus].io_avail) { 2648 io_avail = &pci_bus_res 2649 [res_bus].io_avail; 2650 break; 2651 } 2652 } 2653 } 2654 2655 /* 2656 * first pass - gather what's there 2657 * update/second pass - adjust/allocate regions 2658 * config - allocate regions 2659 */ 2660 if (config_op == CONFIG_INFO) { /* first pass */ 2661 /* take out of the resource map of the bus */ 2662 if (base != 0) { 2663 (void) memlist_remove(io_avail, base, 2664 len); 2665 memlist_insert(io_used, base, len); 2666 } else { 2667 reprogram = 1; 2668 } 2669 pci_bus_res[bus].io_size += len; 2670 } else if ((*io_avail && base == 0) || 2671 pci_bus_res[bus].io_reprogram) { 2672 base = (uint_t)memlist_find(io_avail, len, len); 2673 if (base != 0) { 2674 memlist_insert(io_used, base, len); 2675 /* XXX need to worry about 64-bit? */ 2676 pci_putl(bus, dev, func, offset, 2677 base | type); 2678 base = pci_getl(bus, dev, func, offset); 2679 base &= PCI_BASE_IO_ADDR_M; 2680 } 2681 if (base == 0) { 2682 cmn_err(CE_WARN, "failed to program" 2683 " IO space [%d/%d/%d] BAR@0x%x" 2684 " length 0x%x", 2685 bus, dev, func, offset, len); 2686 } 2687 } 2688 assigned[nasgn].pci_phys_low = base; 2689 nreg++, nasgn++; 2690 2691 } else { 2692 uint64_t len; 2693 /* memory space */ 2694 if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 2695 bar_sz = PCI_BAR_SZ_64; 2696 base_hi = pci_getl(bus, dev, func, offset + 4); 2697 pci_putl(bus, dev, func, offset + 4, 2698 0xffffffff); 2699 value |= (uint64_t)pci_getl(bus, dev, func, 2700 offset + 4) << 32; 2701 pci_putl(bus, dev, func, offset + 4, base_hi); 2702 phys_hi = PCI_ADDR_MEM64; 2703 value &= PCI_BASE_M_ADDR64_M; 2704 } else { 2705 bar_sz = PCI_BAR_SZ_32; 2706 base_hi = 0; 2707 phys_hi = PCI_ADDR_MEM32; 2708 value &= PCI_BASE_M_ADDR_M; 2709 } 2710 2711 /* skip base regs with size of 0 */ 2712 if (value == 0) 2713 continue; 2714 2715 len = ((value ^ (value-1)) + 1) >> 1; 2716 regs[nreg].pci_size_low = 2717 assigned[nasgn].pci_size_low = len & 0xffffffff; 2718 regs[nreg].pci_size_hi = 2719 assigned[nasgn].pci_size_hi = len >> 32; 2720 2721 phys_hi |= (devloc | offset); 2722 if (base & PCI_BASE_PREF_M) 2723 phys_hi |= PCI_PREFETCH_B; 2724 2725 /* 2726 * A device under a subtractive PPB can allocate 2727 * resources from its parent bus if there is no resource 2728 * available on its own bus. 2729 */ 2730 if ((config_op == CONFIG_NEW) && (*mem_avail == NULL)) { 2731 res_bus = bus; 2732 while (pci_bus_res[res_bus].subtractive) { 2733 res_bus = pci_bus_res[res_bus].par_bus; 2734 if (res_bus == (uchar_t)-1) 2735 break; /* root bus already */ 2736 mem_avail = 2737 &pci_bus_res[res_bus].mem_avail; 2738 pmem_avail = 2739 &pci_bus_res [res_bus].pmem_avail; 2740 /* 2741 * Break out as long as at least 2742 * mem_avail is available 2743 */ 2744 if ((*pmem_avail && 2745 (phys_hi & PCI_PREFETCH_B)) || 2746 *mem_avail) { 2747 break; 2748 } 2749 } 2750 } 2751 2752 regs[nreg].pci_phys_hi = 2753 assigned[nasgn].pci_phys_hi = phys_hi; 2754 assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 2755 type = base & ~PCI_BASE_M_ADDR_M; 2756 base &= PCI_BASE_M_ADDR_M; 2757 2758 fbase = (((uint64_t)base_hi) << 32) | base; 2759 2760 if (config_op == CONFIG_INFO) { 2761 /* take out of the resource map of the bus */ 2762 if (fbase != 0) { 2763 /* remove from PMEM and MEM space */ 2764 (void) memlist_remove(mem_avail, 2765 fbase, len); 2766 (void) memlist_remove(pmem_avail, 2767 fbase, len); 2768 /* only note as used in correct map */ 2769 if (phys_hi & PCI_PREFETCH_B) 2770 memlist_insert(pmem_used, 2771 fbase, len); 2772 else 2773 memlist_insert(mem_used, 2774 fbase, len); 2775 } else { 2776 reprogram = 1; 2777 } 2778 pci_bus_res[bus].mem_size += len; 2779 } else if (pci_bus_res[bus].mem_reprogram || 2780 (fbase == 0 && 2781 (*mem_avail != NULL || *pmem_avail != NULL))) { 2782 2783 fbase = 0; 2784 2785 /* 2786 * When desired, attempt a prefetchable 2787 * allocation first 2788 */ 2789 if ((phys_hi & PCI_PREFETCH_B) && 2790 *pmem_avail != NULL) { 2791 fbase = memlist_find(pmem_avail, 2792 len, len); 2793 if (fbase != 0) { 2794 memlist_insert(pmem_used, 2795 fbase, len); 2796 (void) memlist_remove( 2797 pmem_avail, fbase, len); 2798 cmn_err(CE_NOTE, "!program " 2799 "[%x/%x/%x] BAR@0x%x" 2800 " 0x%lx length 0x%lx", 2801 bus, dev, func, offset, 2802 fbase, len); 2803 } 2804 } 2805 /* 2806 * If prefetchable allocation was not 2807 * desired, or failed, attempt ordinary 2808 * memory allocation 2809 */ 2810 if (fbase == 0 && *mem_avail != NULL) { 2811 fbase = memlist_find(mem_avail, 2812 len, len); 2813 if (fbase != 0) { 2814 memlist_insert(mem_used, 2815 fbase, len); 2816 (void) memlist_remove( 2817 mem_avail, fbase, len); 2818 cmn_err(CE_NOTE, "!program " 2819 "[%x/%x/%x] BAR@0x%x" 2820 " 0x%lx length 0x%lx", 2821 bus, dev, func, offset, 2822 fbase, len); 2823 } 2824 } 2825 2826 base_hi = fbase >> 32; 2827 base = fbase & 0xffffffff; 2828 2829 if (fbase != 0) { 2830 pci_putl(bus, dev, func, offset, 2831 base | type); 2832 base = pci_getl(bus, dev, func, offset); 2833 2834 if (bar_sz == PCI_BAR_SZ_64) { 2835 pci_putl(bus, dev, func, 2836 offset + 4, base_hi); 2837 base_hi = pci_getl(bus, dev, 2838 func, offset + 4); 2839 } 2840 2841 base &= PCI_BASE_M_ADDR_M; 2842 } else { 2843 cmn_err(CE_WARN, "failed to program " 2844 "mem space [%x/%x/%x] BAR@0x%x" 2845 " length 0x%"PRIx64, 2846 bus, dev, func, offset, len); 2847 } 2848 } 2849 2850 assigned[nasgn].pci_phys_mid = base_hi; 2851 assigned[nasgn].pci_phys_low = base; 2852 2853 dcmn_err(CE_NOTE, 2854 "![%x/%x/%x] --- %08x.%x.%x.%x.%x", 2855 bus, dev, func, 2856 assigned[nasgn].pci_phys_hi, 2857 assigned[nasgn].pci_phys_mid, 2858 assigned[nasgn].pci_phys_low, 2859 assigned[nasgn].pci_size_hi, 2860 assigned[nasgn].pci_size_low); 2861 2862 nreg++, nasgn++; 2863 } 2864 } 2865 switch (header) { 2866 case PCI_HEADER_ZERO: 2867 offset = PCI_CONF_ROM; 2868 break; 2869 case PCI_HEADER_PPB: 2870 offset = PCI_BCNF_ROM; 2871 break; 2872 default: /* including PCI_HEADER_CARDBUS */ 2873 goto done; 2874 } 2875 2876 /* 2877 * Add the expansion rom memory space 2878 * Determine the size of the ROM base reg; don't write reserved bits 2879 * ROM isn't in the PCI memory space. 2880 */ 2881 base = pci_getl(bus, dev, func, offset); 2882 pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 2883 value = pci_getl(bus, dev, func, offset); 2884 pci_putl(bus, dev, func, offset, base); 2885 if (value & PCI_BASE_ROM_ENABLE) 2886 value &= PCI_BASE_ROM_ADDR_M; 2887 else 2888 value = 0; 2889 2890 if (value != 0) { 2891 uint_t len; 2892 2893 regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 2894 assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 2895 PCI_ADDR_MEM32 | devloc) + offset; 2896 base &= PCI_BASE_ROM_ADDR_M; 2897 assigned[nasgn].pci_phys_low = base; 2898 len = ((value ^ (value-1)) + 1) >> 1; 2899 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 2900 nreg++, nasgn++; 2901 /* take it out of the memory resource */ 2902 if (base != 0) { 2903 (void) memlist_remove(mem_avail, base, len); 2904 memlist_insert(mem_used, base, len); 2905 pci_bus_res[bus].mem_size += len; 2906 } 2907 } 2908 2909 /* 2910 * Account for "legacy" (alias) video adapter resources 2911 */ 2912 2913 /* add the three hard-decode, aliased address spaces for VGA */ 2914 if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 2915 (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 2916 2917 /* VGA hard decode 0x3b0-0x3bb */ 2918 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2919 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2920 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 2921 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 2922 nreg++, nasgn++; 2923 (void) memlist_remove(io_avail, 0x3b0, 0xc); 2924 memlist_insert(io_used, 0x3b0, 0xc); 2925 pci_bus_res[bus].io_size += 0xc; 2926 2927 /* VGA hard decode 0x3c0-0x3df */ 2928 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2929 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2930 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 2931 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 2932 nreg++, nasgn++; 2933 (void) memlist_remove(io_avail, 0x3c0, 0x20); 2934 memlist_insert(io_used, 0x3c0, 0x20); 2935 pci_bus_res[bus].io_size += 0x20; 2936 2937 /* Video memory */ 2938 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2939 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_MEM32 | devloc); 2940 regs[nreg].pci_phys_low = 2941 assigned[nasgn].pci_phys_low = 0xa0000; 2942 regs[nreg].pci_size_low = 2943 assigned[nasgn].pci_size_low = 0x20000; 2944 nreg++, nasgn++; 2945 /* remove from MEM and PMEM space */ 2946 (void) memlist_remove(mem_avail, 0xa0000, 0x20000); 2947 (void) memlist_remove(pmem_avail, 0xa0000, 0x20000); 2948 memlist_insert(mem_used, 0xa0000, 0x20000); 2949 pci_bus_res[bus].mem_size += 0x20000; 2950 } 2951 2952 /* add the hard-decode, aliased address spaces for 8514 */ 2953 if ((baseclass == PCI_CLASS_DISPLAY) && 2954 (subclass == PCI_DISPLAY_VGA) && 2955 (progclass & PCI_DISPLAY_IF_8514)) { 2956 2957 /* hard decode 0x2e8 */ 2958 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2959 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2960 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 2961 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 2962 nreg++, nasgn++; 2963 (void) memlist_remove(io_avail, 0x2e8, 0x1); 2964 memlist_insert(io_used, 0x2e8, 0x1); 2965 pci_bus_res[bus].io_size += 0x1; 2966 2967 /* hard decode 0x2ea-0x2ef */ 2968 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2969 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2970 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 2971 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 2972 nreg++, nasgn++; 2973 (void) memlist_remove(io_avail, 0x2ea, 0x6); 2974 memlist_insert(io_used, 0x2ea, 0x6); 2975 pci_bus_res[bus].io_size += 0x6; 2976 } 2977 2978 done: 2979 dump_memlists("add_reg_props end", bus); 2980 2981 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 2982 (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 2983 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 2984 "assigned-addresses", 2985 (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 2986 2987 return (reprogram); 2988 } 2989 2990 static void 2991 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 2992 int pciex, ushort_t is_pci_bridge) 2993 { 2994 char *dev_type; 2995 int i; 2996 uint_t val; 2997 uint64_t io_range[2], mem_range[2], pmem_range[2]; 2998 uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 2999 uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 3000 uchar_t progclass; 3001 3002 ASSERT(secbus <= subbus); 3003 3004 dump_memlists("add_ppb_props start bus", bus); 3005 dump_memlists("add_ppb_props start secbus", secbus); 3006 3007 /* 3008 * Check if it's a subtractive PPB. 3009 */ 3010 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 3011 if (progclass == PCI_BRIDGE_PCI_IF_SUBDECODE) 3012 pci_bus_res[secbus].subtractive = B_TRUE; 3013 3014 /* 3015 * Some BIOSes lie about max pci busses, we allow for 3016 * such mistakes here 3017 */ 3018 if (subbus > pci_boot_maxbus) { 3019 pci_boot_maxbus = subbus; 3020 alloc_res_array(); 3021 } 3022 3023 ASSERT(pci_bus_res[secbus].dip == NULL); 3024 pci_bus_res[secbus].dip = dip; 3025 pci_bus_res[secbus].par_bus = bus; 3026 3027 dev_type = (pciex && !is_pci_bridge) ? "pciex" : "pci"; 3028 3029 /* setup bus number hierarchy */ 3030 pci_bus_res[secbus].sub_bus = subbus; 3031 /* 3032 * Keep track of the largest subordinate bus number (this is essential 3033 * for peer busses because there is no other way of determining its 3034 * subordinate bus number). 3035 */ 3036 if (subbus > pci_bus_res[bus].sub_bus) 3037 pci_bus_res[bus].sub_bus = subbus; 3038 /* 3039 * Loop through subordinate busses, initializing their parent bus 3040 * field to this bridge's parent. The subordinate busses' parent 3041 * fields may very well be further refined later, as child bridges 3042 * are enumerated. (The value is to note that the subordinate busses 3043 * are not peer busses by changing their par_bus fields to anything 3044 * other than -1.) 3045 */ 3046 for (i = secbus + 1; i <= subbus; i++) 3047 pci_bus_res[i].par_bus = bus; 3048 3049 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 3050 "device_type", dev_type); 3051 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3052 "#address-cells", 3); 3053 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3054 "#size-cells", 2); 3055 3056 /* 3057 * Collect bridge window specifications, and use them to populate 3058 * the "avail" resources for the bus. Not all of those resources will 3059 * end up being available; this is done top-down, and so the initial 3060 * collection of windows populates the 'ranges' property for the 3061 * bus node. Later, as children are found, resources are removed from 3062 * the 'avail' list, so that it becomes the freelist for 3063 * this point in the tree. ranges may be set again after bridge 3064 * reprogramming in fix_ppb_res(), in which case it's set from 3065 * used + avail. 3066 * 3067 * According to PPB spec, the base register should be programmed 3068 * with a value bigger than the limit register when there are 3069 * no resources available. This applies to io, memory, and 3070 * prefetchable memory. 3071 */ 3072 3073 /* 3074 * io range 3075 * We determine i/o windows that are left unconfigured by BIOS 3076 * through its i/o enable bit as Microsoft recommends OEMs to do. 3077 * If it is unset, we disable i/o and mark it for reconfiguration in 3078 * later passes by setting the base > limit 3079 */ 3080 val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM); 3081 if (val & PCI_COMM_IO) { 3082 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 3083 io_range[1] = ((val & PCI_BCNF_IO_MASK) << PCI_BCNF_IO_SHIFT) | 3084 0xfff; 3085 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 3086 io_range[0] = ((val & PCI_BCNF_IO_MASK) << PCI_BCNF_IO_SHIFT); 3087 if ((val & PCI_BCNF_ADDR_MASK) == PCI_BCNF_IO_32BIT) { 3088 uint16_t io_base_hi, io_limit_hi; 3089 io_base_hi = pci_getw(bus, dev, func, 3090 PCI_BCNF_IO_BASE_HI); 3091 io_limit_hi = pci_getw(bus, dev, func, 3092 PCI_BCNF_IO_LIMIT_HI); 3093 3094 io_range[0] |= (uint32_t)io_base_hi << 16; 3095 io_range[1] |= (uint32_t)io_limit_hi << 16; 3096 } 3097 } else { 3098 io_range[0] = 0x9fff; 3099 io_range[1] = 0x1000; 3100 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 3101 (uint8_t)((io_range[0] >> 8) & 0xf0)); 3102 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 3103 (uint8_t)((io_range[1] >> 8) & 0xf0)); 3104 pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 3105 pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 3106 } 3107 3108 if (io_range[0] != 0 && io_range[0] < io_range[1]) { 3109 memlist_insert(&pci_bus_res[secbus].io_avail, 3110 io_range[0], (io_range[1] - io_range[0] + 1)); 3111 memlist_insert(&pci_bus_res[bus].io_used, 3112 io_range[0], (io_range[1] - io_range[0] + 1)); 3113 if (pci_bus_res[bus].io_avail != NULL) { 3114 (void) memlist_remove(&pci_bus_res[bus].io_avail, 3115 io_range[0], (io_range[1] - io_range[0] + 1)); 3116 } 3117 dcmn_err(CE_NOTE, "bus %x io-range: 0x%" PRIx64 "-%" PRIx64, 3118 secbus, io_range[0], io_range[1]); 3119 } 3120 3121 /* mem range */ 3122 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 3123 mem_range[0] = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT); 3124 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 3125 mem_range[1] = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT) | 3126 0xfffff; 3127 if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 3128 memlist_insert(&pci_bus_res[secbus].mem_avail, 3129 mem_range[0], mem_range[1] - mem_range[0] + 1); 3130 memlist_insert(&pci_bus_res[bus].mem_used, 3131 mem_range[0], mem_range[1] - mem_range[0] + 1); 3132 /* remove from parent resource list */ 3133 (void) memlist_remove(&pci_bus_res[bus].mem_avail, 3134 mem_range[0], mem_range[1] - mem_range[0] + 1); 3135 (void) memlist_remove(&pci_bus_res[bus].pmem_avail, 3136 mem_range[0], mem_range[1] - mem_range[0] + 1); 3137 dcmn_err(CE_NOTE, "bus %x mem-range: 0x%" PRIx64 "-%" PRIx64, 3138 secbus, mem_range[0], mem_range[1]); 3139 } 3140 3141 /* prefetchable memory range */ 3142 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 3143 pmem_range[1] = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT) | 3144 0xfffff; 3145 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 3146 pmem_range[0] = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT); 3147 if ((val & PCI_BCNF_ADDR_MASK) == PCI_BCNF_PF_MEM_64BIT) { 3148 uint32_t pf_addr_hi, pf_limit_hi; 3149 pf_addr_hi = pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH); 3150 pf_limit_hi = pci_getl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH); 3151 pmem_range[0] |= (uint64_t)pf_addr_hi << 32; 3152 pmem_range[1] |= (uint64_t)pf_limit_hi << 32; 3153 } 3154 if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 3155 memlist_insert(&pci_bus_res[secbus].pmem_avail, 3156 pmem_range[0], pmem_range[1] - pmem_range[0] + 1); 3157 memlist_insert(&pci_bus_res[bus].pmem_used, 3158 pmem_range[0], pmem_range[1] - pmem_range[0] + 1); 3159 /* remove from parent resource list */ 3160 (void) memlist_remove(&pci_bus_res[bus].pmem_avail, 3161 pmem_range[0], pmem_range[1] - pmem_range[0] + 1); 3162 (void) memlist_remove(&pci_bus_res[bus].mem_avail, 3163 pmem_range[0], pmem_range[1] - pmem_range[0] + 1); 3164 dcmn_err(CE_NOTE, "bus %x pmem-range: 0x%" PRIx64 "-%" PRIx64, 3165 secbus, pmem_range[0], pmem_range[1]); 3166 } 3167 3168 /* 3169 * Add VGA legacy resources to the bridge's pci_bus_res if it 3170 * has VGA_ENABLE set. Note that we put them in 'avail', 3171 * because that's used to populate the ranges prop; they'll be 3172 * removed from there by the VGA device once it's found. Also, 3173 * remove them from the parent's available list and note them as 3174 * used in the parent. 3175 */ 3176 3177 if (pci_getw(bus, dev, func, PCI_BCNF_BCNTRL) & 3178 PCI_BCNF_BCNTRL_VGA_ENABLE) { 3179 3180 memlist_insert(&pci_bus_res[secbus].io_avail, 0x3b0, 0xc); 3181 3182 memlist_insert(&pci_bus_res[bus].io_used, 0x3b0, 0xc); 3183 if (pci_bus_res[bus].io_avail != NULL) { 3184 (void) memlist_remove(&pci_bus_res[bus].io_avail, 3185 0x3b0, 0xc); 3186 } 3187 3188 memlist_insert(&pci_bus_res[secbus].io_avail, 0x3c0, 0x20); 3189 3190 memlist_insert(&pci_bus_res[bus].io_used, 0x3c0, 0x20); 3191 if (pci_bus_res[bus].io_avail != NULL) { 3192 (void) memlist_remove(&pci_bus_res[bus].io_avail, 3193 0x3c0, 0x20); 3194 } 3195 3196 memlist_insert(&pci_bus_res[secbus].mem_avail, 0xa0000, 3197 0x20000); 3198 3199 memlist_insert(&pci_bus_res[bus].mem_used, 0xa0000, 0x20000); 3200 if (pci_bus_res[bus].mem_avail != NULL) { 3201 (void) memlist_remove(&pci_bus_res[bus].mem_avail, 3202 0xa0000, 0x20000); 3203 } 3204 } 3205 add_bus_range_prop(secbus); 3206 add_ranges_prop(secbus, 1); 3207 3208 dump_memlists("add_ppb_props end bus", bus); 3209 dump_memlists("add_ppb_props end secbus", secbus); 3210 } 3211 3212 extern const struct pci_class_strings_s class_pci[]; 3213 extern int class_pci_items; 3214 3215 static void 3216 add_model_prop(dev_info_t *dip, uint_t classcode) 3217 { 3218 const char *desc; 3219 int i; 3220 uchar_t baseclass = classcode >> 16; 3221 uchar_t subclass = (classcode >> 8) & 0xff; 3222 uchar_t progclass = classcode & 0xff; 3223 3224 if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 3225 desc = "IDE controller"; 3226 } else { 3227 for (desc = 0, i = 0; i < class_pci_items; i++) { 3228 if ((baseclass == class_pci[i].base_class) && 3229 (subclass == class_pci[i].sub_class) && 3230 (progclass == class_pci[i].prog_class)) { 3231 desc = class_pci[i].actual_desc; 3232 break; 3233 } 3234 } 3235 if (i == class_pci_items) 3236 desc = "Unknown class of pci/pnpbios device"; 3237 } 3238 3239 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 3240 (char *)desc); 3241 } 3242 3243 static void 3244 add_bus_range_prop(int bus) 3245 { 3246 int bus_range[2]; 3247 3248 if (pci_bus_res[bus].dip == NULL) 3249 return; 3250 bus_range[0] = bus; 3251 bus_range[1] = pci_bus_res[bus].sub_bus; 3252 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 3253 "bus-range", (int *)bus_range, 2); 3254 } 3255 3256 /* 3257 * Handle both PCI root and PCI-PCI bridge range properties; 3258 * non-zero 'ppb' argument select PCI-PCI bridges versus root. 3259 */ 3260 static void 3261 memlist_to_ranges(void **rp, struct memlist *entry, uint_t type, int ppb) 3262 { 3263 ppb_ranges_t *ppb_rp = *rp; 3264 pci_ranges_t *pci_rp = *rp; 3265 3266 while (entry != NULL) { 3267 uint_t atype = type; 3268 if ((type & PCI_REG_ADDR_M) == PCI_ADDR_MEM32 && 3269 (entry->ml_address >= UINT32_MAX || 3270 entry->ml_size >= UINT32_MAX)) { 3271 atype &= ~PCI_ADDR_MEM32; 3272 atype |= PCI_ADDR_MEM64; 3273 } 3274 if (ppb) { 3275 ppb_rp->child_high = ppb_rp->parent_high = atype; 3276 ppb_rp->child_mid = ppb_rp->parent_mid = 3277 (uint32_t)(entry->ml_address >> 32); 3278 ppb_rp->child_low = ppb_rp->parent_low = 3279 (uint32_t)entry->ml_address; 3280 ppb_rp->size_high = 3281 (uint32_t)(entry->ml_size >> 32); 3282 ppb_rp->size_low = (uint32_t)entry->ml_size; 3283 *rp = ++ppb_rp; 3284 } else { 3285 pci_rp->child_high = atype; 3286 pci_rp->child_mid = pci_rp->parent_high = 3287 (uint32_t)(entry->ml_address >> 32); 3288 pci_rp->child_low = pci_rp->parent_low = 3289 (uint32_t)entry->ml_address; 3290 pci_rp->size_high = 3291 (uint32_t)(entry->ml_size >> 32); 3292 pci_rp->size_low = (uint32_t)entry->ml_size; 3293 *rp = ++pci_rp; 3294 } 3295 entry = entry->ml_next; 3296 } 3297 } 3298 3299 static void 3300 add_ranges_prop(int bus, int ppb) 3301 { 3302 int total, alloc_size; 3303 void *rp, *next_rp; 3304 struct memlist *iolist, *memlist, *pmemlist; 3305 3306 /* no devinfo node - unused bus, return */ 3307 if (pci_bus_res[bus].dip == NULL) 3308 return; 3309 3310 dump_memlists("add_ranges_prop", bus); 3311 3312 iolist = memlist = pmemlist = (struct memlist *)NULL; 3313 3314 memlist_merge(&pci_bus_res[bus].io_avail, &iolist); 3315 memlist_merge(&pci_bus_res[bus].io_used, &iolist); 3316 memlist_merge(&pci_bus_res[bus].mem_avail, &memlist); 3317 memlist_merge(&pci_bus_res[bus].mem_used, &memlist); 3318 memlist_merge(&pci_bus_res[bus].pmem_avail, &pmemlist); 3319 memlist_merge(&pci_bus_res[bus].pmem_used, &pmemlist); 3320 3321 total = memlist_count(iolist); 3322 total += memlist_count(memlist); 3323 total += memlist_count(pmemlist); 3324 3325 /* no property is created if no ranges are present */ 3326 if (total == 0) 3327 return; 3328 3329 alloc_size = total * 3330 (ppb ? sizeof (ppb_ranges_t) : sizeof (pci_ranges_t)); 3331 3332 next_rp = rp = kmem_alloc(alloc_size, KM_SLEEP); 3333 3334 memlist_to_ranges(&next_rp, iolist, PCI_ADDR_IO | PCI_REG_REL_M, ppb); 3335 memlist_to_ranges(&next_rp, memlist, 3336 PCI_ADDR_MEM32 | PCI_REG_REL_M, ppb); 3337 memlist_to_ranges(&next_rp, pmemlist, 3338 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M, ppb); 3339 3340 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 3341 "ranges", (int *)rp, alloc_size / sizeof (int)); 3342 3343 kmem_free(rp, alloc_size); 3344 memlist_free_all(&iolist); 3345 memlist_free_all(&memlist); 3346 memlist_free_all(&pmemlist); 3347 } 3348 3349 static void 3350 memlist_remove_list(struct memlist **list, struct memlist *remove_list) 3351 { 3352 while (list && *list && remove_list) { 3353 (void) memlist_remove(list, remove_list->ml_address, 3354 remove_list->ml_size); 3355 remove_list = remove_list->ml_next; 3356 } 3357 } 3358 3359 static int 3360 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 3361 { 3362 int i = 0; 3363 3364 while (list) { 3365 /* assume 32-bit addresses */ 3366 sp->pci_phys_hi = type; 3367 sp->pci_phys_mid = 0; 3368 sp->pci_phys_low = (uint32_t)list->ml_address; 3369 sp->pci_size_hi = 0; 3370 sp->pci_size_low = (uint32_t)list->ml_size; 3371 3372 list = list->ml_next; 3373 sp++, i++; 3374 } 3375 return (i); 3376 } 3377 3378 static void 3379 add_bus_available_prop(int bus) 3380 { 3381 int i, count; 3382 struct pci_phys_spec *sp; 3383 3384 /* no devinfo node - unused bus, return */ 3385 if (pci_bus_res[bus].dip == NULL) 3386 return; 3387 3388 count = memlist_count(pci_bus_res[bus].io_avail) + 3389 memlist_count(pci_bus_res[bus].mem_avail) + 3390 memlist_count(pci_bus_res[bus].pmem_avail); 3391 3392 if (count == 0) /* nothing available */ 3393 return; 3394 3395 sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 3396 i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_avail, 3397 PCI_ADDR_IO | PCI_REG_REL_M); 3398 i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_avail, 3399 PCI_ADDR_MEM32 | PCI_REG_REL_M); 3400 i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_avail, 3401 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 3402 ASSERT(i == count); 3403 3404 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 3405 "available", (int *)sp, 3406 i * sizeof (struct pci_phys_spec) / sizeof (int)); 3407 kmem_free(sp, count * sizeof (*sp)); 3408 } 3409 3410 static void 3411 alloc_res_array(void) 3412 { 3413 static uint_t array_size = 0; 3414 uint_t old_size; 3415 void *old_res; 3416 3417 if (array_size > pci_boot_maxbus + 1) 3418 return; /* array is big enough */ 3419 3420 old_size = array_size; 3421 old_res = pci_bus_res; 3422 3423 if (array_size == 0) 3424 array_size = 16; /* start with a reasonable number */ 3425 3426 while (array_size <= pci_boot_maxbus + 1) 3427 array_size <<= 1; 3428 pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 3429 array_size * sizeof (struct pci_bus_resource), KM_SLEEP); 3430 3431 if (old_res) { /* copy content and free old array */ 3432 bcopy(old_res, pci_bus_res, 3433 old_size * sizeof (struct pci_bus_resource)); 3434 kmem_free(old_res, old_size * sizeof (struct pci_bus_resource)); 3435 } 3436 } 3437 3438 static void 3439 create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 3440 ushort_t deviceid) 3441 { 3442 static dev_info_t *ioapicsnode = NULL; 3443 static int numioapics = 0; 3444 dev_info_t *ioapic_node; 3445 uint64_t physaddr; 3446 uint32_t lobase, hibase = 0; 3447 3448 /* BAR 0 contains the IOAPIC's memory-mapped I/O address */ 3449 lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0); 3450 3451 /* We (and the rest of the world) only support memory-mapped IOAPICs */ 3452 if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM) 3453 return; 3454 3455 if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) 3456 hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4); 3457 3458 lobase &= PCI_BASE_M_ADDR_M; 3459 3460 physaddr = (((uint64_t)hibase) << 32) | lobase; 3461 3462 /* 3463 * Create a nexus node for all IOAPICs under the root node. 3464 */ 3465 if (ioapicsnode == NULL) { 3466 if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME, 3467 (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) { 3468 return; 3469 } 3470 (void) ndi_devi_online(ioapicsnode, 0); 3471 } 3472 3473 /* 3474 * Create a child node for this IOAPIC 3475 */ 3476 ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME, 3477 DEVI_SID_NODEID, numioapics++); 3478 if (ioapic_node == NULL) { 3479 return; 3480 } 3481 3482 /* Vendor and Device ID */ 3483 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 3484 IOAPICS_PROP_VENID, vendorid); 3485 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 3486 IOAPICS_PROP_DEVID, deviceid); 3487 3488 /* device_type */ 3489 (void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node, 3490 "device_type", IOAPICS_DEV_TYPE); 3491 3492 /* reg */ 3493 (void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node, 3494 "reg", physaddr); 3495 } 3496 3497 /* 3498 * NOTE: For PCIe slots, the name is generated from the slot number 3499 * information obtained from Slot Capabilities register. 3500 * For non-PCIe slots, it is generated based on the slot number 3501 * information in the PCI IRQ table. 3502 */ 3503 static void 3504 pciex_slot_names_prop(dev_info_t *dip, ushort_t slot_num) 3505 { 3506 char slotprop[256]; 3507 int len; 3508 3509 bzero(slotprop, sizeof (slotprop)); 3510 3511 /* set mask to 1 as there is only one slot (i.e dev 0) */ 3512 *(uint32_t *)slotprop = 1; 3513 len = 4; 3514 (void) snprintf(slotprop + len, sizeof (slotprop) - len, "pcie%d", 3515 slot_num); 3516 len += strlen(slotprop + len) + 1; 3517 len += len % 4; 3518 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "slot-names", 3519 (int *)slotprop, len / sizeof (int)); 3520 } 3521 3522 /* 3523 * Enable reporting of AER capability next pointer. 3524 * This needs to be done only for CK8-04 devices 3525 * by setting NV_XVR_VEND_CYA1 (offset 0xf40) bit 13 3526 * NOTE: BIOS is disabling this, it needs to be enabled temporarily 3527 * 3528 * This function is adapted from npe_ck804_fix_aer_ptr(), and is 3529 * called from pci_boot.c. 3530 */ 3531 static void 3532 ck804_fix_aer_ptr(dev_info_t *dip, pcie_req_id_t bdf) 3533 { 3534 dev_info_t *rcdip; 3535 ushort_t cya1; 3536 3537 rcdip = pcie_get_rc_dip(dip); 3538 ASSERT(rcdip != NULL); 3539 3540 if ((pci_cfgacc_get16(rcdip, bdf, PCI_CONF_VENID) == 3541 NVIDIA_VENDOR_ID) && 3542 (pci_cfgacc_get16(rcdip, bdf, PCI_CONF_DEVID) == 3543 NVIDIA_CK804_DEVICE_ID) && 3544 (pci_cfgacc_get8(rcdip, bdf, PCI_CONF_REVID) >= 3545 NVIDIA_CK804_AER_VALID_REVID)) { 3546 cya1 = pci_cfgacc_get16(rcdip, bdf, NVIDIA_CK804_VEND_CYA1_OFF); 3547 if (!(cya1 & ~NVIDIA_CK804_VEND_CYA1_ERPT_MASK)) 3548 (void) pci_cfgacc_put16(rcdip, bdf, 3549 NVIDIA_CK804_VEND_CYA1_OFF, 3550 cya1 | NVIDIA_CK804_VEND_CYA1_ERPT_VAL); 3551 } 3552 } 3553