xref: /illumos-gate/usr/src/uts/intel/io/pci/pci_boot.c (revision aedf2b3bb56b025fcaf87b49ec6c8aeea07f16d7)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #include <sys/types.h>
27 #include <sys/stat.h>
28 #include <sys/sysmacros.h>
29 #include <sys/sunndi.h>
30 #include <sys/pci.h>
31 #include <sys/pci_impl.h>
32 #include <sys/pci_cfgspace.h>
33 #include <sys/memlist.h>
34 #include <sys/bootconf.h>
35 #include <io/pci/mps_table.h>
36 #include <sys/pci_cfgspace.h>
37 #include <sys/pci_cfgspace_impl.h>
38 #include <sys/psw.h>
39 #include "../../../../common/pci/pci_strings.h"
40 #include <sys/apic.h>
41 #include <io/pciex/pcie_nvidia.h>
42 #include <sys/hotplug/pci/pciehpc_acpi.h>
43 #include <sys/acpi/acpi.h>
44 #include <sys/acpica.h>
45 #include <sys/intel_iommu.h>
46 #include <sys/iommulib.h>
47 #include <sys/devcache.h>
48 
49 #define	pci_getb	(*pci_getb_func)
50 #define	pci_getw	(*pci_getw_func)
51 #define	pci_getl	(*pci_getl_func)
52 #define	pci_putb	(*pci_putb_func)
53 #define	pci_putw	(*pci_putw_func)
54 #define	pci_putl	(*pci_putl_func)
55 #define	dcmn_err	if (pci_boot_debug) cmn_err
56 
57 #define	CONFIG_INFO	0
58 #define	CONFIG_UPDATE	1
59 #define	CONFIG_NEW	2
60 #define	CONFIG_FIX	3
61 #define	COMPAT_BUFSIZE	512
62 
63 #define	PPB_IO_ALIGNMENT	0x1000		/* 4K aligned */
64 #define	PPB_MEM_ALIGNMENT	0x100000	/* 1M aligned */
65 /* round down to nearest power of two */
66 #define	P2LE(align)					\
67 	{						\
68 		int i = 0;				\
69 		while (align >>= 1)			\
70 			i ++;				\
71 		align = 1 << i;				\
72 	}						\
73 
74 /* for is_vga and list_is_vga_only */
75 
76 enum io_mem {
77 	IO,
78 	MEM
79 };
80 
81 /* See AMD-8111 Datasheet Rev 3.03, Page 149: */
82 #define	LPC_IO_CONTROL_REG_1	0x40
83 #define	AMD8111_ENABLENMI	(uint8_t)0x80
84 #define	DEVID_AMD8111_LPC	0x7468
85 
86 struct pci_fixundo {
87 	uint8_t			bus;
88 	uint8_t			dev;
89 	uint8_t			fn;
90 	void			(*undofn)(uint8_t, uint8_t, uint8_t);
91 	struct pci_fixundo	*next;
92 };
93 
94 struct pci_devfunc {
95 	struct pci_devfunc *next;
96 	dev_info_t *dip;
97 	uchar_t dev;
98 	uchar_t func;
99 	boolean_t reprogram;	/* this device needs to be reprogrammed */
100 };
101 
102 extern int pseudo_isa;
103 extern int pci_bios_maxbus;
104 static uchar_t max_dev_pci = 32;	/* PCI standard */
105 int pci_boot_debug = 0;
106 extern struct memlist *find_bus_res(int, int);
107 static struct pci_fixundo *undolist = NULL;
108 static int num_root_bus = 0;	/* count of root buses */
109 extern volatile int acpi_resource_discovery;
110 
111 /*
112  * Module prototypes
113  */
114 static void enumerate_bus_devs(uchar_t bus, int config_op);
115 static void create_root_bus_dip(uchar_t bus);
116 static void process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t,
117     ushort_t, int);
118 static void add_compatible(dev_info_t *, ushort_t, ushort_t,
119     ushort_t, ushort_t, uchar_t, uint_t, int);
120 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int);
121 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int,
122     ushort_t);
123 static void add_model_prop(dev_info_t *, uint_t);
124 static void add_bus_range_prop(int);
125 static void add_bus_slot_names_prop(int);
126 static void add_ranges_prop(int, int);
127 static void add_bus_available_prop(int);
128 static int get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id);
129 static void fix_ppb_res(uchar_t, boolean_t);
130 static void alloc_res_array();
131 static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid,
132     ushort_t deviceid);
133 static void pciex_slot_names_prop(dev_info_t *, ushort_t);
134 static void populate_bus_res(uchar_t bus);
135 static void memlist_remove_list(struct memlist **list,
136     struct memlist *remove_list);
137 
138 static void pci_scan_bbn(void);
139 static int pci_unitaddr_cache_valid(void);
140 static int pci_bus_unitaddr(int);
141 static void pci_unitaddr_cache_create(void);
142 
143 static int pci_cache_unpack_nvlist(nvf_handle_t, nvlist_t *, char *);
144 static int pci_cache_pack_nvlist(nvf_handle_t, nvlist_t **);
145 static void pci_cache_free_list(nvf_handle_t);
146 
147 extern int pci_slot_names_prop(int, char *, int);
148 
149 /* set non-zero to force PCI peer-bus renumbering */
150 int pci_bus_always_renumber = 0;
151 
152 /*
153  * used to register ISA resource usage which must not be made
154  * "available" from other PCI node' resource maps
155  */
156 static struct {
157 	struct memlist *io_used;
158 	struct memlist *mem_used;
159 } isa_res;
160 
161 /*
162  * PCI unit-address cache management
163  */
164 static nvf_ops_t pci_unitaddr_cache_ops = {
165 	"/etc/devices/pci_unitaddr_persistent",	/* path to cache */
166 	pci_cache_unpack_nvlist,		/* read in nvlist form */
167 	pci_cache_pack_nvlist,			/* convert to nvlist form */
168 	pci_cache_free_list,			/* free data list */
169 	NULL					/* write complete callback */
170 };
171 
172 typedef struct {
173 	list_node_t	pua_nodes;
174 	int		pua_index;
175 	int		pua_addr;
176 } pua_node_t;
177 
178 nvf_handle_t	puafd_handle;
179 int		pua_cache_valid = 0;
180 
181 
182 /*ARGSUSED*/
183 static ACPI_STATUS
184 pci_process_acpi_device(ACPI_HANDLE hdl, UINT32 level, void *ctx, void **rv)
185 {
186 	ACPI_BUFFER	rb;
187 	ACPI_OBJECT	ro;
188 	ACPI_DEVICE_INFO *adi;
189 	int		busnum;
190 
191 	/*
192 	 * Use AcpiGetObjectInfo() to find the device _HID
193 	 * If not a PCI root-bus, ignore this device and continue
194 	 * the walk
195 	 */
196 
197 	rb.Length = ACPI_ALLOCATE_BUFFER;
198 	if (ACPI_FAILURE(AcpiGetObjectInfo(hdl, &rb)))
199 		return (AE_OK);
200 
201 	adi = rb.Pointer;
202 	if (!(adi->Valid & ACPI_VALID_HID)) {
203 		AcpiOsFree(adi);
204 		return (AE_OK);
205 	}
206 
207 	if (strncmp(adi->HardwareId.Value, PCI_ROOT_HID_STRING,
208 	    sizeof (PCI_ROOT_HID_STRING)) &&
209 	    strncmp(adi->HardwareId.Value, PCI_EXPRESS_ROOT_HID_STRING,
210 	    sizeof (PCI_EXPRESS_ROOT_HID_STRING))) {
211 		AcpiOsFree(adi);
212 		return (AE_OK);
213 	}
214 
215 	AcpiOsFree(adi);
216 
217 	/*
218 	 * XXX: ancient Big Bear broken _BBN will result in two
219 	 * bus 0 _BBNs being found, so we need to handle duplicate
220 	 * bus 0 gracefully.  However, broken _BBN does not
221 	 * hide a childless root-bridge so no need to work-around it
222 	 * here
223 	 */
224 	rb.Pointer = &ro;
225 	rb.Length = sizeof (ro);
226 	if (ACPI_SUCCESS(AcpiEvaluateObjectTyped(hdl, "_BBN",
227 	    NULL, &rb, ACPI_TYPE_INTEGER))) {
228 		busnum = ro.Integer.Value;
229 
230 		/*
231 		 * Ignore invalid _BBN return values here (rather
232 		 * than panic) and emit a warning; something else
233 		 * may suffer failure as a result of the broken BIOS.
234 		 */
235 		if ((busnum < 0) || (busnum > pci_bios_maxbus)) {
236 			cmn_err(CE_WARN,
237 			    "pci_process_acpi_device: invalid _BBN 0x%x\n",
238 			    busnum);
239 			return (AE_CTRL_DEPTH);
240 		}
241 
242 		/* PCI with valid _BBN */
243 		if (pci_bus_res[busnum].par_bus == (uchar_t)-1 &&
244 		    pci_bus_res[busnum].dip == NULL)
245 			create_root_bus_dip((uchar_t)busnum);
246 		return (AE_CTRL_DEPTH);
247 	}
248 
249 	/* PCI and no _BBN, continue walk */
250 	return (AE_OK);
251 }
252 
253 /*
254  * Scan the ACPI namespace for all top-level instances of _BBN
255  * in order to discover childless root-bridges (which enumeration
256  * may not find; root-bridges are inferred by the existence of
257  * children).  This scan should find all root-bridges that have
258  * been enumerated, and any childless root-bridges not enumerated.
259  * Root-bridge for bus 0 may not have a _BBN object.
260  */
261 static void
262 pci_scan_bbn()
263 {
264 	void *rv;
265 
266 	(void) AcpiGetDevices(NULL, pci_process_acpi_device, NULL, &rv);
267 }
268 
269 static void
270 pci_unitaddr_cache_init(void)
271 {
272 
273 	puafd_handle = nvf_register_file(&pci_unitaddr_cache_ops);
274 	ASSERT(puafd_handle);
275 
276 	list_create(nvf_list(puafd_handle), sizeof (pua_node_t),
277 	    offsetof(pua_node_t, pua_nodes));
278 
279 	rw_enter(nvf_lock(puafd_handle), RW_WRITER);
280 	(void) nvf_read_file(puafd_handle);
281 	rw_exit(nvf_lock(puafd_handle));
282 }
283 
284 /*
285  * Format of /etc/devices/pci_unitaddr_persistent:
286  *
287  * The persistent record of unit-address assignments contains
288  * a list of name/value pairs, where name is a string representation
289  * of the "index value" of the PCI root-bus and the value is
290  * the assigned unit-address.
291  *
292  * The "index value" is simply the zero-based index of the PCI
293  * root-buses ordered by physical bus number; first PCI bus is 0,
294  * second is 1, and so on.
295  */
296 
297 /*ARGSUSED*/
298 static int
299 pci_cache_unpack_nvlist(nvf_handle_t hdl, nvlist_t *nvl, char *name)
300 {
301 	long		index;
302 	int32_t		value;
303 	nvpair_t	*np;
304 	pua_node_t	*node;
305 
306 	np = NULL;
307 	while ((np = nvlist_next_nvpair(nvl, np)) != NULL) {
308 		/* name of nvpair is index value */
309 		if (ddi_strtol(nvpair_name(np), NULL, 10, &index) != 0)
310 			continue;
311 
312 		if (nvpair_value_int32(np, &value) != 0)
313 			continue;
314 
315 		node = kmem_zalloc(sizeof (pua_node_t), KM_SLEEP);
316 		node->pua_index = index;
317 		node->pua_addr = value;
318 		list_insert_tail(nvf_list(hdl), node);
319 	}
320 
321 	pua_cache_valid = 1;
322 	return (DDI_SUCCESS);
323 }
324 
325 static int
326 pci_cache_pack_nvlist(nvf_handle_t hdl, nvlist_t **ret_nvl)
327 {
328 	int		rval;
329 	nvlist_t	*nvl, *sub_nvl;
330 	list_t		*listp;
331 	pua_node_t	*pua;
332 	char		buf[13];
333 
334 	ASSERT(RW_WRITE_HELD(nvf_lock(hdl)));
335 
336 	rval = nvlist_alloc(&nvl, NV_UNIQUE_NAME, KM_SLEEP);
337 	if (rval != DDI_SUCCESS) {
338 		nvf_error("%s: nvlist alloc error %d\n",
339 		    nvf_cache_name(hdl), rval);
340 		return (DDI_FAILURE);
341 	}
342 
343 	sub_nvl = NULL;
344 	rval = nvlist_alloc(&sub_nvl, NV_UNIQUE_NAME, KM_SLEEP);
345 	if (rval != DDI_SUCCESS)
346 		goto error;
347 
348 	listp = nvf_list(hdl);
349 	for (pua = list_head(listp); pua != NULL;
350 	    pua = list_next(listp, pua)) {
351 		(void) snprintf(buf, sizeof (buf), "%d", pua->pua_index);
352 		rval = nvlist_add_int32(sub_nvl, buf, pua->pua_addr);
353 		if (rval != DDI_SUCCESS)
354 			goto error;
355 	}
356 
357 	rval = nvlist_add_nvlist(nvl, "table", sub_nvl);
358 	if (rval != DDI_SUCCESS)
359 		goto error;
360 	nvlist_free(sub_nvl);
361 
362 	*ret_nvl = nvl;
363 	return (DDI_SUCCESS);
364 
365 error:
366 	if (sub_nvl)
367 		nvlist_free(sub_nvl);
368 	ASSERT(nvl);
369 	nvlist_free(nvl);
370 	*ret_nvl = NULL;
371 	return (DDI_FAILURE);
372 }
373 
374 static void
375 pci_cache_free_list(nvf_handle_t hdl)
376 {
377 	list_t		*listp;
378 	pua_node_t	*pua;
379 
380 	ASSERT(RW_WRITE_HELD(nvf_lock(hdl)));
381 
382 	listp = nvf_list(hdl);
383 	for (pua = list_head(listp); pua != NULL;
384 	    pua = list_next(listp, pua)) {
385 		list_remove(listp, pua);
386 		kmem_free(pua, sizeof (pua_node_t));
387 	}
388 }
389 
390 
391 static int
392 pci_unitaddr_cache_valid(void)
393 {
394 
395 	/* read only, no need for rw lock */
396 	return (pua_cache_valid);
397 }
398 
399 
400 static int
401 pci_bus_unitaddr(int index)
402 {
403 	pua_node_t	*pua;
404 	list_t		*listp;
405 	int		addr;
406 
407 	rw_enter(nvf_lock(puafd_handle), RW_READER);
408 
409 	addr = -1;	/* default return if no match */
410 	listp = nvf_list(puafd_handle);
411 	for (pua = list_head(listp); pua != NULL;
412 	    pua = list_next(listp, pua)) {
413 		if (pua->pua_index == index) {
414 			addr = pua->pua_addr;
415 			break;
416 		}
417 	}
418 
419 	rw_exit(nvf_lock(puafd_handle));
420 	return (addr);
421 }
422 
423 static void
424 pci_unitaddr_cache_create(void)
425 {
426 	int		i, index;
427 	pua_node_t	*node;
428 	list_t		*listp;
429 
430 	rw_enter(nvf_lock(puafd_handle), RW_WRITER);
431 
432 	index = 0;
433 	listp = nvf_list(puafd_handle);
434 	for (i = 0; i <= pci_bios_maxbus; i++) {
435 		/* skip non-root (peer) PCI busses */
436 		if ((pci_bus_res[i].par_bus != (uchar_t)-1) ||
437 		    (pci_bus_res[i].dip == NULL))
438 			continue;
439 		node = kmem_zalloc(sizeof (pua_node_t), KM_SLEEP);
440 		node->pua_index = index++;
441 		node->pua_addr = pci_bus_res[i].root_addr;
442 		list_insert_tail(listp, node);
443 	}
444 
445 	(void) nvf_mark_dirty(puafd_handle);
446 	rw_exit(nvf_lock(puafd_handle));
447 	nvf_wake_daemon();
448 }
449 
450 
451 /*
452  * Enumerate all PCI devices
453  */
454 void
455 pci_setup_tree(void)
456 {
457 	uint_t i, root_bus_addr = 0;
458 
459 	alloc_res_array();
460 	for (i = 0; i <= pci_bios_maxbus; i++) {
461 		pci_bus_res[i].par_bus = (uchar_t)-1;
462 		pci_bus_res[i].root_addr = (uchar_t)-1;
463 		pci_bus_res[i].sub_bus = i;
464 	}
465 
466 	pci_bus_res[0].root_addr = root_bus_addr++;
467 	create_root_bus_dip(0);
468 	enumerate_bus_devs(0, CONFIG_INFO);
469 
470 	/*
471 	 * Now enumerate peer busses
472 	 *
473 	 * We loop till pci_bios_maxbus. On most systems, there is
474 	 * one more bus at the high end, which implements the ISA
475 	 * compatibility bus. We don't care about that.
476 	 *
477 	 * Note: In the old (bootconf) enumeration, the peer bus
478 	 *	address did not use the bus number, and there were
479 	 *	too many peer busses created. The root_bus_addr is
480 	 *	used to maintain the old peer bus address assignment.
481 	 *	However, we stop enumerating phantom peers with no
482 	 *	device below.
483 	 */
484 	for (i = 1; i <= pci_bios_maxbus; i++) {
485 		if (pci_bus_res[i].dip == NULL) {
486 			pci_bus_res[i].root_addr = root_bus_addr++;
487 		}
488 		enumerate_bus_devs(i, CONFIG_INFO);
489 
490 		/* add slot-names property for named pci hot-plug slots */
491 		add_bus_slot_names_prop(i);
492 	}
493 
494 }
495 
496 /*
497  * >0 = present, 0 = not present, <0 = error
498  */
499 static int
500 pci_bbn_present(int bus)
501 {
502 	ACPI_HANDLE	hdl;
503 	int	rv;
504 
505 	/* no dip means no _BBN */
506 	if (pci_bus_res[bus].dip == NULL)
507 		return (0);
508 
509 	rv = -1;	/* default return value in case of error below */
510 	if (ACPI_SUCCESS(acpica_get_handle(pci_bus_res[bus].dip, &hdl))) {
511 		switch (AcpiEvaluateObject(hdl, "_BBN", NULL, NULL)) {
512 		case AE_OK:
513 			rv = 1;
514 			break;
515 		case AE_NOT_FOUND:
516 			rv = 0;
517 			break;
518 		default:
519 			break;
520 		}
521 	}
522 
523 	return (rv);
524 }
525 
526 /*
527  * Return non-zero if any PCI bus in the system has an associated
528  * _BBN object, 0 otherwise.
529  */
530 static int
531 pci_roots_have_bbn(void)
532 {
533 	int	i;
534 
535 	/*
536 	 * Scan the PCI busses and look for at least 1 _BBN
537 	 */
538 	for (i = 0; i <= pci_bios_maxbus; i++) {
539 		/* skip non-root (peer) PCI busses */
540 		if (pci_bus_res[i].par_bus != (uchar_t)-1)
541 			continue;
542 
543 		if (pci_bbn_present(i) > 0)
544 			return (1);
545 	}
546 	return (0);
547 
548 }
549 
550 /*
551  * return non-zero if the machine is one on which we renumber
552  * the internal pci unit-addresses
553  */
554 static int
555 pci_bus_renumber()
556 {
557 	ACPI_TABLE_HEADER *fadt;
558 
559 	if (pci_bus_always_renumber)
560 		return (1);
561 
562 	/* get the FADT */
563 	if (AcpiGetTable(ACPI_SIG_FADT, 1, (ACPI_TABLE_HEADER **)&fadt) !=
564 	    AE_OK)
565 		return (0);
566 
567 	/* compare OEM Table ID to "SUNm31" */
568 	if (strncmp("SUNm31", fadt->OemId, 6))
569 		return (0);
570 	else
571 		return (1);
572 }
573 
574 /*
575  * Initial enumeration of the physical PCI bus hierarchy can
576  * leave 'gaps' in the order of peer PCI bus unit-addresses.
577  * Systems with more than one peer PCI bus *must* have an ACPI
578  * _BBN object associated with each peer bus; use the presence
579  * of this object to remove gaps in the numbering of the peer
580  * PCI bus unit-addresses - only peer busses with an associated
581  * _BBN are counted.
582  */
583 static void
584 pci_renumber_root_busses(void)
585 {
586 	int pci_regs[] = {0, 0, 0};
587 	int	i, root_addr = 0;
588 
589 	/*
590 	 * Currently, we only enable the re-numbering on specific
591 	 * Sun machines; this is a work-around for the more complicated
592 	 * issue of upgrade changing physical device paths
593 	 */
594 	if (!pci_bus_renumber())
595 		return;
596 
597 	/*
598 	 * If we find no _BBN objects at all, we either don't need
599 	 * to do anything or can't do anything anyway
600 	 */
601 	if (!pci_roots_have_bbn())
602 		return;
603 
604 	for (i = 0; i <= pci_bios_maxbus; i++) {
605 		/* skip non-root (peer) PCI busses */
606 		if (pci_bus_res[i].par_bus != (uchar_t)-1)
607 			continue;
608 
609 		if (pci_bbn_present(i) < 1) {
610 			pci_bus_res[i].root_addr = (uchar_t)-1;
611 			continue;
612 		}
613 
614 		ASSERT(pci_bus_res[i].dip != NULL);
615 		if (pci_bus_res[i].root_addr != root_addr) {
616 			/* update reg property for node */
617 			pci_bus_res[i].root_addr = root_addr;
618 			pci_regs[0] = pci_bus_res[i].root_addr;
619 			(void) ndi_prop_update_int_array(DDI_DEV_T_NONE,
620 			    pci_bus_res[i].dip, "reg", (int *)pci_regs, 3);
621 		}
622 		root_addr++;
623 	}
624 }
625 
626 void
627 pci_register_isa_resources(int type, uint32_t base, uint32_t size)
628 {
629 	(void) memlist_insert(
630 	    (type == 1) ?  &isa_res.io_used : &isa_res.mem_used,
631 	    base, size);
632 }
633 
634 /*
635  * Remove the resources which are already used by devices under a subtractive
636  * bridge from the bus's resources lists, because they're not available, and
637  * shouldn't be allocated to other buses.  This is necessary because tracking
638  * resources for subtractive bridges is not complete.  (Subtractive bridges only
639  * track some of their claimed resources, not "the rest of the address space" as
640  * they should, so that allocation to peer non-subtractive PPBs is easier.  We
641  * need a fully-capable global resource allocator).
642  */
643 static void
644 remove_subtractive_res()
645 {
646 	int i, j;
647 	struct memlist *list;
648 
649 	for (i = 0; i <= pci_bios_maxbus; i++) {
650 		if (pci_bus_res[i].subtractive) {
651 			/* remove used io ports */
652 			list = pci_bus_res[i].io_used;
653 			while (list) {
654 				for (j = 0; j <= pci_bios_maxbus; j++)
655 					(void) memlist_remove(
656 					    &pci_bus_res[j].io_avail,
657 					    list->address, list->size);
658 				list = list->next;
659 			}
660 			/* remove used mem resource */
661 			list = pci_bus_res[i].mem_used;
662 			while (list) {
663 				for (j = 0; j <= pci_bios_maxbus; j++) {
664 					(void) memlist_remove(
665 					    &pci_bus_res[j].mem_avail,
666 					    list->address, list->size);
667 					(void) memlist_remove(
668 					    &pci_bus_res[j].pmem_avail,
669 					    list->address, list->size);
670 				}
671 				list = list->next;
672 			}
673 			/* remove used prefetchable mem resource */
674 			list = pci_bus_res[i].pmem_used;
675 			while (list) {
676 				for (j = 0; j <= pci_bios_maxbus; j++) {
677 					(void) memlist_remove(
678 					    &pci_bus_res[j].pmem_avail,
679 					    list->address, list->size);
680 					(void) memlist_remove(
681 					    &pci_bus_res[j].mem_avail,
682 					    list->address, list->size);
683 				}
684 				list = list->next;
685 			}
686 		}
687 	}
688 }
689 
690 /*
691  * Set up (or complete the setup of) the bus_avail resource list
692  */
693 static void
694 setup_bus_res(int bus)
695 {
696 	uchar_t par_bus;
697 
698 	if (pci_bus_res[bus].dip == NULL)	/* unused bus */
699 		return;
700 
701 	/*
702 	 * Set up bus_avail if not already filled in by populate_bus_res()
703 	 */
704 	if (pci_bus_res[bus].bus_avail == NULL) {
705 		ASSERT(pci_bus_res[bus].sub_bus >= bus);
706 		memlist_insert(&pci_bus_res[bus].bus_avail, bus,
707 		    pci_bus_res[bus].sub_bus - bus + 1);
708 	}
709 
710 	ASSERT(pci_bus_res[bus].bus_avail != NULL);
711 
712 	/*
713 	 * Remove resources from parent bus node if this is not a
714 	 * root bus.
715 	 */
716 	par_bus = pci_bus_res[bus].par_bus;
717 	if (par_bus != (uchar_t)-1) {
718 		ASSERT(pci_bus_res[par_bus].bus_avail != NULL);
719 		memlist_remove_list(&pci_bus_res[par_bus].bus_avail,
720 		    pci_bus_res[bus].bus_avail);
721 	}
722 
723 	/* remove self from bus_avail */;
724 	(void) memlist_remove(&pci_bus_res[bus].bus_avail, bus, 1);
725 }
726 
727 static uint64_t
728 get_parbus_io_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align)
729 {
730 	uint64_t addr = 0;
731 	uchar_t res_bus;
732 
733 	/*
734 	 * Skip root(peer) buses in multiple-root-bus systems when
735 	 * ACPI resource discovery was not successfully done.
736 	 */
737 	if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) &&
738 	    (num_root_bus > 1) && (acpi_resource_discovery <= 0))
739 		return (0);
740 
741 	res_bus = parbus;
742 	while (pci_bus_res[res_bus].subtractive) {
743 		if (pci_bus_res[res_bus].io_avail)
744 			break;
745 		res_bus = pci_bus_res[res_bus].par_bus;
746 		if (res_bus == (uchar_t)-1)
747 			break; /* root bus already */
748 	}
749 
750 	if (pci_bus_res[res_bus].io_avail) {
751 		addr = memlist_find(&pci_bus_res[res_bus].io_avail,
752 		    size, align);
753 		if (addr) {
754 			memlist_insert(&pci_bus_res[res_bus].io_used,
755 			    addr, size);
756 
757 			/* free the old resource */
758 			memlist_free_all(&pci_bus_res[bus].io_avail);
759 			memlist_free_all(&pci_bus_res[bus].io_used);
760 
761 			/* add the new resource */
762 			memlist_insert(&pci_bus_res[bus].io_avail, addr, size);
763 		}
764 	}
765 
766 	return (addr);
767 }
768 
769 static uint64_t
770 get_parbus_mem_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align)
771 {
772 	uint64_t addr = 0;
773 	uchar_t res_bus;
774 
775 	/*
776 	 * Skip root(peer) buses in multiple-root-bus systems when
777 	 * ACPI resource discovery was not successfully done.
778 	 */
779 	if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) &&
780 	    (num_root_bus > 1) && (acpi_resource_discovery <= 0))
781 		return (0);
782 
783 	res_bus = parbus;
784 	while (pci_bus_res[res_bus].subtractive) {
785 		if (pci_bus_res[res_bus].mem_avail)
786 			break;
787 		res_bus = pci_bus_res[res_bus].par_bus;
788 		if (res_bus == (uchar_t)-1)
789 			break; /* root bus already */
790 	}
791 
792 	if (pci_bus_res[res_bus].mem_avail) {
793 		addr = memlist_find(&pci_bus_res[res_bus].mem_avail,
794 		    size, align);
795 		if (addr) {
796 			memlist_insert(&pci_bus_res[res_bus].mem_used,
797 			    addr, size);
798 			(void) memlist_remove(&pci_bus_res[res_bus].pmem_avail,
799 			    addr, size);
800 
801 			/* free the old resource */
802 			memlist_free_all(&pci_bus_res[bus].mem_avail);
803 			memlist_free_all(&pci_bus_res[bus].mem_used);
804 
805 			/* add the new resource */
806 			memlist_insert(&pci_bus_res[bus].mem_avail, addr, size);
807 		}
808 	}
809 
810 	return (addr);
811 }
812 
813 /*
814  * given a cap_id, return its cap_id location in config space
815  */
816 static int
817 get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id)
818 {
819 	uint8_t curcap, cap_id_loc;
820 	uint16_t status;
821 	int location = -1;
822 
823 	/*
824 	 * Need to check the Status register for ECP support first.
825 	 * Also please note that for type 1 devices, the
826 	 * offset could change. Should support type 1 next.
827 	 */
828 	status = pci_getw(bus, dev, func, PCI_CONF_STAT);
829 	if (!(status & PCI_STAT_CAP)) {
830 		return (-1);
831 	}
832 	cap_id_loc = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR);
833 
834 	/* Walk the list of capabilities */
835 	while (cap_id_loc && cap_id_loc != (uint8_t)-1) {
836 		curcap = pci_getb(bus, dev, func, cap_id_loc);
837 
838 		if (curcap == cap_id) {
839 			location = cap_id_loc;
840 			break;
841 		}
842 		cap_id_loc = pci_getb(bus, dev, func, cap_id_loc + 1);
843 	}
844 	return (location);
845 }
846 
847 /*
848  * Does this resource element live in the legacy VGA range?
849  */
850 
851 int
852 is_vga(struct memlist *elem, enum io_mem io)
853 {
854 
855 	if (io == IO) {
856 		if ((elem->address == 0x3b0 && elem->size == 0xc) ||
857 		    (elem->address == 0x3c0 && elem->size == 0x20))
858 			return (1);
859 	} else {
860 		if (elem->address == 0xa0000 && elem->size == 0x20000)
861 			return (1);
862 	}
863 	return (0);
864 }
865 
866 /*
867  * Does this entire resource list consist only of legacy VGA resources?
868  */
869 
870 int
871 list_is_vga_only(struct memlist *l, enum io_mem io)
872 {
873 	do {
874 		if (!is_vga(l, io))
875 			return (0);
876 	} while ((l = l->next) != NULL);
877 	return (1);
878 }
879 
880 /*
881  * Assign valid resources to unconfigured pci(e) bridges. We are trying
882  * to reprogram the bridge when its
883  * 		i)   SECBUS == SUBBUS	||
884  * 		ii)  IOBASE > IOLIM	||
885  * 		iii) MEMBASE > MEMLIM
886  * This must be done after one full pass through the PCI tree to collect
887  * all BIOS-configured resources, so that we know what resources are
888  * free and available to assign to the unconfigured PPBs.
889  */
890 static void
891 fix_ppb_res(uchar_t secbus, boolean_t prog_sub)
892 {
893 	uchar_t bus, dev, func;
894 	uchar_t parbus, subbus;
895 	uint_t io_base, io_limit, mem_base, mem_limit;
896 	uint_t io_size, mem_size, io_align, mem_align;
897 	uint64_t addr = 0;
898 	int *regp = NULL;
899 	uint_t reglen;
900 	int rv, cap_ptr, physhi;
901 	dev_info_t *dip;
902 	uint16_t cmd_reg;
903 	struct memlist *list, *scratch_list;
904 
905 	/* skip root (peer) PCI busses */
906 	if (pci_bus_res[secbus].par_bus == (uchar_t)-1)
907 		return;
908 
909 	/* skip subtractive PPB when prog_sub is not TRUE */
910 	if (pci_bus_res[secbus].subtractive && !prog_sub)
911 		return;
912 
913 	/* some entries may be empty due to discontiguous bus numbering */
914 	dip = pci_bus_res[secbus].dip;
915 	if (dip == NULL)
916 		return;
917 
918 	rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
919 	    "reg", &regp, &reglen);
920 	if (rv != DDI_PROP_SUCCESS || reglen == 0)
921 		return;
922 	physhi = regp[0];
923 	ddi_prop_free(regp);
924 
925 	func = (uchar_t)PCI_REG_FUNC_G(physhi);
926 	dev = (uchar_t)PCI_REG_DEV_G(physhi);
927 	bus = (uchar_t)PCI_REG_BUS_G(physhi);
928 
929 	/*
930 	 * If pcie bridge, check to see if link is enabled
931 	 */
932 	cap_ptr = get_pci_cap(bus, dev, func, PCI_CAP_ID_PCI_E);
933 	if (cap_ptr != -1) {
934 		cmd_reg = pci_getw(bus, dev, func,
935 		    (uint16_t)cap_ptr + PCIE_LINKCTL);
936 		if (cmd_reg & PCIE_LINKCTL_LINK_DISABLE) {
937 			dcmn_err(CE_NOTE,
938 			    "!fix_ppb_res: ppb[%x/%x/%x] link is disabled.\n",
939 			    bus, dev, func);
940 			return;
941 		}
942 	}
943 
944 	subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
945 	parbus = pci_bus_res[secbus].par_bus;
946 	ASSERT(parbus == bus);
947 	cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM);
948 
949 	/*
950 	 * If we have a Cardbus bridge, but no bus space
951 	 */
952 	if (pci_bus_res[secbus].num_cbb != 0 &&
953 	    pci_bus_res[secbus].bus_avail == NULL) {
954 		uchar_t range;
955 
956 		/* normally there are 2 buses under a cardbus bridge */
957 		range = pci_bus_res[secbus].num_cbb * 2;
958 
959 		/*
960 		 * Try to find and allocate a bus-range starting at subbus+1
961 		 * from the parent of the PPB.
962 		 */
963 		for (; range != 0; range--) {
964 			if (memlist_find_with_startaddr(
965 			    &pci_bus_res[parbus].bus_avail,
966 			    subbus + 1, range, 1) != NULL)
967 				break; /* find bus range resource at parent */
968 		}
969 		if (range != 0) {
970 			memlist_insert(&pci_bus_res[secbus].bus_avail,
971 			    subbus + 1, range);
972 			subbus = subbus + range;
973 			pci_bus_res[secbus].sub_bus = subbus;
974 			pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus);
975 			add_bus_range_prop(secbus);
976 
977 			cmn_err(CE_NOTE, "!reprogram bus-range on ppb"
978 			    "[%x/%x/%x]: %x ~ %x\n", bus, dev, func,
979 			    secbus, subbus);
980 		}
981 	}
982 
983 	/*
984 	 * Calculate required IO size and alignment
985 	 * If bus io_size is zero, we are going to assign 512 bytes per bus,
986 	 * otherwise, we'll choose the maximum value of such calculation and
987 	 * bus io_size. The size needs to be 4K aligned.
988 	 *
989 	 * We calculate alignment as the largest power of two less than the
990 	 * the sum of all children's IO size requirements, because this will
991 	 * align to the size of the largest child request within that size
992 	 * (which is always a power of two).
993 	 */
994 	io_size = (subbus - secbus + 1) * 0x200;
995 	if (io_size <  pci_bus_res[secbus].io_size)
996 		io_size = pci_bus_res[secbus].io_size;
997 	io_size = P2ROUNDUP(io_size, PPB_IO_ALIGNMENT);
998 	io_align = io_size;
999 	P2LE(io_align);
1000 
1001 	/*
1002 	 * Calculate required MEM size and alignment
1003 	 * If bus mem_size is zero, we are going to assign 1M bytes per bus,
1004 	 * otherwise, we'll choose the maximum value of such calculation and
1005 	 * bus mem_size. The size needs to be 1M aligned.
1006 	 *
1007 	 * For the alignment, refer to the I/O comment above.
1008 	 */
1009 	mem_size = (subbus - secbus + 1) * PPB_MEM_ALIGNMENT;
1010 	if (mem_size < pci_bus_res[secbus].mem_size) {
1011 		mem_size = pci_bus_res[secbus].mem_size;
1012 		mem_size = P2ROUNDUP(mem_size, PPB_MEM_ALIGNMENT);
1013 	}
1014 	mem_align = mem_size;
1015 	P2LE(mem_align);
1016 
1017 	/* Subtractive bridge */
1018 	if (pci_bus_res[secbus].subtractive && prog_sub) {
1019 		/*
1020 		 * We program an arbitrary amount of I/O and memory resource
1021 		 * for the subtractive bridge so that child dynamic-resource-
1022 		 * allocating devices (such as Cardbus bridges) have a chance
1023 		 * of success.  Until we have full-tree resource rebalancing,
1024 		 * dynamic resource allocation (thru busra) only looks at the
1025 		 * parent bridge, so all PPBs must have some allocatable
1026 		 * resource.  For non-subtractive bridges, the resources come
1027 		 * from the base/limit register "windows", but subtractive
1028 		 * bridges often don't program those (since they don't need to).
1029 		 * If we put all the remaining resources on the subtractive
1030 		 * bridge, then peer non-subtractive bridges can't allocate
1031 		 * more space (even though this is probably most correct).
1032 		 * If we put the resources only on the parent, then allocations
1033 		 * from children of subtractive bridges will fail without
1034 		 * special-case code for bypassing the subtractive bridge.
1035 		 * This solution is the middle-ground temporary solution until
1036 		 * we have fully-capable resource allocation.
1037 		 */
1038 
1039 		/*
1040 		 * Add an arbitrary I/O resource to the subtractive PPB
1041 		 */
1042 		if (pci_bus_res[secbus].io_avail == NULL) {
1043 			addr = get_parbus_io_res(parbus, secbus, io_size,
1044 			    io_align);
1045 			if (addr) {
1046 				add_ranges_prop(secbus, 1);
1047 				pci_bus_res[secbus].io_reprogram =
1048 				    pci_bus_res[parbus].io_reprogram;
1049 
1050 				cmn_err(CE_NOTE, "!add io-range on subtractive"
1051 				    " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
1052 				    bus, dev, func, (uint32_t)addr,
1053 				    (uint32_t)addr + io_size - 1);
1054 			}
1055 		}
1056 		/*
1057 		 * Add an arbitrary memory resource to the subtractive PPB
1058 		 */
1059 		if (pci_bus_res[secbus].mem_avail == NULL) {
1060 			addr = get_parbus_mem_res(parbus, secbus, mem_size,
1061 			    mem_align);
1062 			if (addr) {
1063 				add_ranges_prop(secbus, 1);
1064 				pci_bus_res[secbus].mem_reprogram =
1065 				    pci_bus_res[parbus].mem_reprogram;
1066 
1067 				cmn_err(CE_NOTE, "!add mem-range on "
1068 				    "subtractive ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
1069 				    bus, dev, func, (uint32_t)addr,
1070 				    (uint32_t)addr + mem_size - 1);
1071 			}
1072 		}
1073 
1074 		goto cmd_enable;
1075 	}
1076 
1077 	/*
1078 	 * Check to see if we need to reprogram I/O space, either because the
1079 	 * parent bus needed reprogramming and so do we, or because I/O space is
1080 	 * disabled in base/limit or command register.
1081 	 */
1082 	io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW);
1083 	io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW);
1084 	io_base = (io_base & 0xf0) << 8;
1085 	io_limit = ((io_limit & 0xf0) << 8) | 0xfff;
1086 
1087 	/* Form list of all resources passed (avail + used) */
1088 	scratch_list = memlist_dup(pci_bus_res[secbus].io_avail);
1089 	memlist_merge(&pci_bus_res[secbus].io_used, &scratch_list);
1090 
1091 	if ((pci_bus_res[parbus].io_reprogram ||
1092 	    (io_base > io_limit) ||
1093 	    (!(cmd_reg & PCI_COMM_IO))) &&
1094 	    !list_is_vga_only(scratch_list, IO)) {
1095 		if (pci_bus_res[secbus].io_used) {
1096 			memlist_subsume(&pci_bus_res[secbus].io_used,
1097 			    &pci_bus_res[secbus].io_avail);
1098 		}
1099 		if (pci_bus_res[secbus].io_avail &&
1100 		    (!pci_bus_res[parbus].io_reprogram) &&
1101 		    (!pci_bus_res[parbus].subtractive)) {
1102 			/* rechoose old io ports info */
1103 			list = pci_bus_res[secbus].io_avail;
1104 			io_base = 0;
1105 			do {
1106 				if (is_vga(list, IO))
1107 					continue;
1108 				if (!io_base) {
1109 					io_base = (uint_t)list->address;
1110 					io_limit = (uint_t)
1111 					    list->address + list->size - 1;
1112 					io_base =
1113 					    P2ALIGN(io_base, PPB_IO_ALIGNMENT);
1114 				} else {
1115 					if (list->address + list->size >
1116 					    io_limit) {
1117 						io_limit = (uint_t)
1118 						    (list->address +
1119 						    list->size - 1);
1120 					}
1121 				}
1122 			} while ((list = list->next) != NULL);
1123 			/* 4K aligned */
1124 			io_limit = P2ROUNDUP(io_limit, PPB_IO_ALIGNMENT) - 1;
1125 			io_size = io_limit - io_base + 1;
1126 			ASSERT(io_base <= io_limit);
1127 			memlist_free_all(&pci_bus_res[secbus].io_avail);
1128 			memlist_insert(&pci_bus_res[secbus].io_avail,
1129 			    io_base, io_size);
1130 			memlist_insert(&pci_bus_res[parbus].io_used,
1131 			    io_base, io_size);
1132 			(void) memlist_remove(&pci_bus_res[parbus].io_avail,
1133 			    io_base, io_size);
1134 			pci_bus_res[secbus].io_reprogram = B_TRUE;
1135 		} else {
1136 			/* get new io ports from parent bus */
1137 			addr = get_parbus_io_res(parbus, secbus, io_size,
1138 			    io_align);
1139 			if (addr) {
1140 				io_base = addr;
1141 				io_limit = addr + io_size - 1;
1142 				pci_bus_res[secbus].io_reprogram = B_TRUE;
1143 			}
1144 		}
1145 		if (pci_bus_res[secbus].io_reprogram) {
1146 			/* reprogram PPB regs */
1147 			pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW,
1148 			    (uchar_t)((io_base>>8) & 0xf0));
1149 			pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW,
1150 			    (uchar_t)((io_limit>>8) & 0xf0));
1151 			pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0);
1152 			pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0);
1153 			add_ranges_prop(secbus, 1);
1154 
1155 			cmn_err(CE_NOTE, "!reprogram io-range on"
1156 			    " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
1157 			    bus, dev, func, io_base, io_limit);
1158 		}
1159 	}
1160 	memlist_free_all(&scratch_list);
1161 
1162 	/*
1163 	 * Check memory space as we did I/O space.
1164 	 */
1165 	mem_base = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE);
1166 	mem_base = (mem_base & 0xfff0) << 16;
1167 	mem_limit = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT);
1168 	mem_limit = ((mem_limit & 0xfff0) << 16) | 0xfffff;
1169 
1170 	scratch_list = memlist_dup(pci_bus_res[secbus].mem_avail);
1171 	memlist_merge(&pci_bus_res[secbus].mem_used, &scratch_list);
1172 
1173 	if ((pci_bus_res[parbus].mem_reprogram ||
1174 	    (mem_base > mem_limit) ||
1175 	    (!(cmd_reg & PCI_COMM_MAE))) &&
1176 	    !list_is_vga_only(scratch_list, MEM)) {
1177 		if (pci_bus_res[secbus].mem_used) {
1178 			memlist_subsume(&pci_bus_res[secbus].mem_used,
1179 			    &pci_bus_res[secbus].mem_avail);
1180 		}
1181 		if (pci_bus_res[secbus].mem_avail &&
1182 		    (!pci_bus_res[parbus].mem_reprogram) &&
1183 		    (!pci_bus_res[parbus].subtractive)) {
1184 			/* rechoose old mem resource */
1185 			list = pci_bus_res[secbus].mem_avail;
1186 			mem_base = 0;
1187 			do {
1188 				if (is_vga(list, MEM))
1189 					continue;
1190 				if (mem_base == 0) {
1191 					mem_base = (uint_t)list->address;
1192 					mem_base = P2ALIGN(mem_base,
1193 					    PPB_MEM_ALIGNMENT);
1194 					mem_limit = (uint_t)
1195 					    (list->address + list->size - 1);
1196 				} else {
1197 					if ((list->address + list->size) >
1198 					    mem_limit) {
1199 						mem_limit = (uint_t)
1200 						    (list->address +
1201 						    list->size - 1);
1202 					}
1203 				}
1204 			} while ((list = list->next) != NULL);
1205 			mem_limit = P2ROUNDUP(mem_limit, PPB_MEM_ALIGNMENT) - 1;
1206 			mem_size = mem_limit + 1 - mem_base;
1207 			ASSERT(mem_base <= mem_limit);
1208 			memlist_free_all(&pci_bus_res[secbus].mem_avail);
1209 			memlist_insert(&pci_bus_res[secbus].mem_avail,
1210 			    mem_base, mem_size);
1211 			memlist_insert(&pci_bus_res[parbus].mem_used,
1212 			    mem_base, mem_size);
1213 			(void) memlist_remove(&pci_bus_res[parbus].mem_avail,
1214 			    mem_base, mem_size);
1215 			pci_bus_res[secbus].mem_reprogram = B_TRUE;
1216 		} else {
1217 			/* get new mem resource from parent bus */
1218 			addr = get_parbus_mem_res(parbus, secbus, mem_size,
1219 			    mem_align);
1220 			if (addr) {
1221 				mem_base = addr;
1222 				mem_limit = addr + mem_size - 1;
1223 				pci_bus_res[secbus].mem_reprogram = B_TRUE;
1224 			}
1225 		}
1226 
1227 		if (pci_bus_res[secbus].mem_reprogram) {
1228 			/* reprogram PPB MEM regs */
1229 			pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE,
1230 			    (uint16_t)((mem_base>>16) & 0xfff0));
1231 			pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT,
1232 			    (uint16_t)((mem_limit>>16) & 0xfff0));
1233 			/*
1234 			 * Disable PMEM window by setting base > limit.
1235 			 * We currently don't reprogram the PMEM like we've
1236 			 * done for I/O and MEM. (Devices that support prefetch
1237 			 * can use non-prefetch MEM.) Anyway, if the MEM access
1238 			 * bit is initially disabled by BIOS, we disable the
1239 			 * PMEM window manually by setting PMEM base > PMEM
1240 			 * limit here, in case there are incorrect values in
1241 			 * them from BIOS, so that we won't get in trouble once
1242 			 * the MEM access bit is enabled at the end of this
1243 			 * function.
1244 			 */
1245 			if (!(cmd_reg & PCI_COMM_MAE)) {
1246 				pci_putw(bus, dev, func, PCI_BCNF_PF_BASE_LOW,
1247 				    0xfff0);
1248 				pci_putw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW,
1249 				    0x0);
1250 				pci_putl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH,
1251 				    0xffffffff);
1252 				pci_putl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH,
1253 				    0x0);
1254 			}
1255 
1256 			add_ranges_prop(secbus, 1);
1257 
1258 			cmn_err(CE_NOTE, "!reprogram mem-range on"
1259 			    " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
1260 			    bus, dev, func, mem_base, mem_limit);
1261 		}
1262 	}
1263 	memlist_free_all(&scratch_list);
1264 
1265 cmd_enable:
1266 	if (pci_bus_res[secbus].io_avail)
1267 		cmd_reg |= PCI_COMM_IO | PCI_COMM_ME;
1268 	if (pci_bus_res[secbus].mem_avail)
1269 		cmd_reg |= PCI_COMM_MAE | PCI_COMM_ME;
1270 	pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg);
1271 }
1272 
1273 void
1274 pci_reprogram(void)
1275 {
1276 	int i, pci_reconfig = 1;
1277 	char *onoff;
1278 	int bus;
1279 
1280 	/*
1281 	 * Scan ACPI namespace for _BBN objects, make sure that
1282 	 * childless root-bridges appear in devinfo tree
1283 	 */
1284 	pci_scan_bbn();
1285 	pci_unitaddr_cache_init();
1286 
1287 	/*
1288 	 * Fix-up unit-address assignments if cache is available
1289 	 */
1290 	if (pci_unitaddr_cache_valid()) {
1291 		int pci_regs[] = {0, 0, 0};
1292 		int	new_addr;
1293 		int	index = 0;
1294 
1295 		for (bus = 0; bus <= pci_bios_maxbus; bus++) {
1296 			/* skip non-root (peer) PCI busses */
1297 			if ((pci_bus_res[bus].par_bus != (uchar_t)-1) ||
1298 			    (pci_bus_res[bus].dip == NULL))
1299 				continue;
1300 
1301 			new_addr = pci_bus_unitaddr(index);
1302 			if (pci_bus_res[bus].root_addr != new_addr) {
1303 				/* update reg property for node */
1304 				pci_regs[0] = pci_bus_res[bus].root_addr =
1305 				    new_addr;
1306 				(void) ndi_prop_update_int_array(
1307 				    DDI_DEV_T_NONE, pci_bus_res[bus].dip,
1308 				    "reg", (int *)pci_regs, 3);
1309 			}
1310 			index++;
1311 		}
1312 	} else {
1313 		/* perform legacy processing */
1314 		pci_renumber_root_busses();
1315 		pci_unitaddr_cache_create();
1316 	}
1317 
1318 	/*
1319 	 * Do root-bus resource discovery
1320 	 */
1321 	for (bus = 0; bus <= pci_bios_maxbus; bus++) {
1322 		/* skip non-root (peer) PCI busses */
1323 		if (pci_bus_res[bus].par_bus != (uchar_t)-1)
1324 			continue;
1325 
1326 		/*
1327 		 * 1. find resources associated with this root bus
1328 		 */
1329 		populate_bus_res(bus);
1330 
1331 
1332 		/*
1333 		 * 2. Remove used PCI and ISA resources from bus resource map
1334 		 */
1335 
1336 		memlist_remove_list(&pci_bus_res[bus].io_avail,
1337 		    pci_bus_res[bus].io_used);
1338 		memlist_remove_list(&pci_bus_res[bus].mem_avail,
1339 		    pci_bus_res[bus].mem_used);
1340 		memlist_remove_list(&pci_bus_res[bus].pmem_avail,
1341 		    pci_bus_res[bus].pmem_used);
1342 		memlist_remove_list(&pci_bus_res[bus].mem_avail,
1343 		    pci_bus_res[bus].pmem_used);
1344 		memlist_remove_list(&pci_bus_res[bus].pmem_avail,
1345 		    pci_bus_res[bus].mem_used);
1346 
1347 		memlist_remove_list(&pci_bus_res[bus].io_avail,
1348 		    isa_res.io_used);
1349 		memlist_remove_list(&pci_bus_res[bus].mem_avail,
1350 		    isa_res.mem_used);
1351 
1352 		/*
1353 		 * 3. Exclude <1M address range here in case below reserved
1354 		 * ranges for BIOS data area, ROM area etc are wrongly reported
1355 		 * in ACPI resource producer entries for PCI root bus.
1356 		 * 	00000000 - 000003FF	RAM
1357 		 * 	00000400 - 000004FF	BIOS data area
1358 		 * 	00000500 - 0009FFFF	RAM
1359 		 * 	000A0000 - 000BFFFF	VGA RAM
1360 		 * 	000C0000 - 000FFFFF	ROM area
1361 		 */
1362 		(void) memlist_remove(&pci_bus_res[bus].mem_avail, 0, 0x100000);
1363 		(void) memlist_remove(&pci_bus_res[bus].pmem_avail,
1364 		    0, 0x100000);
1365 	}
1366 
1367 	memlist_free_all(&isa_res.io_used);
1368 	memlist_free_all(&isa_res.mem_used);
1369 
1370 	/* add bus-range property for root/peer bus nodes */
1371 	for (i = 0; i <= pci_bios_maxbus; i++) {
1372 		/* create bus-range property on root/peer buses */
1373 		if (pci_bus_res[i].par_bus == (uchar_t)-1)
1374 			add_bus_range_prop(i);
1375 
1376 		/* setup bus range resource on each bus */
1377 		setup_bus_res(i);
1378 	}
1379 
1380 	if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(),
1381 	    DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) {
1382 		if (strcmp(onoff, "off") == 0) {
1383 			pci_reconfig = 0;
1384 			cmn_err(CE_NOTE, "pci device reprogramming disabled");
1385 		}
1386 		ddi_prop_free(onoff);
1387 	}
1388 
1389 	remove_subtractive_res();
1390 
1391 	/* reprogram the non-subtractive PPB */
1392 	if (pci_reconfig)
1393 		for (i = 0; i <= pci_bios_maxbus; i++)
1394 			fix_ppb_res(i, B_FALSE);
1395 
1396 	for (i = 0; i <= pci_bios_maxbus; i++) {
1397 		/* configure devices not configured by BIOS */
1398 		if (pci_reconfig) {
1399 			/*
1400 			 * Reprogram the subtractive PPB. At this time, all its
1401 			 * siblings should have got their resources already.
1402 			 */
1403 			if (pci_bus_res[i].subtractive)
1404 				fix_ppb_res(i, B_TRUE);
1405 			enumerate_bus_devs(i, CONFIG_NEW);
1406 		}
1407 	}
1408 
1409 	/* All dev programmed, so we can create available prop */
1410 	for (i = 0; i <= pci_bios_maxbus; i++)
1411 		add_bus_available_prop(i);
1412 }
1413 
1414 /*
1415  * populate bus resources
1416  */
1417 static void
1418 populate_bus_res(uchar_t bus)
1419 {
1420 
1421 	/* scan BIOS structures */
1422 	pci_bus_res[bus].pmem_avail = find_bus_res(bus, PREFETCH_TYPE);
1423 	pci_bus_res[bus].mem_avail = find_bus_res(bus, MEM_TYPE);
1424 	pci_bus_res[bus].io_avail = find_bus_res(bus, IO_TYPE);
1425 	pci_bus_res[bus].bus_avail = find_bus_res(bus, BUSRANGE_TYPE);
1426 
1427 	/*
1428 	 * attempt to initialize sub_bus from the largest range-end
1429 	 * in the bus_avail list
1430 	 */
1431 	if (pci_bus_res[bus].bus_avail != NULL) {
1432 		struct memlist *entry;
1433 		int current;
1434 
1435 		entry = pci_bus_res[bus].bus_avail;
1436 		while (entry != NULL) {
1437 			current = entry->address + entry->size - 1;
1438 			if (current > pci_bus_res[bus].sub_bus)
1439 				pci_bus_res[bus].sub_bus = current;
1440 			entry = entry->next;
1441 		}
1442 	}
1443 
1444 	if (bus == 0) {
1445 		/*
1446 		 * Special treatment of bus 0:
1447 		 * If no IO/MEM resource from ACPI/MPSPEC/HRT, copy
1448 		 * pcimem from boot and make I/O space the entire range
1449 		 * starting at 0x100.
1450 		 */
1451 		if (pci_bus_res[0].mem_avail == NULL)
1452 			pci_bus_res[0].mem_avail =
1453 			    memlist_dup(bootops->boot_mem->pcimem);
1454 		/* Exclude 0x00 to 0xff of the I/O space, used by all PCs */
1455 		if (pci_bus_res[0].io_avail == NULL)
1456 			memlist_insert(&pci_bus_res[0].io_avail, 0x100, 0xffff);
1457 	}
1458 
1459 	/*
1460 	 * Create 'ranges' property here before any resources are
1461 	 * removed from the resource lists
1462 	 */
1463 	add_ranges_prop(bus, 0);
1464 }
1465 
1466 
1467 /*
1468  * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0...
1469  */
1470 static void
1471 create_root_bus_dip(uchar_t bus)
1472 {
1473 	int pci_regs[] = {0, 0, 0};
1474 	dev_info_t *dip;
1475 
1476 	ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1);
1477 
1478 	num_root_bus++;
1479 	ndi_devi_alloc_sleep(ddi_root_node(), "pci",
1480 	    (pnode_t)DEVI_SID_NODEID, &dip);
1481 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1482 	    "#address-cells", 3);
1483 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1484 	    "#size-cells", 2);
1485 	pci_regs[0] = pci_bus_res[bus].root_addr;
1486 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1487 	    "reg", (int *)pci_regs, 3);
1488 
1489 	/*
1490 	 * If system has PCIe bus, then create different properties
1491 	 */
1492 	if (create_pcie_root_bus(bus, dip) == B_FALSE)
1493 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
1494 		    "device_type", "pci");
1495 
1496 	(void) ndi_devi_bind_driver(dip, 0);
1497 	pci_bus_res[bus].dip = dip;
1498 }
1499 
1500 /*
1501  * For any fixed configuration (often compatability) pci devices
1502  * and those with their own expansion rom, create device nodes
1503  * to hold the already configured device details.
1504  */
1505 void
1506 enumerate_bus_devs(uchar_t bus, int config_op)
1507 {
1508 	uchar_t dev, func, nfunc, header;
1509 	ushort_t venid;
1510 	struct pci_devfunc *devlist = NULL, *entry;
1511 
1512 	if (config_op == CONFIG_NEW) {
1513 		dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus);
1514 	} else if (config_op == CONFIG_FIX) {
1515 		dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus);
1516 	} else
1517 		dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus);
1518 
1519 	if (config_op == CONFIG_NEW) {
1520 		devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata;
1521 		while (devlist) {
1522 			entry = devlist;
1523 			devlist = entry->next;
1524 			if (entry->reprogram ||
1525 			    pci_bus_res[bus].io_reprogram ||
1526 			    pci_bus_res[bus].mem_reprogram) {
1527 				/* reprogram device(s) */
1528 				(void) add_reg_props(entry->dip, bus,
1529 				    entry->dev, entry->func, CONFIG_NEW, 0);
1530 			}
1531 			kmem_free(entry, sizeof (*entry));
1532 		}
1533 		pci_bus_res[bus].privdata = NULL;
1534 		return;
1535 	}
1536 
1537 	for (dev = 0; dev < max_dev_pci; dev++) {
1538 		nfunc = 1;
1539 		for (func = 0; func < nfunc; func++) {
1540 
1541 			dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x",
1542 			    dev, func);
1543 
1544 			venid = pci_getw(bus, dev, func, PCI_CONF_VENID);
1545 
1546 			if ((venid == 0xffff) || (venid == 0)) {
1547 				/* no function at this address */
1548 				continue;
1549 			}
1550 
1551 			header = pci_getb(bus, dev, func, PCI_CONF_HEADER);
1552 			if (header == 0xff) {
1553 				continue; /* illegal value */
1554 			}
1555 
1556 			/*
1557 			 * according to some mail from Microsoft posted
1558 			 * to the pci-drivers alias, their only requirement
1559 			 * for a multifunction device is for the 1st
1560 			 * function to have to PCI_HEADER_MULTI bit set.
1561 			 */
1562 			if ((func == 0) && (header & PCI_HEADER_MULTI)) {
1563 				nfunc = 8;
1564 			}
1565 
1566 			if (config_op == CONFIG_FIX ||
1567 			    config_op == CONFIG_INFO) {
1568 				/*
1569 				 * Create the node, unconditionally, on the
1570 				 * first pass only.  It may still need
1571 				 * resource assignment, which will be
1572 				 * done on the second, CONFIG_NEW, pass.
1573 				 */
1574 				process_devfunc(bus, dev, func, header,
1575 				    venid, config_op);
1576 
1577 			}
1578 		}
1579 	}
1580 
1581 	/* percolate bus used resources up through parents to root */
1582 	if (config_op == CONFIG_INFO) {
1583 		int	par_bus;
1584 
1585 		par_bus = pci_bus_res[bus].par_bus;
1586 		while (par_bus != (uchar_t)-1) {
1587 			pci_bus_res[par_bus].io_size +=
1588 			    pci_bus_res[bus].io_size;
1589 			pci_bus_res[par_bus].mem_size +=
1590 			    pci_bus_res[bus].mem_size;
1591 
1592 			if (pci_bus_res[bus].io_used)
1593 				memlist_merge(&pci_bus_res[bus].io_used,
1594 				    &pci_bus_res[par_bus].io_used);
1595 
1596 			if (pci_bus_res[bus].mem_used)
1597 				memlist_merge(&pci_bus_res[bus].mem_used,
1598 				    &pci_bus_res[par_bus].mem_used);
1599 
1600 			if (pci_bus_res[bus].pmem_used)
1601 				memlist_merge(&pci_bus_res[bus].pmem_used,
1602 				    &pci_bus_res[par_bus].pmem_used);
1603 
1604 			bus = par_bus;
1605 			par_bus = pci_bus_res[par_bus].par_bus;
1606 		}
1607 	}
1608 }
1609 
1610 static int
1611 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid,
1612     ushort_t subvenid, ushort_t subdevid)
1613 {
1614 	static int prop_exist = -1;
1615 	static char *pciide_str;
1616 	char compat[32];
1617 
1618 	if (prop_exist == -1) {
1619 		prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY,
1620 		    ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide",
1621 		    &pciide_str) == DDI_SUCCESS);
1622 	}
1623 
1624 	if (!prop_exist)
1625 		return (0);
1626 
1627 	/* compare property value against various forms of compatible */
1628 	if (subvenid) {
1629 		(void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x",
1630 		    venid, devid, subvenid, subdevid, revid);
1631 		if (strcmp(pciide_str, compat) == 0)
1632 			return (1);
1633 
1634 		(void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x",
1635 		    venid, devid, subvenid, subdevid);
1636 		if (strcmp(pciide_str, compat) == 0)
1637 			return (1);
1638 
1639 		(void) snprintf(compat, sizeof (compat), "pci%x,%x",
1640 		    subvenid, subdevid);
1641 		if (strcmp(pciide_str, compat) == 0)
1642 			return (1);
1643 	}
1644 	(void) snprintf(compat, sizeof (compat), "pci%x,%x.%x",
1645 	    venid, devid, revid);
1646 	if (strcmp(pciide_str, compat) == 0)
1647 		return (1);
1648 
1649 	(void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid);
1650 	if (strcmp(pciide_str, compat) == 0)
1651 		return (1);
1652 
1653 	return (0);
1654 }
1655 
1656 static int
1657 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid,
1658     ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid)
1659 {
1660 	struct ide_table {	/* table for PCI_MASS_OTHER */
1661 		ushort_t venid;
1662 		ushort_t devid;
1663 	} *entry;
1664 
1665 	/* XXX SATA and other devices: need a way to add dynamically */
1666 	static struct ide_table ide_other[] = {
1667 		{0x1095, 0x3112},
1668 		{0x1095, 0x3114},
1669 		{0x1095, 0x3512},
1670 		{0x1095, 0x680},	/* Sil0680 */
1671 		{0x1283, 0x8211},	/* ITE 8211F is subcl PCI_MASS_OTHER */
1672 		{0, 0}
1673 	};
1674 
1675 	if (basecl != PCI_CLASS_MASS)
1676 		return (0);
1677 
1678 	if (subcl == PCI_MASS_IDE) {
1679 		return (1);
1680 	}
1681 
1682 	if (check_pciide_prop(revid, venid, devid, subvenid, subdevid))
1683 		return (1);
1684 
1685 	if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) {
1686 		return (0);
1687 	}
1688 
1689 	entry = &ide_other[0];
1690 	while (entry->venid) {
1691 		if (entry->venid == venid && entry->devid == devid)
1692 			return (1);
1693 		entry++;
1694 	}
1695 	return (0);
1696 }
1697 
1698 static int
1699 is_display(uint_t classcode)
1700 {
1701 	static uint_t disp_classes[] = {
1702 		0x000100,
1703 		0x030000,
1704 		0x030001
1705 	};
1706 	int i, nclasses = sizeof (disp_classes) / sizeof (uint_t);
1707 
1708 	for (i = 0; i < nclasses; i++) {
1709 		if (classcode == disp_classes[i])
1710 			return (1);
1711 	}
1712 	return (0);
1713 }
1714 
1715 static void
1716 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn,
1717     void (*undofn)(uint8_t, uint8_t, uint8_t))
1718 {
1719 	struct pci_fixundo *newundo;
1720 
1721 	newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP);
1722 
1723 	/*
1724 	 * Adding an item to this list means that we must turn its NMIENABLE
1725 	 * bit back on at a later time.
1726 	 */
1727 	newundo->bus = bus;
1728 	newundo->dev = dev;
1729 	newundo->fn = fn;
1730 	newundo->undofn = undofn;
1731 	newundo->next = undolist;
1732 
1733 	/* add to the undo list in LIFO order */
1734 	undolist = newundo;
1735 }
1736 
1737 void
1738 add_pci_fixes(void)
1739 {
1740 	int i;
1741 
1742 	for (i = 0; i <= pci_bios_maxbus; i++) {
1743 		/*
1744 		 * For each bus, apply needed fixes to the appropriate devices.
1745 		 * This must be done before the main enumeration loop because
1746 		 * some fixes must be applied to devices normally encountered
1747 		 * later in the pci scan (e.g. if a fix to device 7 must be
1748 		 * applied before scanning device 6, applying fixes in the
1749 		 * normal enumeration loop would obviously be too late).
1750 		 */
1751 		enumerate_bus_devs(i, CONFIG_FIX);
1752 	}
1753 }
1754 
1755 void
1756 undo_pci_fixes(void)
1757 {
1758 	struct pci_fixundo *nextundo;
1759 	uint8_t bus, dev, fn;
1760 
1761 	/*
1762 	 * All fixes in the undo list are performed unconditionally.  Future
1763 	 * fixes may require selective undo.
1764 	 */
1765 	while (undolist != NULL) {
1766 
1767 		bus = undolist->bus;
1768 		dev = undolist->dev;
1769 		fn = undolist->fn;
1770 
1771 		(*(undolist->undofn))(bus, dev, fn);
1772 
1773 		nextundo = undolist->next;
1774 		kmem_free(undolist, sizeof (struct pci_fixundo));
1775 		undolist = nextundo;
1776 	}
1777 }
1778 
1779 static void
1780 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn)
1781 {
1782 	uint8_t val8;
1783 
1784 	val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1);
1785 	/*
1786 	 * The NMIONERR bit is turned back on to allow the SMM BIOS
1787 	 * to handle more critical PCI errors (e.g. PERR#).
1788 	 */
1789 	val8 |= AMD8111_ENABLENMI;
1790 	pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8);
1791 }
1792 
1793 static void
1794 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn)
1795 {
1796 	uint8_t val8;
1797 
1798 	val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1);
1799 
1800 	if ((val8 & AMD8111_ENABLENMI) == 0)
1801 		return;
1802 
1803 	/*
1804 	 * We reset NMIONERR in the LPC because master-abort on the PCI
1805 	 * bridge side of the 8111 will cause NMI, which might cause SMI,
1806 	 * which sometimes prevents all devices from being enumerated.
1807 	 */
1808 	val8 &= ~AMD8111_ENABLENMI;
1809 
1810 	pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8);
1811 
1812 	add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix);
1813 }
1814 
1815 static void
1816 set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func)
1817 {
1818 	uint16_t status;
1819 	uint8_t header;
1820 	uint8_t cap_ptr;
1821 	uint8_t cap_id;
1822 	uint16_t pmcsr;
1823 
1824 	status = pci_getw(bus, dev, func, PCI_CONF_STAT);
1825 	if (!(status & PCI_STAT_CAP))
1826 		return;	/* No capabilities list */
1827 
1828 	header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M;
1829 	if (header == PCI_HEADER_CARDBUS)
1830 		cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_CAP_PTR);
1831 	else
1832 		cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR);
1833 	/*
1834 	 * Walk the capabilities list searching for a PM entry.
1835 	 */
1836 	while (cap_ptr != PCI_CAP_NEXT_PTR_NULL && cap_ptr >= PCI_CAP_PTR_OFF) {
1837 		cap_ptr &= PCI_CAP_PTR_MASK;
1838 		cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID);
1839 		if (cap_id == PCI_CAP_ID_PM) {
1840 			pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR);
1841 			pmcsr &= ~(PCI_PMCSR_STATE_MASK);
1842 			pmcsr |= PCI_PMCSR_D0; /* D0 state */
1843 			pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr);
1844 			break;
1845 		}
1846 		cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR);
1847 	}
1848 
1849 }
1850 
1851 #define	is_isa(bc, sc)	\
1852 	(((bc) == PCI_CLASS_BRIDGE) && ((sc) == PCI_BRIDGE_ISA))
1853 
1854 static void
1855 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header,
1856     ushort_t vendorid, int config_op)
1857 {
1858 	char nodename[32], unitaddr[5];
1859 	dev_info_t *dip;
1860 	uchar_t basecl, subcl, progcl, intr, revid;
1861 	ushort_t subvenid, subdevid, status;
1862 	ushort_t slot_num;
1863 	uint_t classcode, revclass;
1864 	int reprogram = 0, pciide = 0;
1865 	int power[2] = {1, 1};
1866 	int pciex = 0;
1867 	ushort_t is_pci_bridge = 0;
1868 	struct pci_devfunc *devlist = NULL, *entry = NULL;
1869 	gfx_entry_t *gfxp;
1870 
1871 	ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID);
1872 
1873 	switch (header & PCI_HEADER_TYPE_M) {
1874 	case PCI_HEADER_ZERO:
1875 		subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID);
1876 		subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID);
1877 		break;
1878 	case PCI_HEADER_CARDBUS:
1879 		subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID);
1880 		subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID);
1881 		/* Record the # of cardbus bridges found on the bus */
1882 		if (config_op == CONFIG_INFO)
1883 			pci_bus_res[bus].num_cbb++;
1884 		break;
1885 	default:
1886 		subvenid = 0;
1887 		subdevid = 0;
1888 		break;
1889 	}
1890 
1891 	if (config_op == CONFIG_FIX) {
1892 		if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) {
1893 			pci_fix_amd8111(bus, dev, func);
1894 		}
1895 		return;
1896 	}
1897 
1898 	/* XXX should be use generic names? derive from class? */
1899 	revclass = pci_getl(bus, dev, func, PCI_CONF_REVID);
1900 	classcode = revclass >> 8;
1901 	revid = revclass & 0xff;
1902 
1903 	/* figure out if this is pci-ide */
1904 	basecl = classcode >> 16;
1905 	subcl = (classcode >> 8) & 0xff;
1906 	progcl = classcode & 0xff;
1907 
1908 
1909 	if (is_display(classcode))
1910 		(void) snprintf(nodename, sizeof (nodename), "display");
1911 	else if (!pseudo_isa && is_isa(basecl, subcl))
1912 		(void) snprintf(nodename, sizeof (nodename), "isa");
1913 	else if (subvenid != 0)
1914 		(void) snprintf(nodename, sizeof (nodename),
1915 		    "pci%x,%x", subvenid, subdevid);
1916 	else
1917 		(void) snprintf(nodename, sizeof (nodename),
1918 		    "pci%x,%x", vendorid, deviceid);
1919 
1920 	/* make sure parent bus dip has been created */
1921 	if (pci_bus_res[bus].dip == NULL)
1922 		create_root_bus_dip(bus);
1923 
1924 	ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename,
1925 	    DEVI_SID_NODEID, &dip);
1926 
1927 	if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num,
1928 	    &is_pci_bridge) == B_TRUE)
1929 		pciex = 1;
1930 
1931 	/* add properties */
1932 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid);
1933 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid);
1934 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid);
1935 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1936 	    "class-code", classcode);
1937 	if (func == 0)
1938 		(void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev);
1939 	else
1940 		(void) snprintf(unitaddr, sizeof (unitaddr),
1941 		    "%x,%x", dev, func);
1942 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
1943 	    "unit-address", unitaddr);
1944 
1945 	/* add device_type for display nodes */
1946 	if (is_display(classcode)) {
1947 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
1948 		    "device_type", "display");
1949 	}
1950 	/* add special stuff for header type */
1951 	if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) {
1952 		uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G);
1953 		uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L);
1954 
1955 		if (subvenid != 0) {
1956 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1957 			    "subsystem-id", subdevid);
1958 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1959 			    "subsystem-vendor-id", subvenid);
1960 		}
1961 		if (!pciex)
1962 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1963 			    "min-grant", mingrant);
1964 		if (!pciex)
1965 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1966 			    "max-latency", maxlatency);
1967 	}
1968 
1969 	/* interrupt, record if not 0 */
1970 	intr = pci_getb(bus, dev, func, PCI_CONF_IPIN);
1971 	if (intr != 0)
1972 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1973 		    "interrupts", intr);
1974 
1975 	/*
1976 	 * Add support for 133 mhz pci eventually
1977 	 */
1978 	status = pci_getw(bus, dev, func, PCI_CONF_STAT);
1979 
1980 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1981 	    "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9);
1982 	if (!pciex && (status & PCI_STAT_FBBC))
1983 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip,
1984 		    "fast-back-to-back");
1985 	if (!pciex && (status & PCI_STAT_66MHZ))
1986 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip,
1987 		    "66mhz-capable");
1988 	if (status & PCI_STAT_UDF)
1989 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip,
1990 		    "udf-supported");
1991 	if (pciex && slot_num) {
1992 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1993 		    "physical-slot#", slot_num);
1994 		if (!is_pci_bridge)
1995 			pciex_slot_names_prop(dip, slot_num);
1996 	}
1997 
1998 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1999 	    "power-consumption", power, 2);
2000 
2001 	/* Set the device PM state to D0 */
2002 	set_devpm_d0(bus, dev, func);
2003 
2004 	if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI))
2005 		add_ppb_props(dip, bus, dev, func, pciex, is_pci_bridge);
2006 	else {
2007 		/*
2008 		 * Record the non-PPB devices on the bus for possible
2009 		 * reprogramming at 2nd bus enumeration.
2010 		 * Note: PPB reprogramming is done in fix_ppb_res()
2011 		 */
2012 		devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata;
2013 		entry = kmem_zalloc(sizeof (*entry), KM_SLEEP);
2014 		entry->dip = dip;
2015 		entry->dev = dev;
2016 		entry->func = func;
2017 		entry->next = devlist;
2018 		pci_bus_res[bus].privdata = entry;
2019 	}
2020 
2021 	if (config_op == CONFIG_INFO &&
2022 	    IS_CLASS_IOAPIC(basecl, subcl, progcl)) {
2023 		create_ioapic_node(bus, dev, func, vendorid, deviceid);
2024 	}
2025 
2026 	/* check for ck8-04 based PCI ISA bridge only */
2027 	if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) &&
2028 	    (func == 0))
2029 		add_nvidia_isa_bridge_props(dip, bus, dev, func);
2030 
2031 	if (pciex && is_pci_bridge)
2032 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model",
2033 		    (char *)"PCIe-PCI bridge");
2034 	else
2035 		add_model_prop(dip, classcode);
2036 
2037 	add_compatible(dip, subvenid, subdevid, vendorid, deviceid,
2038 	    revid, classcode, pciex);
2039 
2040 	/*
2041 	 * See if this device is a controller that advertises
2042 	 * itself to be a standard ATA task file controller, or one that
2043 	 * has been hard coded.
2044 	 *
2045 	 * If it is, check if any other higher precedence driver listed in
2046 	 * driver_aliases will claim the node by calling
2047 	 * ddi_compatibile_driver_major.  If so, clear pciide and do not
2048 	 * create a pci-ide node or any other special handling.
2049 	 *
2050 	 * If another driver does not bind, set the node name to pci-ide
2051 	 * and then let the special pci-ide handling for registers and
2052 	 * child pci-ide nodes proceed below.
2053 	 */
2054 	if (is_pciide(basecl, subcl, revid, vendorid, deviceid,
2055 	    subvenid, subdevid) == 1) {
2056 		if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) {
2057 			(void) ndi_devi_set_nodename(dip, "pci-ide", 0);
2058 			pciide = 1;
2059 		}
2060 	}
2061 
2062 	reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide);
2063 	(void) ndi_devi_bind_driver(dip, 0);
2064 
2065 	/* special handling for pci-ide */
2066 	if (pciide) {
2067 		dev_info_t *cdip;
2068 
2069 		/*
2070 		 * Create properties specified by P1275 Working Group
2071 		 * Proposal #414 Version 1
2072 		 */
2073 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
2074 		    "device_type", "pci-ide");
2075 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2076 		    "#address-cells", 1);
2077 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2078 		    "#size-cells", 0);
2079 
2080 		/* allocate two child nodes */
2081 		ndi_devi_alloc_sleep(dip, "ide",
2082 		    (pnode_t)DEVI_SID_NODEID, &cdip);
2083 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip,
2084 		    "reg", 0);
2085 		(void) ndi_devi_bind_driver(cdip, 0);
2086 		ndi_devi_alloc_sleep(dip, "ide",
2087 		    (pnode_t)DEVI_SID_NODEID, &cdip);
2088 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip,
2089 		    "reg", 1);
2090 		(void) ndi_devi_bind_driver(cdip, 0);
2091 
2092 		reprogram = 0;	/* don't reprogram pci-ide bridge */
2093 	}
2094 
2095 	if (is_display(classcode)) {
2096 		gfxp = kmem_zalloc(sizeof (*gfxp), KM_SLEEP);
2097 		gfxp->g_dip = dip;
2098 		gfxp->g_prev = NULL;
2099 		gfxp->g_next = gfx_devinfo_list;
2100 		gfx_devinfo_list = gfxp;
2101 		if (gfxp->g_next)
2102 			gfxp->g_next->g_prev = gfxp;
2103 	}
2104 
2105 	/* special handling for isa */
2106 	if (!pseudo_isa && is_isa(basecl, subcl)) {
2107 		/* add device_type */
2108 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
2109 		    "device_type", "isa");
2110 	}
2111 
2112 	if (reprogram && (entry != NULL))
2113 		entry->reprogram = B_TRUE;
2114 
2115 }
2116 
2117 /*
2118  * Some vendors do not use unique subsystem IDs in their products, which
2119  * makes the use of form 2 compatible names (pciSSSS,ssss) inappropriate.
2120  * Allow for these compatible forms to be excluded on a per-device basis.
2121  */
2122 /*ARGSUSED*/
2123 static boolean_t
2124 subsys_compat_exclude(ushort_t venid, ushort_t devid, ushort_t subvenid,
2125     ushort_t subdevid, uchar_t revid, uint_t classcode)
2126 {
2127 	/* Nvidia display adapters */
2128 	if ((venid == 0x10de) && (is_display(classcode)))
2129 		return (B_TRUE);
2130 
2131 	return (B_FALSE);
2132 }
2133 
2134 /*
2135  * Set the compatible property to a value compliant with
2136  * rev 2.1 of the IEEE1275 PCI binding.
2137  * (Also used for PCI-Express devices).
2138  *
2139  *   pciVVVV,DDDD.SSSS.ssss.RR	(0)
2140  *   pciVVVV,DDDD.SSSS.ssss	(1)
2141  *   pciSSSS,ssss		(2)
2142  *   pciVVVV,DDDD.RR		(3)
2143  *   pciVVVV,DDDD		(4)
2144  *   pciclass,CCSSPP		(5)
2145  *   pciclass,CCSS		(6)
2146  *
2147  * The Subsystem (SSSS) forms are not inserted if
2148  * subsystem-vendor-id is 0.
2149  *
2150  * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above
2151  * property 2 is not created as per "1275 bindings for PCI Express Interconnect"
2152  *
2153  * Set with setprop and \x00 between each
2154  * to generate the encoded string array form.
2155  */
2156 void
2157 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid,
2158     ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode,
2159     int pciex)
2160 {
2161 	int i = 0;
2162 	int size = COMPAT_BUFSIZE;
2163 	char *compat[13];
2164 	char *buf, *curr;
2165 
2166 	curr = buf = kmem_alloc(size, KM_SLEEP);
2167 
2168 	if (pciex) {
2169 		if (subvenid) {
2170 			compat[i++] = curr;	/* form 0 */
2171 			(void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x",
2172 			    vendorid, deviceid, subvenid, subdevid, revid);
2173 			size -= strlen(curr) + 1;
2174 			curr += strlen(curr) + 1;
2175 
2176 			compat[i++] = curr;	/* form 1 */
2177 			(void) snprintf(curr, size, "pciex%x,%x.%x.%x",
2178 			    vendorid, deviceid, subvenid, subdevid);
2179 			size -= strlen(curr) + 1;
2180 			curr += strlen(curr) + 1;
2181 
2182 		}
2183 		compat[i++] = curr;	/* form 3 */
2184 		(void) snprintf(curr, size, "pciex%x,%x.%x",
2185 		    vendorid, deviceid, revid);
2186 		size -= strlen(curr) + 1;
2187 		curr += strlen(curr) + 1;
2188 
2189 		compat[i++] = curr;	/* form 4 */
2190 		(void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid);
2191 		size -= strlen(curr) + 1;
2192 		curr += strlen(curr) + 1;
2193 
2194 		compat[i++] = curr;	/* form 5 */
2195 		(void) snprintf(curr, size, "pciexclass,%06x", classcode);
2196 		size -= strlen(curr) + 1;
2197 		curr += strlen(curr) + 1;
2198 
2199 		compat[i++] = curr;	/* form 6 */
2200 		(void) snprintf(curr, size, "pciexclass,%04x",
2201 		    (classcode >> 8));
2202 		size -= strlen(curr) + 1;
2203 		curr += strlen(curr) + 1;
2204 	}
2205 
2206 	if (subvenid) {
2207 		compat[i++] = curr;	/* form 0 */
2208 		(void) snprintf(curr, size, "pci%x,%x.%x.%x.%x",
2209 		    vendorid, deviceid, subvenid, subdevid, revid);
2210 		size -= strlen(curr) + 1;
2211 		curr += strlen(curr) + 1;
2212 
2213 		compat[i++] = curr;	/* form 1 */
2214 		(void) snprintf(curr, size, "pci%x,%x.%x.%x",
2215 		    vendorid, deviceid, subvenid, subdevid);
2216 		size -= strlen(curr) + 1;
2217 		curr += strlen(curr) + 1;
2218 
2219 		if (subsys_compat_exclude(vendorid, deviceid, subvenid,
2220 		    subdevid, revid, classcode) == B_FALSE) {
2221 			compat[i++] = curr;	/* form 2 */
2222 			(void) snprintf(curr, size, "pci%x,%x", subvenid,
2223 			    subdevid);
2224 			size -= strlen(curr) + 1;
2225 			curr += strlen(curr) + 1;
2226 		}
2227 	}
2228 	compat[i++] = curr;	/* form 3 */
2229 	(void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid);
2230 	size -= strlen(curr) + 1;
2231 	curr += strlen(curr) + 1;
2232 
2233 	compat[i++] = curr;	/* form 4 */
2234 	(void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid);
2235 	size -= strlen(curr) + 1;
2236 	curr += strlen(curr) + 1;
2237 
2238 	compat[i++] = curr;	/* form 5 */
2239 	(void) snprintf(curr, size, "pciclass,%06x", classcode);
2240 	size -= strlen(curr) + 1;
2241 	curr += strlen(curr) + 1;
2242 
2243 	compat[i++] = curr;	/* form 6 */
2244 	(void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8));
2245 	size -= strlen(curr) + 1;
2246 	curr += strlen(curr) + 1;
2247 
2248 	(void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip,
2249 	    "compatible", compat, i);
2250 	kmem_free(buf, COMPAT_BUFSIZE);
2251 }
2252 
2253 /*
2254  * Adjust the reg properties for a dual channel PCI-IDE device.
2255  *
2256  * NOTE: don't do anything that changes the order of the hard-decodes
2257  * and programmed BARs. The kernel driver depends on these values
2258  * being in this order regardless of whether they're for a 'native'
2259  * mode BAR or not.
2260  */
2261 /*
2262  * config info for pci-ide devices
2263  */
2264 static struct {
2265 	uchar_t  native_mask;	/* 0 == 'compatibility' mode, 1 == native */
2266 	uchar_t  bar_offset;	/* offset for alt status register */
2267 	ushort_t addr;		/* compatibility mode base address */
2268 	ushort_t length;	/* number of ports for this BAR */
2269 } pciide_bar[] = {
2270 	{ 0x01, 0, 0x1f0, 8 },	/* primary lower BAR */
2271 	{ 0x01, 2, 0x3f6, 1 },	/* primary upper BAR */
2272 	{ 0x04, 0, 0x170, 8 },	/* secondary lower BAR */
2273 	{ 0x04, 2, 0x376, 1 }	/* secondary upper BAR */
2274 };
2275 
2276 static int
2277 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp)
2278 {
2279 	int hard_decode = 0;
2280 
2281 	/*
2282 	 * Adjust the base and len for the BARs of the PCI-IDE
2283 	 * device's primary and secondary controllers. The first
2284 	 * two BARs are for the primary controller and the next
2285 	 * two BARs are for the secondary controller. The fifth
2286 	 * and sixth bars are never adjusted.
2287 	 */
2288 	if (index >= 0 && index <= 3) {
2289 		*lenp = pciide_bar[index].length;
2290 
2291 		if (progcl & pciide_bar[index].native_mask) {
2292 			*basep += pciide_bar[index].bar_offset;
2293 		} else {
2294 			*basep = pciide_bar[index].addr;
2295 			hard_decode = 1;
2296 		}
2297 	}
2298 
2299 	/*
2300 	 * if either base or len is zero make certain both are zero
2301 	 */
2302 	if (*basep == 0 || *lenp == 0) {
2303 		*basep = 0;
2304 		*lenp = 0;
2305 		hard_decode = 0;
2306 	}
2307 
2308 	return (hard_decode);
2309 }
2310 
2311 
2312 /*
2313  * Add the "reg" and "assigned-addresses" property
2314  */
2315 static int
2316 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func,
2317     int config_op, int pciide)
2318 {
2319 	uchar_t baseclass, subclass, progclass, header;
2320 	ushort_t bar_sz;
2321 	uint_t value = 0, len, devloc;
2322 	uint_t base, base_hi, type;
2323 	ushort_t offset, end;
2324 	int max_basereg, j, reprogram = 0;
2325 	uint_t phys_hi;
2326 	struct memlist **io_avail, **io_used;
2327 	struct memlist **mem_avail, **mem_used;
2328 	struct memlist **pmem_avail, **pmem_used;
2329 	uchar_t res_bus;
2330 
2331 	pci_regspec_t regs[16] = {{0}};
2332 	pci_regspec_t assigned[15] = {{0}};
2333 	int nreg, nasgn;
2334 
2335 	io_avail = &pci_bus_res[bus].io_avail;
2336 	io_used = &pci_bus_res[bus].io_used;
2337 	mem_avail = &pci_bus_res[bus].mem_avail;
2338 	mem_used = &pci_bus_res[bus].mem_used;
2339 	pmem_avail = &pci_bus_res[bus].pmem_avail;
2340 	pmem_used = &pci_bus_res[bus].pmem_used;
2341 
2342 	devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8;
2343 	regs[0].pci_phys_hi = devloc;
2344 	nreg = 1;	/* rest of regs[0] is all zero */
2345 	nasgn = 0;
2346 
2347 	baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS);
2348 	subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS);
2349 	progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS);
2350 	header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M;
2351 
2352 	switch (header) {
2353 	case PCI_HEADER_ZERO:
2354 		max_basereg = PCI_BASE_NUM;
2355 		break;
2356 	case PCI_HEADER_PPB:
2357 		max_basereg = PCI_BCNF_BASE_NUM;
2358 		break;
2359 	case PCI_HEADER_CARDBUS:
2360 		max_basereg = PCI_CBUS_BASE_NUM;
2361 		reprogram = 1;
2362 		break;
2363 	default:
2364 		max_basereg = 0;
2365 		break;
2366 	}
2367 
2368 	/*
2369 	 * Create the register property by saving the current
2370 	 * value of the base register. Write 0xffffffff to the
2371 	 * base register.  Read the value back to determine the
2372 	 * required size of the address space.  Restore the base
2373 	 * register contents.
2374 	 *
2375 	 * Do not disable I/O and memory access; this isn't necessary
2376 	 * since no driver is yet attached to this device, and disabling
2377 	 * I/O and memory access has the side-effect of disabling PCI-PCI
2378 	 * bridge mappings, which makes the bridge transparent to secondary-
2379 	 * bus activity (see sections 4.1-4.3 of the PCI-PCI Bridge
2380 	 * Spec V1.2).
2381 	 */
2382 	end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t);
2383 	for (j = 0, offset = PCI_CONF_BASE0; offset < end;
2384 	    j++, offset += bar_sz) {
2385 		/* determine the size of the address space */
2386 		base = pci_getl(bus, dev, func, offset);
2387 		pci_putl(bus, dev, func, offset, 0xffffffff);
2388 		value = pci_getl(bus, dev, func, offset);
2389 		pci_putl(bus, dev, func, offset, base);
2390 
2391 		/* construct phys hi,med.lo, size hi, lo */
2392 		if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) {
2393 			int hard_decode = 0;
2394 
2395 			/* i/o space */
2396 			bar_sz = PCI_BAR_SZ_32;
2397 			value &= PCI_BASE_IO_ADDR_M;
2398 			len = ((value ^ (value-1)) + 1) >> 1;
2399 
2400 			/* XXX Adjust first 4 IDE registers */
2401 			if (pciide) {
2402 				if (subclass != PCI_MASS_IDE)
2403 					progclass = (PCI_IDE_IF_NATIVE_PRI |
2404 					    PCI_IDE_IF_NATIVE_SEC);
2405 				hard_decode = pciIdeAdjustBAR(progclass, j,
2406 				    &base, &len);
2407 			} else if (value == 0) {
2408 				/* skip base regs with size of 0 */
2409 				continue;
2410 			}
2411 
2412 			regs[nreg].pci_phys_hi = PCI_ADDR_IO | devloc |
2413 			    (hard_decode ? PCI_RELOCAT_B : offset);
2414 			regs[nreg].pci_phys_low = hard_decode ?
2415 			    base & PCI_BASE_IO_ADDR_M : 0;
2416 			assigned[nasgn].pci_phys_hi =
2417 			    PCI_RELOCAT_B | regs[nreg].pci_phys_hi;
2418 			regs[nreg].pci_size_low =
2419 			    assigned[nasgn].pci_size_low = len;
2420 			type = base & (~PCI_BASE_IO_ADDR_M);
2421 			base &= PCI_BASE_IO_ADDR_M;
2422 			/*
2423 			 * A device under a subtractive PPB can allocate
2424 			 * resources from its parent bus if there is no resource
2425 			 * available on its own bus.
2426 			 */
2427 			if ((config_op == CONFIG_NEW) && (*io_avail == NULL)) {
2428 				res_bus = bus;
2429 				while (pci_bus_res[res_bus].subtractive) {
2430 					res_bus = pci_bus_res[res_bus].par_bus;
2431 					if (res_bus == (uchar_t)-1)
2432 						break; /* root bus already */
2433 					if (pci_bus_res[res_bus].io_avail) {
2434 						io_avail = &pci_bus_res
2435 						    [res_bus].io_avail;
2436 						break;
2437 					}
2438 				}
2439 			}
2440 
2441 			/*
2442 			 * first pass - gather what's there
2443 			 * update/second pass - adjust/allocate regions
2444 			 *	config - allocate regions
2445 			 */
2446 			if (config_op == CONFIG_INFO) {	/* first pass */
2447 				/* take out of the resource map of the bus */
2448 				if (base != 0) {
2449 					(void) memlist_remove(io_avail, base,
2450 					    len);
2451 					memlist_insert(io_used, base, len);
2452 				} else {
2453 					reprogram = 1;
2454 				}
2455 				pci_bus_res[bus].io_size += len;
2456 			} else if ((*io_avail && base == 0) ||
2457 			    pci_bus_res[bus].io_reprogram) {
2458 				base = (uint_t)memlist_find(io_avail, len, len);
2459 				if (base != 0) {
2460 					memlist_insert(io_used, base, len);
2461 					/* XXX need to worry about 64-bit? */
2462 					pci_putl(bus, dev, func, offset,
2463 					    base | type);
2464 					base = pci_getl(bus, dev, func, offset);
2465 					base &= PCI_BASE_IO_ADDR_M;
2466 				}
2467 				if (base == 0) {
2468 					cmn_err(CE_WARN, "failed to program"
2469 					    " IO space [%d/%d/%d] BAR@0x%x"
2470 					    " length 0x%x",
2471 					    bus, dev, func, offset, len);
2472 				}
2473 			}
2474 			assigned[nasgn].pci_phys_low = base;
2475 			nreg++, nasgn++;
2476 
2477 		} else {
2478 			/* memory space */
2479 			if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) {
2480 				bar_sz = PCI_BAR_SZ_64;
2481 				base_hi = pci_getl(bus, dev, func, offset + 4);
2482 				phys_hi = PCI_ADDR_MEM64;
2483 			} else {
2484 				bar_sz = PCI_BAR_SZ_32;
2485 				base_hi = 0;
2486 				phys_hi = PCI_ADDR_MEM32;
2487 			}
2488 
2489 			/* skip base regs with size of 0 */
2490 			value &= PCI_BASE_M_ADDR_M;
2491 
2492 			if (value == 0)
2493 				continue;
2494 
2495 			len = ((value ^ (value-1)) + 1) >> 1;
2496 			regs[nreg].pci_size_low =
2497 			    assigned[nasgn].pci_size_low = len;
2498 
2499 			phys_hi |= (devloc | offset);
2500 			if (base & PCI_BASE_PREF_M)
2501 				phys_hi |= PCI_PREFETCH_B;
2502 
2503 			/*
2504 			 * A device under a subtractive PPB can allocate
2505 			 * resources from its parent bus if there is no resource
2506 			 * available on its own bus.
2507 			 */
2508 			if ((config_op == CONFIG_NEW) && (*mem_avail == NULL)) {
2509 				res_bus = bus;
2510 				while (pci_bus_res[res_bus].subtractive) {
2511 					res_bus = pci_bus_res[res_bus].par_bus;
2512 					if (res_bus == (uchar_t)-1)
2513 						break; /* root bus already */
2514 					mem_avail =
2515 					    &pci_bus_res[res_bus].mem_avail;
2516 					pmem_avail =
2517 					    &pci_bus_res [res_bus].pmem_avail;
2518 					/*
2519 					 * Break out as long as at least
2520 					 * mem_avail is available
2521 					 */
2522 					if ((*pmem_avail &&
2523 					    (phys_hi & PCI_PREFETCH_B)) ||
2524 					    *mem_avail)
2525 						break;
2526 				}
2527 			}
2528 
2529 			regs[nreg].pci_phys_hi =
2530 			    assigned[nasgn].pci_phys_hi = phys_hi;
2531 			assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B;
2532 			assigned[nasgn].pci_phys_mid = base_hi;
2533 			type = base & ~PCI_BASE_M_ADDR_M;
2534 			base &= PCI_BASE_M_ADDR_M;
2535 
2536 			if (config_op == CONFIG_INFO) {
2537 				/* take out of the resource map of the bus */
2538 				if (base != NULL) {
2539 					/* remove from PMEM and MEM space */
2540 					(void) memlist_remove(mem_avail,
2541 					    base, len);
2542 					(void) memlist_remove(pmem_avail,
2543 					    base, len);
2544 					/* only note as used in correct map */
2545 					if (phys_hi & PCI_PREFETCH_B)
2546 						memlist_insert(pmem_used,
2547 						    base, len);
2548 					else
2549 						memlist_insert(mem_used,
2550 						    base, len);
2551 				} else {
2552 					reprogram = 1;
2553 				}
2554 				pci_bus_res[bus].mem_size += len;
2555 			} else if ((*mem_avail && base == NULL) ||
2556 			    pci_bus_res[bus].mem_reprogram) {
2557 				/*
2558 				 * When desired, attempt a prefetchable
2559 				 * allocation first
2560 				 */
2561 				if (phys_hi & PCI_PREFETCH_B) {
2562 					base = (uint_t)memlist_find(pmem_avail,
2563 					    len, len);
2564 					if (base != NULL) {
2565 						memlist_insert(pmem_used,
2566 						    base, len);
2567 						(void) memlist_remove(mem_avail,
2568 						    base, len);
2569 					}
2570 				}
2571 				/*
2572 				 * If prefetchable allocation was not
2573 				 * desired, or failed, attempt ordinary
2574 				 * memory allocation
2575 				 */
2576 				if (base == NULL) {
2577 					base = (uint_t)memlist_find(mem_avail,
2578 					    len, len);
2579 					if (base != NULL) {
2580 						memlist_insert(mem_used,
2581 						    base, len);
2582 						(void) memlist_remove(
2583 						    pmem_avail, base, len);
2584 					}
2585 				}
2586 				if (base != NULL) {
2587 					pci_putl(bus, dev, func, offset,
2588 					    base | type);
2589 					base = pci_getl(bus, dev, func, offset);
2590 					base &= PCI_BASE_M_ADDR_M;
2591 				} else
2592 					cmn_err(CE_WARN, "failed to program "
2593 					    "mem space [%d/%d/%d] BAR@0x%x"
2594 					    " length 0x%x",
2595 					    bus, dev, func, offset, len);
2596 			}
2597 			assigned[nasgn].pci_phys_low = base;
2598 			nreg++, nasgn++;
2599 		}
2600 	}
2601 	switch (header) {
2602 	case PCI_HEADER_ZERO:
2603 		offset = PCI_CONF_ROM;
2604 		break;
2605 	case PCI_HEADER_PPB:
2606 		offset = PCI_BCNF_ROM;
2607 		break;
2608 	default: /* including PCI_HEADER_CARDBUS */
2609 		goto done;
2610 	}
2611 
2612 	/*
2613 	 * Add the expansion rom memory space
2614 	 * Determine the size of the ROM base reg; don't write reserved bits
2615 	 * ROM isn't in the PCI memory space.
2616 	 */
2617 	base = pci_getl(bus, dev, func, offset);
2618 	pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M);
2619 	value = pci_getl(bus, dev, func, offset);
2620 	pci_putl(bus, dev, func, offset, base);
2621 	if (value & PCI_BASE_ROM_ENABLE)
2622 		value &= PCI_BASE_ROM_ADDR_M;
2623 	else
2624 		value = 0;
2625 
2626 	if (value != 0) {
2627 		regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset;
2628 		assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B |
2629 		    PCI_ADDR_MEM32 | devloc) + offset;
2630 		base &= PCI_BASE_ROM_ADDR_M;
2631 		assigned[nasgn].pci_phys_low = base;
2632 		len = ((value ^ (value-1)) + 1) >> 1;
2633 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len;
2634 		nreg++, nasgn++;
2635 		/* take it out of the memory resource */
2636 		if (base != NULL) {
2637 			(void) memlist_remove(mem_avail, base, len);
2638 			memlist_insert(mem_used, base, len);
2639 			pci_bus_res[bus].mem_size += len;
2640 		}
2641 	}
2642 
2643 	/*
2644 	 * Account for "legacy" (alias) video adapter resources
2645 	 */
2646 
2647 	/* add the three hard-decode, aliased address spaces for VGA */
2648 	if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) ||
2649 	    (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) {
2650 
2651 		/* VGA hard decode 0x3b0-0x3bb */
2652 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2653 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2654 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0;
2655 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc;
2656 		nreg++, nasgn++;
2657 		(void) memlist_remove(io_avail, 0x3b0, 0xc);
2658 		memlist_insert(io_used, 0x3b0, 0xc);
2659 		pci_bus_res[bus].io_size += 0xc;
2660 
2661 		/* VGA hard decode 0x3c0-0x3df */
2662 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2663 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2664 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0;
2665 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20;
2666 		nreg++, nasgn++;
2667 		(void) memlist_remove(io_avail, 0x3c0, 0x20);
2668 		memlist_insert(io_used, 0x3c0, 0x20);
2669 		pci_bus_res[bus].io_size += 0x20;
2670 
2671 		/* Video memory */
2672 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2673 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_MEM32 | devloc);
2674 		regs[nreg].pci_phys_low =
2675 		    assigned[nasgn].pci_phys_low = 0xa0000;
2676 		regs[nreg].pci_size_low =
2677 		    assigned[nasgn].pci_size_low = 0x20000;
2678 		nreg++, nasgn++;
2679 		/* remove from MEM and PMEM space */
2680 		(void) memlist_remove(mem_avail, 0xa0000, 0x20000);
2681 		(void) memlist_remove(pmem_avail, 0xa0000, 0x20000);
2682 		memlist_insert(mem_used, 0xa0000, 0x20000);
2683 		pci_bus_res[bus].mem_size += 0x20000;
2684 	}
2685 
2686 	/* add the hard-decode, aliased address spaces for 8514 */
2687 	if ((baseclass == PCI_CLASS_DISPLAY) &&
2688 	    (subclass == PCI_DISPLAY_VGA) &&
2689 	    (progclass & PCI_DISPLAY_IF_8514)) {
2690 
2691 		/* hard decode 0x2e8 */
2692 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2693 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2694 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8;
2695 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1;
2696 		nreg++, nasgn++;
2697 		(void) memlist_remove(io_avail, 0x2e8, 0x1);
2698 		memlist_insert(io_used, 0x2e8, 0x1);
2699 		pci_bus_res[bus].io_size += 0x1;
2700 
2701 		/* hard decode 0x2ea-0x2ef */
2702 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
2703 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
2704 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea;
2705 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6;
2706 		nreg++, nasgn++;
2707 		(void) memlist_remove(io_avail, 0x2ea, 0x6);
2708 		memlist_insert(io_used, 0x2ea, 0x6);
2709 		pci_bus_res[bus].io_size += 0x6;
2710 	}
2711 
2712 done:
2713 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg",
2714 	    (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int));
2715 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
2716 	    "assigned-addresses",
2717 	    (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int));
2718 
2719 	return (reprogram);
2720 }
2721 
2722 static void
2723 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func,
2724     int pciex, ushort_t is_pci_bridge)
2725 {
2726 	char *dev_type;
2727 	int i;
2728 	uint_t val, io_range[2], mem_range[2], pmem_range[2];
2729 	uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS);
2730 	uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
2731 	uchar_t progclass;
2732 
2733 	ASSERT(secbus <= subbus);
2734 
2735 	/*
2736 	 * Check if it's a subtractive PPB.
2737 	 */
2738 	progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS);
2739 	if (progclass == PCI_BRIDGE_PCI_IF_SUBDECODE)
2740 		pci_bus_res[secbus].subtractive = B_TRUE;
2741 
2742 	/*
2743 	 * Some BIOSes lie about max pci busses, we allow for
2744 	 * such mistakes here
2745 	 */
2746 	if (subbus > pci_bios_maxbus) {
2747 		pci_bios_maxbus = subbus;
2748 		alloc_res_array();
2749 	}
2750 
2751 	ASSERT(pci_bus_res[secbus].dip == NULL);
2752 	pci_bus_res[secbus].dip = dip;
2753 	pci_bus_res[secbus].par_bus = bus;
2754 
2755 	dev_type = (pciex && !is_pci_bridge) ? "pciex" : "pci";
2756 
2757 	/* setup bus number hierarchy */
2758 	pci_bus_res[secbus].sub_bus = subbus;
2759 	/*
2760 	 * Keep track of the largest subordinate bus number (this is essential
2761 	 * for peer busses because there is no other way of determining its
2762 	 * subordinate bus number).
2763 	 */
2764 	if (subbus > pci_bus_res[bus].sub_bus)
2765 		pci_bus_res[bus].sub_bus = subbus;
2766 	/*
2767 	 * Loop through subordinate busses, initializing their parent bus
2768 	 * field to this bridge's parent.  The subordinate busses' parent
2769 	 * fields may very well be further refined later, as child bridges
2770 	 * are enumerated.  (The value is to note that the subordinate busses
2771 	 * are not peer busses by changing their par_bus fields to anything
2772 	 * other than -1.)
2773 	 */
2774 	for (i = secbus + 1; i <= subbus; i++)
2775 		pci_bus_res[i].par_bus = bus;
2776 
2777 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
2778 	    "device_type", dev_type);
2779 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2780 	    "#address-cells", 3);
2781 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2782 	    "#size-cells", 2);
2783 
2784 	/*
2785 	 * Collect bridge window specifications, and use them to populate
2786 	 * the "avail" resources for the bus.  Not all of those resources will
2787 	 * end up being available; this is done top-down, and so the initial
2788 	 * collection of windows populates the 'ranges' property for the
2789 	 * bus node.  Later, as children are found, resources are removed from
2790 	 * the 'avail' list, so that it becomes the freelist for
2791 	 * this point in the tree.  ranges may be set again after bridge
2792 	 * reprogramming in fix_ppb_res(), in which case it's set from
2793 	 * used + avail.
2794 	 *
2795 	 * According to PPB spec, the base register should be programmed
2796 	 * with a value bigger than the limit register when there are
2797 	 * no resources available. This applies to io, memory, and
2798 	 * prefetchable memory.
2799 	 */
2800 
2801 	/*
2802 	 * io range
2803 	 * We determine i/o windows that are left unconfigured by BIOS
2804 	 * through its i/o enable bit as Microsoft recommends OEMs to do.
2805 	 * If it is unset, we disable i/o and mark it for reconfiguration in
2806 	 * later passes by setting the base > limit
2807 	 */
2808 	val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM);
2809 	if (val & PCI_COMM_IO) {
2810 		val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW);
2811 		io_range[0] = ((val & 0xf0) << 8);
2812 		val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW);
2813 		io_range[1]  = ((val & 0xf0) << 8) | 0xFFF;
2814 	} else {
2815 		io_range[0] = 0x9fff;
2816 		io_range[1] = 0x1000;
2817 		pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW,
2818 		    (uint8_t)((io_range[0] >> 8) & 0xf0));
2819 		pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW,
2820 		    (uint8_t)((io_range[1] >> 8) & 0xf0));
2821 		pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0);
2822 		pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0);
2823 	}
2824 
2825 	if (io_range[0] != 0 && io_range[0] < io_range[1]) {
2826 		memlist_insert(&pci_bus_res[secbus].io_avail,
2827 		    (uint64_t)io_range[0],
2828 		    (uint64_t)(io_range[1] - io_range[0] + 1));
2829 		memlist_insert(&pci_bus_res[bus].io_used,
2830 		    (uint64_t)io_range[0],
2831 		    (uint64_t)(io_range[1] - io_range[0] + 1));
2832 		if (pci_bus_res[bus].io_avail != NULL) {
2833 			(void) memlist_remove(&pci_bus_res[bus].io_avail,
2834 			    (uint64_t)io_range[0],
2835 			    (uint64_t)(io_range[1] - io_range[0] + 1));
2836 		}
2837 		dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x",
2838 		    secbus, io_range[0], io_range[1]);
2839 		/* if 32-bit supported, make sure upper bits are not set */
2840 		if ((val & 0xf) == 1 &&
2841 		    pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) {
2842 			cmn_err(CE_NOTE, "unsupported 32-bit IO address on"
2843 			    " pci-pci bridge [%d/%d/%d]", bus, dev, func);
2844 		}
2845 	}
2846 
2847 	/* mem range */
2848 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE);
2849 	mem_range[0] = ((val & 0xFFF0) << 16);
2850 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT);
2851 	mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF;
2852 	if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) {
2853 		memlist_insert(&pci_bus_res[secbus].mem_avail,
2854 		    (uint64_t)mem_range[0],
2855 		    (uint64_t)(mem_range[1] - mem_range[0] + 1));
2856 		memlist_insert(&pci_bus_res[bus].mem_used,
2857 		    (uint64_t)mem_range[0],
2858 		    (uint64_t)(mem_range[1] - mem_range[0] + 1));
2859 		/* remove from parent resource list */
2860 		(void) memlist_remove(&pci_bus_res[bus].mem_avail,
2861 		    (uint64_t)mem_range[0],
2862 		    (uint64_t)(mem_range[1] - mem_range[0] + 1));
2863 		(void) memlist_remove(&pci_bus_res[bus].pmem_avail,
2864 		    (uint64_t)mem_range[0],
2865 		    (uint64_t)(mem_range[1] - mem_range[0] + 1));
2866 		dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x",
2867 		    secbus, mem_range[0], mem_range[1]);
2868 	}
2869 
2870 	/* prefetchable memory range */
2871 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW);
2872 	pmem_range[0] = ((val & 0xFFF0) << 16);
2873 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW);
2874 	pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF;
2875 	if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) {
2876 		memlist_insert(&pci_bus_res[secbus].pmem_avail,
2877 		    (uint64_t)pmem_range[0],
2878 		    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
2879 		memlist_insert(&pci_bus_res[bus].pmem_used,
2880 		    (uint64_t)pmem_range[0],
2881 		    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
2882 		/* remove from parent resource list */
2883 		(void) memlist_remove(&pci_bus_res[bus].pmem_avail,
2884 		    (uint64_t)pmem_range[0],
2885 		    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
2886 		(void) memlist_remove(&pci_bus_res[bus].mem_avail,
2887 		    (uint64_t)pmem_range[0],
2888 		    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
2889 		dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x",
2890 		    secbus, pmem_range[0], pmem_range[1]);
2891 		/* if 64-bit supported, make sure upper bits are not set */
2892 		if ((val & 0xf) == 1 &&
2893 		    pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) {
2894 			cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on"
2895 			    " pci-pci bridge [%d/%d/%d]", bus, dev, func);
2896 		}
2897 	}
2898 
2899 	/*
2900 	 * Add VGA legacy resources to the bridge's pci_bus_res if it
2901 	 * has VGA_ENABLE set.  Note that we put them in 'avail',
2902 	 * because that's used to populate the ranges prop; they'll be
2903 	 * removed from there by the VGA device once it's found.  Also,
2904 	 * remove them from the parent's available list and note them as
2905 	 * used in the parent.
2906 	 */
2907 
2908 	if (pci_getw(bus, dev, func, PCI_BCNF_BCNTRL) &
2909 	    PCI_BCNF_BCNTRL_VGA_ENABLE) {
2910 
2911 		memlist_insert(&pci_bus_res[secbus].io_avail, 0x3b0, 0xc);
2912 
2913 		memlist_insert(&pci_bus_res[bus].io_used, 0x3b0, 0xc);
2914 		if (pci_bus_res[bus].io_avail != NULL) {
2915 			(void) memlist_remove(&pci_bus_res[bus].io_avail,
2916 			    0x3b0, 0xc);
2917 		}
2918 
2919 		memlist_insert(&pci_bus_res[secbus].io_avail, 0x3c0, 0x20);
2920 
2921 		memlist_insert(&pci_bus_res[bus].io_used, 0x3c0, 0x20);
2922 		if (pci_bus_res[bus].io_avail != NULL) {
2923 			(void) memlist_remove(&pci_bus_res[bus].io_avail,
2924 			    0x3c0, 0x20);
2925 		}
2926 
2927 		memlist_insert(&pci_bus_res[secbus].mem_avail, 0xa0000,
2928 		    0x20000);
2929 
2930 		memlist_insert(&pci_bus_res[bus].mem_used, 0xa0000, 0x20000);
2931 		if (pci_bus_res[bus].mem_avail != NULL) {
2932 			(void) memlist_remove(&pci_bus_res[bus].mem_avail,
2933 			    0xa0000, 0x20000);
2934 		}
2935 	}
2936 	add_bus_range_prop(secbus);
2937 	add_ranges_prop(secbus, 1);
2938 }
2939 
2940 extern const struct pci_class_strings_s class_pci[];
2941 extern int class_pci_items;
2942 
2943 static void
2944 add_model_prop(dev_info_t *dip, uint_t classcode)
2945 {
2946 	const char *desc;
2947 	int i;
2948 	uchar_t baseclass = classcode >> 16;
2949 	uchar_t subclass = (classcode >> 8) & 0xff;
2950 	uchar_t progclass = classcode & 0xff;
2951 
2952 	if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) {
2953 		desc = "IDE controller";
2954 	} else {
2955 		for (desc = 0, i = 0; i < class_pci_items; i++) {
2956 			if ((baseclass == class_pci[i].base_class) &&
2957 			    (subclass == class_pci[i].sub_class) &&
2958 			    (progclass == class_pci[i].prog_class)) {
2959 				desc = class_pci[i].actual_desc;
2960 				break;
2961 			}
2962 		}
2963 		if (i == class_pci_items)
2964 			desc = "Unknown class of pci/pnpbios device";
2965 	}
2966 
2967 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model",
2968 	    (char *)desc);
2969 }
2970 
2971 static void
2972 add_bus_range_prop(int bus)
2973 {
2974 	int bus_range[2];
2975 
2976 	if (pci_bus_res[bus].dip == NULL)
2977 		return;
2978 	bus_range[0] = bus;
2979 	bus_range[1] = pci_bus_res[bus].sub_bus;
2980 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip,
2981 	    "bus-range", (int *)bus_range, 2);
2982 }
2983 
2984 /*
2985  * Add slot-names property for any named pci hot-plug slots
2986  */
2987 static void
2988 add_bus_slot_names_prop(int bus)
2989 {
2990 	char slotprop[256];
2991 	int len;
2992 
2993 	if (pci_bus_res[bus].dip != NULL) {
2994 		/* simply return if the property is already defined */
2995 		if (ddi_prop_exists(DDI_DEV_T_ANY, pci_bus_res[bus].dip,
2996 		    DDI_PROP_DONTPASS, "slot-names"))
2997 			return;
2998 	}
2999 
3000 	len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop));
3001 	if (len > 0) {
3002 		/*
3003 		 * Only create a peer bus node if this bus may be a peer bus.
3004 		 * It may be a peer bus if the dip is NULL and if par_bus is
3005 		 * -1 (par_bus is -1 if this bus was not found to be
3006 		 * subordinate to any PCI-PCI bridge).
3007 		 * If it's not a peer bus, then the ACPI BBN-handling code
3008 		 * will remove it later.
3009 		 */
3010 		if (pci_bus_res[bus].par_bus == (uchar_t)-1 &&
3011 		    pci_bus_res[bus].dip == NULL) {
3012 
3013 			create_root_bus_dip(bus);
3014 		}
3015 		if (pci_bus_res[bus].dip != NULL) {
3016 			ASSERT((len % sizeof (int)) == 0);
3017 			(void) ndi_prop_update_int_array(DDI_DEV_T_NONE,
3018 			    pci_bus_res[bus].dip, "slot-names",
3019 			    (int *)slotprop, len / sizeof (int));
3020 		} else {
3021 			cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI "
3022 			    "IRQ routing table; Not adding slot-names "
3023 			    "property for incorrect bus %d", bus);
3024 		}
3025 	}
3026 }
3027 
3028 /*
3029  * Handle both PCI root and PCI-PCI bridge range properties;
3030  * non-zero 'ppb' argument select PCI-PCI bridges versus root.
3031  */
3032 static void
3033 memlist_to_ranges(void **rp, struct memlist *entry, int type, int ppb)
3034 {
3035 	ppb_ranges_t *ppb_rp = *rp;
3036 	pci_ranges_t *pci_rp = *rp;
3037 
3038 	while (entry != NULL) {
3039 		if (ppb) {
3040 			ppb_rp->child_high = ppb_rp->parent_high = type;
3041 			ppb_rp->child_mid = ppb_rp->parent_mid =
3042 			    (uint32_t)(entry->address >> 32); /* XXX */
3043 			ppb_rp->child_low = ppb_rp->parent_low =
3044 			    (uint32_t)entry->address;
3045 			ppb_rp->size_high =
3046 			    (uint32_t)(entry->size >> 32); /* XXX */
3047 			ppb_rp->size_low = (uint32_t)entry->size;
3048 			*rp = ++ppb_rp;
3049 		} else {
3050 			pci_rp->child_high = type;
3051 			pci_rp->child_mid = pci_rp->parent_high =
3052 			    (uint32_t)(entry->address >> 32); /* XXX */
3053 			pci_rp->child_low = pci_rp->parent_low =
3054 			    (uint32_t)entry->address;
3055 			pci_rp->size_high =
3056 			    (uint32_t)(entry->size >> 32); /* XXX */
3057 			pci_rp->size_low = (uint32_t)entry->size;
3058 			*rp = ++pci_rp;
3059 		}
3060 		entry = entry->next;
3061 	}
3062 }
3063 
3064 static void
3065 add_ranges_prop(int bus, int ppb)
3066 {
3067 	int total, alloc_size;
3068 	void	*rp, *next_rp;
3069 	struct memlist *iolist, *memlist, *pmemlist;
3070 
3071 	/* no devinfo node - unused bus, return */
3072 	if (pci_bus_res[bus].dip == NULL)
3073 		return;
3074 
3075 	iolist = memlist = pmemlist = (struct memlist *)NULL;
3076 
3077 	memlist_merge(&pci_bus_res[bus].io_avail, &iolist);
3078 	memlist_merge(&pci_bus_res[bus].io_used, &iolist);
3079 	memlist_merge(&pci_bus_res[bus].mem_avail, &memlist);
3080 	memlist_merge(&pci_bus_res[bus].mem_used, &memlist);
3081 	memlist_merge(&pci_bus_res[bus].pmem_avail, &pmemlist);
3082 	memlist_merge(&pci_bus_res[bus].pmem_used, &pmemlist);
3083 
3084 	total = memlist_count(iolist);
3085 	total += memlist_count(memlist);
3086 	total += memlist_count(pmemlist);
3087 
3088 	/* no property is created if no ranges are present */
3089 	if (total == 0)
3090 		return;
3091 
3092 	alloc_size = total *
3093 	    (ppb ? sizeof (ppb_ranges_t) : sizeof (pci_ranges_t));
3094 
3095 	next_rp = rp = kmem_alloc(alloc_size, KM_SLEEP);
3096 
3097 	memlist_to_ranges(&next_rp, iolist, PCI_ADDR_IO | PCI_REG_REL_M, ppb);
3098 	memlist_to_ranges(&next_rp, memlist,
3099 	    PCI_ADDR_MEM32 | PCI_REG_REL_M, ppb);
3100 	memlist_to_ranges(&next_rp, pmemlist,
3101 	    PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M, ppb);
3102 
3103 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip,
3104 	    "ranges", (int *)rp, alloc_size / sizeof (int));
3105 
3106 	kmem_free(rp, alloc_size);
3107 	memlist_free_all(&iolist);
3108 	memlist_free_all(&memlist);
3109 	memlist_free_all(&pmemlist);
3110 }
3111 
3112 static void
3113 memlist_remove_list(struct memlist **list, struct memlist *remove_list)
3114 {
3115 	while (list && *list && remove_list) {
3116 		(void) memlist_remove(list, remove_list->address,
3117 		    remove_list->size);
3118 		remove_list = remove_list->next;
3119 	}
3120 }
3121 
3122 static int
3123 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type)
3124 {
3125 	int i = 0;
3126 
3127 	while (list) {
3128 		/* assume 32-bit addresses */
3129 		sp->pci_phys_hi = type;
3130 		sp->pci_phys_mid = 0;
3131 		sp->pci_phys_low = (uint32_t)list->address;
3132 		sp->pci_size_hi = 0;
3133 		sp->pci_size_low = (uint32_t)list->size;
3134 
3135 		list = list->next;
3136 		sp++, i++;
3137 	}
3138 	return (i);
3139 }
3140 
3141 static void
3142 add_bus_available_prop(int bus)
3143 {
3144 	int i, count;
3145 	struct pci_phys_spec *sp;
3146 
3147 	/* no devinfo node - unused bus, return */
3148 	if (pci_bus_res[bus].dip == NULL)
3149 		return;
3150 
3151 	count = memlist_count(pci_bus_res[bus].io_avail) +
3152 	    memlist_count(pci_bus_res[bus].mem_avail) +
3153 	    memlist_count(pci_bus_res[bus].pmem_avail);
3154 
3155 	if (count == 0)		/* nothing available */
3156 		return;
3157 
3158 	sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP);
3159 	i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_avail,
3160 	    PCI_ADDR_IO | PCI_REG_REL_M);
3161 	i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_avail,
3162 	    PCI_ADDR_MEM32 | PCI_REG_REL_M);
3163 	i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_avail,
3164 	    PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M);
3165 	ASSERT(i == count);
3166 
3167 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip,
3168 	    "available", (int *)sp,
3169 	    i * sizeof (struct pci_phys_spec) / sizeof (int));
3170 	kmem_free(sp, count * sizeof (*sp));
3171 }
3172 
3173 static void
3174 alloc_res_array(void)
3175 {
3176 	static int array_max = 0;
3177 	int old_max;
3178 	void *old_res;
3179 
3180 	if (array_max > pci_bios_maxbus + 1)
3181 		return;	/* array is big enough */
3182 
3183 	old_max = array_max;
3184 	old_res = pci_bus_res;
3185 
3186 	if (array_max == 0)
3187 		array_max = 16;	/* start with a reasonable number */
3188 
3189 	while (array_max < pci_bios_maxbus + 1)
3190 		array_max <<= 1;
3191 	pci_bus_res = (struct pci_bus_resource *)kmem_zalloc(
3192 	    array_max * sizeof (struct pci_bus_resource), KM_SLEEP);
3193 
3194 	if (old_res) {	/* copy content and free old array */
3195 		bcopy(old_res, pci_bus_res,
3196 		    old_max * sizeof (struct pci_bus_resource));
3197 		kmem_free(old_res, old_max * sizeof (struct pci_bus_resource));
3198 	}
3199 }
3200 
3201 static void
3202 create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid,
3203     ushort_t deviceid)
3204 {
3205 	static dev_info_t *ioapicsnode = NULL;
3206 	static int numioapics = 0;
3207 	dev_info_t *ioapic_node;
3208 	uint64_t physaddr;
3209 	uint32_t lobase, hibase = 0;
3210 
3211 	/* BAR 0 contains the IOAPIC's memory-mapped I/O address */
3212 	lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0);
3213 
3214 	/* We (and the rest of the world) only support memory-mapped IOAPICs */
3215 	if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM)
3216 		return;
3217 
3218 	if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL)
3219 		hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4);
3220 
3221 	lobase &= PCI_BASE_M_ADDR_M;
3222 
3223 	physaddr = (((uint64_t)hibase) << 32) | lobase;
3224 
3225 	/*
3226 	 * Create a nexus node for all IOAPICs under the root node.
3227 	 */
3228 	if (ioapicsnode == NULL) {
3229 		if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME,
3230 		    (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) {
3231 			return;
3232 		}
3233 		(void) ndi_devi_online(ioapicsnode, 0);
3234 	}
3235 
3236 	/*
3237 	 * Create a child node for this IOAPIC
3238 	 */
3239 	ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME,
3240 	    DEVI_SID_NODEID, numioapics++);
3241 	if (ioapic_node == NULL) {
3242 		return;
3243 	}
3244 
3245 	/* Vendor and Device ID */
3246 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node,
3247 	    IOAPICS_PROP_VENID, vendorid);
3248 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node,
3249 	    IOAPICS_PROP_DEVID, deviceid);
3250 
3251 	/* device_type */
3252 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node,
3253 	    "device_type", IOAPICS_DEV_TYPE);
3254 
3255 	/* reg */
3256 	(void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node,
3257 	    "reg", physaddr);
3258 }
3259 
3260 /*
3261  * NOTE: For PCIe slots, the name is generated from the slot number
3262  * information obtained from Slot Capabilities register.
3263  * For non-PCIe slots, it is generated based on the slot number
3264  * information in the PCI IRQ table.
3265  */
3266 static void
3267 pciex_slot_names_prop(dev_info_t *dip, ushort_t slot_num)
3268 {
3269 	char slotprop[256];
3270 	int len;
3271 
3272 	bzero(slotprop, sizeof (slotprop));
3273 
3274 	/* set mask to 1 as there is only one slot (i.e dev 0) */
3275 	*(uint32_t *)slotprop = 1;
3276 	len = 4;
3277 	(void) snprintf(slotprop + len, sizeof (slotprop) - len, "pcie%d",
3278 	    slot_num);
3279 	len += strlen(slotprop + len) + 1;
3280 	len += len % 4;
3281 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "slot-names",
3282 	    (int *)slotprop, len / sizeof (int));
3283 }
3284