1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/types.h> 27 #include <sys/stat.h> 28 #include <sys/sunndi.h> 29 #include <sys/pci.h> 30 #include <sys/pci_impl.h> 31 #include <sys/pci_cfgspace.h> 32 #include <sys/memlist.h> 33 #include <sys/bootconf.h> 34 #include <io/pci/mps_table.h> 35 #include <sys/pci_cfgspace.h> 36 #include <sys/pci_cfgspace_impl.h> 37 #include <sys/psw.h> 38 #include "../../../../common/pci/pci_strings.h" 39 #include <sys/apic.h> 40 #include <io/pciex/pcie_nvidia.h> 41 #include <io/hotplug/pciehpc/pciehpc_acpi.h> 42 #include <sys/acpi/acpi.h> 43 #include <sys/acpica.h> 44 #include <sys/intel_iommu.h> 45 #include <sys/iommulib.h> 46 47 #define pci_getb (*pci_getb_func) 48 #define pci_getw (*pci_getw_func) 49 #define pci_getl (*pci_getl_func) 50 #define pci_putb (*pci_putb_func) 51 #define pci_putw (*pci_putw_func) 52 #define pci_putl (*pci_putl_func) 53 #define dcmn_err if (pci_boot_debug) cmn_err 54 55 #define CONFIG_INFO 0 56 #define CONFIG_UPDATE 1 57 #define CONFIG_NEW 2 58 #define CONFIG_FIX 3 59 #define COMPAT_BUFSIZE 512 60 61 #define PPB_IO_ALIGNMENT 0x1000 /* 4K aligned */ 62 #define PPB_MEM_ALIGNMENT 0x100000 /* 1M aligned */ 63 64 /* See AMD-8111 Datasheet Rev 3.03, Page 149: */ 65 #define LPC_IO_CONTROL_REG_1 0x40 66 #define AMD8111_ENABLENMI (uint8_t)0x80 67 #define DEVID_AMD8111_LPC 0x7468 68 69 struct pci_fixundo { 70 uint8_t bus; 71 uint8_t dev; 72 uint8_t fn; 73 void (*undofn)(uint8_t, uint8_t, uint8_t); 74 struct pci_fixundo *next; 75 }; 76 77 struct pci_devfunc { 78 struct pci_devfunc *next; 79 dev_info_t *dip; 80 uchar_t dev; 81 uchar_t func; 82 boolean_t reprogram; /* this device needs to be reprogrammed */ 83 }; 84 85 extern int pci_bios_nbus; 86 static uchar_t max_dev_pci = 32; /* PCI standard */ 87 int pci_boot_debug = 0; 88 extern struct memlist *find_bus_res(int, int); 89 static struct pci_fixundo *undolist = NULL; 90 static int num_root_bus = 0; /* count of root buses */ 91 92 /* 93 * Module prototypes 94 */ 95 static void enumerate_bus_devs(uchar_t bus, int config_op); 96 static void create_root_bus_dip(uchar_t bus); 97 static void process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t, 98 ushort_t, int); 99 static void add_compatible(dev_info_t *, ushort_t, ushort_t, 100 ushort_t, ushort_t, uchar_t, uint_t, int); 101 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 102 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, 103 ushort_t); 104 static void add_model_prop(dev_info_t *, uint_t); 105 static void add_bus_range_prop(int); 106 static void add_bus_slot_names_prop(int); 107 static void add_ppb_ranges_prop(int); 108 static void add_bus_available_prop(int); 109 static int get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id); 110 static void fix_ppb_res(uchar_t, boolean_t); 111 static void alloc_res_array(); 112 static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 113 ushort_t deviceid); 114 static void pciex_slot_names_prop(dev_info_t *, ushort_t); 115 116 extern int pci_slot_names_prop(int, char *, int); 117 118 /* set non-zero to force PCI peer-bus renumbering */ 119 int pci_bus_always_renumber = 0; 120 121 /* get the subordinate bus # for a root/peer bus */ 122 static int 123 pci_root_subbus(int bus, uchar_t *subbus) 124 { 125 ACPI_HANDLE hdl; 126 ACPI_BUFFER rb; 127 ACPI_RESOURCE *rp; 128 int rv; 129 130 if (pci_bus_res[bus].dip == NULL) { 131 /* non-used bus # */ 132 return (AE_ERROR); 133 } 134 if (acpica_get_handle(pci_bus_res[bus].dip, &hdl) != AE_OK) { 135 cmn_err(CE_WARN, "!No ACPI obj for bus%d, ACPI OFF?\n", bus); 136 return (AE_ERROR); 137 } 138 139 rb.Length = ACPI_ALLOCATE_BUFFER; 140 if (AcpiGetCurrentResources(hdl, &rb) != AE_OK) { 141 cmn_err(CE_WARN, "!_CRS failed on pci%d\n", bus); 142 return (AE_ERROR); 143 } 144 145 rv = AE_ERROR; 146 147 for (rp = rb.Pointer; rp->Type != ACPI_RESOURCE_TYPE_END_TAG; 148 rp = ACPI_NEXT_RESOURCE(rp)) { 149 150 switch (rp->Type) { 151 case ACPI_RESOURCE_TYPE_ADDRESS16: 152 if (rp->Data.Address.ResourceType != 153 ACPI_BUS_NUMBER_RANGE) 154 continue; 155 *subbus = (uchar_t)rp->Data.Address16.Maximum; 156 dcmn_err(CE_NOTE, "Address16,subbus=%d\n", *subbus); 157 break; 158 case ACPI_RESOURCE_TYPE_ADDRESS32: 159 if (rp->Data.Address.ResourceType != 160 ACPI_BUS_NUMBER_RANGE) 161 continue; 162 *subbus = (uchar_t)rp->Data.Address32.Maximum; 163 dcmn_err(CE_NOTE, "Address32,subbus=%d\n", *subbus); 164 break; 165 case ACPI_RESOURCE_TYPE_ADDRESS64: 166 if (rp->Data.Address.ResourceType != 167 ACPI_BUS_NUMBER_RANGE) 168 continue; 169 *subbus = (uchar_t)rp->Data.Address64.Maximum; 170 dcmn_err(CE_NOTE, "Address64,subbus=%d\n", *subbus); 171 break; 172 case ACPI_RESOURCE_TYPE_EXTENDED_ADDRESS64: 173 if (rp->Data.Address.ResourceType != 174 ACPI_BUS_NUMBER_RANGE) 175 continue; 176 *subbus = (uchar_t)rp->Data.ExtAddress64.Maximum; 177 dcmn_err(CE_NOTE, "ExtAdr64,subbus=%d\n", *subbus); 178 break; 179 default: 180 dcmn_err(CE_NOTE, "rp->Type=%d\n", rp->Type); 181 continue; 182 } 183 184 /* found the bus-range resource */ 185 dcmn_err(CE_NOTE, "pci%d, subbus=%d\n", bus, *subbus); 186 rv = AE_OK; 187 188 /* This breaks out of the resource scanning loop */ 189 break; 190 } 191 192 AcpiOsFree(rb.Pointer); 193 if (rv != AE_OK) 194 cmn_err(CE_NOTE, "!No bus-range resource for pci%d\n", bus); 195 196 return (rv); 197 198 } 199 200 /* 201 * Enumerate all PCI devices 202 */ 203 void 204 pci_setup_tree() 205 { 206 uchar_t i, root_bus_addr = 0; 207 208 alloc_res_array(); 209 for (i = 0; i <= pci_bios_nbus; i++) { 210 pci_bus_res[i].par_bus = (uchar_t)-1; 211 pci_bus_res[i].root_addr = (uchar_t)-1; 212 pci_bus_res[i].sub_bus = i; 213 } 214 215 pci_bus_res[0].root_addr = root_bus_addr++; 216 create_root_bus_dip(0); 217 enumerate_bus_devs(0, CONFIG_INFO); 218 219 /* 220 * Now enumerate peer busses 221 * 222 * We loop till pci_bios_nbus. On most systems, there is 223 * one more bus at the high end, which implements the ISA 224 * compatibility bus. We don't care about that. 225 * 226 * Note: In the old (bootconf) enumeration, the peer bus 227 * address did not use the bus number, and there were 228 * too many peer busses created. The root_bus_addr is 229 * used to maintain the old peer bus address assignment. 230 * However, we stop enumerating phantom peers with no 231 * device below. 232 */ 233 for (i = 1; i <= pci_bios_nbus; i++) { 234 if (pci_bus_res[i].dip == NULL) { 235 pci_bus_res[i].root_addr = root_bus_addr++; 236 } 237 enumerate_bus_devs(i, CONFIG_INFO); 238 239 /* add slot-names property for named pci hot-plug slots */ 240 add_bus_slot_names_prop(i); 241 } 242 243 } 244 245 /* 246 * >0 = present, 0 = not present, <0 = error 247 */ 248 static int 249 pci_bbn_present(int bus) 250 { 251 ACPI_HANDLE hdl; 252 int rv; 253 254 /* no dip means no _BBN */ 255 if (pci_bus_res[bus].dip == NULL) 256 return (0); 257 258 rv = -1; /* default return value in case of error below */ 259 if (ACPI_SUCCESS(acpica_get_handle(pci_bus_res[bus].dip, &hdl))) { 260 switch (AcpiEvaluateObject(hdl, "_BBN", NULL, NULL)) { 261 case AE_OK: 262 rv = 1; 263 break; 264 case AE_NOT_FOUND: 265 rv = 0; 266 break; 267 default: 268 break; 269 } 270 } 271 272 return (rv); 273 } 274 275 /* 276 * Return non-zero if any PCI bus in the system has an associated 277 * _BBN object, 0 otherwise. 278 */ 279 static int 280 pci_roots_have_bbn(void) 281 { 282 int i; 283 284 /* 285 * Scan the PCI busses and look for at least 1 _BBN 286 */ 287 for (i = 0; i <= pci_bios_nbus; i++) { 288 /* skip non-root (peer) PCI busses */ 289 if (pci_bus_res[i].par_bus != (uchar_t)-1) 290 continue; 291 292 if (pci_bbn_present(i) > 0) 293 return (1); 294 } 295 return (0); 296 297 } 298 299 /* 300 * return non-zero if the machine is one on which we renumber 301 * the internal pci unit-addresses 302 */ 303 static int 304 pci_bus_renumber() 305 { 306 ACPI_TABLE_HEADER *fadt; 307 308 if (pci_bus_always_renumber) 309 return (1); 310 311 /* get the FADT */ 312 if (AcpiGetTable(ACPI_SIG_FADT, 1, (ACPI_TABLE_HEADER **)&fadt) != 313 AE_OK) 314 return (0); 315 316 /* compare OEM Table ID to "SUNm31" */ 317 if (strncmp("SUNm31", fadt->OemId, 6)) 318 return (0); 319 else 320 return (1); 321 } 322 323 /* 324 * Initial enumeration of the physical PCI bus hierarchy can 325 * leave 'gaps' in the order of peer PCI bus unit-addresses. 326 * Systems with more than one peer PCI bus *must* have an ACPI 327 * _BBN object associated with each peer bus; use the presence 328 * of this object to remove gaps in the numbering of the peer 329 * PCI bus unit-addresses - only peer busses with an associated 330 * _BBN are counted. 331 */ 332 static void 333 pci_renumber_root_busses(void) 334 { 335 int pci_regs[] = {0, 0, 0}; 336 int i, root_addr = 0; 337 338 /* 339 * Currently, we only enable the re-numbering on specific 340 * Sun machines; this is a work-around for the more complicated 341 * issue of upgrade changing physical device paths 342 */ 343 if (!pci_bus_renumber()) 344 return; 345 346 /* 347 * If we find no _BBN objects at all, we either don't need 348 * to do anything or can't do anything anyway 349 */ 350 if (!pci_roots_have_bbn()) 351 return; 352 353 for (i = 0; i <= pci_bios_nbus; i++) { 354 /* skip non-root (peer) PCI busses */ 355 if (pci_bus_res[i].par_bus != (uchar_t)-1) 356 continue; 357 358 if (pci_bbn_present(i) < 1) { 359 pci_bus_res[i].root_addr = (uchar_t)-1; 360 continue; 361 } 362 363 ASSERT(pci_bus_res[i].dip != NULL); 364 if (pci_bus_res[i].root_addr != root_addr) { 365 /* update reg property for node */ 366 pci_bus_res[i].root_addr = root_addr; 367 pci_regs[0] = pci_bus_res[i].root_addr; 368 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 369 pci_bus_res[i].dip, "reg", (int *)pci_regs, 3); 370 } 371 root_addr++; 372 } 373 } 374 375 static void 376 remove_resource_range(struct memlist **list, int *ranges, int range_count) 377 { 378 struct range { 379 uint32_t base; 380 uint32_t len; 381 }; 382 int index; 383 384 for (index = 0; index < range_count; index++) { 385 /* all done if list is or has become empty */ 386 if (*list == NULL) 387 break; 388 (void) memlist_remove(list, 389 (uint64_t)((struct range *)ranges)[index].base, 390 (uint64_t)((struct range *)ranges)[index].len); 391 } 392 } 393 394 static void 395 remove_used_resources() 396 { 397 dev_info_t *used; 398 int *narray; 399 uint_t ncount; 400 int status; 401 int bus; 402 403 used = ddi_find_devinfo("used-resources", -1, 0); 404 if (used == NULL) 405 return; 406 407 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used, 408 DDI_PROP_DONTPASS, "io-space", &narray, &ncount); 409 if (status == DDI_PROP_SUCCESS) { 410 for (bus = 0; bus <= pci_bios_nbus; bus++) 411 remove_resource_range(&pci_bus_res[bus].io_ports, 412 narray, ncount / 2); 413 ddi_prop_free(narray); 414 } 415 416 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used, 417 DDI_PROP_DONTPASS, "device-memory", &narray, &ncount); 418 if (status == DDI_PROP_SUCCESS) { 419 for (bus = 0; bus <= pci_bios_nbus; bus++) 420 remove_resource_range(&pci_bus_res[bus].mem_space, 421 narray, ncount / 2); 422 ddi_prop_free(narray); 423 } 424 } 425 426 /* 427 * Remove the resources which are already used by devices under a subtractive 428 * bridge from the bus's resources lists, because they're not available, and 429 * shouldn't be allocated to other buses. This is necessary because tracking 430 * resources for subtractive bridges is not complete. (Subtractive bridges only 431 * track some of their claimed resources, not "the rest of the address space" as 432 * they should, so that allocation to peer non-subtractive PPBs is easier. We 433 * need a fully-capable global resource allocator). 434 */ 435 static void 436 remove_subtractive_res() 437 { 438 int i, j; 439 struct memlist *list; 440 441 for (i = 0; i <= pci_bios_nbus; i++) { 442 if (pci_bus_res[i].subtractive) { 443 /* remove used io ports */ 444 list = pci_bus_res[i].io_ports_used; 445 while (list) { 446 for (j = 0; j <= pci_bios_nbus; j++) { 447 if (pci_bus_res[j].io_ports) 448 (void) memlist_remove( 449 &pci_bus_res[j].io_ports, 450 list->address, list->size); 451 } 452 list = list->next; 453 } 454 /* remove used mem resource */ 455 list = pci_bus_res[i].mem_space_used; 456 while (list) { 457 for (j = 0; j <= pci_bios_nbus; j++) { 458 if (pci_bus_res[j].mem_space) 459 (void) memlist_remove( 460 &pci_bus_res[j].mem_space, 461 list->address, list->size); 462 if (pci_bus_res[j].pmem_space) 463 (void) memlist_remove( 464 &pci_bus_res[j].pmem_space, 465 list->address, list->size); 466 } 467 list = list->next; 468 } 469 /* remove used prefetchable mem resource */ 470 list = pci_bus_res[i].pmem_space_used; 471 while (list) { 472 for (j = 0; j <= pci_bios_nbus; j++) { 473 if (pci_bus_res[j].pmem_space) 474 (void) memlist_remove( 475 &pci_bus_res[j].pmem_space, 476 list->address, list->size); 477 if (pci_bus_res[j].mem_space) 478 (void) memlist_remove( 479 &pci_bus_res[j].mem_space, 480 list->address, list->size); 481 } 482 list = list->next; 483 } 484 } 485 } 486 } 487 488 /* Set up this bus's "bus_space" resource list */ 489 static void 490 setup_bus_res(int bus) 491 { 492 uchar_t par_bus; 493 uchar_t sub_bus; 494 495 if (pci_bus_res[bus].dip == NULL) /* unused bus */ 496 return; 497 498 sub_bus = pci_bus_res[bus].sub_bus; 499 ASSERT(sub_bus >= bus); 500 ASSERT(pci_bus_res[bus].bus_space == NULL); 501 if (sub_bus > bus) { 502 /* 503 * Keep the remaining available bus range in bus_space. 504 * ('bus' is already allocated) 505 */ 506 memlist_insert(&pci_bus_res[bus].bus_space, bus + 1, 507 sub_bus - bus); 508 } 509 510 /* 511 * Remove resources from parent bus node if this is not a 512 * root bus. 513 */ 514 par_bus = pci_bus_res[bus].par_bus; 515 if (par_bus != (uchar_t)-1) { 516 ASSERT(pci_bus_res[par_bus].bus_space != NULL); 517 (void) memlist_remove(&pci_bus_res[par_bus].bus_space, 518 bus, sub_bus - bus + 1); 519 } 520 } 521 522 static uint64_t 523 get_parbus_io_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 524 { 525 uint64_t addr = 0; 526 uchar_t res_bus; 527 528 /* 529 * Skip root(peer) buses in multiple-root-bus systems, as currently 530 * the initial resources set on each root bus might not be correctly 531 * accounted for. (We need to read resources from ACPI as well as 532 * the MP tables and hotplug tables.) 533 */ 534 if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 535 (num_root_bus > 1)) 536 return (0); 537 538 res_bus = parbus; 539 while (pci_bus_res[res_bus].subtractive) { 540 if (pci_bus_res[res_bus].io_ports) 541 break; 542 res_bus = pci_bus_res[res_bus].par_bus; 543 if (res_bus == (uchar_t)-1) 544 break; /* root bus already */ 545 } 546 547 if (pci_bus_res[res_bus].io_ports) { 548 addr = memlist_find(&pci_bus_res[res_bus].io_ports, 549 size, align); 550 if (addr) { 551 memlist_insert(&pci_bus_res[res_bus].io_ports_used, 552 addr, size); 553 /* free the old resource */ 554 memlist_free_all(&pci_bus_res[bus].io_ports); 555 /* add the new resource */ 556 memlist_insert(&pci_bus_res[bus].io_ports, addr, size); 557 } 558 } 559 560 return (addr); 561 } 562 563 static uint64_t 564 get_parbus_mem_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 565 { 566 uint64_t addr = 0; 567 uchar_t res_bus; 568 569 /* 570 * Skip root(peer) buses in multiple-root-bus systems, as currently 571 * the initial resources set on each root bus might not be correctly 572 * accounted for. (We need to read resources from ACPI as well as 573 * the MP tables and hotplug tables.) 574 */ 575 if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 576 (num_root_bus > 1)) 577 return (0); 578 579 res_bus = parbus; 580 while (pci_bus_res[res_bus].subtractive) { 581 if (pci_bus_res[res_bus].mem_space) 582 break; 583 res_bus = pci_bus_res[res_bus].par_bus; 584 if (res_bus == (uchar_t)-1) 585 break; /* root bus already */ 586 } 587 588 if (pci_bus_res[res_bus].mem_space) { 589 addr = memlist_find(&pci_bus_res[res_bus].mem_space, 590 size, align); 591 if (addr) { 592 memlist_insert(&pci_bus_res[res_bus].mem_space_used, 593 addr, size); 594 /* remove it from PMEM resource also */ 595 if (pci_bus_res[res_bus].pmem_space) 596 (void) memlist_remove( 597 &pci_bus_res[res_bus].pmem_space, 598 addr, size); 599 /* free the old resource */ 600 memlist_free_all(&pci_bus_res[bus].mem_space); 601 /* add the new resource */ 602 memlist_insert(&pci_bus_res[bus].mem_space, addr, size); 603 } 604 } 605 606 return (addr); 607 } 608 609 /* 610 * given a cap_id, return its cap_id location in config space 611 */ 612 static int 613 get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id) 614 { 615 uint8_t curcap, cap_id_loc; 616 uint16_t status; 617 int location = -1; 618 619 /* 620 * Need to check the Status register for ECP support first. 621 * Also please note that for type 1 devices, the 622 * offset could change. Should support type 1 next. 623 */ 624 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 625 if (!(status & PCI_STAT_CAP)) { 626 return (-1); 627 } 628 cap_id_loc = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 629 630 /* Walk the list of capabilities */ 631 while (cap_id_loc && cap_id_loc != (uint8_t)-1) { 632 curcap = pci_getb(bus, dev, func, cap_id_loc); 633 634 if (curcap == cap_id) { 635 location = cap_id_loc; 636 break; 637 } 638 cap_id_loc = pci_getb(bus, dev, func, cap_id_loc + 1); 639 } 640 return (location); 641 } 642 643 /* 644 * Assign valid resources to unconfigured pci(e) bridges. We are trying 645 * to reprogram the bridge when its 646 * i) SECBUS == SUBBUS || 647 * ii) IOBASE > IOLIM || 648 * iii) MEMBASE > MEMLIM 649 * This must be done after one full pass through the PCI tree to collect 650 * all BIOS-configured resources, so that we know what resources are 651 * free and available to assign to the unconfigured PPBs. 652 */ 653 static void 654 fix_ppb_res(uchar_t secbus, boolean_t prog_sub) 655 { 656 uchar_t bus, dev, func; 657 uchar_t parbus, subbus; 658 uint_t io_base, io_limit, mem_base, mem_limit; 659 uint_t io_size, mem_size; 660 uint64_t addr = 0; 661 int *regp = NULL; 662 uint_t reglen; 663 int rv, cap_ptr, physhi; 664 dev_info_t *dip; 665 uint16_t cmd_reg; 666 struct memlist *list; 667 668 /* skip root (peer) PCI busses */ 669 if (pci_bus_res[secbus].par_bus == (uchar_t)-1) 670 return; 671 672 /* skip subtractive PPB when prog_sub is not TRUE */ 673 if (pci_bus_res[secbus].subtractive && !prog_sub) 674 return; 675 676 /* some entries may be empty due to discontiguous bus numbering */ 677 dip = pci_bus_res[secbus].dip; 678 if (dip == NULL) 679 return; 680 681 rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 682 "reg", ®p, ®len); 683 ASSERT(rv == DDI_PROP_SUCCESS && reglen > 0); 684 physhi = regp[0]; 685 ddi_prop_free(regp); 686 687 func = (uchar_t)PCI_REG_FUNC_G(physhi); 688 dev = (uchar_t)PCI_REG_DEV_G(physhi); 689 bus = (uchar_t)PCI_REG_BUS_G(physhi); 690 691 /* 692 * If pcie bridge, check to see if link is enabled 693 */ 694 cap_ptr = get_pci_cap(bus, dev, func, PCI_CAP_ID_PCI_E); 695 if (cap_ptr != -1) { 696 cmd_reg = pci_getw(bus, dev, func, 697 (uint16_t)cap_ptr + PCIE_LINKCTL); 698 if (cmd_reg & PCIE_LINKCTL_LINK_DISABLE) { 699 dcmn_err(CE_NOTE, 700 "!fix_ppb_res: ppb[%x/%x/%x] link is disabled.\n", 701 bus, dev, func); 702 return; 703 } 704 } 705 706 subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 707 parbus = pci_bus_res[secbus].par_bus; 708 ASSERT(parbus == bus); 709 cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 710 711 /* 712 * If we have a Cardbus bridge, but no bus space 713 */ 714 if (pci_bus_res[secbus].num_cbb != 0 && 715 pci_bus_res[secbus].bus_space == NULL) { 716 uchar_t range; 717 718 /* normally there are 2 buses under a cardbus bridge */ 719 range = pci_bus_res[secbus].num_cbb * 2; 720 721 /* 722 * Try to find and allocate a bus-range starting at subbus+1 723 * from the parent of the PPB. 724 */ 725 for (; range != 0; range--) { 726 if (memlist_find_with_startaddr( 727 &pci_bus_res[parbus].bus_space, 728 subbus + 1, range, 1) != NULL) 729 break; /* find bus range resource at parent */ 730 } 731 if (range != 0) { 732 memlist_insert(&pci_bus_res[secbus].bus_space, 733 subbus + 1, range); 734 subbus = subbus + range; 735 pci_bus_res[secbus].sub_bus = subbus; 736 pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus); 737 add_bus_range_prop(secbus); 738 739 cmn_err(CE_NOTE, "!reprogram bus-range on ppb" 740 "[%x/%x/%x]: %x ~ %x\n", bus, dev, func, 741 secbus, subbus); 742 } 743 } 744 745 /* 746 * Calculate required IO size 747 * We are going to assign 512 bytes per bus. The size needs to be 748 * 4K aligned and the maximum size is 16K. 749 */ 750 io_size = (subbus - secbus + 1) * 0x200; 751 io_size = (io_size + PPB_IO_ALIGNMENT) & (~(PPB_IO_ALIGNMENT - 1)); 752 if (io_size > 0x4 * PPB_IO_ALIGNMENT) 753 io_size = 0x4 * PPB_IO_ALIGNMENT; 754 /* 755 * Calculate required MEM size 756 * We are going to assign 1M bytes per bus. The size needs to be 757 * 1M aligned and the maximum size is 8M. 758 */ 759 mem_size = (subbus - secbus + 1) * PPB_MEM_ALIGNMENT; 760 if (mem_size > 0x8 * PPB_MEM_ALIGNMENT) 761 mem_size = 0x8 * PPB_MEM_ALIGNMENT; 762 763 /* Subtractive bridge */ 764 if (pci_bus_res[secbus].subtractive && prog_sub) { 765 /* 766 * We program an arbitrary amount of I/O and memory resource 767 * for the subtractive bridge so that child dynamic-resource- 768 * allocating devices (such as Cardbus bridges) have a chance 769 * of success. Until we have full-tree resource rebalancing, 770 * dynamic resource allocation (thru busra) only looks at the 771 * parent bridge, so all PPBs must have some allocatable 772 * resource. For non-subtractive bridges, the resources come 773 * from the base/limit register "windows", but subtractive 774 * bridges often don't program those (since they don't need to). 775 * If we put all the remaining resources on the subtractive 776 * bridge, then peer non-subtractive bridges can't allocate 777 * more space (even though this is probably most correct). 778 * If we put the resources only on the parent, then allocations 779 * from children of subtractive bridges will fail without 780 * special-case code for bypassing the subtractive bridge. 781 * This solution is the middle-ground temporary solution until 782 * we have fully-capable resource allocation. 783 */ 784 785 /* 786 * Add an arbitrary I/O resource to the subtractive PPB 787 */ 788 if (pci_bus_res[secbus].io_ports == NULL) { 789 addr = get_parbus_io_res(parbus, secbus, io_size, 790 PPB_IO_ALIGNMENT); 791 if (addr) { 792 add_ppb_ranges_prop(secbus); 793 pci_bus_res[secbus].io_reprogram = 794 pci_bus_res[parbus].io_reprogram; 795 796 cmn_err(CE_NOTE, "!add io-range on subtractive" 797 " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 798 bus, dev, func, (uint32_t)addr, 799 (uint32_t)addr + io_size - 1); 800 } 801 } 802 /* 803 * Add an arbitrary memory resource to the subtractive PPB 804 */ 805 if (pci_bus_res[secbus].mem_space == NULL) { 806 addr = get_parbus_mem_res(parbus, secbus, mem_size, 807 PPB_MEM_ALIGNMENT); 808 if (addr) { 809 add_ppb_ranges_prop(secbus); 810 pci_bus_res[secbus].mem_reprogram = 811 pci_bus_res[parbus].mem_reprogram; 812 813 cmn_err(CE_NOTE, "!add mem-range on " 814 "subtractive ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 815 bus, dev, func, (uint32_t)addr, 816 (uint32_t)addr + mem_size - 1); 817 } 818 } 819 820 goto cmd_enable; 821 } 822 823 /* 824 * Check to see if we need to reprogram I/O space, either because the 825 * parent bus needed reprogramming and so do we, or because I/O space is 826 * disabled in base/limit or command register. 827 */ 828 io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 829 io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 830 io_base = (io_base & 0xf0) << 8; 831 io_limit = ((io_limit & 0xf0) << 8) | 0xfff; 832 833 if (pci_bus_res[parbus].io_reprogram || (io_base > io_limit) || 834 (!(cmd_reg & PCI_COMM_IO))) { 835 if (pci_bus_res[secbus].io_ports_used) { 836 memlist_merge(&pci_bus_res[secbus].io_ports_used, 837 &pci_bus_res[secbus].io_ports); 838 } 839 if (pci_bus_res[secbus].io_ports && 840 (!pci_bus_res[parbus].io_reprogram) && 841 (!pci_bus_res[parbus].subtractive)) { 842 /* rechoose old io ports info */ 843 list = pci_bus_res[secbus].io_ports; 844 io_base = (uint_t)list->address; 845 /* 4K aligned */ 846 io_base = io_base & (~(PPB_IO_ALIGNMENT - 1)); 847 io_limit = (uint_t)(list->address + list->size); 848 while (list->next) { 849 list = list->next; 850 if ((list->address + list->size) > io_limit) 851 io_limit = (uint_t) 852 (list->address + list->size); 853 } 854 io_limit = io_limit - 1; 855 /* 4K aligned */ 856 io_limit = (io_limit + PPB_IO_ALIGNMENT) & 857 (~(PPB_IO_ALIGNMENT - 1)); 858 io_size = io_limit - io_base; 859 io_limit = io_limit - 1; 860 ASSERT(io_base <= io_limit); 861 memlist_free_all(&pci_bus_res[secbus].io_ports); 862 memlist_insert(&pci_bus_res[secbus].io_ports, 863 io_base, io_size); 864 memlist_insert(&pci_bus_res[parbus].io_ports_used, 865 io_base, io_size); 866 if (pci_bus_res[parbus].io_ports) 867 (void) memlist_remove( 868 &pci_bus_res[parbus].io_ports, 869 io_base, io_size); 870 pci_bus_res[secbus].io_reprogram = B_TRUE; 871 } else { 872 /* get new io ports from parent bus */ 873 addr = get_parbus_io_res(parbus, secbus, io_size, 874 PPB_IO_ALIGNMENT); 875 if (addr) { 876 io_base = addr; 877 io_limit = addr + io_size - 1; 878 pci_bus_res[secbus].io_reprogram = B_TRUE; 879 } 880 } 881 if (pci_bus_res[secbus].io_reprogram) { 882 /* reprogram PPB regs */ 883 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 884 (uchar_t)((io_base>>8) & 0xf0)); 885 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 886 (uchar_t)((io_limit>>8) & 0xf0)); 887 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 888 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 889 add_ppb_ranges_prop(secbus); 890 891 cmn_err(CE_NOTE, "!reprogram io-range on" 892 " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 893 bus, dev, func, io_base, io_limit); 894 } 895 } 896 897 /* 898 * Check memory space as we did I/O space. 899 */ 900 mem_base = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 901 mem_base = (mem_base & 0xfff0) << 16; 902 mem_limit = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 903 mem_limit = ((mem_limit & 0xfff0) << 16) | 0xfffff; 904 905 if (pci_bus_res[parbus].mem_reprogram || (mem_base > mem_limit) || 906 (!(cmd_reg & PCI_COMM_MAE))) { 907 if (pci_bus_res[secbus].mem_space_used) { 908 memlist_merge(&pci_bus_res[secbus].mem_space_used, 909 &pci_bus_res[secbus].mem_space); 910 } 911 if (pci_bus_res[secbus].mem_space && 912 (!pci_bus_res[parbus].mem_reprogram) && 913 (!pci_bus_res[parbus].subtractive)) { 914 /* rechoose old mem resource */ 915 list = pci_bus_res[secbus].mem_space; 916 mem_base = (uint_t)list->address; 917 /* 1M aligned */ 918 mem_base = mem_base & (~0xfffff); 919 mem_limit = (uint_t)(list->address + list->size); 920 while (list->next) { 921 list = list->next; 922 if ((list->address + list->size) > mem_limit) 923 mem_limit = (uint_t) 924 (list->address + list->size); 925 } 926 mem_limit = mem_limit - 1; 927 /* 1M aligned */ 928 mem_limit = (mem_limit + PPB_MEM_ALIGNMENT) & 929 (~(PPB_MEM_ALIGNMENT - 1)); 930 mem_size = mem_limit - mem_base; 931 mem_limit = mem_limit - 1; 932 ASSERT(mem_base <= mem_limit); 933 memlist_free_all(&pci_bus_res[secbus].mem_space); 934 memlist_insert(&pci_bus_res[secbus].mem_space, 935 mem_base, mem_size); 936 memlist_insert(&pci_bus_res[parbus].mem_space_used, 937 mem_base, mem_size); 938 if (pci_bus_res[parbus].mem_space) 939 (void) memlist_remove( 940 &pci_bus_res[parbus].mem_space, 941 mem_base, mem_size); 942 pci_bus_res[secbus].mem_reprogram = B_TRUE; 943 } else { 944 /* get new mem resource from parent bus */ 945 addr = get_parbus_mem_res(parbus, secbus, mem_size, 946 PPB_MEM_ALIGNMENT); 947 if (addr) { 948 mem_base = addr; 949 mem_limit = addr + mem_size - 1; 950 pci_bus_res[secbus].mem_reprogram = B_TRUE; 951 } 952 } 953 954 if (pci_bus_res[secbus].mem_reprogram) { 955 /* reprogram PPB regs */ 956 pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE, 957 (uint16_t)((mem_base>>16) & 0xfff0)); 958 pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT, 959 (uint16_t)((mem_limit>>16) & 0xfff0)); 960 add_ppb_ranges_prop(secbus); 961 962 cmn_err(CE_NOTE, "!reprogram mem-range on" 963 " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 964 bus, dev, func, mem_base, mem_limit); 965 } 966 } 967 968 cmd_enable: 969 if (pci_bus_res[secbus].io_ports) 970 cmd_reg |= PCI_COMM_IO | PCI_COMM_ME; 971 if (pci_bus_res[secbus].mem_space) 972 cmd_reg |= PCI_COMM_MAE | PCI_COMM_ME; 973 pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 974 } 975 976 void 977 pci_reprogram(void) 978 { 979 int i, pci_reconfig = 1; 980 char *onoff; 981 982 /* 983 * Excise phantom roots if possible 984 */ 985 pci_renumber_root_busses(); 986 987 /* add bus-range property for root/peer bus nodes */ 988 for (i = 0; i <= pci_bios_nbus; i++) { 989 if (pci_bus_res[i].par_bus == (uchar_t)-1) { 990 uchar_t subbus; 991 if (pci_root_subbus(i, &subbus) == AE_OK) 992 pci_bus_res[i].sub_bus = subbus; 993 add_bus_range_prop(i); 994 } 995 /* setup bus range resource on each bus */ 996 setup_bus_res(i); 997 } 998 999 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 1000 DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 1001 if (strcmp(onoff, "off") == 0) { 1002 pci_reconfig = 0; 1003 cmn_err(CE_NOTE, "pci device reprogramming disabled"); 1004 } 1005 ddi_prop_free(onoff); 1006 } 1007 1008 /* remove used-resources from PCI resource maps */ 1009 remove_used_resources(); 1010 remove_subtractive_res(); 1011 1012 /* reprogram the non-subtractive PPB */ 1013 if (pci_reconfig) 1014 for (i = 0; i <= pci_bios_nbus; i++) 1015 fix_ppb_res(i, B_FALSE); 1016 1017 for (i = 0; i <= pci_bios_nbus; i++) { 1018 /* configure devices not configured by BIOS */ 1019 if (pci_reconfig) { 1020 /* 1021 * Reprogram the subtractive PPB. At this time, all its 1022 * siblings should have got their resources already. 1023 */ 1024 if (pci_bus_res[i].subtractive) 1025 fix_ppb_res(i, B_TRUE); 1026 enumerate_bus_devs(i, CONFIG_NEW); 1027 } 1028 /* All dev programmed, so we can create available prop */ 1029 add_bus_available_prop(i); 1030 } 1031 } 1032 1033 /* 1034 * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 1035 */ 1036 static void 1037 create_root_bus_dip(uchar_t bus) 1038 { 1039 int pci_regs[] = {0, 0, 0}; 1040 dev_info_t *dip; 1041 1042 ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 1043 1044 num_root_bus++; 1045 ndi_devi_alloc_sleep(ddi_root_node(), "pci", 1046 (pnode_t)DEVI_SID_NODEID, &dip); 1047 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1048 "#address-cells", 3); 1049 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1050 "#size-cells", 2); 1051 pci_regs[0] = pci_bus_res[bus].root_addr; 1052 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1053 "reg", (int *)pci_regs, 3); 1054 1055 /* 1056 * If system has PCIe bus, then create different properties 1057 */ 1058 if (create_pcie_root_bus(bus, dip) == B_FALSE) 1059 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1060 "device_type", "pci"); 1061 1062 (void) ndi_devi_bind_driver(dip, 0); 1063 pci_bus_res[bus].dip = dip; 1064 pci_bus_res[bus].pmem_space = find_bus_res(bus, PREFETCH_TYPE); 1065 pci_bus_res[bus].mem_space = find_bus_res(bus, MEM_TYPE); 1066 pci_bus_res[bus].io_ports = find_bus_res(bus, IO_TYPE); 1067 1068 if (bus != 0) 1069 return; 1070 1071 /* 1072 * Special treatment of bus 0: 1073 * If no resource from MPSPEC/HRT, copy pcimem from boot 1074 * and make I/O space the entire range starting at 0x100. There 1075 * is no difference between prefetchable memory or not. 1076 */ 1077 if (pci_bus_res[0].mem_space == NULL) 1078 pci_bus_res[0].mem_space = 1079 memlist_dup(bootops->boot_mem->pcimem); 1080 /* Exclude 0x00 to 0xff of the I/O space, used by all PCs */ 1081 if (pci_bus_res[0].io_ports == NULL) 1082 memlist_insert(&pci_bus_res[0].io_ports, 0x100, 0xffff); 1083 } 1084 1085 /* 1086 * For any fixed configuration (often compatability) pci devices 1087 * and those with their own expansion rom, create device nodes 1088 * to hold the already configured device details. 1089 */ 1090 void 1091 enumerate_bus_devs(uchar_t bus, int config_op) 1092 { 1093 uchar_t dev, func, nfunc, header; 1094 ushort_t venid; 1095 struct pci_devfunc *devlist = NULL, *entry; 1096 1097 if (config_op == CONFIG_NEW) { 1098 dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 1099 } else if (config_op == CONFIG_FIX) { 1100 dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus); 1101 } else 1102 dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 1103 1104 for (dev = 0; dev < max_dev_pci; dev++) { 1105 nfunc = 1; 1106 for (func = 0; func < nfunc; func++) { 1107 1108 dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", 1109 dev, func); 1110 1111 venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 1112 1113 if ((venid == 0xffff) || (venid == 0)) { 1114 /* no function at this address */ 1115 continue; 1116 } 1117 1118 header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 1119 if (header == 0xff) { 1120 continue; /* illegal value */ 1121 } 1122 1123 /* 1124 * according to some mail from Microsoft posted 1125 * to the pci-drivers alias, their only requirement 1126 * for a multifunction device is for the 1st 1127 * function to have to PCI_HEADER_MULTI bit set. 1128 */ 1129 if ((func == 0) && (header & PCI_HEADER_MULTI)) { 1130 nfunc = 8; 1131 } 1132 1133 if (config_op == CONFIG_FIX || 1134 config_op == CONFIG_INFO) { 1135 /* 1136 * Create the node, unconditionally, on the 1137 * first pass only. It may still need 1138 * resource assignment, which will be 1139 * done on the second, CONFIG_NEW, pass. 1140 */ 1141 process_devfunc(bus, dev, func, header, 1142 venid, config_op); 1143 1144 } 1145 } 1146 } 1147 1148 if (config_op == CONFIG_NEW) { 1149 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 1150 while (devlist) { 1151 entry = devlist; 1152 devlist = entry->next; 1153 if (entry->reprogram || 1154 pci_bus_res[bus].io_reprogram || 1155 pci_bus_res[bus].mem_reprogram) { 1156 /* reprogram device(s) */ 1157 (void) add_reg_props(entry->dip, bus, 1158 entry->dev, entry->func, CONFIG_NEW, 0); 1159 } 1160 kmem_free(entry, sizeof (*entry)); 1161 } 1162 pci_bus_res[bus].privdata = NULL; 1163 } 1164 } 1165 1166 static int 1167 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 1168 ushort_t subvenid, ushort_t subdevid) 1169 { 1170 static int prop_exist = -1; 1171 static char *pciide_str; 1172 char compat[32]; 1173 1174 if (prop_exist == -1) { 1175 prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 1176 ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 1177 &pciide_str) == DDI_SUCCESS); 1178 } 1179 1180 if (!prop_exist) 1181 return (0); 1182 1183 /* compare property value against various forms of compatible */ 1184 if (subvenid) { 1185 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 1186 venid, devid, subvenid, subdevid, revid); 1187 if (strcmp(pciide_str, compat) == 0) 1188 return (1); 1189 1190 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 1191 venid, devid, subvenid, subdevid); 1192 if (strcmp(pciide_str, compat) == 0) 1193 return (1); 1194 1195 (void) snprintf(compat, sizeof (compat), "pci%x,%x", 1196 subvenid, subdevid); 1197 if (strcmp(pciide_str, compat) == 0) 1198 return (1); 1199 } 1200 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 1201 venid, devid, revid); 1202 if (strcmp(pciide_str, compat) == 0) 1203 return (1); 1204 1205 (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 1206 if (strcmp(pciide_str, compat) == 0) 1207 return (1); 1208 1209 return (0); 1210 } 1211 1212 static int 1213 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 1214 ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 1215 { 1216 struct ide_table { /* table for PCI_MASS_OTHER */ 1217 ushort_t venid; 1218 ushort_t devid; 1219 } *entry; 1220 1221 /* XXX SATA and other devices: need a way to add dynamically */ 1222 static struct ide_table ide_other[] = { 1223 {0x1095, 0x3112}, 1224 {0x1095, 0x3114}, 1225 {0x1095, 0x3512}, 1226 {0x1095, 0x680}, /* Sil0680 */ 1227 {0x1283, 0x8211}, /* ITE 8211F is subcl PCI_MASS_OTHER */ 1228 {0, 0} 1229 }; 1230 1231 if (basecl != PCI_CLASS_MASS) 1232 return (0); 1233 1234 if (subcl == PCI_MASS_IDE) { 1235 return (1); 1236 } 1237 1238 if (check_pciide_prop(revid, venid, devid, subvenid, subdevid)) 1239 return (1); 1240 1241 if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 1242 return (0); 1243 } 1244 1245 entry = &ide_other[0]; 1246 while (entry->venid) { 1247 if (entry->venid == venid && entry->devid == devid) 1248 return (1); 1249 entry++; 1250 } 1251 return (0); 1252 } 1253 1254 static int 1255 is_display(uint_t classcode) 1256 { 1257 static uint_t disp_classes[] = { 1258 0x000100, 1259 0x030000, 1260 0x030001 1261 }; 1262 int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 1263 1264 for (i = 0; i < nclasses; i++) { 1265 if (classcode == disp_classes[i]) 1266 return (1); 1267 } 1268 return (0); 1269 } 1270 1271 static void 1272 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn, 1273 void (*undofn)(uint8_t, uint8_t, uint8_t)) 1274 { 1275 struct pci_fixundo *newundo; 1276 1277 newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP); 1278 1279 /* 1280 * Adding an item to this list means that we must turn its NMIENABLE 1281 * bit back on at a later time. 1282 */ 1283 newundo->bus = bus; 1284 newundo->dev = dev; 1285 newundo->fn = fn; 1286 newundo->undofn = undofn; 1287 newundo->next = undolist; 1288 1289 /* add to the undo list in LIFO order */ 1290 undolist = newundo; 1291 } 1292 1293 void 1294 add_pci_fixes(void) 1295 { 1296 int i; 1297 1298 for (i = 0; i <= pci_bios_nbus; i++) { 1299 /* 1300 * For each bus, apply needed fixes to the appropriate devices. 1301 * This must be done before the main enumeration loop because 1302 * some fixes must be applied to devices normally encountered 1303 * later in the pci scan (e.g. if a fix to device 7 must be 1304 * applied before scanning device 6, applying fixes in the 1305 * normal enumeration loop would obviously be too late). 1306 */ 1307 enumerate_bus_devs(i, CONFIG_FIX); 1308 } 1309 } 1310 1311 void 1312 undo_pci_fixes(void) 1313 { 1314 struct pci_fixundo *nextundo; 1315 uint8_t bus, dev, fn; 1316 1317 /* 1318 * All fixes in the undo list are performed unconditionally. Future 1319 * fixes may require selective undo. 1320 */ 1321 while (undolist != NULL) { 1322 1323 bus = undolist->bus; 1324 dev = undolist->dev; 1325 fn = undolist->fn; 1326 1327 (*(undolist->undofn))(bus, dev, fn); 1328 1329 nextundo = undolist->next; 1330 kmem_free(undolist, sizeof (struct pci_fixundo)); 1331 undolist = nextundo; 1332 } 1333 } 1334 1335 static void 1336 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn) 1337 { 1338 uint8_t val8; 1339 1340 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1341 /* 1342 * The NMIONERR bit is turned back on to allow the SMM BIOS 1343 * to handle more critical PCI errors (e.g. PERR#). 1344 */ 1345 val8 |= AMD8111_ENABLENMI; 1346 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1347 } 1348 1349 static void 1350 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn) 1351 { 1352 uint8_t val8; 1353 1354 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1355 1356 if ((val8 & AMD8111_ENABLENMI) == 0) 1357 return; 1358 1359 /* 1360 * We reset NMIONERR in the LPC because master-abort on the PCI 1361 * bridge side of the 8111 will cause NMI, which might cause SMI, 1362 * which sometimes prevents all devices from being enumerated. 1363 */ 1364 val8 &= ~AMD8111_ENABLENMI; 1365 1366 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1367 1368 add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix); 1369 } 1370 1371 static void 1372 set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func) 1373 { 1374 uint16_t status; 1375 uint8_t header; 1376 uint8_t cap_ptr; 1377 uint8_t cap_id; 1378 uint16_t pmcsr; 1379 1380 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 1381 if (!(status & PCI_STAT_CAP)) 1382 return; /* No capabilities list */ 1383 1384 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1385 if (header == PCI_HEADER_CARDBUS) 1386 cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_RESERVED1); 1387 else 1388 cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 1389 /* 1390 * Walk the capabilities list searching for a PM entry. 1391 */ 1392 while (cap_ptr != PCI_CAP_NEXT_PTR_NULL && cap_ptr >= PCI_CAP_PTR_OFF) { 1393 cap_ptr &= PCI_CAP_PTR_MASK; 1394 cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID); 1395 if (cap_id == PCI_CAP_ID_PM) { 1396 pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR); 1397 pmcsr &= ~(PCI_PMCSR_STATE_MASK); 1398 pmcsr |= PCI_PMCSR_D0; /* D0 state */ 1399 pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr); 1400 break; 1401 } 1402 cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR); 1403 } 1404 1405 } 1406 1407 static void 1408 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 1409 ushort_t vendorid, int config_op) 1410 { 1411 char nodename[32], unitaddr[5]; 1412 dev_info_t *dip; 1413 uchar_t basecl, subcl, progcl, intr, revid; 1414 ushort_t subvenid, subdevid, status; 1415 ushort_t slot_num; 1416 uint_t classcode, revclass; 1417 int reprogram = 0, pciide = 0; 1418 int power[2] = {1, 1}; 1419 int pciex = 0; 1420 ushort_t is_pci_bridge = 0; 1421 struct pci_devfunc *devlist = NULL, *entry = NULL; 1422 iommu_private_t *private; 1423 gfx_entry_t *gfxp; 1424 1425 ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 1426 1427 switch (header & PCI_HEADER_TYPE_M) { 1428 case PCI_HEADER_ZERO: 1429 subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 1430 subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 1431 break; 1432 case PCI_HEADER_CARDBUS: 1433 subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 1434 subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 1435 /* Record the # of cardbus bridges found on the bus */ 1436 if (config_op == CONFIG_INFO) 1437 pci_bus_res[bus].num_cbb++; 1438 break; 1439 default: 1440 subvenid = 0; 1441 subdevid = 0; 1442 break; 1443 } 1444 1445 if (config_op == CONFIG_FIX) { 1446 if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) { 1447 pci_fix_amd8111(bus, dev, func); 1448 } 1449 return; 1450 } 1451 1452 /* XXX should be use generic names? derive from class? */ 1453 revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 1454 classcode = revclass >> 8; 1455 revid = revclass & 0xff; 1456 1457 /* figure out if this is pci-ide */ 1458 basecl = classcode >> 16; 1459 subcl = (classcode >> 8) & 0xff; 1460 progcl = classcode & 0xff; 1461 1462 1463 if (is_display(classcode)) 1464 (void) snprintf(nodename, sizeof (nodename), "display"); 1465 else if (subvenid != 0) 1466 (void) snprintf(nodename, sizeof (nodename), 1467 "pci%x,%x", subvenid, subdevid); 1468 else 1469 (void) snprintf(nodename, sizeof (nodename), 1470 "pci%x,%x", vendorid, deviceid); 1471 1472 /* make sure parent bus dip has been created */ 1473 if (pci_bus_res[bus].dip == NULL) { 1474 create_root_bus_dip(bus); 1475 } 1476 1477 ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 1478 DEVI_SID_NODEID, &dip); 1479 1480 if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num, 1481 &is_pci_bridge) == B_TRUE) 1482 pciex = 1; 1483 1484 /* add properties */ 1485 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 1486 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 1487 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 1488 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1489 "class-code", classcode); 1490 if (func == 0) 1491 (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 1492 else 1493 (void) snprintf(unitaddr, sizeof (unitaddr), 1494 "%x,%x", dev, func); 1495 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1496 "unit-address", unitaddr); 1497 1498 /* add device_type for display nodes */ 1499 if (is_display(classcode)) { 1500 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1501 "device_type", "display"); 1502 } 1503 /* add special stuff for header type */ 1504 if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 1505 uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 1506 uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 1507 1508 if (subvenid != 0) { 1509 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1510 "subsystem-id", subdevid); 1511 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1512 "subsystem-vendor-id", subvenid); 1513 } 1514 if (!pciex) 1515 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1516 "min-grant", mingrant); 1517 if (!pciex) 1518 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1519 "max-latency", maxlatency); 1520 } 1521 1522 /* interrupt, record if not 0 */ 1523 intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 1524 if (intr != 0) 1525 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1526 "interrupts", intr); 1527 1528 /* 1529 * Add support for 133 mhz pci eventually 1530 */ 1531 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 1532 1533 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1534 "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 1535 if (!pciex && (status & PCI_STAT_FBBC)) 1536 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1537 "fast-back-to-back"); 1538 if (!pciex && (status & PCI_STAT_66MHZ)) 1539 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1540 "66mhz-capable"); 1541 if (status & PCI_STAT_UDF) 1542 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1543 "udf-supported"); 1544 if (pciex && slot_num) { 1545 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1546 "physical-slot#", slot_num); 1547 if (!is_pci_bridge) 1548 pciex_slot_names_prop(dip, slot_num); 1549 } 1550 1551 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1552 "power-consumption", power, 2); 1553 1554 /* Set the device PM state to D0 */ 1555 set_devpm_d0(bus, dev, func); 1556 1557 if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) 1558 add_ppb_props(dip, bus, dev, func, pciex, is_pci_bridge); 1559 else { 1560 /* 1561 * Record the non-PPB devices on the bus for possible 1562 * reprogramming at 2nd bus enumeration. 1563 * Note: PPB reprogramming is done in fix_ppb_res() 1564 */ 1565 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 1566 entry = kmem_zalloc(sizeof (*entry), KM_SLEEP); 1567 entry->dip = dip; 1568 entry->dev = dev; 1569 entry->func = func; 1570 entry->next = devlist; 1571 pci_bus_res[bus].privdata = entry; 1572 } 1573 1574 if (config_op == CONFIG_INFO && 1575 IS_CLASS_IOAPIC(basecl, subcl, progcl)) { 1576 create_ioapic_node(bus, dev, func, vendorid, deviceid); 1577 } 1578 1579 /* check for ck8-04 based PCI ISA bridge only */ 1580 if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) && 1581 (func == 0)) 1582 add_nvidia_isa_bridge_props(dip, bus, dev, func); 1583 1584 if (pciex && is_pci_bridge) 1585 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 1586 (char *)"PCIe-PCI bridge"); 1587 else 1588 add_model_prop(dip, classcode); 1589 1590 add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 1591 revid, classcode, pciex); 1592 1593 /* 1594 * See if this device is a controller that advertises 1595 * itself to be a standard ATA task file controller, or one that 1596 * has been hard coded. 1597 * 1598 * If it is, check if any other higher precedence driver listed in 1599 * driver_aliases will claim the node by calling 1600 * ddi_compatibile_driver_major. If so, clear pciide and do not 1601 * create a pci-ide node or any other special handling. 1602 * 1603 * If another driver does not bind, set the node name to pci-ide 1604 * and then let the special pci-ide handling for registers and 1605 * child pci-ide nodes proceed below. 1606 */ 1607 if (is_pciide(basecl, subcl, revid, vendorid, deviceid, 1608 subvenid, subdevid) == 1) { 1609 if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) { 1610 (void) ndi_devi_set_nodename(dip, "pci-ide", 0); 1611 pciide = 1; 1612 } 1613 } 1614 1615 reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 1616 (void) ndi_devi_bind_driver(dip, 0); 1617 1618 /* special handling for pci-ide */ 1619 if (pciide) { 1620 dev_info_t *cdip; 1621 1622 /* 1623 * Create properties specified by P1275 Working Group 1624 * Proposal #414 Version 1 1625 */ 1626 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1627 "device_type", "pci-ide"); 1628 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1629 "#address-cells", 1); 1630 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1631 "#size-cells", 0); 1632 1633 /* allocate two child nodes */ 1634 ndi_devi_alloc_sleep(dip, "ide", 1635 (pnode_t)DEVI_SID_NODEID, &cdip); 1636 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 1637 "reg", 0); 1638 (void) ndi_devi_bind_driver(cdip, 0); 1639 ndi_devi_alloc_sleep(dip, "ide", 1640 (pnode_t)DEVI_SID_NODEID, &cdip); 1641 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 1642 "reg", 1); 1643 (void) ndi_devi_bind_driver(cdip, 0); 1644 1645 reprogram = 0; /* don't reprogram pci-ide bridge */ 1646 } 1647 1648 /* allocate and set up iommu private */ 1649 private = kmem_alloc(sizeof (iommu_private_t), KM_SLEEP); 1650 private->idp_seg = 0; 1651 private->idp_bus = bus; 1652 private->idp_devfn = (dev << 3) | func; 1653 private->idp_sec = 0; 1654 private->idp_sub = 0; 1655 private->idp_bbp_type = IOMMU_PPB_NONE; 1656 /* record the bridge */ 1657 private->idp_is_bridge = ((basecl == PCI_CLASS_BRIDGE) && 1658 (subcl == PCI_BRIDGE_PCI)); 1659 if (private->idp_is_bridge) { 1660 private->idp_sec = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 1661 private->idp_sub = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 1662 if (pciex && is_pci_bridge) 1663 private->idp_bbp_type = IOMMU_PPB_PCIE_PCI; 1664 else if (pciex) 1665 private->idp_bbp_type = IOMMU_PPB_PCIE_PCIE; 1666 else 1667 private->idp_bbp_type = IOMMU_PPB_PCI_PCI; 1668 } 1669 /* record the special devices */ 1670 private->idp_is_display = (is_display(classcode) ? B_TRUE : B_FALSE); 1671 private->idp_is_lpc = ((basecl == PCI_CLASS_BRIDGE) && 1672 (subcl == PCI_BRIDGE_ISA)); 1673 private->idp_intel_domain = NULL; 1674 /* hook the private to dip */ 1675 DEVI(dip)->devi_iommu_private = private; 1676 1677 if (private->idp_is_display == B_TRUE) { 1678 gfxp = kmem_zalloc(sizeof (*gfxp), KM_SLEEP); 1679 gfxp->g_dip = dip; 1680 gfxp->g_prev = NULL; 1681 gfxp->g_next = gfx_devinfo_list; 1682 gfx_devinfo_list = gfxp; 1683 if (gfxp->g_next) 1684 gfxp->g_next->g_prev = gfxp; 1685 } 1686 1687 if (reprogram && (entry != NULL)) 1688 entry->reprogram = B_TRUE; 1689 } 1690 1691 /* 1692 * Set the compatible property to a value compliant with 1693 * rev 2.1 of the IEEE1275 PCI binding. 1694 * (Also used for PCI-Express devices). 1695 * 1696 * pciVVVV,DDDD.SSSS.ssss.RR (0) 1697 * pciVVVV,DDDD.SSSS.ssss (1) 1698 * pciSSSS,ssss (2) 1699 * pciVVVV,DDDD.RR (3) 1700 * pciVVVV,DDDD (4) 1701 * pciclass,CCSSPP (5) 1702 * pciclass,CCSS (6) 1703 * 1704 * The Subsystem (SSSS) forms are not inserted if 1705 * subsystem-vendor-id is 0. 1706 * 1707 * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above 1708 * property 2 is not created as per "1275 bindings for PCI Express Interconnect" 1709 * 1710 * Set with setprop and \x00 between each 1711 * to generate the encoded string array form. 1712 */ 1713 void 1714 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 1715 ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode, 1716 int pciex) 1717 { 1718 int i = 0; 1719 int size = COMPAT_BUFSIZE; 1720 char *compat[13]; 1721 char *buf, *curr; 1722 1723 curr = buf = kmem_alloc(size, KM_SLEEP); 1724 1725 if (pciex) { 1726 if (subvenid) { 1727 compat[i++] = curr; /* form 0 */ 1728 (void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x", 1729 vendorid, deviceid, subvenid, subdevid, revid); 1730 size -= strlen(curr) + 1; 1731 curr += strlen(curr) + 1; 1732 1733 compat[i++] = curr; /* form 1 */ 1734 (void) snprintf(curr, size, "pciex%x,%x.%x.%x", 1735 vendorid, deviceid, subvenid, subdevid); 1736 size -= strlen(curr) + 1; 1737 curr += strlen(curr) + 1; 1738 1739 } 1740 compat[i++] = curr; /* form 3 */ 1741 (void) snprintf(curr, size, "pciex%x,%x.%x", 1742 vendorid, deviceid, revid); 1743 size -= strlen(curr) + 1; 1744 curr += strlen(curr) + 1; 1745 1746 compat[i++] = curr; /* form 4 */ 1747 (void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid); 1748 size -= strlen(curr) + 1; 1749 curr += strlen(curr) + 1; 1750 1751 compat[i++] = curr; /* form 5 */ 1752 (void) snprintf(curr, size, "pciexclass,%06x", classcode); 1753 size -= strlen(curr) + 1; 1754 curr += strlen(curr) + 1; 1755 1756 compat[i++] = curr; /* form 6 */ 1757 (void) snprintf(curr, size, "pciexclass,%04x", 1758 (classcode >> 8)); 1759 size -= strlen(curr) + 1; 1760 curr += strlen(curr) + 1; 1761 } 1762 1763 if (subvenid) { 1764 compat[i++] = curr; /* form 0 */ 1765 (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 1766 vendorid, deviceid, subvenid, subdevid, revid); 1767 size -= strlen(curr) + 1; 1768 curr += strlen(curr) + 1; 1769 1770 compat[i++] = curr; /* form 1 */ 1771 (void) snprintf(curr, size, "pci%x,%x.%x.%x", 1772 vendorid, deviceid, subvenid, subdevid); 1773 size -= strlen(curr) + 1; 1774 curr += strlen(curr) + 1; 1775 1776 compat[i++] = curr; /* form 2 */ 1777 (void) snprintf(curr, size, "pci%x,%x", subvenid, subdevid); 1778 size -= strlen(curr) + 1; 1779 curr += strlen(curr) + 1; 1780 } 1781 compat[i++] = curr; /* form 3 */ 1782 (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 1783 size -= strlen(curr) + 1; 1784 curr += strlen(curr) + 1; 1785 1786 compat[i++] = curr; /* form 4 */ 1787 (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 1788 size -= strlen(curr) + 1; 1789 curr += strlen(curr) + 1; 1790 1791 compat[i++] = curr; /* form 5 */ 1792 (void) snprintf(curr, size, "pciclass,%06x", classcode); 1793 size -= strlen(curr) + 1; 1794 curr += strlen(curr) + 1; 1795 1796 compat[i++] = curr; /* form 6 */ 1797 (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 1798 size -= strlen(curr) + 1; 1799 curr += strlen(curr) + 1; 1800 1801 (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 1802 "compatible", compat, i); 1803 kmem_free(buf, COMPAT_BUFSIZE); 1804 } 1805 1806 /* 1807 * Adjust the reg properties for a dual channel PCI-IDE device. 1808 * 1809 * NOTE: don't do anything that changes the order of the hard-decodes 1810 * and programmed BARs. The kernel driver depends on these values 1811 * being in this order regardless of whether they're for a 'native' 1812 * mode BAR or not. 1813 */ 1814 /* 1815 * config info for pci-ide devices 1816 */ 1817 static struct { 1818 uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 1819 uchar_t bar_offset; /* offset for alt status register */ 1820 ushort_t addr; /* compatibility mode base address */ 1821 ushort_t length; /* number of ports for this BAR */ 1822 } pciide_bar[] = { 1823 { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 1824 { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 1825 { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 1826 { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 1827 }; 1828 1829 static int 1830 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 1831 { 1832 int hard_decode = 0; 1833 1834 /* 1835 * Adjust the base and len for the BARs of the PCI-IDE 1836 * device's primary and secondary controllers. The first 1837 * two BARs are for the primary controller and the next 1838 * two BARs are for the secondary controller. The fifth 1839 * and sixth bars are never adjusted. 1840 */ 1841 if (index >= 0 && index <= 3) { 1842 *lenp = pciide_bar[index].length; 1843 1844 if (progcl & pciide_bar[index].native_mask) { 1845 *basep += pciide_bar[index].bar_offset; 1846 } else { 1847 *basep = pciide_bar[index].addr; 1848 hard_decode = 1; 1849 } 1850 } 1851 1852 /* 1853 * if either base or len is zero make certain both are zero 1854 */ 1855 if (*basep == 0 || *lenp == 0) { 1856 *basep = 0; 1857 *lenp = 0; 1858 hard_decode = 0; 1859 } 1860 1861 return (hard_decode); 1862 } 1863 1864 1865 /* 1866 * Add the "reg" and "assigned-addresses" property 1867 */ 1868 static int 1869 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 1870 int config_op, int pciide) 1871 { 1872 uchar_t baseclass, subclass, progclass, header; 1873 ushort_t bar_sz; 1874 uint_t value = 0, len, devloc; 1875 uint_t base, base_hi, type; 1876 ushort_t offset, end; 1877 int max_basereg, j, reprogram = 0; 1878 uint_t phys_hi; 1879 struct memlist **io_res, **mres, **mem_res, **pmem_res; 1880 struct memlist **io_res_used, **mres_used; 1881 struct memlist **mem_res_used, **pmem_res_used; 1882 uchar_t res_bus; 1883 1884 pci_regspec_t regs[16] = {{0}}; 1885 pci_regspec_t assigned[15] = {{0}}; 1886 int nreg, nasgn; 1887 1888 io_res = &pci_bus_res[bus].io_ports; 1889 io_res_used = &pci_bus_res[bus].io_ports_used; 1890 mem_res = &pci_bus_res[bus].mem_space; 1891 mem_res_used = &pci_bus_res[bus].mem_space_used; 1892 if (bus == 0) { /* for bus 0, there is only mem_space */ 1893 pmem_res = mem_res; 1894 pmem_res_used = mem_res_used; 1895 } else { 1896 pmem_res = &pci_bus_res[bus].pmem_space; 1897 pmem_res_used = &pci_bus_res[bus].pmem_space_used; 1898 } 1899 1900 devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 1901 regs[0].pci_phys_hi = devloc; 1902 nreg = 1; /* rest of regs[0] is all zero */ 1903 nasgn = 0; 1904 1905 baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 1906 subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 1907 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 1908 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1909 1910 switch (header) { 1911 case PCI_HEADER_ZERO: 1912 max_basereg = PCI_BASE_NUM; 1913 break; 1914 case PCI_HEADER_PPB: 1915 max_basereg = PCI_BCNF_BASE_NUM; 1916 break; 1917 case PCI_HEADER_CARDBUS: 1918 max_basereg = PCI_CBUS_BASE_NUM; 1919 break; 1920 default: 1921 max_basereg = 0; 1922 break; 1923 } 1924 1925 /* 1926 * Create the register property by saving the current 1927 * value of the base register. Write 0xffffffff to the 1928 * base register. Read the value back to determine the 1929 * required size of the address space. Restore the base 1930 * register contents. 1931 * 1932 * Do not disable I/O and memory access; this isn't necessary 1933 * since no driver is yet attached to this device, and disabling 1934 * I/O and memory access has the side-effect of disabling PCI-PCI 1935 * bridge mappings, which makes the bridge transparent to secondary- 1936 * bus activity (see sections 4.1-4.3 of the PCI-PCI Bridge 1937 * Spec V1.2). 1938 */ 1939 end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 1940 for (j = 0, offset = PCI_CONF_BASE0; offset < end; 1941 j++, offset += bar_sz) { 1942 int hard_decode = 0; 1943 1944 /* determine the size of the address space */ 1945 base = pci_getl(bus, dev, func, offset); 1946 pci_putl(bus, dev, func, offset, 0xffffffff); 1947 value = pci_getl(bus, dev, func, offset); 1948 pci_putl(bus, dev, func, offset, base); 1949 1950 /* construct phys hi,med.lo, size hi, lo */ 1951 if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 1952 /* i/o space */ 1953 bar_sz = PCI_BAR_SZ_32; 1954 value &= PCI_BASE_IO_ADDR_M; 1955 len = ((value ^ (value-1)) + 1) >> 1; 1956 1957 /* XXX Adjust first 4 IDE registers */ 1958 if (pciide) { 1959 if (subclass != PCI_MASS_IDE) 1960 progclass = (PCI_IDE_IF_NATIVE_PRI | 1961 PCI_IDE_IF_NATIVE_SEC); 1962 hard_decode = pciIdeAdjustBAR(progclass, j, 1963 &base, &len); 1964 } else if (value == 0) { 1965 /* skip base regs with size of 0 */ 1966 continue; 1967 } 1968 1969 regs[nreg].pci_size_low = 1970 assigned[nasgn].pci_size_low = len; 1971 if (!hard_decode) { 1972 regs[nreg].pci_phys_hi = 1973 (PCI_ADDR_IO | devloc) + offset; 1974 } else { 1975 regs[nreg].pci_phys_hi = 1976 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + 1977 offset; 1978 regs[nreg].pci_phys_low = 1979 base & PCI_BASE_IO_ADDR_M; 1980 } 1981 assigned[nasgn].pci_phys_hi = 1982 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + offset; 1983 type = base & (~PCI_BASE_IO_ADDR_M); 1984 base &= PCI_BASE_IO_ADDR_M; 1985 /* 1986 * A device under a subtractive PPB can allocate 1987 * resources from its parent bus if there is no resource 1988 * available on its own bus. 1989 */ 1990 if ((config_op == CONFIG_NEW) && (*io_res == NULL)) { 1991 res_bus = bus; 1992 while (pci_bus_res[res_bus].subtractive) { 1993 res_bus = pci_bus_res[res_bus].par_bus; 1994 if (res_bus == (uchar_t)-1) 1995 break; /* root bus already */ 1996 if (pci_bus_res[res_bus].io_ports) { 1997 io_res = &pci_bus_res 1998 [res_bus].io_ports; 1999 break; 2000 } 2001 } 2002 } 2003 2004 /* 2005 * first pass - gather what's there 2006 * update/second pass - adjust/allocate regions 2007 * config - allocate regions 2008 */ 2009 if (config_op == CONFIG_INFO) { /* first pass */ 2010 /* take out of the resource map of the bus */ 2011 if (base != 0) { 2012 if (*io_res) 2013 (void) memlist_remove(io_res, 2014 base, len); 2015 memlist_insert(io_res_used, base, len); 2016 } else 2017 reprogram = 1; 2018 } else if ((*io_res && base == 0) || 2019 pci_bus_res[bus].io_reprogram) { 2020 base = (uint_t)memlist_find(io_res, len, len); 2021 if (base != 0) { 2022 memlist_insert(io_res_used, base, len); 2023 /* XXX need to worry about 64-bit? */ 2024 pci_putl(bus, dev, func, offset, 2025 base | type); 2026 base = pci_getl(bus, dev, func, offset); 2027 base &= PCI_BASE_IO_ADDR_M; 2028 } 2029 if (base == 0) { 2030 cmn_err(CE_WARN, "failed to program" 2031 " IO space [%d/%d/%d] BAR@0x%x" 2032 " length 0x%x", 2033 bus, dev, func, offset, len); 2034 } 2035 } 2036 assigned[nasgn].pci_phys_low = base; 2037 nreg++, nasgn++; 2038 2039 } else { 2040 /* memory space */ 2041 if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 2042 bar_sz = PCI_BAR_SZ_64; 2043 base_hi = pci_getl(bus, dev, func, offset + 4); 2044 phys_hi = PCI_ADDR_MEM64; 2045 } else { 2046 bar_sz = PCI_BAR_SZ_32; 2047 base_hi = 0; 2048 phys_hi = PCI_ADDR_MEM32; 2049 } 2050 2051 /* skip base regs with size of 0 */ 2052 value &= PCI_BASE_M_ADDR_M; 2053 2054 if (value == 0) { 2055 continue; 2056 } 2057 len = ((value ^ (value-1)) + 1) >> 1; 2058 regs[nreg].pci_size_low = 2059 assigned[nasgn].pci_size_low = len; 2060 2061 phys_hi |= (devloc | offset); 2062 if (base & PCI_BASE_PREF_M) { 2063 mres = pmem_res; 2064 mres_used = pmem_res_used; 2065 phys_hi |= PCI_PREFETCH_B; 2066 } else { 2067 mres = mem_res; 2068 mres_used = mem_res_used; 2069 } 2070 /* 2071 * A device under a subtractive PPB can allocate 2072 * resources from its parent bus if there is no resource 2073 * available on its own bus. 2074 */ 2075 if ((config_op == CONFIG_NEW) && (*mres == NULL)) { 2076 res_bus = bus; 2077 while (pci_bus_res[res_bus].subtractive) { 2078 res_bus = pci_bus_res[res_bus].par_bus; 2079 if (res_bus == (uchar_t)-1) 2080 break; /* root bus already */ 2081 mem_res = 2082 &pci_bus_res[res_bus].mem_space; 2083 if (res_bus == 0) 2084 pmem_res = mem_res; 2085 else 2086 pmem_res = &pci_bus_res 2087 [res_bus].pmem_space; 2088 if (phys_hi & PCI_PREFETCH_B) 2089 mres = pmem_res; 2090 else 2091 mres = mem_res; 2092 if (*mres) 2093 break; 2094 } 2095 } 2096 2097 regs[nreg].pci_phys_hi = 2098 assigned[nasgn].pci_phys_hi = phys_hi; 2099 assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 2100 assigned[nasgn].pci_phys_mid = base_hi; 2101 type = base & ~PCI_BASE_M_ADDR_M; 2102 base &= PCI_BASE_M_ADDR_M; 2103 2104 if (config_op == CONFIG_INFO) { 2105 /* take out of the resource map of the bus */ 2106 if (base != 0) { 2107 if (*mem_res) { 2108 /* remove it from MEM space */ 2109 (void) memlist_remove(mem_res, 2110 base, len); 2111 } 2112 if (mem_res != pmem_res && *pmem_res) { 2113 /* remove it from PMEM space */ 2114 (void) memlist_remove(pmem_res, 2115 base, len); 2116 } 2117 memlist_insert(mres_used, base, len); 2118 } else 2119 reprogram = 1; 2120 } else if ((*mres && base == 0) || 2121 pci_bus_res[bus].mem_reprogram) { 2122 base = (uint_t)memlist_find(mres, len, len); 2123 if (base != NULL) { 2124 if (mres != mem_res && *mem_res) { 2125 /* remove it from MEM space */ 2126 (void) memlist_remove(mem_res, 2127 base, len); 2128 } else if (mres != pmem_res && 2129 *pmem_res) { 2130 /* remove it from PMEM space */ 2131 (void) memlist_remove(pmem_res, 2132 base, len); 2133 } 2134 memlist_insert(mres_used, base, len); 2135 pci_putl(bus, dev, func, offset, 2136 base | type); 2137 base = pci_getl(bus, dev, func, offset); 2138 base &= PCI_BASE_M_ADDR_M; 2139 } 2140 2141 if (base == 0) { 2142 cmn_err(CE_WARN, "failed to program " 2143 "mem space [%d/%d/%d] BAR@0x%x" 2144 " length 0x%x", 2145 bus, dev, func, offset, len); 2146 } 2147 } 2148 assigned[nasgn].pci_phys_low = base; 2149 nreg++, nasgn++; 2150 } 2151 } 2152 switch (header) { 2153 case PCI_HEADER_ZERO: 2154 offset = PCI_CONF_ROM; 2155 break; 2156 case PCI_HEADER_PPB: 2157 offset = PCI_BCNF_ROM; 2158 break; 2159 default: /* including PCI_HEADER_CARDBUS */ 2160 goto done; 2161 } 2162 2163 /* 2164 * Add the expansion rom memory space 2165 * Determine the size of the ROM base reg; don't write reserved bits 2166 * ROM isn't in the PCI memory space. 2167 */ 2168 base = pci_getl(bus, dev, func, offset); 2169 pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 2170 value = pci_getl(bus, dev, func, offset); 2171 pci_putl(bus, dev, func, offset, base); 2172 if (value & PCI_BASE_ROM_ENABLE) 2173 value &= PCI_BASE_ROM_ADDR_M; 2174 else 2175 value = 0; 2176 2177 if (value != 0) { 2178 regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 2179 assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 2180 PCI_ADDR_MEM32 | devloc) + offset; 2181 base &= PCI_BASE_ROM_ADDR_M; 2182 assigned[nasgn].pci_phys_low = base; 2183 len = ((value ^ (value-1)) + 1) >> 1; 2184 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 2185 nreg++, nasgn++; 2186 /* take it out of the memory resource */ 2187 if (*mem_res && base != 0) 2188 (void) memlist_remove(mem_res, base, len); 2189 if (base != 0) 2190 memlist_insert(mem_res, base, len); 2191 } 2192 2193 /* 2194 * The following are ISA resources. There are not part 2195 * of the PCI local bus resources. So don't attempt to 2196 * do resource accounting against PCI. 2197 */ 2198 2199 /* add the three hard-decode, aliased address spaces for VGA */ 2200 if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 2201 (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 2202 2203 /* VGA hard decode 0x3b0-0x3bb */ 2204 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2205 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2206 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 2207 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 2208 nreg++, nasgn++; 2209 2210 /* VGA hard decode 0x3c0-0x3df */ 2211 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2212 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2213 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 2214 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 2215 nreg++, nasgn++; 2216 2217 /* Video memory */ 2218 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2219 (PCI_RELOCAT_B | PCI_ADDR_MEM32 | devloc); 2220 regs[nreg].pci_phys_low = 2221 assigned[nasgn].pci_phys_low = 0xa0000; 2222 regs[nreg].pci_size_low = 2223 assigned[nasgn].pci_size_low = 0x20000; 2224 nreg++, nasgn++; 2225 } 2226 2227 /* add the hard-decode, aliased address spaces for 8514 */ 2228 if ((baseclass == PCI_CLASS_DISPLAY) && 2229 (subclass == PCI_DISPLAY_VGA) && 2230 (progclass & PCI_DISPLAY_IF_8514)) { 2231 2232 /* hard decode 0x2e8 */ 2233 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2234 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2235 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 2236 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 2237 nreg++, nasgn++; 2238 2239 /* hard decode 0x2ea-0x2ef */ 2240 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2241 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2242 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 2243 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 2244 nreg++, nasgn++; 2245 } 2246 2247 done: 2248 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 2249 (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 2250 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 2251 "assigned-addresses", 2252 (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 2253 2254 return (reprogram); 2255 } 2256 2257 static void 2258 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 2259 int pciex, ushort_t is_pci_bridge) 2260 { 2261 char *dev_type; 2262 int i; 2263 uint_t val, io_range[2], mem_range[2], pmem_range[2]; 2264 uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 2265 uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 2266 uchar_t progclass; 2267 2268 ASSERT(secbus <= subbus); 2269 2270 /* 2271 * Check if it's a subtractive PPB. 2272 */ 2273 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 2274 if (progclass == PCI_BRIDGE_PCI_IF_SUBDECODE) 2275 pci_bus_res[secbus].subtractive = B_TRUE; 2276 2277 /* 2278 * Some BIOSes lie about max pci busses, we allow for 2279 * such mistakes here 2280 */ 2281 if (subbus > pci_bios_nbus) { 2282 pci_bios_nbus = subbus; 2283 alloc_res_array(); 2284 } 2285 2286 ASSERT(pci_bus_res[secbus].dip == NULL); 2287 pci_bus_res[secbus].dip = dip; 2288 pci_bus_res[secbus].par_bus = bus; 2289 2290 dev_type = (pciex && !is_pci_bridge) ? "pciex" : "pci"; 2291 2292 /* setup bus number hierarchy */ 2293 pci_bus_res[secbus].sub_bus = subbus; 2294 /* 2295 * Keep track of the largest subordinate bus number (this is essential 2296 * for peer busses because there is no other way of determining its 2297 * subordinate bus number). 2298 */ 2299 if (subbus > pci_bus_res[bus].sub_bus) 2300 pci_bus_res[bus].sub_bus = subbus; 2301 /* 2302 * Loop through subordinate busses, initializing their parent bus 2303 * field to this bridge's parent. The subordinate busses' parent 2304 * fields may very well be further refined later, as child bridges 2305 * are enumerated. (The value is to note that the subordinate busses 2306 * are not peer busses by changing their par_bus fields to anything 2307 * other than -1.) 2308 */ 2309 for (i = secbus + 1; i <= subbus; i++) 2310 pci_bus_res[i].par_bus = bus; 2311 2312 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 2313 "device_type", dev_type); 2314 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2315 "#address-cells", 3); 2316 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2317 "#size-cells", 2); 2318 2319 /* 2320 * According to PPB spec, the base register should be programmed 2321 * with a value bigger than the limit register when there are 2322 * no resources available. This applies to io, memory, and 2323 * prefetchable memory. 2324 */ 2325 2326 /* 2327 * io range 2328 * We determine i/o windows that are left unconfigured by BIOS 2329 * through its i/o enable bit as Microsoft recommends OEMs to do. 2330 * If it is unset, we disable i/o and mark it for reconfiguration in 2331 * later passes by setting the base > limit 2332 */ 2333 val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM); 2334 if (val & PCI_COMM_IO) { 2335 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 2336 io_range[0] = ((val & 0xf0) << 8); 2337 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 2338 io_range[1] = ((val & 0xf0) << 8) | 0xFFF; 2339 } else { 2340 io_range[0] = 0x9fff; 2341 io_range[1] = 0x1000; 2342 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 2343 (uint8_t)((io_range[0] >> 8) & 0xf0)); 2344 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 2345 (uint8_t)((io_range[1] >> 8) & 0xf0)); 2346 pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 2347 pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 2348 } 2349 2350 if (io_range[0] != 0 && io_range[0] < io_range[1]) { 2351 memlist_insert(&pci_bus_res[secbus].io_ports, 2352 (uint64_t)io_range[0], 2353 (uint64_t)(io_range[1] - io_range[0] + 1)); 2354 memlist_insert(&pci_bus_res[bus].io_ports_used, 2355 (uint64_t)io_range[0], 2356 (uint64_t)(io_range[1] - io_range[0] + 1)); 2357 if (pci_bus_res[bus].io_ports != NULL) { 2358 (void) memlist_remove(&pci_bus_res[bus].io_ports, 2359 (uint64_t)io_range[0], 2360 (uint64_t)(io_range[1] - io_range[0] + 1)); 2361 } 2362 dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x", 2363 secbus, io_range[0], io_range[1]); 2364 /* if 32-bit supported, make sure upper bits are not set */ 2365 if ((val & 0xf) == 1 && 2366 pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) { 2367 cmn_err(CE_NOTE, "unsupported 32-bit IO address on" 2368 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 2369 } 2370 } 2371 2372 /* mem range */ 2373 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 2374 mem_range[0] = ((val & 0xFFF0) << 16); 2375 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 2376 mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 2377 if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 2378 memlist_insert(&pci_bus_res[secbus].mem_space, 2379 (uint64_t)mem_range[0], 2380 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2381 memlist_insert(&pci_bus_res[bus].mem_space_used, 2382 (uint64_t)mem_range[0], 2383 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2384 /* remove from parent resource list */ 2385 if (pci_bus_res[bus].mem_space != NULL) { 2386 (void) memlist_remove(&pci_bus_res[bus].mem_space, 2387 (uint64_t)mem_range[0], 2388 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2389 } 2390 if (pci_bus_res[bus].pmem_space != NULL) { 2391 (void) memlist_remove(&pci_bus_res[bus].pmem_space, 2392 (uint64_t)mem_range[0], 2393 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2394 } 2395 dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x", 2396 secbus, mem_range[0], mem_range[1]); 2397 } 2398 2399 /* prefetchable memory range */ 2400 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 2401 pmem_range[0] = ((val & 0xFFF0) << 16); 2402 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 2403 pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 2404 if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 2405 memlist_insert(&pci_bus_res[secbus].pmem_space, 2406 (uint64_t)pmem_range[0], 2407 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2408 memlist_insert(&pci_bus_res[bus].pmem_space_used, 2409 (uint64_t)pmem_range[0], 2410 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2411 /* remove from parent resource list */ 2412 if (pci_bus_res[bus].pmem_space != NULL) { 2413 (void) memlist_remove(&pci_bus_res[bus].pmem_space, 2414 (uint64_t)pmem_range[0], 2415 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2416 } 2417 if (pci_bus_res[bus].mem_space != NULL) { 2418 (void) memlist_remove(&pci_bus_res[bus].mem_space, 2419 (uint64_t)pmem_range[0], 2420 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2421 } 2422 dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x", 2423 secbus, pmem_range[0], pmem_range[1]); 2424 /* if 64-bit supported, make sure upper bits are not set */ 2425 if ((val & 0xf) == 1 && 2426 pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) { 2427 cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on" 2428 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 2429 } 2430 } 2431 2432 add_bus_range_prop(secbus); 2433 add_ppb_ranges_prop(secbus); 2434 } 2435 2436 extern const struct pci_class_strings_s class_pci[]; 2437 extern int class_pci_items; 2438 2439 static void 2440 add_model_prop(dev_info_t *dip, uint_t classcode) 2441 { 2442 const char *desc; 2443 int i; 2444 uchar_t baseclass = classcode >> 16; 2445 uchar_t subclass = (classcode >> 8) & 0xff; 2446 uchar_t progclass = classcode & 0xff; 2447 2448 if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 2449 desc = "IDE controller"; 2450 } else { 2451 for (desc = 0, i = 0; i < class_pci_items; i++) { 2452 if ((baseclass == class_pci[i].base_class) && 2453 (subclass == class_pci[i].sub_class) && 2454 (progclass == class_pci[i].prog_class)) { 2455 desc = class_pci[i].actual_desc; 2456 break; 2457 } 2458 } 2459 if (i == class_pci_items) 2460 desc = "Unknown class of pci/pnpbios device"; 2461 } 2462 2463 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 2464 (char *)desc); 2465 } 2466 2467 static void 2468 add_bus_range_prop(int bus) 2469 { 2470 int bus_range[2]; 2471 2472 if (pci_bus_res[bus].dip == NULL) 2473 return; 2474 bus_range[0] = bus; 2475 bus_range[1] = pci_bus_res[bus].sub_bus; 2476 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 2477 "bus-range", (int *)bus_range, 2); 2478 } 2479 2480 /* 2481 * Add slot-names property for any named pci hot-plug slots 2482 */ 2483 static void 2484 add_bus_slot_names_prop(int bus) 2485 { 2486 char slotprop[256]; 2487 int len; 2488 2489 if (pci_bus_res[bus].dip != NULL) { 2490 /* simply return if the property is already defined */ 2491 if (ddi_prop_exists(DDI_DEV_T_ANY, pci_bus_res[bus].dip, 2492 DDI_PROP_DONTPASS, "slot-names")) 2493 return; 2494 } 2495 2496 len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); 2497 if (len > 0) { 2498 /* 2499 * Only create a peer bus node if this bus may be a peer bus. 2500 * It may be a peer bus if the dip is NULL and if par_bus is 2501 * -1 (par_bus is -1 if this bus was not found to be 2502 * subordinate to any PCI-PCI bridge). 2503 * If it's not a peer bus, then the ACPI BBN-handling code 2504 * will remove it later. 2505 */ 2506 if (pci_bus_res[bus].par_bus == (uchar_t)-1 && 2507 pci_bus_res[bus].dip == NULL) { 2508 2509 create_root_bus_dip(bus); 2510 } 2511 if (pci_bus_res[bus].dip != NULL) { 2512 ASSERT((len % sizeof (int)) == 0); 2513 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 2514 pci_bus_res[bus].dip, "slot-names", 2515 (int *)slotprop, len / sizeof (int)); 2516 } else { 2517 cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI " 2518 "IRQ routing table; Not adding slot-names " 2519 "property for incorrect bus %d", bus); 2520 } 2521 } 2522 } 2523 2524 static int 2525 memlist_to_range(ppb_ranges_t *rp, struct memlist *entry, int type) 2526 { 2527 if (entry == NULL) 2528 return (0); 2529 2530 /* assume 32-bit addresses */ 2531 rp->child_high = rp->parent_high = type; 2532 rp->child_mid = rp->parent_mid = 0; 2533 rp->child_low = rp->parent_low = (uint32_t)entry->address; 2534 rp->size_high = 0; 2535 rp->size_low = (uint32_t)entry->size; 2536 return (1); 2537 } 2538 2539 static void 2540 add_ppb_ranges_prop(int bus) 2541 { 2542 int i = 0; 2543 ppb_ranges_t *rp; 2544 2545 rp = kmem_alloc(3 * sizeof (*rp), KM_SLEEP); 2546 2547 i = memlist_to_range(&rp[0], pci_bus_res[bus].io_ports, 2548 PCI_ADDR_IO | PCI_REG_REL_M); 2549 i += memlist_to_range(&rp[i], pci_bus_res[bus].mem_space, 2550 PCI_ADDR_MEM32 | PCI_REG_REL_M); 2551 i += memlist_to_range(&rp[i], pci_bus_res[bus].pmem_space, 2552 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 2553 2554 if (i != 0) 2555 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 2556 pci_bus_res[bus].dip, "ranges", (int *)rp, 2557 i * sizeof (ppb_ranges_t) / sizeof (int)); 2558 kmem_free(rp, 3 * sizeof (*rp)); 2559 } 2560 2561 static int 2562 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 2563 { 2564 int i = 0; 2565 2566 while (list) { 2567 /* assume 32-bit addresses */ 2568 sp->pci_phys_hi = type; 2569 sp->pci_phys_mid = 0; 2570 sp->pci_phys_low = (uint32_t)list->address; 2571 sp->pci_size_hi = 0; 2572 sp->pci_size_low = (uint32_t)list->size; 2573 2574 list = list->next; 2575 sp++, i++; 2576 } 2577 return (i); 2578 } 2579 2580 static void 2581 add_bus_available_prop(int bus) 2582 { 2583 int i, count; 2584 struct pci_phys_spec *sp; 2585 2586 count = memlist_count(pci_bus_res[bus].io_ports) + 2587 memlist_count(pci_bus_res[bus].mem_space) + 2588 memlist_count(pci_bus_res[bus].pmem_space); 2589 2590 if (count == 0) /* nothing available */ 2591 return; 2592 2593 sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 2594 i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_ports, 2595 PCI_ADDR_IO | PCI_REG_REL_M); 2596 i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_space, 2597 PCI_ADDR_MEM32 | PCI_REG_REL_M); 2598 i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_space, 2599 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 2600 ASSERT(i == count); 2601 2602 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 2603 "available", (int *)sp, 2604 i * sizeof (struct pci_phys_spec) / sizeof (int)); 2605 kmem_free(sp, count * sizeof (*sp)); 2606 } 2607 2608 static void 2609 alloc_res_array(void) 2610 { 2611 static int array_max = 0; 2612 int old_max; 2613 void *old_res; 2614 2615 if (array_max > pci_bios_nbus + 1) 2616 return; /* array is big enough */ 2617 2618 old_max = array_max; 2619 old_res = pci_bus_res; 2620 2621 if (array_max == 0) 2622 array_max = 16; /* start with a reasonable number */ 2623 2624 while (array_max < pci_bios_nbus + 1) 2625 array_max <<= 1; 2626 pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 2627 array_max * sizeof (struct pci_bus_resource), KM_SLEEP); 2628 2629 if (old_res) { /* copy content and free old array */ 2630 bcopy(old_res, pci_bus_res, 2631 old_max * sizeof (struct pci_bus_resource)); 2632 kmem_free(old_res, old_max * sizeof (struct pci_bus_resource)); 2633 } 2634 } 2635 2636 static void 2637 create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 2638 ushort_t deviceid) 2639 { 2640 static dev_info_t *ioapicsnode = NULL; 2641 static int numioapics = 0; 2642 dev_info_t *ioapic_node; 2643 uint64_t physaddr; 2644 uint32_t lobase, hibase = 0; 2645 2646 /* BAR 0 contains the IOAPIC's memory-mapped I/O address */ 2647 lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0); 2648 2649 /* We (and the rest of the world) only support memory-mapped IOAPICs */ 2650 if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM) 2651 return; 2652 2653 if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) 2654 hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4); 2655 2656 lobase &= PCI_BASE_M_ADDR_M; 2657 2658 physaddr = (((uint64_t)hibase) << 32) | lobase; 2659 2660 /* 2661 * Create a nexus node for all IOAPICs under the root node. 2662 */ 2663 if (ioapicsnode == NULL) { 2664 if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME, 2665 (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) { 2666 return; 2667 } 2668 (void) ndi_devi_online(ioapicsnode, 0); 2669 } 2670 2671 /* 2672 * Create a child node for this IOAPIC 2673 */ 2674 ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME, 2675 DEVI_SID_NODEID, numioapics++); 2676 if (ioapic_node == NULL) { 2677 return; 2678 } 2679 2680 /* Vendor and Device ID */ 2681 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 2682 IOAPICS_PROP_VENID, vendorid); 2683 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 2684 IOAPICS_PROP_DEVID, deviceid); 2685 2686 /* device_type */ 2687 (void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node, 2688 "device_type", IOAPICS_DEV_TYPE); 2689 2690 /* reg */ 2691 (void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node, 2692 "reg", physaddr); 2693 } 2694 2695 /* 2696 * NOTE: For PCIe slots, the name is generated from the slot number 2697 * information obtained from Slot Capabilities register. 2698 * For non-PCIe slots, it is generated based on the slot number 2699 * information in the PCI IRQ table. 2700 */ 2701 static void 2702 pciex_slot_names_prop(dev_info_t *dip, ushort_t slot_num) 2703 { 2704 char slotprop[256]; 2705 int len; 2706 2707 bzero(slotprop, sizeof (slotprop)); 2708 2709 /* set mask to 1 as there is only one slot (i.e dev 0) */ 2710 *(uint32_t *)slotprop = 1; 2711 len = 4; 2712 (void) snprintf(slotprop + len, sizeof (slotprop) - len, "pcie%d", 2713 slot_num); 2714 len += strlen(slotprop + len) + 1; 2715 len += len % 4; 2716 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "slot-names", 2717 (int *)slotprop, len / sizeof (int)); 2718 } 2719