1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/stat.h> 30 #include <sys/sunndi.h> 31 #include <sys/pci.h> 32 #include <sys/pci_impl.h> 33 #include <sys/pci_cfgspace.h> 34 #include <sys/memlist.h> 35 #include <sys/bootconf.h> 36 #include <io/pci/mps_table.h> 37 #include <sys/pci_cfgspace.h> 38 #include <sys/pci_cfgspace_impl.h> 39 #include <sys/psw.h> 40 #include "../../../../common/pci/pci_strings.h" 41 #include <sys/apic.h> 42 #include <io/pciex/pcie_nvidia.h> 43 #include <io/hotplug/pciehpc/pciehpc_acpi.h> 44 #include <sys/acpi/acpi.h> 45 #include <sys/acpica.h> 46 47 #define pci_getb (*pci_getb_func) 48 #define pci_getw (*pci_getw_func) 49 #define pci_getl (*pci_getl_func) 50 #define pci_putb (*pci_putb_func) 51 #define pci_putw (*pci_putw_func) 52 #define pci_putl (*pci_putl_func) 53 #define dcmn_err if (pci_boot_debug) cmn_err 54 55 #define CONFIG_INFO 0 56 #define CONFIG_UPDATE 1 57 #define CONFIG_NEW 2 58 #define CONFIG_FIX 3 59 #define COMPAT_BUFSIZE 512 60 61 /* See AMD-8111 Datasheet Rev 3.03, Page 149: */ 62 #define LPC_IO_CONTROL_REG_1 0x40 63 #define AMD8111_ENABLENMI (uint8_t)0x80 64 #define DEVID_AMD8111_LPC 0x7468 65 66 struct pci_fixundo { 67 uint8_t bus; 68 uint8_t dev; 69 uint8_t fn; 70 void (*undofn)(uint8_t, uint8_t, uint8_t); 71 struct pci_fixundo *next; 72 }; 73 74 extern int pci_bios_nbus; 75 static uchar_t max_dev_pci = 32; /* PCI standard */ 76 int pci_boot_debug = 0; 77 extern struct memlist *find_bus_res(int, int); 78 static struct pci_fixundo *undolist = NULL; 79 80 /* 81 * Module prototypes 82 */ 83 static void enumerate_bus_devs(uchar_t bus, int config_op); 84 static void create_root_bus_dip(uchar_t bus); 85 static dev_info_t *process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t, 86 ushort_t, int); 87 static void add_compatible(dev_info_t *, ushort_t, ushort_t, 88 ushort_t, ushort_t, uchar_t, uint_t, int); 89 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 90 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int); 91 static void add_model_prop(dev_info_t *, uint_t); 92 static void add_bus_range_prop(int); 93 static void add_bus_slot_names_prop(int); 94 static void add_ppb_ranges_prop(int); 95 static void add_bus_available_prop(int); 96 static ACPI_STATUS lookup_acpi_obj(ACPI_HANDLE, char *, ACPI_HANDLE *); 97 static int check_ppb_hotplug(dev_info_t *); 98 static void fix_ppb_res(uchar_t); 99 static void alloc_res_array(); 100 static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 101 ushort_t deviceid); 102 103 extern int pci_slot_names_prop(int, char *, int); 104 extern ACPI_STATUS pciehpc_acpi_eval_osc(ACPI_HANDLE, uint32_t *); 105 106 /* set non-zero to force PCI peer-bus renumbering */ 107 int pci_bus_always_renumber = 0; 108 109 /* get the subordinate bus # for a root/peer bus */ 110 static int 111 pci_root_subbus(int bus, uchar_t *subbus) 112 { 113 ACPI_HANDLE hdl; 114 ACPI_BUFFER rb; 115 ACPI_RESOURCE *rp; 116 int rv; 117 118 if (pci_bus_res[bus].dip == NULL) { 119 /* non-used bus # */ 120 return (AE_ERROR); 121 } 122 if (acpica_get_handle(pci_bus_res[bus].dip, &hdl) != AE_OK) { 123 cmn_err(CE_WARN, "!No ACPI obj for bus%d, ACPI OFF?\n", bus); 124 return (AE_ERROR); 125 } 126 127 rb.Length = ACPI_ALLOCATE_BUFFER; 128 if (AcpiGetCurrentResources(hdl, &rb) != AE_OK) { 129 cmn_err(CE_WARN, "!_CRS failed on pci%d\n", bus); 130 return (AE_ERROR); 131 } 132 133 rv = AE_ERROR; 134 135 for (rp = rb.Pointer; rp->Type != ACPI_RESOURCE_TYPE_END_TAG; 136 rp = ACPI_NEXT_RESOURCE(rp)) { 137 138 switch (rp->Type) { 139 case ACPI_RESOURCE_TYPE_ADDRESS16: 140 if (rp->Data.Address.ResourceType != 141 ACPI_BUS_NUMBER_RANGE) 142 continue; 143 *subbus = (uchar_t)rp->Data.Address16.Maximum; 144 dcmn_err(CE_NOTE, "Address16,subbus=%d\n", *subbus); 145 break; 146 case ACPI_RESOURCE_TYPE_ADDRESS32: 147 if (rp->Data.Address.ResourceType != 148 ACPI_BUS_NUMBER_RANGE) 149 continue; 150 *subbus = (uchar_t)rp->Data.Address32.Maximum; 151 dcmn_err(CE_NOTE, "Address32,subbus=%d\n", *subbus); 152 break; 153 case ACPI_RESOURCE_TYPE_ADDRESS64: 154 if (rp->Data.Address.ResourceType != 155 ACPI_BUS_NUMBER_RANGE) 156 continue; 157 *subbus = (uchar_t)rp->Data.Address64.Maximum; 158 dcmn_err(CE_NOTE, "Address64,subbus=%d\n", *subbus); 159 break; 160 case ACPI_RESOURCE_TYPE_EXTENDED_ADDRESS64: 161 if (rp->Data.Address.ResourceType != 162 ACPI_BUS_NUMBER_RANGE) 163 continue; 164 *subbus = (uchar_t)rp->Data.ExtAddress64.Maximum; 165 dcmn_err(CE_NOTE, "ExtAdr64,subbus=%d\n", *subbus); 166 break; 167 default: 168 dcmn_err(CE_NOTE, "rp->Type=%d\n", rp->Type); 169 continue; 170 } 171 172 /* found the bus-range resource */ 173 dcmn_err(CE_NOTE, "pci%d, subbus=%d\n", bus, *subbus); 174 rv = AE_OK; 175 176 /* This breaks out of the resource scanning loop */ 177 break; 178 } 179 180 AcpiOsFree(rb.Pointer); 181 if (rv != AE_OK) 182 cmn_err(CE_NOTE, "!No bus-range resource for pci%d\n", bus); 183 184 return (rv); 185 186 } 187 188 /* 189 * Enumerate all PCI devices 190 */ 191 void 192 pci_setup_tree() 193 { 194 uchar_t i, root_bus_addr = 0; 195 196 alloc_res_array(); 197 for (i = 0; i <= pci_bios_nbus; i++) { 198 pci_bus_res[i].par_bus = (uchar_t)-1; 199 pci_bus_res[i].root_addr = (uchar_t)-1; 200 pci_bus_res[i].sub_bus = i; 201 } 202 203 pci_bus_res[0].root_addr = root_bus_addr++; 204 create_root_bus_dip(0); 205 enumerate_bus_devs(0, CONFIG_INFO); 206 207 /* 208 * Now enumerate peer busses 209 * 210 * We loop till pci_bios_nbus. On most systems, there is 211 * one more bus at the high end, which implements the ISA 212 * compatibility bus. We don't care about that. 213 * 214 * Note: In the old (bootconf) enumeration, the peer bus 215 * address did not use the bus number, and there were 216 * too many peer busses created. The root_bus_addr is 217 * used to maintain the old peer bus address assignment. 218 * However, we stop enumerating phantom peers with no 219 * device below. 220 */ 221 for (i = 1; i <= pci_bios_nbus; i++) { 222 if (pci_bus_res[i].dip == NULL) { 223 pci_bus_res[i].root_addr = root_bus_addr++; 224 } 225 enumerate_bus_devs(i, CONFIG_INFO); 226 227 /* add slot-names property for named pci hot-plug slots */ 228 add_bus_slot_names_prop(i); 229 } 230 231 } 232 233 /* 234 * >0 = present, 0 = not present, <0 = error 235 */ 236 static int 237 pci_bbn_present(int bus) 238 { 239 ACPI_HANDLE hdl; 240 ACPI_BUFFER rb; 241 int rv; 242 243 /* no dip means no _BBN */ 244 if (pci_bus_res[bus].dip == NULL) 245 return (0); 246 247 rv = acpica_get_handle(pci_bus_res[bus].dip, &hdl); 248 if (rv != AE_OK) 249 return (-1); 250 251 rb.Length = ACPI_ALLOCATE_BUFFER; 252 253 rv = AcpiEvaluateObject(hdl, "_BBN", NULL, &rb); 254 255 if (rb.Length > 0) 256 AcpiOsFree(rb.Pointer); 257 258 if (rv == AE_OK) 259 return (1); 260 else if (rv == AE_NOT_FOUND) 261 return (0); 262 else 263 return (-1); 264 } 265 266 /* 267 * Return non-zero if any PCI bus in the system has an associated 268 * _BBN object, 0 otherwise. 269 */ 270 static int 271 pci_roots_have_bbn(void) 272 { 273 int i; 274 275 /* 276 * Scan the PCI busses and look for at least 1 _BBN 277 */ 278 for (i = 0; i <= pci_bios_nbus; i++) { 279 /* skip non-root (peer) PCI busses */ 280 if (pci_bus_res[i].par_bus != (uchar_t)-1) 281 continue; 282 283 if (pci_bbn_present(i) > 0) 284 return (1); 285 } 286 return (0); 287 288 } 289 290 /* 291 * return non-zero if the machine is one on which we renumber 292 * the internal pci unit-addresses 293 */ 294 static int 295 pci_bus_renumber() 296 { 297 ACPI_TABLE_HEADER *fadt; 298 299 if (pci_bus_always_renumber) 300 return (1); 301 302 /* get the FADT */ 303 if (AcpiGetFirmwareTable(FADT_SIG, 1, ACPI_LOGICAL_ADDRESSING, 304 (ACPI_TABLE_HEADER **)&fadt) != AE_OK) 305 return (0); 306 307 /* compare OEM Table ID to "SUNm31" */ 308 if (strncmp("SUNm31", fadt->OemId, 6)) 309 return (0); 310 else 311 return (1); 312 } 313 314 /* 315 * Initial enumeration of the physical PCI bus hierarchy can 316 * leave 'gaps' in the order of peer PCI bus unit-addresses. 317 * Systems with more than one peer PCI bus *must* have an ACPI 318 * _BBN object associated with each peer bus; use the presence 319 * of this object to remove gaps in the numbering of the peer 320 * PCI bus unit-addresses - only peer busses with an associated 321 * _BBN are counted. 322 */ 323 static void 324 pci_renumber_root_busses(void) 325 { 326 int pci_regs[] = {0, 0, 0}; 327 int i, root_addr = 0; 328 329 /* 330 * Currently, we only enable the re-numbering on specific 331 * Sun machines; this is a work-around for the more complicated 332 * issue of upgrade changing physical device paths 333 */ 334 if (!pci_bus_renumber()) 335 return; 336 337 /* 338 * If we find no _BBN objects at all, we either don't need 339 * to do anything or can't do anything anyway 340 */ 341 if (!pci_roots_have_bbn()) 342 return; 343 344 for (i = 0; i <= pci_bios_nbus; i++) { 345 /* skip non-root (peer) PCI busses */ 346 if (pci_bus_res[i].par_bus != (uchar_t)-1) 347 continue; 348 349 if (pci_bbn_present(i) < 1) { 350 pci_bus_res[i].root_addr = (uchar_t)-1; 351 continue; 352 } 353 354 ASSERT(pci_bus_res[i].dip != NULL); 355 if (pci_bus_res[i].root_addr != root_addr) { 356 /* update reg property for node */ 357 pci_bus_res[i].root_addr = root_addr; 358 pci_regs[0] = pci_bus_res[i].root_addr; 359 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 360 pci_bus_res[i].dip, "reg", (int *)pci_regs, 3); 361 } 362 root_addr++; 363 } 364 } 365 366 static void 367 remove_resource_range(struct memlist **list, int *ranges, int range_count) 368 { 369 struct range { 370 uint32_t base; 371 uint32_t len; 372 }; 373 int index; 374 375 for (index = 0; index < range_count; index++) { 376 /* all done if list is or has become empty */ 377 if (*list == NULL) 378 break; 379 (void) memlist_remove(list, 380 (uint64_t)((struct range *)ranges)[index].base, 381 (uint64_t)((struct range *)ranges)[index].len); 382 } 383 } 384 385 static void 386 remove_used_resources() 387 { 388 dev_info_t *used; 389 int *narray; 390 uint_t ncount; 391 int status; 392 int bus; 393 394 used = ddi_find_devinfo("used-resources", -1, 0); 395 if (used == NULL) 396 return; 397 398 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used, 399 DDI_PROP_DONTPASS, "io-space", &narray, &ncount); 400 if (status == DDI_PROP_SUCCESS) { 401 for (bus = 0; bus <= pci_bios_nbus; bus++) 402 remove_resource_range(&pci_bus_res[bus].io_ports, 403 narray, ncount / 2); 404 ddi_prop_free(narray); 405 } 406 407 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used, 408 DDI_PROP_DONTPASS, "device-memory", &narray, &ncount); 409 if (status == DDI_PROP_SUCCESS) { 410 for (bus = 0; bus <= pci_bios_nbus; bus++) 411 remove_resource_range(&pci_bus_res[bus].mem_space, 412 narray, ncount / 2); 413 ddi_prop_free(narray); 414 } 415 } 416 417 /* 418 * Walk up ACPI namespace starting from parobj looking for object with name 419 */ 420 static ACPI_STATUS 421 lookup_acpi_obj(ACPI_HANDLE parobj, char *name, ACPI_HANDLE *retobjp) 422 { 423 ACPI_HANDLE obj; 424 425 do { 426 if (AcpiGetHandle(parobj, name, retobjp) == AE_OK) { 427 ASSERT(*retobjp != NULL); 428 return (AE_OK); 429 } 430 obj = parobj; 431 } while (AcpiGetParent(obj, &parobj) == AE_OK); 432 433 *retobjp = NULL; 434 return (AE_NOT_FOUND); 435 } 436 437 static int 438 check_ppb_hotplug(dev_info_t *dip) 439 { 440 ACPI_HANDLE pcibus_obj; 441 ACPI_HANDLE obj; 442 uint32_t hp_mode = ACPI_HP_MODE; 443 444 if (ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 445 "pci-hotplug-type", INBAND_HPC_NONE) != INBAND_HPC_PCIE) 446 return (0); 447 448 if (acpica_get_handle(dip, &pcibus_obj) != AE_OK) 449 return (0); 450 451 if (lookup_acpi_obj(pcibus_obj, "_OSC", &obj) == AE_OK) { 452 if (pciehpc_acpi_eval_osc(obj, &hp_mode) != AE_OK) 453 hp_mode = ACPI_HP_MODE; 454 } 455 456 if (hp_mode == NATIVE_HP_MODE) 457 return (1); 458 459 /* 460 * if ACPI hotplug mode, a child obj for the slot is also required 461 */ 462 if (AcpiGetNextObject(ACPI_TYPE_DEVICE, pcibus_obj, NULL, &obj) != 463 AE_OK) 464 return (0); 465 466 return (1); 467 } 468 469 /* 470 * Assign i/o resources to unconfigured hotplug bridges after the first pass. 471 * It must be after the first pass in order to use the ports left over after 472 * accounting for i/o resources of bridges that have been configured by bios. 473 * We are expecting unconfigured bridges to be empty bridges otherwise 474 * this resource assignment needs to be done at an earlier stage. 475 */ 476 static void 477 fix_ppb_res(uchar_t secbus) 478 { 479 uchar_t bus, dev, func; 480 uint_t base, limit; 481 uint_t io_size = 0x1000; /* io range must be mult of and 4k aligned */ 482 uint64_t addr; 483 int *regp = NULL; 484 uint_t reglen; 485 int rv, cap_ptr, physhi; 486 dev_info_t *dip; 487 488 /* some entries may be empty due to discontiguous bus numbering */ 489 dip = pci_bus_res[secbus].dip; 490 if (dip == NULL) 491 return; 492 493 if (!check_ppb_hotplug(dip)) 494 return; 495 496 rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 497 "reg", ®p, ®len); 498 ASSERT(rv == DDI_PROP_SUCCESS && reglen > 0); 499 physhi = regp[0]; 500 ddi_prop_free(regp); 501 502 func = (uchar_t)PCI_REG_FUNC_G(physhi); 503 dev = (uchar_t)PCI_REG_DEV_G(physhi); 504 bus = (uchar_t)PCI_REG_BUS_G(physhi); 505 ASSERT(bus == pci_bus_res[secbus].par_bus); 506 507 /* 508 * Check if the slot is enabled 509 */ 510 cap_ptr = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 511 "pcie-capid-pointer", PCI_CAP_NEXT_PTR_NULL); 512 if (cap_ptr == PCI_CAP_NEXT_PTR_NULL) 513 return; 514 515 if (pci_getw(bus, dev, func, (uint16_t)cap_ptr + PCIE_LINKCTL) & 516 PCIE_LINKCTL_LINK_DISABLE) 517 return; 518 519 /* 520 * base >= limit means that the bridge was not configured 521 * This may have been set by the bios or by add_ppb_props() upon 522 * detecting that I/O was disabled 523 */ 524 525 /* 526 * I/O; check and attempt to allocate io_size amount from parent 527 */ 528 base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 529 limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 530 ASSERT(base != 0xff && limit != 0xff); 531 532 base = (base & 0xf0) << 8; 533 limit = ((limit & 0xf0) << 8) | 0xfff; 534 535 addr = 0; 536 if ((base > limit || base == 0) && 537 pci_bus_res[bus].io_ports != NULL) { 538 addr = memlist_find(&pci_bus_res[bus].io_ports, io_size, 539 0x1000); 540 ASSERT(addr <= 0xffff - io_size); 541 } 542 if (addr != 0) { 543 memlist_insert(&pci_bus_res[secbus].io_ports, addr, io_size); 544 base = addr; 545 limit = addr + io_size - 1; 546 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 547 (uint8_t)((base >> 8) & 0xf0)); 548 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 549 (uint8_t)((limit >> 8) & 0xf0)); 550 } 551 552 /* 553 * Account for new resources 554 */ 555 add_ppb_ranges_prop(secbus); 556 } 557 558 void 559 pci_reprogram(void) 560 { 561 int i, pci_reconfig = 1; 562 char *onoff; 563 564 /* 565 * Excise phantom roots if possible 566 */ 567 pci_renumber_root_busses(); 568 569 /* add bus-range property for root/peer bus nodes */ 570 for (i = 0; i <= pci_bios_nbus; i++) { 571 if (pci_bus_res[i].par_bus == (uchar_t)-1) { 572 uchar_t subbus; 573 if (pci_root_subbus(i, &subbus) == AE_OK) 574 pci_bus_res[i].sub_bus = subbus; 575 add_bus_range_prop(i); 576 } 577 } 578 579 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 580 DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 581 if (strcmp(onoff, "off") == 0) { 582 pci_reconfig = 0; 583 cmn_err(CE_NOTE, "pci device reprogramming disabled"); 584 } 585 ddi_prop_free(onoff); 586 } 587 588 /* remove used-resources from PCI resource maps */ 589 remove_used_resources(); 590 591 for (i = 0; i <= pci_bios_nbus; i++) { 592 /* configure devices not configured by bios */ 593 if (pci_reconfig) { 594 fix_ppb_res(i); 595 enumerate_bus_devs(i, CONFIG_NEW); 596 } 597 /* All dev programmed, so we can create available prop */ 598 add_bus_available_prop(i); 599 } 600 } 601 602 /* 603 * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 604 */ 605 static void 606 create_root_bus_dip(uchar_t bus) 607 { 608 int pci_regs[] = {0, 0, 0}; 609 dev_info_t *dip; 610 611 ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 612 613 ndi_devi_alloc_sleep(ddi_root_node(), "pci", 614 (pnode_t)DEVI_SID_NODEID, &dip); 615 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 616 "#address-cells", 3); 617 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 618 "#size-cells", 2); 619 pci_regs[0] = pci_bus_res[bus].root_addr; 620 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 621 "reg", (int *)pci_regs, 3); 622 623 /* 624 * If system has PCIe bus, then create different properties 625 */ 626 if (create_pcie_root_bus(bus, dip) == B_FALSE) 627 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 628 "device_type", "pci"); 629 630 (void) ndi_devi_bind_driver(dip, 0); 631 pci_bus_res[bus].dip = dip; 632 pci_bus_res[bus].pmem_space = find_bus_res(bus, PREFETCH_TYPE); 633 pci_bus_res[bus].mem_space = find_bus_res(bus, MEM_TYPE); 634 pci_bus_res[bus].io_ports = find_bus_res(bus, IO_TYPE); 635 636 if (bus != 0) 637 return; 638 639 /* 640 * Special treatment of bus 0: 641 * If no resource from MPSPEC/HRT, copy pcimem from boot 642 * and make I/O space the entire range starting at 0x100. There 643 * is no difference between prefetchable memory or not. 644 */ 645 if (pci_bus_res[0].mem_space == NULL) 646 pci_bus_res[0].mem_space = 647 memlist_dup(bootops->boot_mem->pcimem); 648 /* Exclude 0x00 to 0xff of the I/O space, used by all PCs */ 649 if (pci_bus_res[0].io_ports == NULL) 650 memlist_insert(&pci_bus_res[0].io_ports, 0x100, 0xffff); 651 } 652 653 /* 654 * For any fixed configuration (often compatability) pci devices 655 * and those with their own expansion rom, create device nodes 656 * to hold the already configured device details. 657 */ 658 void 659 enumerate_bus_devs(uchar_t bus, int config_op) 660 { 661 uchar_t dev, func, nfunc, header; 662 ushort_t venid; 663 dev_info_t *dip; 664 struct pci_devfunc { 665 struct pci_devfunc *next; 666 dev_info_t *dip; 667 uchar_t bus; 668 uchar_t dev; 669 uchar_t func; 670 } *devlist = NULL, *entry; 671 672 if (config_op == CONFIG_NEW) { 673 dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 674 } else if (config_op == CONFIG_FIX) { 675 dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus); 676 } else 677 dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 678 679 for (dev = 0; dev < max_dev_pci; dev++) { 680 nfunc = 1; 681 for (func = 0; func < nfunc; func++) { 682 683 dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", 684 dev, func); 685 686 venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 687 688 if ((venid == 0xffff) || (venid == 0)) { 689 /* no function at this address */ 690 continue; 691 } 692 693 header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 694 if (header == 0xff) { 695 continue; /* illegal value */ 696 } 697 698 /* 699 * according to some mail from Microsoft posted 700 * to the pci-drivers alias, their only requirement 701 * for a multifunction device is for the 1st 702 * function to have to PCI_HEADER_MULTI bit set. 703 */ 704 if ((func == 0) && (header & PCI_HEADER_MULTI)) { 705 nfunc = 8; 706 } 707 708 if (config_op == CONFIG_FIX) { 709 /* 710 * If we're processing PCI fixes, no dip 711 * will be returned. 712 */ 713 (void) process_devfunc(bus, dev, func, header, 714 venid, config_op); 715 716 } else if (config_op == CONFIG_INFO) { 717 /* 718 * Create the node, unconditionally, on the 719 * first pass only. It may still need 720 * resource assignment, which will be 721 * done on the second, CONFIG_NEW, pass. 722 */ 723 dip = process_devfunc(bus, dev, func, header, 724 venid, config_op); 725 /* 726 * If dip isn't null, put on a list to 727 * save for reprogramming when config_op 728 * is CONFIG_NEW. 729 */ 730 731 if (dip) { 732 entry = kmem_alloc(sizeof (*entry), 733 KM_SLEEP); 734 entry->dip = dip; 735 entry->dev = dev; 736 entry->func = func; 737 entry->next = devlist; 738 devlist = entry; 739 } 740 } 741 } 742 } 743 744 if (config_op == CONFIG_NEW) { 745 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 746 while (devlist) { 747 entry = devlist; 748 devlist = entry->next; 749 cmn_err(CE_NOTE, 750 "!reprogram pci device [%d/%d/%d] (%s)", 751 bus, entry->dev, entry->func, 752 ddi_driver_name(entry->dip)); 753 (void) add_reg_props(entry->dip, bus, entry->dev, 754 entry->func, CONFIG_UPDATE, 0); 755 kmem_free(entry, sizeof (*entry)); 756 } 757 pci_bus_res[bus].privdata = NULL; 758 } else if (config_op != CONFIG_FIX) { 759 pci_bus_res[bus].privdata = devlist; 760 } 761 } 762 763 static int 764 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 765 ushort_t subvenid, ushort_t subdevid) 766 { 767 static int prop_exist = -1; 768 static char *pciide_str; 769 char compat[32]; 770 771 if (prop_exist == -1) { 772 prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 773 ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 774 &pciide_str) == DDI_SUCCESS); 775 } 776 777 if (!prop_exist) 778 return (0); 779 780 /* compare property value against various forms of compatible */ 781 if (subvenid) { 782 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 783 venid, devid, subvenid, subdevid, revid); 784 if (strcmp(pciide_str, compat) == 0) 785 return (1); 786 787 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 788 venid, devid, subvenid, subdevid); 789 if (strcmp(pciide_str, compat) == 0) 790 return (1); 791 792 (void) snprintf(compat, sizeof (compat), "pci%x,%x", 793 subvenid, subdevid); 794 if (strcmp(pciide_str, compat) == 0) 795 return (1); 796 } 797 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 798 venid, devid, revid); 799 if (strcmp(pciide_str, compat) == 0) 800 return (1); 801 802 (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 803 if (strcmp(pciide_str, compat) == 0) 804 return (1); 805 806 return (0); 807 } 808 809 static int 810 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 811 ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 812 { 813 struct ide_table { /* table for PCI_MASS_OTHER */ 814 ushort_t venid; 815 ushort_t devid; 816 } *entry; 817 818 /* XXX SATA devices: need a way to add dynamically */ 819 static struct ide_table ide_other[] = { 820 {0x1095, 0x3112}, 821 {0x1095, 0x3114}, 822 {0x1095, 0x3512}, 823 {0, 0} 824 }; 825 826 if (basecl != PCI_CLASS_MASS) 827 return (0); 828 829 if (subcl == PCI_MASS_IDE) { 830 return (1); 831 } 832 833 if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 834 return (0); 835 } 836 837 entry = &ide_other[0]; 838 while (entry->venid) { 839 if (entry->venid == venid && entry->devid == devid) 840 return (1); 841 entry++; 842 } 843 return (check_pciide_prop(revid, venid, devid, subvenid, subdevid)); 844 } 845 846 static int 847 is_display(uint_t classcode) 848 { 849 static uint_t disp_classes[] = { 850 0x000100, 851 0x030000, 852 0x030001 853 }; 854 int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 855 856 for (i = 0; i < nclasses; i++) { 857 if (classcode == disp_classes[i]) 858 return (1); 859 } 860 return (0); 861 } 862 863 static void 864 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn, 865 void (*undofn)(uint8_t, uint8_t, uint8_t)) 866 { 867 struct pci_fixundo *newundo; 868 869 newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP); 870 871 /* 872 * Adding an item to this list means that we must turn its NMIENABLE 873 * bit back on at a later time. 874 */ 875 newundo->bus = bus; 876 newundo->dev = dev; 877 newundo->fn = fn; 878 newundo->undofn = undofn; 879 newundo->next = undolist; 880 881 /* add to the undo list in LIFO order */ 882 undolist = newundo; 883 } 884 885 void 886 add_pci_fixes(void) 887 { 888 int i; 889 890 for (i = 0; i <= pci_bios_nbus; i++) { 891 /* 892 * For each bus, apply needed fixes to the appropriate devices. 893 * This must be done before the main enumeration loop because 894 * some fixes must be applied to devices normally encountered 895 * later in the pci scan (e.g. if a fix to device 7 must be 896 * applied before scanning device 6, applying fixes in the 897 * normal enumeration loop would obviously be too late). 898 */ 899 enumerate_bus_devs(i, CONFIG_FIX); 900 } 901 } 902 903 void 904 undo_pci_fixes(void) 905 { 906 struct pci_fixundo *nextundo; 907 uint8_t bus, dev, fn; 908 909 /* 910 * All fixes in the undo list are performed unconditionally. Future 911 * fixes may require selective undo. 912 */ 913 while (undolist != NULL) { 914 915 bus = undolist->bus; 916 dev = undolist->dev; 917 fn = undolist->fn; 918 919 (*(undolist->undofn))(bus, dev, fn); 920 921 nextundo = undolist->next; 922 kmem_free(undolist, sizeof (struct pci_fixundo)); 923 undolist = nextundo; 924 } 925 } 926 927 static void 928 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn) 929 { 930 uint8_t val8; 931 932 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 933 /* 934 * The NMIONERR bit is turned back on to allow the SMM BIOS 935 * to handle more critical PCI errors (e.g. PERR#). 936 */ 937 val8 |= AMD8111_ENABLENMI; 938 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 939 } 940 941 static void 942 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn) 943 { 944 uint8_t val8; 945 946 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 947 948 if ((val8 & AMD8111_ENABLENMI) == 0) 949 return; 950 951 /* 952 * We reset NMIONERR in the LPC because master-abort on the PCI 953 * bridge side of the 8111 will cause NMI, which might cause SMI, 954 * which sometimes prevents all devices from being enumerated. 955 */ 956 val8 &= ~AMD8111_ENABLENMI; 957 958 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 959 960 add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix); 961 } 962 963 static dev_info_t * 964 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 965 ushort_t vendorid, int config_op) 966 { 967 char nodename[32], unitaddr[5]; 968 dev_info_t *dip; 969 uchar_t basecl, subcl, progcl, intr, revid; 970 ushort_t subvenid, subdevid, status; 971 ushort_t slot_num; 972 uint_t classcode, revclass; 973 int reprogram = 0, pciide = 0; 974 int power[2] = {1, 1}; 975 int pciex = 0; 976 ushort_t is_pci_bridge = 0; 977 978 ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 979 980 switch (header & PCI_HEADER_TYPE_M) { 981 case PCI_HEADER_ZERO: 982 subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 983 subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 984 break; 985 case PCI_HEADER_CARDBUS: 986 subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 987 subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 988 break; 989 default: 990 subvenid = 0; 991 subdevid = 0; 992 break; 993 } 994 995 if (config_op == CONFIG_FIX) { 996 if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) { 997 pci_fix_amd8111(bus, dev, func); 998 } 999 return (NULL); 1000 } 1001 1002 /* XXX should be use generic names? derive from class? */ 1003 revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 1004 classcode = revclass >> 8; 1005 revid = revclass & 0xff; 1006 1007 /* figure out if this is pci-ide */ 1008 basecl = classcode >> 16; 1009 subcl = (classcode >> 8) & 0xff; 1010 progcl = classcode & 0xff; 1011 1012 1013 if (is_display(classcode)) 1014 (void) snprintf(nodename, sizeof (nodename), "display"); 1015 else if (subvenid != 0) 1016 (void) snprintf(nodename, sizeof (nodename), 1017 "pci%x,%x", subvenid, subdevid); 1018 else 1019 (void) snprintf(nodename, sizeof (nodename), 1020 "pci%x,%x", vendorid, deviceid); 1021 1022 /* make sure parent bus dip has been created */ 1023 if (pci_bus_res[bus].dip == NULL) { 1024 create_root_bus_dip(bus); 1025 } 1026 1027 ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 1028 DEVI_SID_NODEID, &dip); 1029 1030 if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num, 1031 &is_pci_bridge) == B_TRUE) 1032 pciex = 1; 1033 1034 /* add properties */ 1035 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 1036 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 1037 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 1038 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1039 "class-code", classcode); 1040 if (func == 0) 1041 (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 1042 else 1043 (void) snprintf(unitaddr, sizeof (unitaddr), 1044 "%x,%x", dev, func); 1045 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1046 "unit-address", unitaddr); 1047 1048 /* add device_type for display nodes */ 1049 if (is_display(classcode)) { 1050 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1051 "device_type", "display"); 1052 } 1053 /* add special stuff for header type */ 1054 if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 1055 uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 1056 uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 1057 1058 if (subvenid != 0) { 1059 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1060 "subsystem-id", subdevid); 1061 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1062 "subsystem-vendor-id", subvenid); 1063 } 1064 if (!pciex) 1065 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1066 "min-grant", mingrant); 1067 if (!pciex) 1068 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1069 "max-latency", maxlatency); 1070 } 1071 1072 /* interrupt, record if not 0 */ 1073 intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 1074 if (intr != 0) 1075 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1076 "interrupts", intr); 1077 1078 /* 1079 * Add support for 133 mhz pci eventually 1080 */ 1081 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 1082 1083 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1084 "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 1085 if (!pciex && (status & PCI_STAT_FBBC)) 1086 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1087 "fast-back-to-back"); 1088 if (!pciex && (status & PCI_STAT_66MHZ)) 1089 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1090 "66mhz-capable"); 1091 if (status & PCI_STAT_UDF) 1092 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1093 "udf-supported"); 1094 if (pciex && slot_num) 1095 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1096 "physical-slot#", slot_num); 1097 1098 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1099 "power-consumption", power, 2); 1100 1101 if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) 1102 add_ppb_props(dip, bus, dev, func, pciex); 1103 1104 if (config_op == CONFIG_INFO && 1105 IS_CLASS_IOAPIC(basecl, subcl, progcl)) { 1106 create_ioapic_node(bus, dev, func, vendorid, deviceid); 1107 } 1108 1109 /* check for ck8-04 based PCI ISA bridge only */ 1110 if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) && 1111 (func == 0)) 1112 add_nvidia_isa_bridge_props(dip, bus, dev, func); 1113 1114 if (pciex && is_pci_bridge) 1115 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 1116 (char *)"PCIe-PCI bridge"); 1117 else 1118 add_model_prop(dip, classcode); 1119 1120 add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 1121 revid, classcode, pciex); 1122 1123 /* 1124 * See if this device is a controller that advertises 1125 * itself to be a standard ATA task file controller, or one that 1126 * has been hard coded. 1127 * 1128 * If it is, check if any other higher precedence driver listed in 1129 * driver_aliases will claim the node by calling 1130 * ddi_compatibile_driver_major. If so, clear pciide and do not 1131 * create a pci-ide node or any other special handling. 1132 * 1133 * If another driver does not bind, set the node name to pci-ide 1134 * and then let the special pci-ide handling for registers and 1135 * child pci-ide nodes proceed below. 1136 */ 1137 if (is_pciide(basecl, subcl, revid, vendorid, deviceid, 1138 subvenid, subdevid) == 1) { 1139 if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) { 1140 (void) ndi_devi_set_nodename(dip, "pci-ide", 0); 1141 pciide = 1; 1142 } 1143 } 1144 1145 reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 1146 (void) ndi_devi_bind_driver(dip, 0); 1147 1148 /* special handling for pci-ide */ 1149 if (pciide) { 1150 dev_info_t *cdip; 1151 1152 /* 1153 * Create properties specified by P1275 Working Group 1154 * Proposal #414 Version 1 1155 */ 1156 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1157 "device_type", "pci-ide"); 1158 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1159 "#address-cells", 1); 1160 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1161 "#size-cells", 0); 1162 1163 /* allocate two child nodes */ 1164 ndi_devi_alloc_sleep(dip, "ide", 1165 (pnode_t)DEVI_SID_NODEID, &cdip); 1166 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 1167 "reg", 0); 1168 (void) ndi_devi_bind_driver(cdip, 0); 1169 ndi_devi_alloc_sleep(dip, "ide", 1170 (pnode_t)DEVI_SID_NODEID, &cdip); 1171 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 1172 "reg", 1); 1173 (void) ndi_devi_bind_driver(cdip, 0); 1174 1175 reprogram = 0; /* don't reprogram pci-ide bridge */ 1176 } 1177 1178 1179 if (reprogram) 1180 return (dip); 1181 return (NULL); 1182 } 1183 1184 /* 1185 * Set the compatible property to a value compliant with 1186 * rev 2.1 of the IEEE1275 PCI binding. 1187 * (Also used for PCI-Express devices). 1188 * 1189 * pciVVVV,DDDD.SSSS.ssss.RR (0) 1190 * pciVVVV,DDDD.SSSS.ssss (1) 1191 * pciSSSS,ssss (2) 1192 * pciVVVV,DDDD.RR (3) 1193 * pciVVVV,DDDD (4) 1194 * pciclass,CCSSPP (5) 1195 * pciclass,CCSS (6) 1196 * 1197 * The Subsystem (SSSS) forms are not inserted if 1198 * subsystem-vendor-id is 0. 1199 * 1200 * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above 1201 * property 2 is not created as per "1275 bindings for PCI Express Interconnect" 1202 * 1203 * Set with setprop and \x00 between each 1204 * to generate the encoded string array form. 1205 */ 1206 void 1207 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 1208 ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode, 1209 int pciex) 1210 { 1211 int i = 0; 1212 int size = COMPAT_BUFSIZE; 1213 char *compat[13]; 1214 char *buf, *curr; 1215 1216 curr = buf = kmem_alloc(size, KM_SLEEP); 1217 1218 if (pciex) { 1219 if (subvenid) { 1220 compat[i++] = curr; /* form 0 */ 1221 (void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x", 1222 vendorid, deviceid, subvenid, subdevid, revid); 1223 size -= strlen(curr) + 1; 1224 curr += strlen(curr) + 1; 1225 1226 compat[i++] = curr; /* form 1 */ 1227 (void) snprintf(curr, size, "pciex%x,%x.%x.%x", 1228 vendorid, deviceid, subvenid, subdevid); 1229 size -= strlen(curr) + 1; 1230 curr += strlen(curr) + 1; 1231 1232 } 1233 compat[i++] = curr; /* form 3 */ 1234 (void) snprintf(curr, size, "pciex%x,%x.%x", 1235 vendorid, deviceid, revid); 1236 size -= strlen(curr) + 1; 1237 curr += strlen(curr) + 1; 1238 1239 compat[i++] = curr; /* form 4 */ 1240 (void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid); 1241 size -= strlen(curr) + 1; 1242 curr += strlen(curr) + 1; 1243 1244 compat[i++] = curr; /* form 5 */ 1245 (void) snprintf(curr, size, "pciexclass,%06x", classcode); 1246 size -= strlen(curr) + 1; 1247 curr += strlen(curr) + 1; 1248 1249 compat[i++] = curr; /* form 6 */ 1250 (void) snprintf(curr, size, "pciexclass,%04x", 1251 (classcode >> 8)); 1252 size -= strlen(curr) + 1; 1253 curr += strlen(curr) + 1; 1254 } 1255 1256 if (subvenid) { 1257 compat[i++] = curr; /* form 0 */ 1258 (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 1259 vendorid, deviceid, subvenid, subdevid, revid); 1260 size -= strlen(curr) + 1; 1261 curr += strlen(curr) + 1; 1262 1263 compat[i++] = curr; /* form 1 */ 1264 (void) snprintf(curr, size, "pci%x,%x.%x.%x", 1265 vendorid, deviceid, subvenid, subdevid); 1266 size -= strlen(curr) + 1; 1267 curr += strlen(curr) + 1; 1268 1269 compat[i++] = curr; /* form 2 */ 1270 (void) snprintf(curr, size, "pci%x,%x", subvenid, subdevid); 1271 size -= strlen(curr) + 1; 1272 curr += strlen(curr) + 1; 1273 } 1274 compat[i++] = curr; /* form 3 */ 1275 (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 1276 size -= strlen(curr) + 1; 1277 curr += strlen(curr) + 1; 1278 1279 compat[i++] = curr; /* form 4 */ 1280 (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 1281 size -= strlen(curr) + 1; 1282 curr += strlen(curr) + 1; 1283 1284 compat[i++] = curr; /* form 5 */ 1285 (void) snprintf(curr, size, "pciclass,%06x", classcode); 1286 size -= strlen(curr) + 1; 1287 curr += strlen(curr) + 1; 1288 1289 compat[i++] = curr; /* form 6 */ 1290 (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 1291 size -= strlen(curr) + 1; 1292 curr += strlen(curr) + 1; 1293 1294 (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 1295 "compatible", compat, i); 1296 kmem_free(buf, COMPAT_BUFSIZE); 1297 } 1298 1299 /* 1300 * Adjust the reg properties for a dual channel PCI-IDE device. 1301 * 1302 * NOTE: don't do anything that changes the order of the hard-decodes 1303 * and programmed BARs. The kernel driver depends on these values 1304 * being in this order regardless of whether they're for a 'native' 1305 * mode BAR or not. 1306 */ 1307 /* 1308 * config info for pci-ide devices 1309 */ 1310 static struct { 1311 uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 1312 uchar_t bar_offset; /* offset for alt status register */ 1313 ushort_t addr; /* compatibility mode base address */ 1314 ushort_t length; /* number of ports for this BAR */ 1315 } pciide_bar[] = { 1316 { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 1317 { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 1318 { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 1319 { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 1320 }; 1321 1322 static int 1323 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 1324 { 1325 int hard_decode = 0; 1326 1327 /* 1328 * Adjust the base and len for the BARs of the PCI-IDE 1329 * device's primary and secondary controllers. The first 1330 * two BARs are for the primary controller and the next 1331 * two BARs are for the secondary controller. The fifth 1332 * and sixth bars are never adjusted. 1333 */ 1334 if (index >= 0 && index <= 3) { 1335 *lenp = pciide_bar[index].length; 1336 1337 if (progcl & pciide_bar[index].native_mask) { 1338 *basep += pciide_bar[index].bar_offset; 1339 } else { 1340 *basep = pciide_bar[index].addr; 1341 hard_decode = 1; 1342 } 1343 } 1344 1345 /* 1346 * if either base or len is zero make certain both are zero 1347 */ 1348 if (*basep == 0 || *lenp == 0) { 1349 *basep = 0; 1350 *lenp = 0; 1351 hard_decode = 0; 1352 } 1353 1354 return (hard_decode); 1355 } 1356 1357 1358 /* 1359 * Add the "reg" and "assigned-addresses" property 1360 */ 1361 static int 1362 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 1363 int config_op, int pciide) 1364 { 1365 uchar_t baseclass, subclass, progclass, header; 1366 ushort_t bar_sz; 1367 uint_t value = 0, len, devloc; 1368 uint_t base, base_hi, type; 1369 ushort_t offset, end; 1370 int max_basereg, j, reprogram = 0; 1371 uint_t phys_hi; 1372 struct memlist **io_res, **mres, **mem_res, **pmem_res; 1373 uint16_t cmd_reg; 1374 1375 pci_regspec_t regs[16] = {{0}}; 1376 pci_regspec_t assigned[15] = {{0}}; 1377 int nreg, nasgn, enable = 0; 1378 1379 io_res = &pci_bus_res[bus].io_ports; 1380 mem_res = &pci_bus_res[bus].mem_space; 1381 if (bus == 0) /* for bus 0, there is only mem_space */ 1382 pmem_res = mem_res; 1383 else 1384 pmem_res = &pci_bus_res[bus].pmem_space; 1385 1386 devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 1387 regs[0].pci_phys_hi = devloc; 1388 nreg = 1; /* rest of regs[0] is all zero */ 1389 nasgn = 0; 1390 1391 baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 1392 subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 1393 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 1394 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1395 1396 switch (header) { 1397 case PCI_HEADER_ZERO: 1398 max_basereg = PCI_BASE_NUM; 1399 break; 1400 case PCI_HEADER_PPB: 1401 max_basereg = PCI_BCNF_BASE_NUM; 1402 break; 1403 case PCI_HEADER_CARDBUS: 1404 max_basereg = PCI_CBUS_BASE_NUM; 1405 break; 1406 default: 1407 max_basereg = 0; 1408 break; 1409 } 1410 1411 /* 1412 * Create the register property by saving the current 1413 * value of the base register. Write 0xffffffff to the 1414 * base register. Read the value back to determine the 1415 * required size of the address space. Restore the base 1416 * register contents. 1417 * 1418 * Do not disable I/O and memory access; this isn't necessary 1419 * since no driver is yet attached to this device, and disabling 1420 * I/O and memory access has the side-effect of disabling PCI-PCI 1421 * bridge mappings, which makes the bridge transparent to secondary- 1422 * bus activity (see sections 4.1-4.3 of the PCI-PCI Bridge 1423 * Spec V1.2). 1424 */ 1425 end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 1426 for (j = 0, offset = PCI_CONF_BASE0; offset < end; 1427 j++, offset += bar_sz) { 1428 int hard_decode = 0; 1429 1430 /* determine the size of the address space */ 1431 base = pci_getl(bus, dev, func, offset); 1432 pci_putl(bus, dev, func, offset, 0xffffffff); 1433 value = pci_getl(bus, dev, func, offset); 1434 pci_putl(bus, dev, func, offset, base); 1435 1436 /* construct phys hi,med.lo, size hi, lo */ 1437 if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 1438 /* i/o space */ 1439 bar_sz = PCI_BAR_SZ_32; 1440 value &= PCI_BASE_IO_ADDR_M; 1441 len = ((value ^ (value-1)) + 1) >> 1; 1442 1443 /* XXX Adjust first 4 IDE registers */ 1444 if (pciide) { 1445 if (subclass != PCI_MASS_IDE) 1446 progclass = (PCI_IDE_IF_NATIVE_PRI | 1447 PCI_IDE_IF_NATIVE_SEC); 1448 hard_decode = pciIdeAdjustBAR(progclass, j, 1449 &base, &len); 1450 } else if (value == 0) { 1451 /* skip base regs with size of 0 */ 1452 continue; 1453 } 1454 1455 regs[nreg].pci_size_low = 1456 assigned[nasgn].pci_size_low = len; 1457 if (!hard_decode) { 1458 regs[nreg].pci_phys_hi = 1459 (PCI_ADDR_IO | devloc) + offset; 1460 } else { 1461 regs[nreg].pci_phys_hi = 1462 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + 1463 offset; 1464 regs[nreg].pci_phys_low = 1465 base & PCI_BASE_IO_ADDR_M; 1466 } 1467 assigned[nasgn].pci_phys_hi = 1468 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + offset; 1469 type = base & (~PCI_BASE_IO_ADDR_M); 1470 base &= PCI_BASE_IO_ADDR_M; 1471 1472 /* 1473 * first pass - gather what's there 1474 * update/second pass - adjust/allocate regions 1475 * config - allocate regions 1476 */ 1477 if (config_op == CONFIG_INFO) { /* first pass */ 1478 /* take out of the resource map of the bus */ 1479 if (*io_res && base != 0) 1480 (void) memlist_remove(io_res, 1481 (uint64_t)base, (uint64_t)len); 1482 else if (*io_res) 1483 reprogram = 1; 1484 } else if (*io_res && base == 0) { 1485 base = (uint_t)memlist_find(io_res, 1486 (uint64_t)len, (uint64_t)0x4); 1487 if (base != 0) { 1488 /* XXX need to worry about 64-bit? */ 1489 pci_putl(bus, dev, func, offset, 1490 base | type); 1491 base = pci_getl(bus, dev, func, offset); 1492 base &= PCI_BASE_IO_ADDR_M; 1493 } 1494 if (base == 0) { 1495 cmn_err(CE_WARN, "failed to program" 1496 " IO space [%d/%d/%d] BAR@0x%x" 1497 " length 0x%x", 1498 bus, dev, func, offset, len); 1499 } else 1500 enable |= PCI_COMM_IO; 1501 } 1502 assigned[nasgn].pci_phys_low = base; 1503 nreg++, nasgn++; 1504 1505 } else { 1506 /* memory space */ 1507 if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 1508 bar_sz = PCI_BAR_SZ_64; 1509 base_hi = pci_getl(bus, dev, func, offset + 4); 1510 phys_hi = PCI_ADDR_MEM64; 1511 } else { 1512 bar_sz = PCI_BAR_SZ_32; 1513 base_hi = 0; 1514 phys_hi = PCI_ADDR_MEM32; 1515 } 1516 1517 /* skip base regs with size of 0 */ 1518 value &= PCI_BASE_M_ADDR_M; 1519 1520 if (value == 0) { 1521 continue; 1522 } 1523 len = ((value ^ (value-1)) + 1) >> 1; 1524 regs[nreg].pci_size_low = 1525 assigned[nasgn].pci_size_low = len; 1526 1527 phys_hi |= (devloc | offset); 1528 if (base & PCI_BASE_PREF_M) { 1529 mres = pmem_res; 1530 phys_hi |= PCI_PREFETCH_B; 1531 } else { 1532 mres = mem_res; 1533 } 1534 regs[nreg].pci_phys_hi = 1535 assigned[nasgn].pci_phys_hi = phys_hi; 1536 assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 1537 assigned[nasgn].pci_phys_mid = base_hi; 1538 type = base & ~PCI_BASE_M_ADDR_M; 1539 base &= PCI_BASE_M_ADDR_M; 1540 1541 if (config_op == CONFIG_INFO) { 1542 /* take out of the resource map of the bus */ 1543 if (*mres && base != 0) { 1544 (void) memlist_remove(mres, 1545 (uint64_t)base, (uint64_t)len); 1546 } else if (*mres) 1547 reprogram = 1; 1548 } else if (*mres && base == 0) { 1549 base = (uint_t)memlist_find(mres, 1550 (uint64_t)len, (uint64_t)0x1000); 1551 if (base != NULL) { 1552 pci_putl(bus, dev, func, offset, 1553 base | type); 1554 base = pci_getl(bus, dev, func, offset); 1555 base &= PCI_BASE_M_ADDR_M; 1556 } 1557 1558 if (base == 0) { 1559 cmn_err(CE_WARN, "failed to program " 1560 "mem space [%d/%d/%d] BAR@0x%x" 1561 " length 0x%x", 1562 bus, dev, func, offset, len); 1563 } else 1564 enable |= PCI_COMM_MAE; 1565 } 1566 assigned[nasgn].pci_phys_low = base; 1567 nreg++, nasgn++; 1568 } 1569 } 1570 switch (header) { 1571 case PCI_HEADER_ZERO: 1572 offset = PCI_CONF_ROM; 1573 break; 1574 case PCI_HEADER_PPB: 1575 offset = PCI_BCNF_ROM; 1576 break; 1577 default: /* including PCI_HEADER_CARDBUS */ 1578 goto done; 1579 } 1580 1581 /* 1582 * Add the expansion rom memory space 1583 * Determine the size of the ROM base reg; don't write reserved bits 1584 * ROM isn't in the PCI memory space. 1585 */ 1586 base = pci_getl(bus, dev, func, offset); 1587 pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 1588 value = pci_getl(bus, dev, func, offset); 1589 pci_putl(bus, dev, func, offset, base); 1590 if (value & PCI_BASE_ROM_ENABLE) 1591 value &= PCI_BASE_ROM_ADDR_M; 1592 else 1593 value = 0; 1594 1595 if (value != 0) { 1596 regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 1597 assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 1598 PCI_ADDR_MEM32 | devloc) + offset; 1599 base &= PCI_BASE_ROM_ADDR_M; 1600 assigned[nasgn].pci_phys_low = base; 1601 len = ((value ^ (value-1)) + 1) >> 1; 1602 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 1603 nreg++, nasgn++; 1604 /* take it out of the memory resource */ 1605 if (*mem_res && base != 0) 1606 (void) memlist_remove(mem_res, 1607 (uint64_t)base, (uint64_t)len); 1608 } 1609 1610 /* 1611 * The following are ISA resources. There are not part 1612 * of the PCI local bus resources. So don't attempt to 1613 * do resource accounting against PCI. 1614 */ 1615 1616 /* add the three hard-decode, aliased address spaces for VGA */ 1617 if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 1618 (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 1619 1620 /* VGA hard decode 0x3b0-0x3bb */ 1621 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1622 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1623 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 1624 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 1625 nreg++, nasgn++; 1626 1627 /* VGA hard decode 0x3c0-0x3df */ 1628 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1629 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1630 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 1631 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 1632 nreg++, nasgn++; 1633 1634 /* Video memory */ 1635 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1636 (PCI_RELOCAT_B | PCI_ADDR_MEM32 | devloc); 1637 regs[nreg].pci_phys_low = 1638 assigned[nasgn].pci_phys_low = 0xa0000; 1639 regs[nreg].pci_size_low = 1640 assigned[nasgn].pci_size_low = 0x20000; 1641 nreg++, nasgn++; 1642 } 1643 1644 /* add the hard-decode, aliased address spaces for 8514 */ 1645 if ((baseclass == PCI_CLASS_DISPLAY) && 1646 (subclass == PCI_DISPLAY_VGA) && 1647 (progclass & PCI_DISPLAY_IF_8514)) { 1648 1649 /* hard decode 0x2e8 */ 1650 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1651 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1652 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 1653 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 1654 nreg++, nasgn++; 1655 1656 /* hard decode 0x2ea-0x2ef */ 1657 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1658 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1659 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 1660 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 1661 nreg++, nasgn++; 1662 } 1663 1664 done: 1665 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 1666 (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 1667 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1668 "assigned-addresses", 1669 (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 1670 if (config_op == CONFIG_NEW && enable) { 1671 cmn_err(CE_NOTE, 1672 "!enable PCI device [%d/%d/%d]", bus, dev, func); 1673 cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 1674 cmd_reg |= (enable | PCI_COMM_ME); 1675 pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 1676 } 1677 return (reprogram); 1678 } 1679 1680 static void 1681 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 1682 int pciex) 1683 { 1684 char *dev_type; 1685 int i; 1686 uint_t val, io_range[2], mem_range[2], pmem_range[2]; 1687 uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 1688 uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 1689 ASSERT(secbus <= subbus); 1690 1691 /* 1692 * Some BIOSes lie about max pci busses, we allow for 1693 * such mistakes here 1694 */ 1695 if (subbus > pci_bios_nbus) { 1696 pci_bios_nbus = subbus; 1697 alloc_res_array(); 1698 } 1699 1700 ASSERT(pci_bus_res[secbus].dip == NULL); 1701 pci_bus_res[secbus].dip = dip; 1702 pci_bus_res[secbus].par_bus = bus; 1703 1704 dev_type = pciex ? "pciex" : "pci"; 1705 1706 /* setup bus number hierarchy */ 1707 pci_bus_res[secbus].sub_bus = subbus; 1708 /* 1709 * Keep track of the largest subordinate bus number (this is essential 1710 * for peer busses because there is no other way of determining its 1711 * subordinate bus number). 1712 */ 1713 if (subbus > pci_bus_res[bus].sub_bus) 1714 pci_bus_res[bus].sub_bus = subbus; 1715 /* 1716 * Loop through subordinate busses, initializing their parent bus 1717 * field to this bridge's parent. The subordinate busses' parent 1718 * fields may very well be further refined later, as child bridges 1719 * are enumerated. (The value is to note that the subordinate busses 1720 * are not peer busses by changing their par_bus fields to anything 1721 * other than -1.) 1722 */ 1723 for (i = secbus + 1; i <= subbus; i++) 1724 pci_bus_res[i].par_bus = bus; 1725 1726 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1727 "device_type", dev_type); 1728 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1729 "#address-cells", 3); 1730 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1731 "#size-cells", 2); 1732 1733 /* 1734 * According to PPB spec, the base register should be programmed 1735 * with a value bigger than the limit register when there are 1736 * no resources available. This applies to io, memory, and 1737 * prefetchable memory. 1738 */ 1739 1740 /* 1741 * io range 1742 * We determine i/o windows that are left unconfigured by bios 1743 * through its i/o enable bit as Microsoft recommends OEMs to do. 1744 * If it is unset, we disable i/o and mark it for reconfiguration in 1745 * later passes by setting the base > limit 1746 */ 1747 val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM); 1748 if (val & PCI_COMM_IO) { 1749 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 1750 io_range[0] = ((val & 0xf0) << 8); 1751 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 1752 io_range[1] = ((val & 0xf0) << 8) | 0xFFF; 1753 } else { 1754 io_range[0] = 0x9fff; 1755 io_range[1] = 0x1000; 1756 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 1757 (uint8_t)((io_range[0] >> 8) & 0xf0)); 1758 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 1759 (uint8_t)((io_range[1] >> 8) & 0xf0)); 1760 pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 1761 pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 1762 } 1763 1764 if (io_range[0] != 0 && io_range[0] < io_range[1]) { 1765 memlist_insert(&pci_bus_res[secbus].io_ports, 1766 (uint64_t)io_range[0], 1767 (uint64_t)(io_range[1] - io_range[0] + 1)); 1768 if (pci_bus_res[bus].io_ports != NULL) { 1769 (void) memlist_remove(&pci_bus_res[bus].io_ports, 1770 (uint64_t)io_range[0], 1771 (uint64_t)(io_range[1] - io_range[0] + 1)); 1772 } 1773 dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x", 1774 secbus, io_range[0], io_range[1]); 1775 /* if 32-bit supported, make sure upper bits are not set */ 1776 if ((val & 0xf) == 1 && 1777 pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) { 1778 cmn_err(CE_NOTE, "unsupported 32-bit IO address on" 1779 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 1780 } 1781 } 1782 1783 /* mem range */ 1784 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 1785 mem_range[0] = ((val & 0xFFF0) << 16); 1786 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 1787 mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 1788 if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 1789 memlist_insert(&pci_bus_res[secbus].mem_space, 1790 (uint64_t)mem_range[0], 1791 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 1792 /* remove from parent resouce list */ 1793 if (pci_bus_res[bus].mem_space != NULL) { 1794 (void) memlist_remove(&pci_bus_res[bus].mem_space, 1795 (uint64_t)mem_range[0], 1796 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 1797 } 1798 dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x", 1799 secbus, mem_range[0], mem_range[1]); 1800 } 1801 1802 /* prefetchable memory range */ 1803 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 1804 pmem_range[0] = ((val & 0xFFF0) << 16); 1805 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 1806 pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 1807 if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 1808 memlist_insert(&pci_bus_res[secbus].pmem_space, 1809 (uint64_t)pmem_range[0], 1810 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 1811 if (pci_bus_res[bus].pmem_space != NULL) { 1812 (void) memlist_remove(&pci_bus_res[bus].pmem_space, 1813 (uint64_t)pmem_range[0], 1814 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 1815 } 1816 dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x", 1817 secbus, pmem_range[0], pmem_range[1]); 1818 /* if 64-bit supported, make sure upper bits are not set */ 1819 if ((val & 0xf) == 1 && 1820 pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) { 1821 cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on" 1822 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 1823 } 1824 } 1825 1826 add_bus_range_prop(secbus); 1827 add_ppb_ranges_prop(secbus); 1828 } 1829 1830 extern const struct pci_class_strings_s class_pci[]; 1831 extern int class_pci_items; 1832 1833 static void 1834 add_model_prop(dev_info_t *dip, uint_t classcode) 1835 { 1836 const char *desc; 1837 int i; 1838 uchar_t baseclass = classcode >> 16; 1839 uchar_t subclass = (classcode >> 8) & 0xff; 1840 uchar_t progclass = classcode & 0xff; 1841 1842 if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 1843 desc = "IDE controller"; 1844 } else { 1845 for (desc = 0, i = 0; i < class_pci_items; i++) { 1846 if ((baseclass == class_pci[i].base_class) && 1847 (subclass == class_pci[i].sub_class) && 1848 (progclass == class_pci[i].prog_class)) { 1849 desc = class_pci[i].actual_desc; 1850 break; 1851 } 1852 } 1853 if (i == class_pci_items) 1854 desc = "Unknown class of pci/pnpbios device"; 1855 } 1856 1857 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 1858 (char *)desc); 1859 } 1860 1861 static void 1862 add_bus_range_prop(int bus) 1863 { 1864 int bus_range[2]; 1865 1866 if (pci_bus_res[bus].dip == NULL) 1867 return; 1868 bus_range[0] = bus; 1869 bus_range[1] = pci_bus_res[bus].sub_bus; 1870 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 1871 "bus-range", (int *)bus_range, 2); 1872 } 1873 1874 /* 1875 * Add slot-names property for any named pci hot-plug slots 1876 */ 1877 static void 1878 add_bus_slot_names_prop(int bus) 1879 { 1880 char slotprop[256]; 1881 int len; 1882 1883 len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); 1884 if (len > 0) { 1885 /* 1886 * Only create a peer bus node if this bus may be a peer bus. 1887 * It may be a peer bus if the dip is NULL and if par_bus is 1888 * -1 (par_bus is -1 if this bus was not found to be 1889 * subordinate to any PCI-PCI bridge). 1890 * If it's not a peer bus, then the ACPI BBN-handling code 1891 * will remove it later. 1892 */ 1893 if (pci_bus_res[bus].par_bus == (uchar_t)-1 && 1894 pci_bus_res[bus].dip == NULL) { 1895 1896 create_root_bus_dip(bus); 1897 } 1898 if (pci_bus_res[bus].dip != NULL) { 1899 ASSERT((len % sizeof (int)) == 0); 1900 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 1901 pci_bus_res[bus].dip, "slot-names", 1902 (int *)slotprop, len / sizeof (int)); 1903 } else { 1904 cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI " 1905 "IRQ routing table; Not adding slot-names " 1906 "property for incorrect bus %d", bus); 1907 } 1908 } 1909 } 1910 1911 static int 1912 memlist_to_range(ppb_ranges_t *rp, struct memlist *entry, int type) 1913 { 1914 if (entry == NULL) 1915 return (0); 1916 1917 /* assume 32-bit addresses */ 1918 rp->child_high = rp->parent_high = type; 1919 rp->child_mid = rp->parent_mid = 0; 1920 rp->child_low = rp->parent_low = (uint32_t)entry->address; 1921 rp->size_high = 0; 1922 rp->size_low = (uint32_t)entry->size; 1923 return (1); 1924 } 1925 1926 static void 1927 add_ppb_ranges_prop(int bus) 1928 { 1929 int i = 0; 1930 ppb_ranges_t *rp; 1931 1932 rp = kmem_alloc(3 * sizeof (*rp), KM_SLEEP); 1933 1934 i = memlist_to_range(&rp[0], pci_bus_res[bus].io_ports, 1935 PCI_ADDR_IO | PCI_REG_REL_M); 1936 i += memlist_to_range(&rp[i], pci_bus_res[bus].mem_space, 1937 PCI_ADDR_MEM32 | PCI_REG_REL_M); 1938 i += memlist_to_range(&rp[i], pci_bus_res[bus].pmem_space, 1939 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 1940 1941 if (i != 0) 1942 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 1943 pci_bus_res[bus].dip, "ranges", (int *)rp, 1944 i * sizeof (ppb_ranges_t) / sizeof (int)); 1945 kmem_free(rp, 3 * sizeof (*rp)); 1946 } 1947 1948 static int 1949 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 1950 { 1951 int i = 0; 1952 1953 while (list) { 1954 /* assume 32-bit addresses */ 1955 sp->pci_phys_hi = type; 1956 sp->pci_phys_mid = 0; 1957 sp->pci_phys_low = (uint32_t)list->address; 1958 sp->pci_size_hi = 0; 1959 sp->pci_size_low = (uint32_t)list->size; 1960 1961 list = list->next; 1962 sp++, i++; 1963 } 1964 return (i); 1965 } 1966 1967 static void 1968 add_bus_available_prop(int bus) 1969 { 1970 int i, count; 1971 struct pci_phys_spec *sp; 1972 1973 count = memlist_count(pci_bus_res[bus].io_ports) + 1974 memlist_count(pci_bus_res[bus].mem_space) + 1975 memlist_count(pci_bus_res[bus].pmem_space); 1976 1977 if (count == 0) /* nothing available */ 1978 return; 1979 1980 sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 1981 i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_ports, 1982 PCI_ADDR_IO | PCI_REG_REL_M); 1983 i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_space, 1984 PCI_ADDR_MEM32 | PCI_REG_REL_M); 1985 i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_space, 1986 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 1987 ASSERT(i == count); 1988 1989 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 1990 "available", (int *)sp, 1991 i * sizeof (struct pci_phys_spec) / sizeof (int)); 1992 kmem_free(sp, count * sizeof (*sp)); 1993 } 1994 1995 static void 1996 alloc_res_array(void) 1997 { 1998 static int array_max = 0; 1999 int old_max; 2000 void *old_res; 2001 2002 if (array_max > pci_bios_nbus + 1) 2003 return; /* array is big enough */ 2004 2005 old_max = array_max; 2006 old_res = pci_bus_res; 2007 2008 if (array_max == 0) 2009 array_max = 16; /* start with a reasonable number */ 2010 2011 while (array_max < pci_bios_nbus + 1) 2012 array_max <<= 1; 2013 pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 2014 array_max * sizeof (struct pci_bus_resource), KM_SLEEP); 2015 2016 if (old_res) { /* copy content and free old array */ 2017 bcopy(old_res, pci_bus_res, 2018 old_max * sizeof (struct pci_bus_resource)); 2019 kmem_free(old_res, old_max * sizeof (struct pci_bus_resource)); 2020 } 2021 } 2022 2023 static void 2024 create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 2025 ushort_t deviceid) 2026 { 2027 static dev_info_t *ioapicsnode = NULL; 2028 static int numioapics = 0; 2029 dev_info_t *ioapic_node; 2030 uint64_t physaddr; 2031 uint32_t lobase, hibase = 0; 2032 2033 /* BAR 0 contains the IOAPIC's memory-mapped I/O address */ 2034 lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0); 2035 2036 /* We (and the rest of the world) only support memory-mapped IOAPICs */ 2037 if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM) 2038 return; 2039 2040 if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) 2041 hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4); 2042 2043 lobase &= PCI_BASE_M_ADDR_M; 2044 2045 physaddr = (((uint64_t)hibase) << 32) | lobase; 2046 2047 /* 2048 * Create a nexus node for all IOAPICs under the root node. 2049 */ 2050 if (ioapicsnode == NULL) { 2051 if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME, 2052 (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) { 2053 return; 2054 } 2055 (void) ndi_devi_online(ioapicsnode, 0); 2056 } 2057 2058 /* 2059 * Create a child node for this IOAPIC 2060 */ 2061 ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME, 2062 DEVI_SID_NODEID, numioapics++); 2063 if (ioapic_node == NULL) { 2064 return; 2065 } 2066 2067 /* Vendor and Device ID */ 2068 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 2069 IOAPICS_PROP_VENID, vendorid); 2070 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 2071 IOAPICS_PROP_DEVID, deviceid); 2072 2073 /* device_type */ 2074 (void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node, 2075 "device_type", IOAPICS_DEV_TYPE); 2076 2077 /* reg */ 2078 (void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node, 2079 "reg", physaddr); 2080 } 2081