1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright 2019 Joyent, Inc. 24 */ 25 26 #include <sys/types.h> 27 #include <sys/stat.h> 28 #include <sys/sysmacros.h> 29 #include <sys/sunndi.h> 30 #include <sys/pci.h> 31 #include <sys/pci_impl.h> 32 #include <sys/pcie_impl.h> 33 #include <sys/memlist.h> 34 #include <sys/bootconf.h> 35 #include <io/pci/mps_table.h> 36 #include <sys/pci_cfgacc.h> 37 #include <sys/pci_cfgspace.h> 38 #include <sys/pci_cfgspace_impl.h> 39 #include <sys/psw.h> 40 #include "../../../../common/pci/pci_strings.h" 41 #include <sys/apic.h> 42 #include <io/pciex/pcie_nvidia.h> 43 #include <sys/hotplug/pci/pciehpc_acpi.h> 44 #include <sys/acpi/acpi.h> 45 #include <sys/acpica.h> 46 #include <sys/iommulib.h> 47 #include <sys/devcache.h> 48 #include <sys/pci_cfgacc_x86.h> 49 50 #define pci_getb (*pci_getb_func) 51 #define pci_getw (*pci_getw_func) 52 #define pci_getl (*pci_getl_func) 53 #define pci_putb (*pci_putb_func) 54 #define pci_putw (*pci_putw_func) 55 #define pci_putl (*pci_putl_func) 56 #define dcmn_err if (pci_boot_debug) cmn_err 57 58 #define CONFIG_INFO 0 59 #define CONFIG_UPDATE 1 60 #define CONFIG_NEW 2 61 #define CONFIG_FIX 3 62 #define COMPAT_BUFSIZE 512 63 64 #define PPB_IO_ALIGNMENT 0x1000 /* 4K aligned */ 65 #define PPB_MEM_ALIGNMENT 0x100000 /* 1M aligned */ 66 /* round down to nearest power of two */ 67 #define P2LE(align) \ 68 { \ 69 int i = 0; \ 70 while (align >>= 1) \ 71 i ++; \ 72 align = 1 << i; \ 73 } \ 74 75 /* for is_vga and list_is_vga_only */ 76 77 enum io_mem { 78 IO, 79 MEM 80 }; 81 82 /* See AMD-8111 Datasheet Rev 3.03, Page 149: */ 83 #define LPC_IO_CONTROL_REG_1 0x40 84 #define AMD8111_ENABLENMI (uint8_t)0x80 85 #define DEVID_AMD8111_LPC 0x7468 86 87 struct pci_fixundo { 88 uint8_t bus; 89 uint8_t dev; 90 uint8_t fn; 91 void (*undofn)(uint8_t, uint8_t, uint8_t); 92 struct pci_fixundo *next; 93 }; 94 95 struct pci_devfunc { 96 struct pci_devfunc *next; 97 dev_info_t *dip; 98 uchar_t dev; 99 uchar_t func; 100 boolean_t reprogram; /* this device needs to be reprogrammed */ 101 }; 102 103 extern int apic_nvidia_io_max; 104 extern int pseudo_isa; 105 extern int pci_bios_maxbus; 106 static uchar_t max_dev_pci = 32; /* PCI standard */ 107 int pci_boot_debug = 0; 108 extern struct memlist *find_bus_res(int, int); 109 static struct pci_fixundo *undolist = NULL; 110 static int num_root_bus = 0; /* count of root buses */ 111 extern volatile int acpi_resource_discovery; 112 extern uint64_t mcfg_mem_base; 113 extern void pci_cfgacc_add_workaround(uint16_t, uchar_t, uchar_t); 114 extern dev_info_t *pcie_get_rc_dip(dev_info_t *); 115 116 /* 117 * Module prototypes 118 */ 119 static void enumerate_bus_devs(uchar_t bus, int config_op); 120 static void create_root_bus_dip(uchar_t bus); 121 static void process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t, 122 ushort_t, int); 123 static void add_compatible(dev_info_t *, ushort_t, ushort_t, 124 ushort_t, ushort_t, uchar_t, uint_t, int); 125 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 126 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, 127 ushort_t); 128 static void add_model_prop(dev_info_t *, uint_t); 129 static void add_bus_range_prop(int); 130 static void add_bus_slot_names_prop(int); 131 static void add_ranges_prop(int, int); 132 static void add_bus_available_prop(int); 133 static int get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id); 134 static void fix_ppb_res(uchar_t, boolean_t); 135 static void alloc_res_array(); 136 static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 137 ushort_t deviceid); 138 static void pciex_slot_names_prop(dev_info_t *, ushort_t); 139 static void populate_bus_res(uchar_t bus); 140 static void memlist_remove_list(struct memlist **list, 141 struct memlist *remove_list); 142 static void ck804_fix_aer_ptr(dev_info_t *, pcie_req_id_t); 143 144 static void pci_scan_bbn(void); 145 static int pci_unitaddr_cache_valid(void); 146 static int pci_bus_unitaddr(int); 147 static void pci_unitaddr_cache_create(void); 148 149 static int pci_cache_unpack_nvlist(nvf_handle_t, nvlist_t *, char *); 150 static int pci_cache_pack_nvlist(nvf_handle_t, nvlist_t **); 151 static void pci_cache_free_list(nvf_handle_t); 152 153 extern int pci_slot_names_prop(int, char *, int); 154 155 /* set non-zero to force PCI peer-bus renumbering */ 156 int pci_bus_always_renumber = 0; 157 158 /* 159 * used to register ISA resource usage which must not be made 160 * "available" from other PCI node' resource maps 161 */ 162 static struct { 163 struct memlist *io_used; 164 struct memlist *mem_used; 165 } isa_res; 166 167 /* 168 * PCI unit-address cache management 169 */ 170 static nvf_ops_t pci_unitaddr_cache_ops = { 171 "/etc/devices/pci_unitaddr_persistent", /* path to cache */ 172 pci_cache_unpack_nvlist, /* read in nvlist form */ 173 pci_cache_pack_nvlist, /* convert to nvlist form */ 174 pci_cache_free_list, /* free data list */ 175 NULL /* write complete callback */ 176 }; 177 178 typedef struct { 179 list_node_t pua_nodes; 180 int pua_index; 181 int pua_addr; 182 } pua_node_t; 183 184 nvf_handle_t puafd_handle; 185 int pua_cache_valid = 0; 186 187 188 /*ARGSUSED*/ 189 static ACPI_STATUS 190 pci_process_acpi_device(ACPI_HANDLE hdl, UINT32 level, void *ctx, void **rv) 191 { 192 ACPI_BUFFER rb; 193 ACPI_OBJECT ro; 194 ACPI_DEVICE_INFO *adi; 195 int busnum; 196 197 /* 198 * Use AcpiGetObjectInfo() to find the device _HID 199 * If not a PCI root-bus, ignore this device and continue 200 * the walk 201 */ 202 if (ACPI_FAILURE(AcpiGetObjectInfo(hdl, &adi))) 203 return (AE_OK); 204 205 if (!(adi->Valid & ACPI_VALID_HID)) { 206 AcpiOsFree(adi); 207 return (AE_OK); 208 } 209 210 if (strncmp(adi->HardwareId.String, PCI_ROOT_HID_STRING, 211 sizeof (PCI_ROOT_HID_STRING)) && 212 strncmp(adi->HardwareId.String, PCI_EXPRESS_ROOT_HID_STRING, 213 sizeof (PCI_EXPRESS_ROOT_HID_STRING))) { 214 AcpiOsFree(adi); 215 return (AE_OK); 216 } 217 218 AcpiOsFree(adi); 219 220 /* 221 * XXX: ancient Big Bear broken _BBN will result in two 222 * bus 0 _BBNs being found, so we need to handle duplicate 223 * bus 0 gracefully. However, broken _BBN does not 224 * hide a childless root-bridge so no need to work-around it 225 * here 226 */ 227 rb.Pointer = &ro; 228 rb.Length = sizeof (ro); 229 if (ACPI_SUCCESS(AcpiEvaluateObjectTyped(hdl, "_BBN", 230 NULL, &rb, ACPI_TYPE_INTEGER))) { 231 busnum = ro.Integer.Value; 232 233 /* 234 * Ignore invalid _BBN return values here (rather 235 * than panic) and emit a warning; something else 236 * may suffer failure as a result of the broken BIOS. 237 */ 238 if ((busnum < 0) || (busnum > pci_bios_maxbus)) { 239 dcmn_err(CE_NOTE, 240 "pci_process_acpi_device: invalid _BBN 0x%x\n", 241 busnum); 242 return (AE_CTRL_DEPTH); 243 } 244 245 /* PCI with valid _BBN */ 246 if (pci_bus_res[busnum].par_bus == (uchar_t)-1 && 247 pci_bus_res[busnum].dip == NULL) 248 create_root_bus_dip((uchar_t)busnum); 249 return (AE_CTRL_DEPTH); 250 } 251 252 /* PCI and no _BBN, continue walk */ 253 return (AE_OK); 254 } 255 256 /* 257 * Scan the ACPI namespace for all top-level instances of _BBN 258 * in order to discover childless root-bridges (which enumeration 259 * may not find; root-bridges are inferred by the existence of 260 * children). This scan should find all root-bridges that have 261 * been enumerated, and any childless root-bridges not enumerated. 262 * Root-bridge for bus 0 may not have a _BBN object. 263 */ 264 static void 265 pci_scan_bbn() 266 { 267 void *rv; 268 269 (void) AcpiGetDevices(NULL, pci_process_acpi_device, NULL, &rv); 270 } 271 272 static void 273 pci_unitaddr_cache_init(void) 274 { 275 276 puafd_handle = nvf_register_file(&pci_unitaddr_cache_ops); 277 ASSERT(puafd_handle); 278 279 list_create(nvf_list(puafd_handle), sizeof (pua_node_t), 280 offsetof(pua_node_t, pua_nodes)); 281 282 rw_enter(nvf_lock(puafd_handle), RW_WRITER); 283 (void) nvf_read_file(puafd_handle); 284 rw_exit(nvf_lock(puafd_handle)); 285 } 286 287 /* 288 * Format of /etc/devices/pci_unitaddr_persistent: 289 * 290 * The persistent record of unit-address assignments contains 291 * a list of name/value pairs, where name is a string representation 292 * of the "index value" of the PCI root-bus and the value is 293 * the assigned unit-address. 294 * 295 * The "index value" is simply the zero-based index of the PCI 296 * root-buses ordered by physical bus number; first PCI bus is 0, 297 * second is 1, and so on. 298 */ 299 300 /*ARGSUSED*/ 301 static int 302 pci_cache_unpack_nvlist(nvf_handle_t hdl, nvlist_t *nvl, char *name) 303 { 304 long index; 305 int32_t value; 306 nvpair_t *np; 307 pua_node_t *node; 308 309 np = NULL; 310 while ((np = nvlist_next_nvpair(nvl, np)) != NULL) { 311 /* name of nvpair is index value */ 312 if (ddi_strtol(nvpair_name(np), NULL, 10, &index) != 0) 313 continue; 314 315 if (nvpair_value_int32(np, &value) != 0) 316 continue; 317 318 node = kmem_zalloc(sizeof (pua_node_t), KM_SLEEP); 319 node->pua_index = index; 320 node->pua_addr = value; 321 list_insert_tail(nvf_list(hdl), node); 322 } 323 324 pua_cache_valid = 1; 325 return (DDI_SUCCESS); 326 } 327 328 static int 329 pci_cache_pack_nvlist(nvf_handle_t hdl, nvlist_t **ret_nvl) 330 { 331 int rval; 332 nvlist_t *nvl, *sub_nvl; 333 list_t *listp; 334 pua_node_t *pua; 335 char buf[13]; 336 337 ASSERT(RW_WRITE_HELD(nvf_lock(hdl))); 338 339 rval = nvlist_alloc(&nvl, NV_UNIQUE_NAME, KM_SLEEP); 340 if (rval != DDI_SUCCESS) { 341 nvf_error("%s: nvlist alloc error %d\n", 342 nvf_cache_name(hdl), rval); 343 return (DDI_FAILURE); 344 } 345 346 sub_nvl = NULL; 347 rval = nvlist_alloc(&sub_nvl, NV_UNIQUE_NAME, KM_SLEEP); 348 if (rval != DDI_SUCCESS) 349 goto error; 350 351 listp = nvf_list(hdl); 352 for (pua = list_head(listp); pua != NULL; 353 pua = list_next(listp, pua)) { 354 (void) snprintf(buf, sizeof (buf), "%d", pua->pua_index); 355 rval = nvlist_add_int32(sub_nvl, buf, pua->pua_addr); 356 if (rval != DDI_SUCCESS) 357 goto error; 358 } 359 360 rval = nvlist_add_nvlist(nvl, "table", sub_nvl); 361 if (rval != DDI_SUCCESS) 362 goto error; 363 nvlist_free(sub_nvl); 364 365 *ret_nvl = nvl; 366 return (DDI_SUCCESS); 367 368 error: 369 nvlist_free(sub_nvl); 370 ASSERT(nvl); 371 nvlist_free(nvl); 372 *ret_nvl = NULL; 373 return (DDI_FAILURE); 374 } 375 376 static void 377 pci_cache_free_list(nvf_handle_t hdl) 378 { 379 list_t *listp; 380 pua_node_t *pua; 381 382 ASSERT(RW_WRITE_HELD(nvf_lock(hdl))); 383 384 listp = nvf_list(hdl); 385 for (pua = list_head(listp); pua != NULL; 386 pua = list_next(listp, pua)) { 387 list_remove(listp, pua); 388 kmem_free(pua, sizeof (pua_node_t)); 389 } 390 } 391 392 393 static int 394 pci_unitaddr_cache_valid(void) 395 { 396 397 /* read only, no need for rw lock */ 398 return (pua_cache_valid); 399 } 400 401 402 static int 403 pci_bus_unitaddr(int index) 404 { 405 pua_node_t *pua; 406 list_t *listp; 407 int addr; 408 409 rw_enter(nvf_lock(puafd_handle), RW_READER); 410 411 addr = -1; /* default return if no match */ 412 listp = nvf_list(puafd_handle); 413 for (pua = list_head(listp); pua != NULL; 414 pua = list_next(listp, pua)) { 415 if (pua->pua_index == index) { 416 addr = pua->pua_addr; 417 break; 418 } 419 } 420 421 rw_exit(nvf_lock(puafd_handle)); 422 return (addr); 423 } 424 425 static void 426 pci_unitaddr_cache_create(void) 427 { 428 int i, index; 429 pua_node_t *node; 430 list_t *listp; 431 432 rw_enter(nvf_lock(puafd_handle), RW_WRITER); 433 434 index = 0; 435 listp = nvf_list(puafd_handle); 436 for (i = 0; i <= pci_bios_maxbus; i++) { 437 /* skip non-root (peer) PCI busses */ 438 if ((pci_bus_res[i].par_bus != (uchar_t)-1) || 439 (pci_bus_res[i].dip == NULL)) 440 continue; 441 node = kmem_zalloc(sizeof (pua_node_t), KM_SLEEP); 442 node->pua_index = index++; 443 node->pua_addr = pci_bus_res[i].root_addr; 444 list_insert_tail(listp, node); 445 } 446 447 (void) nvf_mark_dirty(puafd_handle); 448 rw_exit(nvf_lock(puafd_handle)); 449 nvf_wake_daemon(); 450 } 451 452 453 /* 454 * Enumerate all PCI devices 455 */ 456 void 457 pci_setup_tree(void) 458 { 459 uint_t i, root_bus_addr = 0; 460 461 alloc_res_array(); 462 for (i = 0; i <= pci_bios_maxbus; i++) { 463 pci_bus_res[i].par_bus = (uchar_t)-1; 464 pci_bus_res[i].root_addr = (uchar_t)-1; 465 pci_bus_res[i].sub_bus = i; 466 } 467 468 pci_bus_res[0].root_addr = root_bus_addr++; 469 create_root_bus_dip(0); 470 enumerate_bus_devs(0, CONFIG_INFO); 471 472 /* 473 * Now enumerate peer busses 474 * 475 * We loop till pci_bios_maxbus. On most systems, there is 476 * one more bus at the high end, which implements the ISA 477 * compatibility bus. We don't care about that. 478 * 479 * Note: In the old (bootconf) enumeration, the peer bus 480 * address did not use the bus number, and there were 481 * too many peer busses created. The root_bus_addr is 482 * used to maintain the old peer bus address assignment. 483 * However, we stop enumerating phantom peers with no 484 * device below. 485 */ 486 for (i = 1; i <= pci_bios_maxbus; i++) { 487 if (pci_bus_res[i].dip == NULL) { 488 pci_bus_res[i].root_addr = root_bus_addr++; 489 } 490 enumerate_bus_devs(i, CONFIG_INFO); 491 492 /* add slot-names property for named pci hot-plug slots */ 493 add_bus_slot_names_prop(i); 494 } 495 } 496 497 /* 498 * >0 = present, 0 = not present, <0 = error 499 */ 500 static int 501 pci_bbn_present(int bus) 502 { 503 ACPI_HANDLE hdl; 504 int rv; 505 506 /* no dip means no _BBN */ 507 if (pci_bus_res[bus].dip == NULL) 508 return (0); 509 510 rv = -1; /* default return value in case of error below */ 511 if (ACPI_SUCCESS(acpica_get_handle(pci_bus_res[bus].dip, &hdl))) { 512 switch (AcpiEvaluateObject(hdl, "_BBN", NULL, NULL)) { 513 case AE_OK: 514 rv = 1; 515 break; 516 case AE_NOT_FOUND: 517 rv = 0; 518 break; 519 default: 520 break; 521 } 522 } 523 524 return (rv); 525 } 526 527 /* 528 * Return non-zero if any PCI bus in the system has an associated 529 * _BBN object, 0 otherwise. 530 */ 531 static int 532 pci_roots_have_bbn(void) 533 { 534 int i; 535 536 /* 537 * Scan the PCI busses and look for at least 1 _BBN 538 */ 539 for (i = 0; i <= pci_bios_maxbus; i++) { 540 /* skip non-root (peer) PCI busses */ 541 if (pci_bus_res[i].par_bus != (uchar_t)-1) 542 continue; 543 544 if (pci_bbn_present(i) > 0) 545 return (1); 546 } 547 return (0); 548 549 } 550 551 /* 552 * return non-zero if the machine is one on which we renumber 553 * the internal pci unit-addresses 554 */ 555 static int 556 pci_bus_renumber() 557 { 558 ACPI_TABLE_HEADER *fadt; 559 560 if (pci_bus_always_renumber) 561 return (1); 562 563 /* get the FADT */ 564 if (AcpiGetTable(ACPI_SIG_FADT, 1, (ACPI_TABLE_HEADER **)&fadt) != 565 AE_OK) 566 return (0); 567 568 /* compare OEM Table ID to "SUNm31" */ 569 if (strncmp("SUNm31", fadt->OemId, 6)) 570 return (0); 571 else 572 return (1); 573 } 574 575 /* 576 * Initial enumeration of the physical PCI bus hierarchy can 577 * leave 'gaps' in the order of peer PCI bus unit-addresses. 578 * Systems with more than one peer PCI bus *must* have an ACPI 579 * _BBN object associated with each peer bus; use the presence 580 * of this object to remove gaps in the numbering of the peer 581 * PCI bus unit-addresses - only peer busses with an associated 582 * _BBN are counted. 583 */ 584 static void 585 pci_renumber_root_busses(void) 586 { 587 int pci_regs[] = {0, 0, 0}; 588 int i, root_addr = 0; 589 590 /* 591 * Currently, we only enable the re-numbering on specific 592 * Sun machines; this is a work-around for the more complicated 593 * issue of upgrade changing physical device paths 594 */ 595 if (!pci_bus_renumber()) 596 return; 597 598 /* 599 * If we find no _BBN objects at all, we either don't need 600 * to do anything or can't do anything anyway 601 */ 602 if (!pci_roots_have_bbn()) 603 return; 604 605 for (i = 0; i <= pci_bios_maxbus; i++) { 606 /* skip non-root (peer) PCI busses */ 607 if (pci_bus_res[i].par_bus != (uchar_t)-1) 608 continue; 609 610 if (pci_bbn_present(i) < 1) { 611 pci_bus_res[i].root_addr = (uchar_t)-1; 612 continue; 613 } 614 615 ASSERT(pci_bus_res[i].dip != NULL); 616 if (pci_bus_res[i].root_addr != root_addr) { 617 /* update reg property for node */ 618 pci_bus_res[i].root_addr = root_addr; 619 pci_regs[0] = pci_bus_res[i].root_addr; 620 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 621 pci_bus_res[i].dip, "reg", (int *)pci_regs, 3); 622 } 623 root_addr++; 624 } 625 } 626 627 void 628 pci_register_isa_resources(int type, uint32_t base, uint32_t size) 629 { 630 (void) memlist_insert( 631 (type == 1) ? &isa_res.io_used : &isa_res.mem_used, 632 base, size); 633 } 634 635 /* 636 * Remove the resources which are already used by devices under a subtractive 637 * bridge from the bus's resources lists, because they're not available, and 638 * shouldn't be allocated to other buses. This is necessary because tracking 639 * resources for subtractive bridges is not complete. (Subtractive bridges only 640 * track some of their claimed resources, not "the rest of the address space" as 641 * they should, so that allocation to peer non-subtractive PPBs is easier. We 642 * need a fully-capable global resource allocator). 643 */ 644 static void 645 remove_subtractive_res() 646 { 647 int i, j; 648 struct memlist *list; 649 650 for (i = 0; i <= pci_bios_maxbus; i++) { 651 if (pci_bus_res[i].subtractive) { 652 /* remove used io ports */ 653 list = pci_bus_res[i].io_used; 654 while (list) { 655 for (j = 0; j <= pci_bios_maxbus; j++) 656 (void) memlist_remove( 657 &pci_bus_res[j].io_avail, 658 list->ml_address, list->ml_size); 659 list = list->ml_next; 660 } 661 /* remove used mem resource */ 662 list = pci_bus_res[i].mem_used; 663 while (list) { 664 for (j = 0; j <= pci_bios_maxbus; j++) { 665 (void) memlist_remove( 666 &pci_bus_res[j].mem_avail, 667 list->ml_address, list->ml_size); 668 (void) memlist_remove( 669 &pci_bus_res[j].pmem_avail, 670 list->ml_address, list->ml_size); 671 } 672 list = list->ml_next; 673 } 674 /* remove used prefetchable mem resource */ 675 list = pci_bus_res[i].pmem_used; 676 while (list) { 677 for (j = 0; j <= pci_bios_maxbus; j++) { 678 (void) memlist_remove( 679 &pci_bus_res[j].pmem_avail, 680 list->ml_address, list->ml_size); 681 (void) memlist_remove( 682 &pci_bus_res[j].mem_avail, 683 list->ml_address, list->ml_size); 684 } 685 list = list->ml_next; 686 } 687 } 688 } 689 } 690 691 /* 692 * Set up (or complete the setup of) the bus_avail resource list 693 */ 694 static void 695 setup_bus_res(int bus) 696 { 697 uchar_t par_bus; 698 699 if (pci_bus_res[bus].dip == NULL) /* unused bus */ 700 return; 701 702 /* 703 * Set up bus_avail if not already filled in by populate_bus_res() 704 */ 705 if (pci_bus_res[bus].bus_avail == NULL) { 706 ASSERT(pci_bus_res[bus].sub_bus >= bus); 707 memlist_insert(&pci_bus_res[bus].bus_avail, bus, 708 pci_bus_res[bus].sub_bus - bus + 1); 709 } 710 711 ASSERT(pci_bus_res[bus].bus_avail != NULL); 712 713 /* 714 * Remove resources from parent bus node if this is not a 715 * root bus. 716 */ 717 par_bus = pci_bus_res[bus].par_bus; 718 if (par_bus != (uchar_t)-1) { 719 ASSERT(pci_bus_res[par_bus].bus_avail != NULL); 720 memlist_remove_list(&pci_bus_res[par_bus].bus_avail, 721 pci_bus_res[bus].bus_avail); 722 } 723 724 /* remove self from bus_avail */; 725 (void) memlist_remove(&pci_bus_res[bus].bus_avail, bus, 1); 726 } 727 728 static uint64_t 729 get_parbus_io_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 730 { 731 uint64_t addr = 0; 732 uchar_t res_bus; 733 734 /* 735 * Skip root(peer) buses in multiple-root-bus systems when 736 * ACPI resource discovery was not successfully done. 737 */ 738 if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 739 (num_root_bus > 1) && (acpi_resource_discovery <= 0)) 740 return (0); 741 742 res_bus = parbus; 743 while (pci_bus_res[res_bus].subtractive) { 744 if (pci_bus_res[res_bus].io_avail) 745 break; 746 res_bus = pci_bus_res[res_bus].par_bus; 747 if (res_bus == (uchar_t)-1) 748 break; /* root bus already */ 749 } 750 751 if (pci_bus_res[res_bus].io_avail) { 752 addr = memlist_find(&pci_bus_res[res_bus].io_avail, 753 size, align); 754 if (addr) { 755 memlist_insert(&pci_bus_res[res_bus].io_used, 756 addr, size); 757 758 /* free the old resource */ 759 memlist_free_all(&pci_bus_res[bus].io_avail); 760 memlist_free_all(&pci_bus_res[bus].io_used); 761 762 /* add the new resource */ 763 memlist_insert(&pci_bus_res[bus].io_avail, addr, size); 764 } 765 } 766 767 return (addr); 768 } 769 770 static uint64_t 771 get_parbus_mem_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 772 { 773 uint64_t addr = 0; 774 uchar_t res_bus; 775 776 /* 777 * Skip root(peer) buses in multiple-root-bus systems when 778 * ACPI resource discovery was not successfully done. 779 */ 780 if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 781 (num_root_bus > 1) && (acpi_resource_discovery <= 0)) 782 return (0); 783 784 res_bus = parbus; 785 while (pci_bus_res[res_bus].subtractive) { 786 if (pci_bus_res[res_bus].mem_avail) 787 break; 788 res_bus = pci_bus_res[res_bus].par_bus; 789 if (res_bus == (uchar_t)-1) 790 break; /* root bus already */ 791 } 792 793 if (pci_bus_res[res_bus].mem_avail) { 794 addr = memlist_find(&pci_bus_res[res_bus].mem_avail, 795 size, align); 796 if (addr) { 797 memlist_insert(&pci_bus_res[res_bus].mem_used, 798 addr, size); 799 (void) memlist_remove(&pci_bus_res[res_bus].pmem_avail, 800 addr, size); 801 802 /* free the old resource */ 803 memlist_free_all(&pci_bus_res[bus].mem_avail); 804 memlist_free_all(&pci_bus_res[bus].mem_used); 805 806 /* add the new resource */ 807 memlist_insert(&pci_bus_res[bus].mem_avail, addr, size); 808 } 809 } 810 811 return (addr); 812 } 813 814 /* 815 * given a cap_id, return its cap_id location in config space 816 */ 817 static int 818 get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id) 819 { 820 uint8_t curcap, cap_id_loc; 821 uint16_t status; 822 int location = -1; 823 824 /* 825 * Need to check the Status register for ECP support first. 826 * Also please note that for type 1 devices, the 827 * offset could change. Should support type 1 next. 828 */ 829 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 830 if (!(status & PCI_STAT_CAP)) { 831 return (-1); 832 } 833 cap_id_loc = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 834 835 /* Walk the list of capabilities */ 836 while (cap_id_loc && cap_id_loc != (uint8_t)-1) { 837 curcap = pci_getb(bus, dev, func, cap_id_loc); 838 839 if (curcap == cap_id) { 840 location = cap_id_loc; 841 break; 842 } 843 cap_id_loc = pci_getb(bus, dev, func, cap_id_loc + 1); 844 } 845 return (location); 846 } 847 848 /* 849 * Does this resource element live in the legacy VGA range? 850 */ 851 852 int 853 is_vga(struct memlist *elem, enum io_mem io) 854 { 855 856 if (io == IO) { 857 if ((elem->ml_address == 0x3b0 && elem->ml_size == 0xc) || 858 (elem->ml_address == 0x3c0 && elem->ml_size == 0x20)) 859 return (1); 860 } else { 861 if (elem->ml_address == 0xa0000 && elem->ml_size == 0x20000) 862 return (1); 863 } 864 return (0); 865 } 866 867 /* 868 * Does this entire resource list consist only of legacy VGA resources? 869 */ 870 871 int 872 list_is_vga_only(struct memlist *l, enum io_mem io) 873 { 874 do { 875 if (!is_vga(l, io)) 876 return (0); 877 } while ((l = l->ml_next) != NULL); 878 return (1); 879 } 880 881 /* 882 * Assign valid resources to unconfigured pci(e) bridges. We are trying 883 * to reprogram the bridge when its 884 * i) SECBUS == SUBBUS || 885 * ii) IOBASE > IOLIM || 886 * iii) MEMBASE > MEMLIM 887 * This must be done after one full pass through the PCI tree to collect 888 * all BIOS-configured resources, so that we know what resources are 889 * free and available to assign to the unconfigured PPBs. 890 */ 891 static void 892 fix_ppb_res(uchar_t secbus, boolean_t prog_sub) 893 { 894 uchar_t bus, dev, func; 895 uchar_t parbus, subbus; 896 uint_t io_base, io_limit, mem_base; 897 uint_t io_size, io_align; 898 uint64_t mem_size, mem_align, mem_limit; 899 uint64_t addr = 0; 900 int *regp = NULL; 901 uint_t reglen; 902 int rv, cap_ptr, physhi; 903 dev_info_t *dip; 904 uint16_t cmd_reg; 905 struct memlist *list, *scratch_list; 906 907 /* skip root (peer) PCI busses */ 908 if (pci_bus_res[secbus].par_bus == (uchar_t)-1) 909 return; 910 911 /* skip subtractive PPB when prog_sub is not TRUE */ 912 if (pci_bus_res[secbus].subtractive && !prog_sub) 913 return; 914 915 /* some entries may be empty due to discontiguous bus numbering */ 916 dip = pci_bus_res[secbus].dip; 917 if (dip == NULL) 918 return; 919 920 rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 921 "reg", ®p, ®len); 922 if (rv != DDI_PROP_SUCCESS || reglen == 0) 923 return; 924 physhi = regp[0]; 925 ddi_prop_free(regp); 926 927 func = (uchar_t)PCI_REG_FUNC_G(physhi); 928 dev = (uchar_t)PCI_REG_DEV_G(physhi); 929 bus = (uchar_t)PCI_REG_BUS_G(physhi); 930 931 /* 932 * If pcie bridge, check to see if link is enabled 933 */ 934 cap_ptr = get_pci_cap(bus, dev, func, PCI_CAP_ID_PCI_E); 935 if (cap_ptr != -1) { 936 cmd_reg = pci_getw(bus, dev, func, 937 (uint16_t)cap_ptr + PCIE_LINKCTL); 938 if (cmd_reg & PCIE_LINKCTL_LINK_DISABLE) { 939 dcmn_err(CE_NOTE, 940 "!fix_ppb_res: ppb[%x/%x/%x] link is disabled.\n", 941 bus, dev, func); 942 return; 943 } 944 } 945 946 subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 947 parbus = pci_bus_res[secbus].par_bus; 948 ASSERT(parbus == bus); 949 cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 950 951 /* 952 * If we have a Cardbus bridge, but no bus space 953 */ 954 if (pci_bus_res[secbus].num_cbb != 0 && 955 pci_bus_res[secbus].bus_avail == NULL) { 956 uchar_t range; 957 958 /* normally there are 2 buses under a cardbus bridge */ 959 range = pci_bus_res[secbus].num_cbb * 2; 960 961 /* 962 * Try to find and allocate a bus-range starting at subbus+1 963 * from the parent of the PPB. 964 */ 965 for (; range != 0; range--) { 966 if (memlist_find_with_startaddr( 967 &pci_bus_res[parbus].bus_avail, 968 subbus + 1, range, 1) != 0) 969 break; /* find bus range resource at parent */ 970 } 971 if (range != 0) { 972 memlist_insert(&pci_bus_res[secbus].bus_avail, 973 subbus + 1, range); 974 subbus = subbus + range; 975 pci_bus_res[secbus].sub_bus = subbus; 976 pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus); 977 add_bus_range_prop(secbus); 978 979 cmn_err(CE_NOTE, "!reprogram bus-range on ppb" 980 "[%x/%x/%x]: %x ~ %x\n", bus, dev, func, 981 secbus, subbus); 982 } 983 } 984 985 /* 986 * Calculate required IO size and alignment 987 * If bus io_size is zero, we are going to assign 512 bytes per bus, 988 * otherwise, we'll choose the maximum value of such calculation and 989 * bus io_size. The size needs to be 4K aligned. 990 * 991 * We calculate alignment as the largest power of two less than the 992 * the sum of all children's IO size requirements, because this will 993 * align to the size of the largest child request within that size 994 * (which is always a power of two). 995 */ 996 io_size = (subbus - secbus + 1) * 0x200; 997 if (io_size < pci_bus_res[secbus].io_size) 998 io_size = pci_bus_res[secbus].io_size; 999 io_size = P2ROUNDUP(io_size, PPB_IO_ALIGNMENT); 1000 io_align = io_size; 1001 P2LE(io_align); 1002 1003 /* 1004 * Calculate required MEM size and alignment 1005 * If bus mem_size is zero, we are going to assign 1M bytes per bus, 1006 * otherwise, we'll choose the maximum value of such calculation and 1007 * bus mem_size. The size needs to be 1M aligned. 1008 * 1009 * For the alignment, refer to the I/O comment above. 1010 */ 1011 mem_size = (subbus - secbus + 1) * PPB_MEM_ALIGNMENT; 1012 if (mem_size < pci_bus_res[secbus].mem_size) { 1013 mem_size = pci_bus_res[secbus].mem_size; 1014 mem_size = P2ROUNDUP(mem_size, PPB_MEM_ALIGNMENT); 1015 } 1016 mem_align = mem_size; 1017 P2LE(mem_align); 1018 1019 /* Subtractive bridge */ 1020 if (pci_bus_res[secbus].subtractive && prog_sub) { 1021 /* 1022 * We program an arbitrary amount of I/O and memory resource 1023 * for the subtractive bridge so that child dynamic-resource- 1024 * allocating devices (such as Cardbus bridges) have a chance 1025 * of success. Until we have full-tree resource rebalancing, 1026 * dynamic resource allocation (thru busra) only looks at the 1027 * parent bridge, so all PPBs must have some allocatable 1028 * resource. For non-subtractive bridges, the resources come 1029 * from the base/limit register "windows", but subtractive 1030 * bridges often don't program those (since they don't need to). 1031 * If we put all the remaining resources on the subtractive 1032 * bridge, then peer non-subtractive bridges can't allocate 1033 * more space (even though this is probably most correct). 1034 * If we put the resources only on the parent, then allocations 1035 * from children of subtractive bridges will fail without 1036 * special-case code for bypassing the subtractive bridge. 1037 * This solution is the middle-ground temporary solution until 1038 * we have fully-capable resource allocation. 1039 */ 1040 1041 /* 1042 * Add an arbitrary I/O resource to the subtractive PPB 1043 */ 1044 if (pci_bus_res[secbus].io_avail == NULL) { 1045 addr = get_parbus_io_res(parbus, secbus, io_size, 1046 io_align); 1047 if (addr) { 1048 add_ranges_prop(secbus, 1); 1049 pci_bus_res[secbus].io_reprogram = 1050 pci_bus_res[parbus].io_reprogram; 1051 1052 cmn_err(CE_NOTE, "!add io-range on subtractive" 1053 " ppb[%x/%x/%x]: " 1054 "0x%"PRIx64" ~ 0x%"PRIx64"\n", 1055 bus, dev, func, addr, addr + io_size - 1); 1056 } 1057 } 1058 /* 1059 * Add an arbitrary memory resource to the subtractive PPB 1060 */ 1061 if (pci_bus_res[secbus].mem_avail == NULL) { 1062 addr = get_parbus_mem_res(parbus, secbus, mem_size, 1063 mem_align); 1064 if (addr) { 1065 add_ranges_prop(secbus, 1); 1066 pci_bus_res[secbus].mem_reprogram = 1067 pci_bus_res[parbus].mem_reprogram; 1068 1069 cmn_err(CE_NOTE, "!add mem-range on " 1070 "subtractive ppb[%x/%x/%x]: " 1071 "0x%"PRIx64" ~ 0x%"PRIx64"\n", 1072 bus, dev, func, 1073 addr, addr + mem_size - 1); 1074 } 1075 } 1076 1077 goto cmd_enable; 1078 } 1079 1080 /* 1081 * Check to see if we need to reprogram I/O space, either because the 1082 * parent bus needed reprogramming and so do we, or because I/O space is 1083 * disabled in base/limit or command register. 1084 */ 1085 io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 1086 io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 1087 io_base = (io_base & PCI_BCNF_IO_MASK) << PCI_BCNF_IO_SHIFT; 1088 io_limit = ((io_limit & PCI_BCNF_IO_MASK) << PCI_BCNF_IO_SHIFT) | 0xfff; 1089 if ((io_base & PCI_BCNF_ADDR_MASK) == PCI_BCNF_IO_32BIT) { 1090 uint16_t io_base_hi, io_limit_hi; 1091 io_base_hi = pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI); 1092 io_limit_hi = pci_getw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI); 1093 1094 io_base |= (uint_t)io_base_hi << 16; 1095 io_limit |= (uint_t)io_limit_hi << 16; 1096 } 1097 1098 /* Form list of all resources passed (avail + used) */ 1099 scratch_list = memlist_dup(pci_bus_res[secbus].io_avail); 1100 memlist_merge(&pci_bus_res[secbus].io_used, &scratch_list); 1101 1102 if ((pci_bus_res[parbus].io_reprogram || 1103 (io_base > io_limit) || 1104 (!(cmd_reg & PCI_COMM_IO))) && 1105 !list_is_vga_only(scratch_list, IO)) { 1106 if (pci_bus_res[secbus].io_used) { 1107 memlist_subsume(&pci_bus_res[secbus].io_used, 1108 &pci_bus_res[secbus].io_avail); 1109 } 1110 if (pci_bus_res[secbus].io_avail && 1111 (!pci_bus_res[parbus].io_reprogram) && 1112 (!pci_bus_res[parbus].subtractive)) { 1113 /* rechoose old io ports info */ 1114 list = pci_bus_res[secbus].io_avail; 1115 io_base = 0; 1116 do { 1117 if (is_vga(list, IO)) 1118 continue; 1119 if (!io_base) { 1120 io_base = (uint_t)list->ml_address; 1121 io_limit = (uint_t)list->ml_address + 1122 list->ml_size - 1; 1123 io_base = 1124 P2ALIGN(io_base, PPB_IO_ALIGNMENT); 1125 } else { 1126 if (list->ml_address + list->ml_size > 1127 io_limit) { 1128 io_limit = (uint_t) 1129 (list->ml_address + 1130 list->ml_size - 1); 1131 } 1132 } 1133 } while ((list = list->ml_next) != NULL); 1134 /* 4K aligned */ 1135 io_limit = P2ROUNDUP(io_limit, PPB_IO_ALIGNMENT) - 1; 1136 io_size = io_limit - io_base + 1; 1137 ASSERT(io_base <= io_limit); 1138 memlist_free_all(&pci_bus_res[secbus].io_avail); 1139 memlist_insert(&pci_bus_res[secbus].io_avail, 1140 io_base, io_size); 1141 memlist_insert(&pci_bus_res[parbus].io_used, 1142 io_base, io_size); 1143 (void) memlist_remove(&pci_bus_res[parbus].io_avail, 1144 io_base, io_size); 1145 pci_bus_res[secbus].io_reprogram = B_TRUE; 1146 } else { 1147 /* get new io ports from parent bus */ 1148 addr = get_parbus_io_res(parbus, secbus, io_size, 1149 io_align); 1150 if (addr) { 1151 io_base = addr; 1152 io_limit = addr + io_size - 1; 1153 pci_bus_res[secbus].io_reprogram = B_TRUE; 1154 } 1155 } 1156 if (pci_bus_res[secbus].io_reprogram) { 1157 /* reprogram PPB regs */ 1158 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 1159 (uchar_t)((io_base>>8) & 0xf0)); 1160 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 1161 (uchar_t)((io_limit>>8) & 0xf0)); 1162 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 1163 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 1164 add_ranges_prop(secbus, 1); 1165 1166 cmn_err(CE_NOTE, "!reprogram io-range on" 1167 " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 1168 bus, dev, func, io_base, io_limit); 1169 } 1170 } 1171 memlist_free_all(&scratch_list); 1172 1173 /* 1174 * Check memory space as we did I/O space. 1175 */ 1176 mem_base = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 1177 mem_base = (mem_base & 0xfff0) << 16; 1178 mem_limit = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 1179 mem_limit = ((mem_limit & 0xfff0) << 16) | 0xfffff; 1180 1181 scratch_list = memlist_dup(pci_bus_res[secbus].mem_avail); 1182 memlist_merge(&pci_bus_res[secbus].mem_used, &scratch_list); 1183 1184 if ((pci_bus_res[parbus].mem_reprogram || 1185 (mem_base > mem_limit) || 1186 (!(cmd_reg & PCI_COMM_MAE))) && 1187 !list_is_vga_only(scratch_list, MEM)) { 1188 if (pci_bus_res[secbus].mem_used) { 1189 memlist_subsume(&pci_bus_res[secbus].mem_used, 1190 &pci_bus_res[secbus].mem_avail); 1191 } 1192 if (pci_bus_res[secbus].mem_avail && 1193 (!pci_bus_res[parbus].mem_reprogram) && 1194 (!pci_bus_res[parbus].subtractive)) { 1195 /* rechoose old mem resource */ 1196 list = pci_bus_res[secbus].mem_avail; 1197 mem_base = 0; 1198 do { 1199 if (is_vga(list, MEM)) 1200 continue; 1201 if (mem_base == 0) { 1202 mem_base = list->ml_address; 1203 mem_base = P2ALIGN(mem_base, 1204 PPB_MEM_ALIGNMENT); 1205 mem_limit = (list->ml_address + 1206 list->ml_size - 1); 1207 } else { 1208 if ((list->ml_address + list->ml_size) > 1209 mem_limit) { 1210 mem_limit = 1211 (list->ml_address + 1212 list->ml_size - 1); 1213 } 1214 } 1215 } while ((list = list->ml_next) != NULL); 1216 mem_limit = P2ROUNDUP(mem_limit, PPB_MEM_ALIGNMENT) - 1; 1217 mem_size = mem_limit + 1 - mem_base; 1218 ASSERT(mem_base <= mem_limit); 1219 memlist_free_all(&pci_bus_res[secbus].mem_avail); 1220 memlist_insert(&pci_bus_res[secbus].mem_avail, 1221 mem_base, mem_size); 1222 memlist_insert(&pci_bus_res[parbus].mem_used, 1223 mem_base, mem_size); 1224 (void) memlist_remove(&pci_bus_res[parbus].mem_avail, 1225 mem_base, mem_size); 1226 pci_bus_res[secbus].mem_reprogram = B_TRUE; 1227 } else { 1228 /* get new mem resource from parent bus */ 1229 addr = get_parbus_mem_res(parbus, secbus, mem_size, 1230 mem_align); 1231 if (addr) { 1232 mem_base = addr; 1233 mem_limit = addr + mem_size - 1; 1234 pci_bus_res[secbus].mem_reprogram = B_TRUE; 1235 } 1236 } 1237 1238 if (pci_bus_res[secbus].mem_reprogram) { 1239 /* reprogram PPB MEM regs */ 1240 pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE, 1241 (uint16_t)((mem_base>>16) & 0xfff0)); 1242 pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT, 1243 (uint16_t)((mem_limit>>16) & 0xfff0)); 1244 /* 1245 * Disable PMEM window by setting base > limit. 1246 * We currently don't reprogram the PMEM like we've 1247 * done for I/O and MEM. (Devices that support prefetch 1248 * can use non-prefetch MEM.) Anyway, if the MEM access 1249 * bit is initially disabled by BIOS, we disable the 1250 * PMEM window manually by setting PMEM base > PMEM 1251 * limit here, in case there are incorrect values in 1252 * them from BIOS, so that we won't get in trouble once 1253 * the MEM access bit is enabled at the end of this 1254 * function. 1255 */ 1256 if (!(cmd_reg & PCI_COMM_MAE)) { 1257 pci_putw(bus, dev, func, PCI_BCNF_PF_BASE_LOW, 1258 0xfff0); 1259 pci_putw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW, 1260 0x0); 1261 pci_putl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH, 1262 0xffffffff); 1263 pci_putl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH, 1264 0x0); 1265 } 1266 1267 add_ranges_prop(secbus, 1); 1268 1269 cmn_err(CE_NOTE, "!reprogram mem-range on" 1270 " ppb[%x/%x/%x]: 0x%x ~ 0x%"PRIx64"\n", 1271 bus, dev, func, mem_base, mem_limit); 1272 } 1273 } 1274 memlist_free_all(&scratch_list); 1275 1276 cmd_enable: 1277 if (pci_bus_res[secbus].io_avail) 1278 cmd_reg |= PCI_COMM_IO | PCI_COMM_ME; 1279 if (pci_bus_res[secbus].mem_avail) 1280 cmd_reg |= PCI_COMM_MAE | PCI_COMM_ME; 1281 pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 1282 } 1283 1284 void 1285 pci_reprogram(void) 1286 { 1287 int i, pci_reconfig = 1; 1288 char *onoff; 1289 int bus; 1290 1291 /* 1292 * Scan ACPI namespace for _BBN objects, make sure that 1293 * childless root-bridges appear in devinfo tree 1294 */ 1295 pci_scan_bbn(); 1296 pci_unitaddr_cache_init(); 1297 1298 /* 1299 * Fix-up unit-address assignments if cache is available 1300 */ 1301 if (pci_unitaddr_cache_valid()) { 1302 int pci_regs[] = {0, 0, 0}; 1303 int new_addr; 1304 int index = 0; 1305 1306 for (bus = 0; bus <= pci_bios_maxbus; bus++) { 1307 /* skip non-root (peer) PCI busses */ 1308 if ((pci_bus_res[bus].par_bus != (uchar_t)-1) || 1309 (pci_bus_res[bus].dip == NULL)) 1310 continue; 1311 1312 new_addr = pci_bus_unitaddr(index); 1313 if (pci_bus_res[bus].root_addr != new_addr) { 1314 /* update reg property for node */ 1315 pci_regs[0] = pci_bus_res[bus].root_addr = 1316 new_addr; 1317 (void) ndi_prop_update_int_array( 1318 DDI_DEV_T_NONE, pci_bus_res[bus].dip, 1319 "reg", (int *)pci_regs, 3); 1320 } 1321 index++; 1322 } 1323 } else { 1324 /* perform legacy processing */ 1325 pci_renumber_root_busses(); 1326 pci_unitaddr_cache_create(); 1327 } 1328 1329 /* 1330 * Do root-bus resource discovery 1331 */ 1332 for (bus = 0; bus <= pci_bios_maxbus; bus++) { 1333 /* skip non-root (peer) PCI busses */ 1334 if (pci_bus_res[bus].par_bus != (uchar_t)-1) 1335 continue; 1336 1337 /* 1338 * 1. find resources associated with this root bus 1339 */ 1340 populate_bus_res(bus); 1341 1342 1343 /* 1344 * 2. Remove used PCI and ISA resources from bus resource map 1345 */ 1346 1347 memlist_remove_list(&pci_bus_res[bus].io_avail, 1348 pci_bus_res[bus].io_used); 1349 memlist_remove_list(&pci_bus_res[bus].mem_avail, 1350 pci_bus_res[bus].mem_used); 1351 memlist_remove_list(&pci_bus_res[bus].pmem_avail, 1352 pci_bus_res[bus].pmem_used); 1353 memlist_remove_list(&pci_bus_res[bus].mem_avail, 1354 pci_bus_res[bus].pmem_used); 1355 memlist_remove_list(&pci_bus_res[bus].pmem_avail, 1356 pci_bus_res[bus].mem_used); 1357 1358 memlist_remove_list(&pci_bus_res[bus].io_avail, 1359 isa_res.io_used); 1360 memlist_remove_list(&pci_bus_res[bus].mem_avail, 1361 isa_res.mem_used); 1362 1363 /* 1364 * 3. Exclude <1M address range here in case below reserved 1365 * ranges for BIOS data area, ROM area etc are wrongly reported 1366 * in ACPI resource producer entries for PCI root bus. 1367 * 00000000 - 000003FF RAM 1368 * 00000400 - 000004FF BIOS data area 1369 * 00000500 - 0009FFFF RAM 1370 * 000A0000 - 000BFFFF VGA RAM 1371 * 000C0000 - 000FFFFF ROM area 1372 */ 1373 (void) memlist_remove(&pci_bus_res[bus].mem_avail, 0, 0x100000); 1374 (void) memlist_remove(&pci_bus_res[bus].pmem_avail, 1375 0, 0x100000); 1376 } 1377 1378 memlist_free_all(&isa_res.io_used); 1379 memlist_free_all(&isa_res.mem_used); 1380 1381 /* add bus-range property for root/peer bus nodes */ 1382 for (i = 0; i <= pci_bios_maxbus; i++) { 1383 /* create bus-range property on root/peer buses */ 1384 if (pci_bus_res[i].par_bus == (uchar_t)-1) 1385 add_bus_range_prop(i); 1386 1387 /* setup bus range resource on each bus */ 1388 setup_bus_res(i); 1389 } 1390 1391 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 1392 DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 1393 if (strcmp(onoff, "off") == 0) { 1394 pci_reconfig = 0; 1395 cmn_err(CE_NOTE, "pci device reprogramming disabled"); 1396 } 1397 ddi_prop_free(onoff); 1398 } 1399 1400 remove_subtractive_res(); 1401 1402 /* reprogram the non-subtractive PPB */ 1403 if (pci_reconfig) 1404 for (i = 0; i <= pci_bios_maxbus; i++) 1405 fix_ppb_res(i, B_FALSE); 1406 1407 for (i = 0; i <= pci_bios_maxbus; i++) { 1408 /* configure devices not configured by BIOS */ 1409 if (pci_reconfig) { 1410 /* 1411 * Reprogram the subtractive PPB. At this time, all its 1412 * siblings should have got their resources already. 1413 */ 1414 if (pci_bus_res[i].subtractive) 1415 fix_ppb_res(i, B_TRUE); 1416 enumerate_bus_devs(i, CONFIG_NEW); 1417 } 1418 } 1419 1420 /* All dev programmed, so we can create available prop */ 1421 for (i = 0; i <= pci_bios_maxbus; i++) 1422 add_bus_available_prop(i); 1423 } 1424 1425 /* 1426 * populate bus resources 1427 */ 1428 static void 1429 populate_bus_res(uchar_t bus) 1430 { 1431 1432 /* scan BIOS structures */ 1433 pci_bus_res[bus].pmem_avail = find_bus_res(bus, PREFETCH_TYPE); 1434 pci_bus_res[bus].mem_avail = find_bus_res(bus, MEM_TYPE); 1435 pci_bus_res[bus].io_avail = find_bus_res(bus, IO_TYPE); 1436 pci_bus_res[bus].bus_avail = find_bus_res(bus, BUSRANGE_TYPE); 1437 1438 /* 1439 * attempt to initialize sub_bus from the largest range-end 1440 * in the bus_avail list 1441 */ 1442 if (pci_bus_res[bus].bus_avail != NULL) { 1443 struct memlist *entry; 1444 int current; 1445 1446 entry = pci_bus_res[bus].bus_avail; 1447 while (entry != NULL) { 1448 current = entry->ml_address + entry->ml_size - 1; 1449 if (current > pci_bus_res[bus].sub_bus) 1450 pci_bus_res[bus].sub_bus = current; 1451 entry = entry->ml_next; 1452 } 1453 } 1454 1455 if (bus == 0) { 1456 /* 1457 * Special treatment of bus 0: 1458 * If no IO/MEM resource from ACPI/MPSPEC/HRT, copy 1459 * pcimem from boot and make I/O space the entire range 1460 * starting at 0x100. 1461 */ 1462 if (pci_bus_res[0].mem_avail == NULL) 1463 pci_bus_res[0].mem_avail = 1464 memlist_dup(bootops->boot_mem->pcimem); 1465 /* Exclude 0x00 to 0xff of the I/O space, used by all PCs */ 1466 if (pci_bus_res[0].io_avail == NULL) 1467 memlist_insert(&pci_bus_res[0].io_avail, 0x100, 0xffff); 1468 } 1469 1470 /* 1471 * Create 'ranges' property here before any resources are 1472 * removed from the resource lists 1473 */ 1474 add_ranges_prop(bus, 0); 1475 } 1476 1477 1478 /* 1479 * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 1480 */ 1481 static void 1482 create_root_bus_dip(uchar_t bus) 1483 { 1484 int pci_regs[] = {0, 0, 0}; 1485 dev_info_t *dip; 1486 1487 ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 1488 1489 num_root_bus++; 1490 ndi_devi_alloc_sleep(ddi_root_node(), "pci", 1491 (pnode_t)DEVI_SID_NODEID, &dip); 1492 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1493 "#address-cells", 3); 1494 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1495 "#size-cells", 2); 1496 pci_regs[0] = pci_bus_res[bus].root_addr; 1497 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1498 "reg", (int *)pci_regs, 3); 1499 1500 /* 1501 * If system has PCIe bus, then create different properties 1502 */ 1503 if (create_pcie_root_bus(bus, dip) == B_FALSE) 1504 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1505 "device_type", "pci"); 1506 1507 (void) ndi_devi_bind_driver(dip, 0); 1508 pci_bus_res[bus].dip = dip; 1509 } 1510 1511 /* 1512 * For any fixed configuration (often compatability) pci devices 1513 * and those with their own expansion rom, create device nodes 1514 * to hold the already configured device details. 1515 */ 1516 void 1517 enumerate_bus_devs(uchar_t bus, int config_op) 1518 { 1519 uchar_t dev, func, nfunc, header; 1520 ushort_t venid; 1521 struct pci_devfunc *devlist = NULL, *entry; 1522 1523 if (config_op == CONFIG_NEW) { 1524 dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 1525 } else if (config_op == CONFIG_FIX) { 1526 dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus); 1527 } else 1528 dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 1529 1530 if (config_op == CONFIG_NEW) { 1531 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 1532 while (devlist) { 1533 entry = devlist; 1534 devlist = entry->next; 1535 if (entry->reprogram || 1536 pci_bus_res[bus].io_reprogram || 1537 pci_bus_res[bus].mem_reprogram) { 1538 /* reprogram device(s) */ 1539 (void) add_reg_props(entry->dip, bus, 1540 entry->dev, entry->func, CONFIG_NEW, 0); 1541 } 1542 kmem_free(entry, sizeof (*entry)); 1543 } 1544 pci_bus_res[bus].privdata = NULL; 1545 return; 1546 } 1547 1548 for (dev = 0; dev < max_dev_pci; dev++) { 1549 nfunc = 1; 1550 for (func = 0; func < nfunc; func++) { 1551 1552 dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", 1553 dev, func); 1554 1555 venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 1556 1557 if ((venid == 0xffff) || (venid == 0)) { 1558 /* no function at this address */ 1559 continue; 1560 } 1561 1562 header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 1563 if (header == 0xff) { 1564 continue; /* illegal value */ 1565 } 1566 1567 /* 1568 * according to some mail from Microsoft posted 1569 * to the pci-drivers alias, their only requirement 1570 * for a multifunction device is for the 1st 1571 * function to have to PCI_HEADER_MULTI bit set. 1572 */ 1573 if ((func == 0) && (header & PCI_HEADER_MULTI)) { 1574 nfunc = 8; 1575 } 1576 1577 if (config_op == CONFIG_FIX || 1578 config_op == CONFIG_INFO) { 1579 /* 1580 * Create the node, unconditionally, on the 1581 * first pass only. It may still need 1582 * resource assignment, which will be 1583 * done on the second, CONFIG_NEW, pass. 1584 */ 1585 process_devfunc(bus, dev, func, header, 1586 venid, config_op); 1587 1588 } 1589 } 1590 } 1591 1592 /* percolate bus used resources up through parents to root */ 1593 if (config_op == CONFIG_INFO) { 1594 int par_bus; 1595 1596 par_bus = pci_bus_res[bus].par_bus; 1597 while (par_bus != (uchar_t)-1) { 1598 pci_bus_res[par_bus].io_size += 1599 pci_bus_res[bus].io_size; 1600 pci_bus_res[par_bus].mem_size += 1601 pci_bus_res[bus].mem_size; 1602 1603 if (pci_bus_res[bus].io_used) 1604 memlist_merge(&pci_bus_res[bus].io_used, 1605 &pci_bus_res[par_bus].io_used); 1606 1607 if (pci_bus_res[bus].mem_used) 1608 memlist_merge(&pci_bus_res[bus].mem_used, 1609 &pci_bus_res[par_bus].mem_used); 1610 1611 if (pci_bus_res[bus].pmem_used) 1612 memlist_merge(&pci_bus_res[bus].pmem_used, 1613 &pci_bus_res[par_bus].pmem_used); 1614 1615 bus = par_bus; 1616 par_bus = pci_bus_res[par_bus].par_bus; 1617 } 1618 } 1619 } 1620 1621 static int 1622 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 1623 ushort_t subvenid, ushort_t subdevid) 1624 { 1625 static int prop_exist = -1; 1626 static char *pciide_str; 1627 char compat[32]; 1628 1629 if (prop_exist == -1) { 1630 prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 1631 ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 1632 &pciide_str) == DDI_SUCCESS); 1633 } 1634 1635 if (!prop_exist) 1636 return (0); 1637 1638 /* compare property value against various forms of compatible */ 1639 if (subvenid) { 1640 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 1641 venid, devid, subvenid, subdevid, revid); 1642 if (strcmp(pciide_str, compat) == 0) 1643 return (1); 1644 1645 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 1646 venid, devid, subvenid, subdevid); 1647 if (strcmp(pciide_str, compat) == 0) 1648 return (1); 1649 1650 (void) snprintf(compat, sizeof (compat), "pci%x,%x", 1651 subvenid, subdevid); 1652 if (strcmp(pciide_str, compat) == 0) 1653 return (1); 1654 } 1655 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 1656 venid, devid, revid); 1657 if (strcmp(pciide_str, compat) == 0) 1658 return (1); 1659 1660 (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 1661 if (strcmp(pciide_str, compat) == 0) 1662 return (1); 1663 1664 return (0); 1665 } 1666 1667 static int 1668 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 1669 ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 1670 { 1671 struct ide_table { /* table for PCI_MASS_OTHER */ 1672 ushort_t venid; 1673 ushort_t devid; 1674 } *entry; 1675 1676 /* XXX SATA and other devices: need a way to add dynamically */ 1677 static struct ide_table ide_other[] = { 1678 {0x1095, 0x3112}, 1679 {0x1095, 0x3114}, 1680 {0x1095, 0x3512}, 1681 {0x1095, 0x680}, /* Sil0680 */ 1682 {0x1283, 0x8211}, /* ITE 8211F is subcl PCI_MASS_OTHER */ 1683 {0, 0} 1684 }; 1685 1686 if (basecl != PCI_CLASS_MASS) 1687 return (0); 1688 1689 if (subcl == PCI_MASS_IDE) { 1690 return (1); 1691 } 1692 1693 if (check_pciide_prop(revid, venid, devid, subvenid, subdevid)) 1694 return (1); 1695 1696 if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 1697 return (0); 1698 } 1699 1700 entry = &ide_other[0]; 1701 while (entry->venid) { 1702 if (entry->venid == venid && entry->devid == devid) 1703 return (1); 1704 entry++; 1705 } 1706 return (0); 1707 } 1708 1709 static int 1710 is_display(uint_t classcode) 1711 { 1712 static uint_t disp_classes[] = { 1713 0x000100, 1714 0x030000, 1715 0x030001 1716 }; 1717 int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 1718 1719 for (i = 0; i < nclasses; i++) { 1720 if (classcode == disp_classes[i]) 1721 return (1); 1722 } 1723 return (0); 1724 } 1725 1726 static void 1727 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn, 1728 void (*undofn)(uint8_t, uint8_t, uint8_t)) 1729 { 1730 struct pci_fixundo *newundo; 1731 1732 newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP); 1733 1734 /* 1735 * Adding an item to this list means that we must turn its NMIENABLE 1736 * bit back on at a later time. 1737 */ 1738 newundo->bus = bus; 1739 newundo->dev = dev; 1740 newundo->fn = fn; 1741 newundo->undofn = undofn; 1742 newundo->next = undolist; 1743 1744 /* add to the undo list in LIFO order */ 1745 undolist = newundo; 1746 } 1747 1748 void 1749 add_pci_fixes(void) 1750 { 1751 int i; 1752 1753 for (i = 0; i <= pci_bios_maxbus; i++) { 1754 /* 1755 * For each bus, apply needed fixes to the appropriate devices. 1756 * This must be done before the main enumeration loop because 1757 * some fixes must be applied to devices normally encountered 1758 * later in the pci scan (e.g. if a fix to device 7 must be 1759 * applied before scanning device 6, applying fixes in the 1760 * normal enumeration loop would obviously be too late). 1761 */ 1762 enumerate_bus_devs(i, CONFIG_FIX); 1763 } 1764 } 1765 1766 void 1767 undo_pci_fixes(void) 1768 { 1769 struct pci_fixundo *nextundo; 1770 uint8_t bus, dev, fn; 1771 1772 /* 1773 * All fixes in the undo list are performed unconditionally. Future 1774 * fixes may require selective undo. 1775 */ 1776 while (undolist != NULL) { 1777 1778 bus = undolist->bus; 1779 dev = undolist->dev; 1780 fn = undolist->fn; 1781 1782 (*(undolist->undofn))(bus, dev, fn); 1783 1784 nextundo = undolist->next; 1785 kmem_free(undolist, sizeof (struct pci_fixundo)); 1786 undolist = nextundo; 1787 } 1788 } 1789 1790 static void 1791 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn) 1792 { 1793 uint8_t val8; 1794 1795 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1796 /* 1797 * The NMIONERR bit is turned back on to allow the SMM BIOS 1798 * to handle more critical PCI errors (e.g. PERR#). 1799 */ 1800 val8 |= AMD8111_ENABLENMI; 1801 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1802 } 1803 1804 static void 1805 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn) 1806 { 1807 uint8_t val8; 1808 1809 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1810 1811 if ((val8 & AMD8111_ENABLENMI) == 0) 1812 return; 1813 1814 /* 1815 * We reset NMIONERR in the LPC because master-abort on the PCI 1816 * bridge side of the 8111 will cause NMI, which might cause SMI, 1817 * which sometimes prevents all devices from being enumerated. 1818 */ 1819 val8 &= ~AMD8111_ENABLENMI; 1820 1821 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1822 1823 add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix); 1824 } 1825 1826 static void 1827 set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func) 1828 { 1829 uint16_t status; 1830 uint8_t header; 1831 uint8_t cap_ptr; 1832 uint8_t cap_id; 1833 uint16_t pmcsr; 1834 1835 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 1836 if (!(status & PCI_STAT_CAP)) 1837 return; /* No capabilities list */ 1838 1839 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1840 if (header == PCI_HEADER_CARDBUS) 1841 cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_CAP_PTR); 1842 else 1843 cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 1844 /* 1845 * Walk the capabilities list searching for a PM entry. 1846 */ 1847 while (cap_ptr != PCI_CAP_NEXT_PTR_NULL && cap_ptr >= PCI_CAP_PTR_OFF) { 1848 cap_ptr &= PCI_CAP_PTR_MASK; 1849 cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID); 1850 if (cap_id == PCI_CAP_ID_PM) { 1851 pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR); 1852 pmcsr &= ~(PCI_PMCSR_STATE_MASK); 1853 pmcsr |= PCI_PMCSR_D0; /* D0 state */ 1854 pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr); 1855 break; 1856 } 1857 cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR); 1858 } 1859 1860 } 1861 1862 #define is_isa(bc, sc) \ 1863 (((bc) == PCI_CLASS_BRIDGE) && ((sc) == PCI_BRIDGE_ISA)) 1864 1865 static void 1866 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 1867 ushort_t vendorid, int config_op) 1868 { 1869 char nodename[32], unitaddr[5]; 1870 dev_info_t *dip; 1871 uchar_t basecl, subcl, progcl, intr, revid; 1872 ushort_t subvenid, subdevid, status; 1873 ushort_t slot_num; 1874 uint_t classcode, revclass; 1875 int reprogram = 0, pciide = 0; 1876 int power[2] = {1, 1}; 1877 int pciex = 0; 1878 ushort_t is_pci_bridge = 0; 1879 struct pci_devfunc *devlist = NULL, *entry = NULL; 1880 boolean_t slot_valid; 1881 gfx_entry_t *gfxp; 1882 pcie_req_id_t bdf; 1883 1884 ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 1885 1886 switch (header & PCI_HEADER_TYPE_M) { 1887 case PCI_HEADER_ZERO: 1888 subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 1889 subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 1890 break; 1891 case PCI_HEADER_CARDBUS: 1892 subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 1893 subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 1894 /* Record the # of cardbus bridges found on the bus */ 1895 if (config_op == CONFIG_INFO) 1896 pci_bus_res[bus].num_cbb++; 1897 break; 1898 default: 1899 subvenid = 0; 1900 subdevid = 0; 1901 break; 1902 } 1903 1904 if (config_op == CONFIG_FIX) { 1905 if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) { 1906 pci_fix_amd8111(bus, dev, func); 1907 } 1908 return; 1909 } 1910 1911 /* XXX should be use generic names? derive from class? */ 1912 revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 1913 classcode = revclass >> 8; 1914 revid = revclass & 0xff; 1915 1916 /* figure out if this is pci-ide */ 1917 basecl = classcode >> 16; 1918 subcl = (classcode >> 8) & 0xff; 1919 progcl = classcode & 0xff; 1920 1921 1922 if (is_display(classcode)) 1923 (void) snprintf(nodename, sizeof (nodename), "display"); 1924 else if (!pseudo_isa && is_isa(basecl, subcl)) 1925 (void) snprintf(nodename, sizeof (nodename), "isa"); 1926 else if (subvenid != 0) 1927 (void) snprintf(nodename, sizeof (nodename), 1928 "pci%x,%x", subvenid, subdevid); 1929 else 1930 (void) snprintf(nodename, sizeof (nodename), 1931 "pci%x,%x", vendorid, deviceid); 1932 1933 /* make sure parent bus dip has been created */ 1934 if (pci_bus_res[bus].dip == NULL) 1935 create_root_bus_dip(bus); 1936 1937 ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 1938 DEVI_SID_NODEID, &dip); 1939 1940 if (check_if_device_is_pciex(dip, bus, dev, func, &slot_valid, 1941 &slot_num, &is_pci_bridge) == B_TRUE) 1942 pciex = 1; 1943 1944 bdf = PCI_GETBDF(bus, dev, func); 1945 /* 1946 * Record BAD AMD bridges which don't support MMIO config access. 1947 */ 1948 if (IS_BAD_AMD_NTBRIDGE(vendorid, deviceid) || 1949 IS_AMD_8132_CHIP(vendorid, deviceid)) { 1950 uchar_t secbus = 0; 1951 uchar_t subbus = 0; 1952 1953 if ((basecl == PCI_CLASS_BRIDGE) && 1954 (subcl == PCI_BRIDGE_PCI)) { 1955 secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 1956 subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 1957 } 1958 pci_cfgacc_add_workaround(bdf, secbus, subbus); 1959 } 1960 1961 /* 1962 * Only populate bus_t if this device is sitting under a PCIE root 1963 * complex. Some particular machines have both a PCIE root complex and 1964 * a PCI hostbridge, in which case only devices under the PCIE root 1965 * complex will have their bus_t populated. 1966 */ 1967 if (pcie_get_rc_dip(dip) != NULL) { 1968 ck804_fix_aer_ptr(dip, bdf); 1969 (void) pcie_init_bus(dip, bdf, PCIE_BUS_INITIAL); 1970 } 1971 1972 /* add properties */ 1973 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 1974 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 1975 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 1976 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1977 "class-code", classcode); 1978 if (func == 0) 1979 (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 1980 else 1981 (void) snprintf(unitaddr, sizeof (unitaddr), 1982 "%x,%x", dev, func); 1983 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1984 "unit-address", unitaddr); 1985 1986 /* add device_type for display nodes */ 1987 if (is_display(classcode)) { 1988 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1989 "device_type", "display"); 1990 } 1991 /* add special stuff for header type */ 1992 if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 1993 uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 1994 uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 1995 1996 if (subvenid != 0) { 1997 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1998 "subsystem-id", subdevid); 1999 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2000 "subsystem-vendor-id", subvenid); 2001 } 2002 if (!pciex) 2003 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2004 "min-grant", mingrant); 2005 if (!pciex) 2006 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2007 "max-latency", maxlatency); 2008 } 2009 2010 /* interrupt, record if not 0 */ 2011 intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 2012 if (intr != 0) 2013 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2014 "interrupts", intr); 2015 2016 /* 2017 * Add support for 133 mhz pci eventually 2018 */ 2019 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 2020 2021 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2022 "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 2023 if (!pciex && (status & PCI_STAT_FBBC)) 2024 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 2025 "fast-back-to-back"); 2026 if (!pciex && (status & PCI_STAT_66MHZ)) 2027 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 2028 "66mhz-capable"); 2029 if (status & PCI_STAT_UDF) 2030 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 2031 "udf-supported"); 2032 if (pciex && slot_valid) { 2033 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2034 "physical-slot#", slot_num); 2035 if (!is_pci_bridge) 2036 pciex_slot_names_prop(dip, slot_num); 2037 } 2038 2039 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 2040 "power-consumption", power, 2); 2041 2042 /* Set the device PM state to D0 */ 2043 set_devpm_d0(bus, dev, func); 2044 2045 if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) 2046 add_ppb_props(dip, bus, dev, func, pciex, is_pci_bridge); 2047 else { 2048 /* 2049 * Record the non-PPB devices on the bus for possible 2050 * reprogramming at 2nd bus enumeration. 2051 * Note: PPB reprogramming is done in fix_ppb_res() 2052 */ 2053 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 2054 entry = kmem_zalloc(sizeof (*entry), KM_SLEEP); 2055 entry->dip = dip; 2056 entry->dev = dev; 2057 entry->func = func; 2058 entry->next = devlist; 2059 pci_bus_res[bus].privdata = entry; 2060 } 2061 2062 if (IS_CLASS_IOAPIC(basecl, subcl, progcl)) { 2063 create_ioapic_node(bus, dev, func, vendorid, deviceid); 2064 } 2065 2066 /* check for NVIDIA CK8-04/MCP55 based LPC bridge */ 2067 if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) && 2068 (func == 0)) { 2069 add_nvidia_isa_bridge_props(dip, bus, dev, func); 2070 /* each LPC bridge has an integrated IOAPIC */ 2071 apic_nvidia_io_max++; 2072 } 2073 2074 if (pciex && is_pci_bridge) 2075 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 2076 (char *)"PCIe-PCI bridge"); 2077 else 2078 add_model_prop(dip, classcode); 2079 2080 add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 2081 revid, classcode, pciex); 2082 2083 /* 2084 * See if this device is a controller that advertises 2085 * itself to be a standard ATA task file controller, or one that 2086 * has been hard coded. 2087 * 2088 * If it is, check if any other higher precedence driver listed in 2089 * driver_aliases will claim the node by calling 2090 * ddi_compatibile_driver_major. If so, clear pciide and do not 2091 * create a pci-ide node or any other special handling. 2092 * 2093 * If another driver does not bind, set the node name to pci-ide 2094 * and then let the special pci-ide handling for registers and 2095 * child pci-ide nodes proceed below. 2096 */ 2097 if (is_pciide(basecl, subcl, revid, vendorid, deviceid, 2098 subvenid, subdevid) == 1) { 2099 if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) { 2100 (void) ndi_devi_set_nodename(dip, "pci-ide", 0); 2101 pciide = 1; 2102 } 2103 } 2104 2105 DEVI_SET_PCI(dip); 2106 reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 2107 (void) ndi_devi_bind_driver(dip, 0); 2108 2109 /* special handling for pci-ide */ 2110 if (pciide) { 2111 dev_info_t *cdip; 2112 2113 /* 2114 * Create properties specified by P1275 Working Group 2115 * Proposal #414 Version 1 2116 */ 2117 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 2118 "device_type", "pci-ide"); 2119 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2120 "#address-cells", 1); 2121 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2122 "#size-cells", 0); 2123 2124 /* allocate two child nodes */ 2125 ndi_devi_alloc_sleep(dip, "ide", 2126 (pnode_t)DEVI_SID_NODEID, &cdip); 2127 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 2128 "reg", 0); 2129 (void) ndi_devi_bind_driver(cdip, 0); 2130 ndi_devi_alloc_sleep(dip, "ide", 2131 (pnode_t)DEVI_SID_NODEID, &cdip); 2132 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 2133 "reg", 1); 2134 (void) ndi_devi_bind_driver(cdip, 0); 2135 2136 reprogram = 0; /* don't reprogram pci-ide bridge */ 2137 } 2138 2139 if (is_display(classcode)) { 2140 gfxp = kmem_zalloc(sizeof (*gfxp), KM_SLEEP); 2141 gfxp->g_dip = dip; 2142 gfxp->g_prev = NULL; 2143 gfxp->g_next = gfx_devinfo_list; 2144 gfx_devinfo_list = gfxp; 2145 if (gfxp->g_next) 2146 gfxp->g_next->g_prev = gfxp; 2147 } 2148 2149 /* special handling for isa */ 2150 if (!pseudo_isa && is_isa(basecl, subcl)) { 2151 /* add device_type */ 2152 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 2153 "device_type", "isa"); 2154 } 2155 2156 if (reprogram && (entry != NULL)) 2157 entry->reprogram = B_TRUE; 2158 2159 } 2160 2161 /* 2162 * Some vendors do not use unique subsystem IDs in their products, which 2163 * makes the use of form 2 compatible names (pciSSSS,ssss) inappropriate. 2164 * Allow for these compatible forms to be excluded on a per-device basis. 2165 */ 2166 /*ARGSUSED*/ 2167 static boolean_t 2168 subsys_compat_exclude(ushort_t venid, ushort_t devid, ushort_t subvenid, 2169 ushort_t subdevid, uchar_t revid, uint_t classcode) 2170 { 2171 /* Nvidia display adapters */ 2172 if ((venid == 0x10de) && (is_display(classcode))) 2173 return (B_TRUE); 2174 2175 /* 2176 * 8086,166 is the Ivy Bridge built-in graphics controller on some 2177 * models. Unfortunately 8086,2044 is the Skylake Server processor 2178 * memory channel device. The Ivy Bridge device uses the Skylake 2179 * ID as its sub-device ID. The GPU is not a memory controller DIMM 2180 * channel. 2181 */ 2182 if (venid == 0x8086 && devid == 0x166 && subvenid == 0x8086 && 2183 subdevid == 0x2044) { 2184 return (B_TRUE); 2185 } 2186 2187 return (B_FALSE); 2188 } 2189 2190 /* 2191 * Set the compatible property to a value compliant with rev 2.1 of the IEEE1275 2192 * PCI binding. This is also used for PCI express devices and we have our own 2193 * minor additions. 2194 * 2195 * pciVVVV,DDDD.SSSS.ssss.RR (0) 2196 * pciVVVV,DDDD.SSSS.ssss (1) 2197 * pciSSSS,ssss,s (2+) 2198 * pciSSSS,ssss (2) 2199 * pciVVVV,DDDD.RR (3) 2200 * pciVVVV,DDDD,p (4+) 2201 * pciVVVV,DDDD (4) 2202 * pciclass,CCSSPP (5) 2203 * pciclass,CCSS (6) 2204 * 2205 * The Subsystem (SSSS) forms are not inserted if subsystem-vendor-id is 0 or if 2206 * it is a case where we know that the IDs overlap. 2207 * 2208 * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above and 2209 * property 2 is not created as per "1275 bindings for PCI Express 2210 * Interconnect". 2211 * 2212 * Unlike on SPARC, we generate both the "pciex" and "pci" versions of the 2213 * above. The problem with property 2 is that it has an ambiguity with 2214 * property 4. To make sure that drivers can specify either form of 2 or 4 2215 * without ambiguity we add a suffix. The 'p' suffix represents the primary ID, 2216 * meaning that it is guaranteed to be form 4. The 's' suffix means that it is 2217 * sub-vendor and sub-device form, meaning it is guaranteed to be form 2. 2218 * 2219 * Set with setprop and \x00 between each to generate the encoded string array 2220 * form. 2221 */ 2222 void 2223 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 2224 ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode, 2225 int pciex) 2226 { 2227 int i = 0; 2228 int size = COMPAT_BUFSIZE; 2229 char *compat[15]; 2230 char *buf, *curr; 2231 2232 curr = buf = kmem_alloc(size, KM_SLEEP); 2233 2234 if (pciex) { 2235 if (subvenid) { 2236 compat[i++] = curr; /* form 0 */ 2237 (void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x", 2238 vendorid, deviceid, subvenid, subdevid, revid); 2239 size -= strlen(curr) + 1; 2240 curr += strlen(curr) + 1; 2241 2242 compat[i++] = curr; /* form 1 */ 2243 (void) snprintf(curr, size, "pciex%x,%x.%x.%x", 2244 vendorid, deviceid, subvenid, subdevid); 2245 size -= strlen(curr) + 1; 2246 curr += strlen(curr) + 1; 2247 2248 } 2249 compat[i++] = curr; /* form 3 */ 2250 (void) snprintf(curr, size, "pciex%x,%x.%x", 2251 vendorid, deviceid, revid); 2252 size -= strlen(curr) + 1; 2253 curr += strlen(curr) + 1; 2254 2255 compat[i++] = curr; /* form 4 */ 2256 (void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid); 2257 size -= strlen(curr) + 1; 2258 curr += strlen(curr) + 1; 2259 2260 compat[i++] = curr; /* form 5 */ 2261 (void) snprintf(curr, size, "pciexclass,%06x", classcode); 2262 size -= strlen(curr) + 1; 2263 curr += strlen(curr) + 1; 2264 2265 compat[i++] = curr; /* form 6 */ 2266 (void) snprintf(curr, size, "pciexclass,%04x", 2267 (classcode >> 8)); 2268 size -= strlen(curr) + 1; 2269 curr += strlen(curr) + 1; 2270 } 2271 2272 if (subvenid) { 2273 compat[i++] = curr; /* form 0 */ 2274 (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 2275 vendorid, deviceid, subvenid, subdevid, revid); 2276 size -= strlen(curr) + 1; 2277 curr += strlen(curr) + 1; 2278 2279 compat[i++] = curr; /* form 1 */ 2280 (void) snprintf(curr, size, "pci%x,%x.%x.%x", 2281 vendorid, deviceid, subvenid, subdevid); 2282 size -= strlen(curr) + 1; 2283 curr += strlen(curr) + 1; 2284 2285 if (subsys_compat_exclude(vendorid, deviceid, subvenid, 2286 subdevid, revid, classcode) == B_FALSE) { 2287 compat[i++] = curr; /* form 2+ */ 2288 (void) snprintf(curr, size, "pci%x,%x,s", subvenid, 2289 subdevid); 2290 size -= strlen(curr) + 1; 2291 curr += strlen(curr) + 1; 2292 2293 compat[i++] = curr; /* form 2 */ 2294 (void) snprintf(curr, size, "pci%x,%x", subvenid, 2295 subdevid); 2296 size -= strlen(curr) + 1; 2297 curr += strlen(curr) + 1; 2298 } 2299 } 2300 compat[i++] = curr; /* form 3 */ 2301 (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 2302 size -= strlen(curr) + 1; 2303 curr += strlen(curr) + 1; 2304 2305 compat[i++] = curr; /* form 4+ */ 2306 (void) snprintf(curr, size, "pci%x,%x,p", vendorid, deviceid); 2307 size -= strlen(curr) + 1; 2308 curr += strlen(curr) + 1; 2309 2310 compat[i++] = curr; /* form 4 */ 2311 (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 2312 size -= strlen(curr) + 1; 2313 curr += strlen(curr) + 1; 2314 2315 compat[i++] = curr; /* form 5 */ 2316 (void) snprintf(curr, size, "pciclass,%06x", classcode); 2317 size -= strlen(curr) + 1; 2318 curr += strlen(curr) + 1; 2319 2320 compat[i++] = curr; /* form 6 */ 2321 (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 2322 size -= strlen(curr) + 1; 2323 curr += strlen(curr) + 1; 2324 2325 (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 2326 "compatible", compat, i); 2327 kmem_free(buf, COMPAT_BUFSIZE); 2328 } 2329 2330 /* 2331 * Adjust the reg properties for a dual channel PCI-IDE device. 2332 * 2333 * NOTE: don't do anything that changes the order of the hard-decodes 2334 * and programmed BARs. The kernel driver depends on these values 2335 * being in this order regardless of whether they're for a 'native' 2336 * mode BAR or not. 2337 */ 2338 /* 2339 * config info for pci-ide devices 2340 */ 2341 static struct { 2342 uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 2343 uchar_t bar_offset; /* offset for alt status register */ 2344 ushort_t addr; /* compatibility mode base address */ 2345 ushort_t length; /* number of ports for this BAR */ 2346 } pciide_bar[] = { 2347 { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 2348 { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 2349 { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 2350 { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 2351 }; 2352 2353 static int 2354 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 2355 { 2356 int hard_decode = 0; 2357 2358 /* 2359 * Adjust the base and len for the BARs of the PCI-IDE 2360 * device's primary and secondary controllers. The first 2361 * two BARs are for the primary controller and the next 2362 * two BARs are for the secondary controller. The fifth 2363 * and sixth bars are never adjusted. 2364 */ 2365 if (index >= 0 && index <= 3) { 2366 *lenp = pciide_bar[index].length; 2367 2368 if (progcl & pciide_bar[index].native_mask) { 2369 *basep += pciide_bar[index].bar_offset; 2370 } else { 2371 *basep = pciide_bar[index].addr; 2372 hard_decode = 1; 2373 } 2374 } 2375 2376 /* 2377 * if either base or len is zero make certain both are zero 2378 */ 2379 if (*basep == 0 || *lenp == 0) { 2380 *basep = 0; 2381 *lenp = 0; 2382 hard_decode = 0; 2383 } 2384 2385 return (hard_decode); 2386 } 2387 2388 2389 /* 2390 * Add the "reg" and "assigned-addresses" property 2391 */ 2392 static int 2393 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 2394 int config_op, int pciide) 2395 { 2396 uchar_t baseclass, subclass, progclass, header; 2397 ushort_t bar_sz; 2398 uint64_t value = 0; 2399 uint_t devloc; 2400 uint_t base, base_hi, type; 2401 ushort_t offset, end; 2402 int max_basereg, j, reprogram = 0; 2403 uint_t phys_hi; 2404 struct memlist **io_avail, **io_used; 2405 struct memlist **mem_avail, **mem_used; 2406 struct memlist **pmem_avail, **pmem_used; 2407 uchar_t res_bus; 2408 2409 pci_regspec_t regs[16] = {{0}}; 2410 pci_regspec_t assigned[15] = {{0}}; 2411 int nreg, nasgn; 2412 2413 io_avail = &pci_bus_res[bus].io_avail; 2414 io_used = &pci_bus_res[bus].io_used; 2415 mem_avail = &pci_bus_res[bus].mem_avail; 2416 mem_used = &pci_bus_res[bus].mem_used; 2417 pmem_avail = &pci_bus_res[bus].pmem_avail; 2418 pmem_used = &pci_bus_res[bus].pmem_used; 2419 2420 devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 2421 regs[0].pci_phys_hi = devloc; 2422 nreg = 1; /* rest of regs[0] is all zero */ 2423 nasgn = 0; 2424 2425 baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 2426 subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 2427 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 2428 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 2429 2430 switch (header) { 2431 case PCI_HEADER_ZERO: 2432 max_basereg = PCI_BASE_NUM; 2433 break; 2434 case PCI_HEADER_PPB: 2435 max_basereg = PCI_BCNF_BASE_NUM; 2436 break; 2437 case PCI_HEADER_CARDBUS: 2438 max_basereg = PCI_CBUS_BASE_NUM; 2439 reprogram = 1; 2440 break; 2441 default: 2442 max_basereg = 0; 2443 break; 2444 } 2445 2446 /* 2447 * Create the register property by saving the current 2448 * value of the base register. Write 0xffffffff to the 2449 * base register. Read the value back to determine the 2450 * required size of the address space. Restore the base 2451 * register contents. 2452 * 2453 * Do not disable I/O and memory access for bridges; this 2454 * has the side-effect of making the bridge transparent to 2455 * secondary-bus activity (see sections 4.1-4.3 of the 2456 * PCI-PCI Bridge Spec V1.2). For non-bridges, disable 2457 * I/O and memory access to avoid difficulty with USB 2458 * emulation (see OHCI spec1.0a appendix B 2459 * "Host Controller Mapping") 2460 */ 2461 end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 2462 for (j = 0, offset = PCI_CONF_BASE0; offset < end; 2463 j++, offset += bar_sz) { 2464 uint_t command; 2465 2466 /* determine the size of the address space */ 2467 base = pci_getl(bus, dev, func, offset); 2468 if (baseclass != PCI_CLASS_BRIDGE) { 2469 command = (uint_t)pci_getw(bus, dev, func, 2470 PCI_CONF_COMM); 2471 pci_putw(bus, dev, func, PCI_CONF_COMM, 2472 command & ~(PCI_COMM_MAE | PCI_COMM_IO)); 2473 } 2474 pci_putl(bus, dev, func, offset, 0xffffffff); 2475 value = pci_getl(bus, dev, func, offset); 2476 pci_putl(bus, dev, func, offset, base); 2477 if (baseclass != PCI_CLASS_BRIDGE) 2478 pci_putw(bus, dev, func, PCI_CONF_COMM, command); 2479 2480 /* construct phys hi,med.lo, size hi, lo */ 2481 if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 2482 int hard_decode = 0; 2483 uint_t len; 2484 2485 /* i/o space */ 2486 bar_sz = PCI_BAR_SZ_32; 2487 value &= PCI_BASE_IO_ADDR_M; 2488 len = ((value ^ (value-1)) + 1) >> 1; 2489 2490 /* XXX Adjust first 4 IDE registers */ 2491 if (pciide) { 2492 if (subclass != PCI_MASS_IDE) 2493 progclass = (PCI_IDE_IF_NATIVE_PRI | 2494 PCI_IDE_IF_NATIVE_SEC); 2495 hard_decode = pciIdeAdjustBAR(progclass, j, 2496 &base, &len); 2497 } else if (value == 0) { 2498 /* skip base regs with size of 0 */ 2499 continue; 2500 } 2501 2502 regs[nreg].pci_phys_hi = PCI_ADDR_IO | devloc | 2503 (hard_decode ? PCI_RELOCAT_B : offset); 2504 regs[nreg].pci_phys_low = hard_decode ? 2505 base & PCI_BASE_IO_ADDR_M : 0; 2506 assigned[nasgn].pci_phys_hi = 2507 PCI_RELOCAT_B | regs[nreg].pci_phys_hi; 2508 regs[nreg].pci_size_low = 2509 assigned[nasgn].pci_size_low = len; 2510 type = base & (~PCI_BASE_IO_ADDR_M); 2511 base &= PCI_BASE_IO_ADDR_M; 2512 /* 2513 * A device under a subtractive PPB can allocate 2514 * resources from its parent bus if there is no resource 2515 * available on its own bus. 2516 */ 2517 if ((config_op == CONFIG_NEW) && (*io_avail == NULL)) { 2518 res_bus = bus; 2519 while (pci_bus_res[res_bus].subtractive) { 2520 res_bus = pci_bus_res[res_bus].par_bus; 2521 if (res_bus == (uchar_t)-1) 2522 break; /* root bus already */ 2523 if (pci_bus_res[res_bus].io_avail) { 2524 io_avail = &pci_bus_res 2525 [res_bus].io_avail; 2526 break; 2527 } 2528 } 2529 } 2530 2531 /* 2532 * first pass - gather what's there 2533 * update/second pass - adjust/allocate regions 2534 * config - allocate regions 2535 */ 2536 if (config_op == CONFIG_INFO) { /* first pass */ 2537 /* take out of the resource map of the bus */ 2538 if (base != 0) { 2539 (void) memlist_remove(io_avail, base, 2540 len); 2541 memlist_insert(io_used, base, len); 2542 } else { 2543 reprogram = 1; 2544 } 2545 pci_bus_res[bus].io_size += len; 2546 } else if ((*io_avail && base == 0) || 2547 pci_bus_res[bus].io_reprogram) { 2548 base = (uint_t)memlist_find(io_avail, len, len); 2549 if (base != 0) { 2550 memlist_insert(io_used, base, len); 2551 /* XXX need to worry about 64-bit? */ 2552 pci_putl(bus, dev, func, offset, 2553 base | type); 2554 base = pci_getl(bus, dev, func, offset); 2555 base &= PCI_BASE_IO_ADDR_M; 2556 } 2557 if (base == 0) { 2558 cmn_err(CE_WARN, "failed to program" 2559 " IO space [%d/%d/%d] BAR@0x%x" 2560 " length 0x%x", 2561 bus, dev, func, offset, len); 2562 } 2563 } 2564 assigned[nasgn].pci_phys_low = base; 2565 nreg++, nasgn++; 2566 2567 } else { 2568 uint64_t len; 2569 /* memory space */ 2570 if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 2571 bar_sz = PCI_BAR_SZ_64; 2572 base_hi = pci_getl(bus, dev, func, offset + 4); 2573 pci_putl(bus, dev, func, offset + 4, 2574 0xffffffff); 2575 value |= (uint64_t)pci_getl(bus, dev, func, 2576 offset + 4) << 32; 2577 pci_putl(bus, dev, func, offset + 4, base_hi); 2578 phys_hi = PCI_ADDR_MEM64; 2579 value &= PCI_BASE_M_ADDR64_M; 2580 } else { 2581 bar_sz = PCI_BAR_SZ_32; 2582 base_hi = 0; 2583 phys_hi = PCI_ADDR_MEM32; 2584 value &= PCI_BASE_M_ADDR_M; 2585 } 2586 2587 /* skip base regs with size of 0 */ 2588 if (value == 0) 2589 continue; 2590 2591 len = ((value ^ (value-1)) + 1) >> 1; 2592 regs[nreg].pci_size_low = 2593 assigned[nasgn].pci_size_low = len & 0xffffffff; 2594 regs[nreg].pci_size_hi = 2595 assigned[nasgn].pci_size_hi = len >> 32; 2596 2597 phys_hi |= (devloc | offset); 2598 if (base & PCI_BASE_PREF_M) 2599 phys_hi |= PCI_PREFETCH_B; 2600 2601 /* 2602 * A device under a subtractive PPB can allocate 2603 * resources from its parent bus if there is no resource 2604 * available on its own bus. 2605 */ 2606 if ((config_op == CONFIG_NEW) && (*mem_avail == NULL)) { 2607 res_bus = bus; 2608 while (pci_bus_res[res_bus].subtractive) { 2609 res_bus = pci_bus_res[res_bus].par_bus; 2610 if (res_bus == (uchar_t)-1) 2611 break; /* root bus already */ 2612 mem_avail = 2613 &pci_bus_res[res_bus].mem_avail; 2614 pmem_avail = 2615 &pci_bus_res [res_bus].pmem_avail; 2616 /* 2617 * Break out as long as at least 2618 * mem_avail is available 2619 */ 2620 if ((*pmem_avail && 2621 (phys_hi & PCI_PREFETCH_B)) || 2622 *mem_avail) 2623 break; 2624 } 2625 } 2626 2627 regs[nreg].pci_phys_hi = 2628 assigned[nasgn].pci_phys_hi = phys_hi; 2629 assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 2630 assigned[nasgn].pci_phys_mid = base_hi; 2631 type = base & ~PCI_BASE_M_ADDR_M; 2632 base &= PCI_BASE_M_ADDR_M; 2633 2634 if (config_op == CONFIG_INFO) { 2635 /* take out of the resource map of the bus */ 2636 if (base != 0) { 2637 /* remove from PMEM and MEM space */ 2638 (void) memlist_remove(mem_avail, 2639 base, len); 2640 (void) memlist_remove(pmem_avail, 2641 base, len); 2642 /* only note as used in correct map */ 2643 if (phys_hi & PCI_PREFETCH_B) 2644 memlist_insert(pmem_used, 2645 base, len); 2646 else 2647 memlist_insert(mem_used, 2648 base, len); 2649 } else { 2650 reprogram = 1; 2651 } 2652 pci_bus_res[bus].mem_size += len; 2653 } else if ((*mem_avail && base == 0) || 2654 pci_bus_res[bus].mem_reprogram) { 2655 /* 2656 * When desired, attempt a prefetchable 2657 * allocation first 2658 */ 2659 if (phys_hi & PCI_PREFETCH_B) { 2660 base = (uint_t)memlist_find(pmem_avail, 2661 len, len); 2662 if (base != 0) { 2663 memlist_insert(pmem_used, 2664 base, len); 2665 (void) memlist_remove(mem_avail, 2666 base, len); 2667 } 2668 } 2669 /* 2670 * If prefetchable allocation was not 2671 * desired, or failed, attempt ordinary 2672 * memory allocation 2673 */ 2674 if (base == 0) { 2675 base = (uint_t)memlist_find(mem_avail, 2676 len, len); 2677 if (base != 0) { 2678 memlist_insert(mem_used, 2679 base, len); 2680 (void) memlist_remove( 2681 pmem_avail, base, len); 2682 } 2683 } 2684 if (base != 0) { 2685 pci_putl(bus, dev, func, offset, 2686 base | type); 2687 base = pci_getl(bus, dev, func, offset); 2688 base &= PCI_BASE_M_ADDR_M; 2689 } else 2690 cmn_err(CE_WARN, "failed to program " 2691 "mem space [%d/%d/%d] BAR@0x%x" 2692 " length 0x%"PRIx64, 2693 bus, dev, func, offset, len); 2694 } 2695 assigned[nasgn].pci_phys_low = base; 2696 nreg++, nasgn++; 2697 } 2698 } 2699 switch (header) { 2700 case PCI_HEADER_ZERO: 2701 offset = PCI_CONF_ROM; 2702 break; 2703 case PCI_HEADER_PPB: 2704 offset = PCI_BCNF_ROM; 2705 break; 2706 default: /* including PCI_HEADER_CARDBUS */ 2707 goto done; 2708 } 2709 2710 /* 2711 * Add the expansion rom memory space 2712 * Determine the size of the ROM base reg; don't write reserved bits 2713 * ROM isn't in the PCI memory space. 2714 */ 2715 base = pci_getl(bus, dev, func, offset); 2716 pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 2717 value = pci_getl(bus, dev, func, offset); 2718 pci_putl(bus, dev, func, offset, base); 2719 if (value & PCI_BASE_ROM_ENABLE) 2720 value &= PCI_BASE_ROM_ADDR_M; 2721 else 2722 value = 0; 2723 2724 if (value != 0) { 2725 uint_t len; 2726 2727 regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 2728 assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 2729 PCI_ADDR_MEM32 | devloc) + offset; 2730 base &= PCI_BASE_ROM_ADDR_M; 2731 assigned[nasgn].pci_phys_low = base; 2732 len = ((value ^ (value-1)) + 1) >> 1; 2733 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 2734 nreg++, nasgn++; 2735 /* take it out of the memory resource */ 2736 if (base != 0) { 2737 (void) memlist_remove(mem_avail, base, len); 2738 memlist_insert(mem_used, base, len); 2739 pci_bus_res[bus].mem_size += len; 2740 } 2741 } 2742 2743 /* 2744 * Account for "legacy" (alias) video adapter resources 2745 */ 2746 2747 /* add the three hard-decode, aliased address spaces for VGA */ 2748 if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 2749 (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 2750 2751 /* VGA hard decode 0x3b0-0x3bb */ 2752 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2753 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2754 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 2755 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 2756 nreg++, nasgn++; 2757 (void) memlist_remove(io_avail, 0x3b0, 0xc); 2758 memlist_insert(io_used, 0x3b0, 0xc); 2759 pci_bus_res[bus].io_size += 0xc; 2760 2761 /* VGA hard decode 0x3c0-0x3df */ 2762 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2763 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2764 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 2765 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 2766 nreg++, nasgn++; 2767 (void) memlist_remove(io_avail, 0x3c0, 0x20); 2768 memlist_insert(io_used, 0x3c0, 0x20); 2769 pci_bus_res[bus].io_size += 0x20; 2770 2771 /* Video memory */ 2772 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2773 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_MEM32 | devloc); 2774 regs[nreg].pci_phys_low = 2775 assigned[nasgn].pci_phys_low = 0xa0000; 2776 regs[nreg].pci_size_low = 2777 assigned[nasgn].pci_size_low = 0x20000; 2778 nreg++, nasgn++; 2779 /* remove from MEM and PMEM space */ 2780 (void) memlist_remove(mem_avail, 0xa0000, 0x20000); 2781 (void) memlist_remove(pmem_avail, 0xa0000, 0x20000); 2782 memlist_insert(mem_used, 0xa0000, 0x20000); 2783 pci_bus_res[bus].mem_size += 0x20000; 2784 } 2785 2786 /* add the hard-decode, aliased address spaces for 8514 */ 2787 if ((baseclass == PCI_CLASS_DISPLAY) && 2788 (subclass == PCI_DISPLAY_VGA) && 2789 (progclass & PCI_DISPLAY_IF_8514)) { 2790 2791 /* hard decode 0x2e8 */ 2792 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2793 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2794 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 2795 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 2796 nreg++, nasgn++; 2797 (void) memlist_remove(io_avail, 0x2e8, 0x1); 2798 memlist_insert(io_used, 0x2e8, 0x1); 2799 pci_bus_res[bus].io_size += 0x1; 2800 2801 /* hard decode 0x2ea-0x2ef */ 2802 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2803 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2804 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 2805 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 2806 nreg++, nasgn++; 2807 (void) memlist_remove(io_avail, 0x2ea, 0x6); 2808 memlist_insert(io_used, 0x2ea, 0x6); 2809 pci_bus_res[bus].io_size += 0x6; 2810 } 2811 2812 done: 2813 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 2814 (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 2815 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 2816 "assigned-addresses", 2817 (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 2818 2819 return (reprogram); 2820 } 2821 2822 static void 2823 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 2824 int pciex, ushort_t is_pci_bridge) 2825 { 2826 char *dev_type; 2827 int i; 2828 uint_t val; 2829 uint64_t io_range[2], mem_range[2], pmem_range[2]; 2830 uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 2831 uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 2832 uchar_t progclass; 2833 2834 ASSERT(secbus <= subbus); 2835 2836 /* 2837 * Check if it's a subtractive PPB. 2838 */ 2839 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 2840 if (progclass == PCI_BRIDGE_PCI_IF_SUBDECODE) 2841 pci_bus_res[secbus].subtractive = B_TRUE; 2842 2843 /* 2844 * Some BIOSes lie about max pci busses, we allow for 2845 * such mistakes here 2846 */ 2847 if (subbus > pci_bios_maxbus) { 2848 pci_bios_maxbus = subbus; 2849 alloc_res_array(); 2850 } 2851 2852 ASSERT(pci_bus_res[secbus].dip == NULL); 2853 pci_bus_res[secbus].dip = dip; 2854 pci_bus_res[secbus].par_bus = bus; 2855 2856 dev_type = (pciex && !is_pci_bridge) ? "pciex" : "pci"; 2857 2858 /* setup bus number hierarchy */ 2859 pci_bus_res[secbus].sub_bus = subbus; 2860 /* 2861 * Keep track of the largest subordinate bus number (this is essential 2862 * for peer busses because there is no other way of determining its 2863 * subordinate bus number). 2864 */ 2865 if (subbus > pci_bus_res[bus].sub_bus) 2866 pci_bus_res[bus].sub_bus = subbus; 2867 /* 2868 * Loop through subordinate busses, initializing their parent bus 2869 * field to this bridge's parent. The subordinate busses' parent 2870 * fields may very well be further refined later, as child bridges 2871 * are enumerated. (The value is to note that the subordinate busses 2872 * are not peer busses by changing their par_bus fields to anything 2873 * other than -1.) 2874 */ 2875 for (i = secbus + 1; i <= subbus; i++) 2876 pci_bus_res[i].par_bus = bus; 2877 2878 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 2879 "device_type", dev_type); 2880 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2881 "#address-cells", 3); 2882 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2883 "#size-cells", 2); 2884 2885 /* 2886 * Collect bridge window specifications, and use them to populate 2887 * the "avail" resources for the bus. Not all of those resources will 2888 * end up being available; this is done top-down, and so the initial 2889 * collection of windows populates the 'ranges' property for the 2890 * bus node. Later, as children are found, resources are removed from 2891 * the 'avail' list, so that it becomes the freelist for 2892 * this point in the tree. ranges may be set again after bridge 2893 * reprogramming in fix_ppb_res(), in which case it's set from 2894 * used + avail. 2895 * 2896 * According to PPB spec, the base register should be programmed 2897 * with a value bigger than the limit register when there are 2898 * no resources available. This applies to io, memory, and 2899 * prefetchable memory. 2900 */ 2901 2902 /* 2903 * io range 2904 * We determine i/o windows that are left unconfigured by BIOS 2905 * through its i/o enable bit as Microsoft recommends OEMs to do. 2906 * If it is unset, we disable i/o and mark it for reconfiguration in 2907 * later passes by setting the base > limit 2908 */ 2909 val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM); 2910 if (val & PCI_COMM_IO) { 2911 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 2912 io_range[0] = ((val & PCI_BCNF_IO_MASK) << PCI_BCNF_IO_SHIFT); 2913 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 2914 io_range[1] = ((val & PCI_BCNF_IO_MASK) << PCI_BCNF_IO_SHIFT) | 2915 0xfff; 2916 if ((io_range[0] & PCI_BCNF_ADDR_MASK) == PCI_BCNF_IO_32BIT) { 2917 uint16_t io_base_hi, io_limit_hi; 2918 io_base_hi = pci_getw(bus, dev, func, 2919 PCI_BCNF_IO_BASE_HI); 2920 io_limit_hi = pci_getw(bus, dev, func, 2921 PCI_BCNF_IO_LIMIT_HI); 2922 2923 io_range[0] |= (uint32_t)io_base_hi << 16; 2924 io_range[1] |= (uint32_t)io_limit_hi << 16; 2925 } 2926 } else { 2927 io_range[0] = 0x9fff; 2928 io_range[1] = 0x1000; 2929 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 2930 (uint8_t)((io_range[0] >> 8) & 0xf0)); 2931 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 2932 (uint8_t)((io_range[1] >> 8) & 0xf0)); 2933 pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 2934 pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 2935 } 2936 2937 if (io_range[0] != 0 && io_range[0] < io_range[1]) { 2938 memlist_insert(&pci_bus_res[secbus].io_avail, 2939 io_range[0], (io_range[1] - io_range[0] + 1)); 2940 memlist_insert(&pci_bus_res[bus].io_used, 2941 io_range[0], (io_range[1] - io_range[0] + 1)); 2942 if (pci_bus_res[bus].io_avail != NULL) { 2943 (void) memlist_remove(&pci_bus_res[bus].io_avail, 2944 io_range[0], (io_range[1] - io_range[0] + 1)); 2945 } 2946 dcmn_err(CE_NOTE, "bus %d io-range: 0x%" PRIx64 "-%" PRIx64, 2947 secbus, io_range[0], io_range[1]); 2948 } 2949 2950 /* mem range */ 2951 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 2952 mem_range[0] = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT); 2953 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 2954 mem_range[1] = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT) | 2955 0xfffff; 2956 if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 2957 memlist_insert(&pci_bus_res[secbus].mem_avail, 2958 (uint64_t)mem_range[0], 2959 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2960 memlist_insert(&pci_bus_res[bus].mem_used, 2961 (uint64_t)mem_range[0], 2962 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2963 /* remove from parent resource list */ 2964 (void) memlist_remove(&pci_bus_res[bus].mem_avail, 2965 (uint64_t)mem_range[0], 2966 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2967 (void) memlist_remove(&pci_bus_res[bus].pmem_avail, 2968 (uint64_t)mem_range[0], 2969 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2970 dcmn_err(CE_NOTE, "bus %d mem-range: 0x%" PRIx64 "-%" PRIx64, 2971 secbus, mem_range[0], mem_range[1]); 2972 } 2973 2974 /* prefetchable memory range */ 2975 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 2976 pmem_range[0] = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT); 2977 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 2978 pmem_range[1] = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT) | 2979 0xfffff; 2980 if ((pmem_range[0] & PCI_BCNF_ADDR_MASK) == PCI_BCNF_PF_MEM_64BIT) { 2981 uint32_t pf_addr_hi, pf_limit_hi; 2982 pf_addr_hi = pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH); 2983 pf_limit_hi = pci_getl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH); 2984 pmem_range[0] |= (uint64_t)pf_addr_hi << 32; 2985 pmem_range[1] |= (uint64_t)pf_limit_hi << 32; 2986 } 2987 if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 2988 memlist_insert(&pci_bus_res[secbus].pmem_avail, 2989 (uint64_t)pmem_range[0], 2990 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2991 memlist_insert(&pci_bus_res[bus].pmem_used, 2992 (uint64_t)pmem_range[0], 2993 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2994 /* remove from parent resource list */ 2995 (void) memlist_remove(&pci_bus_res[bus].pmem_avail, 2996 (uint64_t)pmem_range[0], 2997 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2998 (void) memlist_remove(&pci_bus_res[bus].mem_avail, 2999 (uint64_t)pmem_range[0], 3000 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 3001 dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%" PRIx64 "-%" PRIx64, 3002 secbus, pmem_range[0], pmem_range[1]); 3003 } 3004 3005 /* 3006 * Add VGA legacy resources to the bridge's pci_bus_res if it 3007 * has VGA_ENABLE set. Note that we put them in 'avail', 3008 * because that's used to populate the ranges prop; they'll be 3009 * removed from there by the VGA device once it's found. Also, 3010 * remove them from the parent's available list and note them as 3011 * used in the parent. 3012 */ 3013 3014 if (pci_getw(bus, dev, func, PCI_BCNF_BCNTRL) & 3015 PCI_BCNF_BCNTRL_VGA_ENABLE) { 3016 3017 memlist_insert(&pci_bus_res[secbus].io_avail, 0x3b0, 0xc); 3018 3019 memlist_insert(&pci_bus_res[bus].io_used, 0x3b0, 0xc); 3020 if (pci_bus_res[bus].io_avail != NULL) { 3021 (void) memlist_remove(&pci_bus_res[bus].io_avail, 3022 0x3b0, 0xc); 3023 } 3024 3025 memlist_insert(&pci_bus_res[secbus].io_avail, 0x3c0, 0x20); 3026 3027 memlist_insert(&pci_bus_res[bus].io_used, 0x3c0, 0x20); 3028 if (pci_bus_res[bus].io_avail != NULL) { 3029 (void) memlist_remove(&pci_bus_res[bus].io_avail, 3030 0x3c0, 0x20); 3031 } 3032 3033 memlist_insert(&pci_bus_res[secbus].mem_avail, 0xa0000, 3034 0x20000); 3035 3036 memlist_insert(&pci_bus_res[bus].mem_used, 0xa0000, 0x20000); 3037 if (pci_bus_res[bus].mem_avail != NULL) { 3038 (void) memlist_remove(&pci_bus_res[bus].mem_avail, 3039 0xa0000, 0x20000); 3040 } 3041 } 3042 add_bus_range_prop(secbus); 3043 add_ranges_prop(secbus, 1); 3044 } 3045 3046 extern const struct pci_class_strings_s class_pci[]; 3047 extern int class_pci_items; 3048 3049 static void 3050 add_model_prop(dev_info_t *dip, uint_t classcode) 3051 { 3052 const char *desc; 3053 int i; 3054 uchar_t baseclass = classcode >> 16; 3055 uchar_t subclass = (classcode >> 8) & 0xff; 3056 uchar_t progclass = classcode & 0xff; 3057 3058 if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 3059 desc = "IDE controller"; 3060 } else { 3061 for (desc = 0, i = 0; i < class_pci_items; i++) { 3062 if ((baseclass == class_pci[i].base_class) && 3063 (subclass == class_pci[i].sub_class) && 3064 (progclass == class_pci[i].prog_class)) { 3065 desc = class_pci[i].actual_desc; 3066 break; 3067 } 3068 } 3069 if (i == class_pci_items) 3070 desc = "Unknown class of pci/pnpbios device"; 3071 } 3072 3073 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 3074 (char *)desc); 3075 } 3076 3077 static void 3078 add_bus_range_prop(int bus) 3079 { 3080 int bus_range[2]; 3081 3082 if (pci_bus_res[bus].dip == NULL) 3083 return; 3084 bus_range[0] = bus; 3085 bus_range[1] = pci_bus_res[bus].sub_bus; 3086 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 3087 "bus-range", (int *)bus_range, 2); 3088 } 3089 3090 /* 3091 * Add slot-names property for any named pci hot-plug slots 3092 */ 3093 static void 3094 add_bus_slot_names_prop(int bus) 3095 { 3096 char slotprop[256]; 3097 int len; 3098 extern int pci_irq_nroutes; 3099 char *slotcap_name; 3100 3101 /* 3102 * If no irq routing table, then go with the slot-names as set up 3103 * in pciex_slot_names_prop() from slot capability register (if any). 3104 */ 3105 if (pci_irq_nroutes == 0) 3106 return; 3107 3108 /* 3109 * Otherise delete the slot-names we already have and use the irq 3110 * routing table values as returned by pci_slot_names_prop() instead, 3111 * but keep any property of value "pcie0" as that can't be represented 3112 * in the irq routing table. 3113 */ 3114 if (pci_bus_res[bus].dip != NULL) { 3115 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pci_bus_res[bus].dip, 3116 DDI_PROP_DONTPASS, "slot-names", &slotcap_name) != 3117 DDI_SUCCESS || strcmp(slotcap_name, "pcie0") != 0) 3118 (void) ndi_prop_remove(DDI_DEV_T_NONE, 3119 pci_bus_res[bus].dip, "slot-names"); 3120 } 3121 3122 len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); 3123 if (len > 0) { 3124 /* 3125 * Only create a peer bus node if this bus may be a peer bus. 3126 * It may be a peer bus if the dip is NULL and if par_bus is 3127 * -1 (par_bus is -1 if this bus was not found to be 3128 * subordinate to any PCI-PCI bridge). 3129 * If it's not a peer bus, then the ACPI BBN-handling code 3130 * will remove it later. 3131 */ 3132 if (pci_bus_res[bus].par_bus == (uchar_t)-1 && 3133 pci_bus_res[bus].dip == NULL) { 3134 3135 create_root_bus_dip(bus); 3136 } 3137 if (pci_bus_res[bus].dip != NULL) { 3138 ASSERT((len % sizeof (int)) == 0); 3139 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 3140 pci_bus_res[bus].dip, "slot-names", 3141 (int *)slotprop, len / sizeof (int)); 3142 } else { 3143 cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI " 3144 "IRQ routing table; Not adding slot-names " 3145 "property for incorrect bus %d", bus); 3146 } 3147 } 3148 } 3149 3150 /* 3151 * Handle both PCI root and PCI-PCI bridge range properties; 3152 * non-zero 'ppb' argument select PCI-PCI bridges versus root. 3153 */ 3154 static void 3155 memlist_to_ranges(void **rp, struct memlist *entry, uint_t type, int ppb) 3156 { 3157 ppb_ranges_t *ppb_rp = *rp; 3158 pci_ranges_t *pci_rp = *rp; 3159 3160 while (entry != NULL) { 3161 uint_t atype = type; 3162 if ((type & PCI_REG_ADDR_M) == PCI_ADDR_MEM32 && 3163 (entry->ml_address >= UINT32_MAX || 3164 entry->ml_size >= UINT32_MAX)) { 3165 atype &= ~PCI_ADDR_MEM32; 3166 atype |= PCI_ADDR_MEM64; 3167 } 3168 if (ppb) { 3169 ppb_rp->child_high = ppb_rp->parent_high = atype; 3170 ppb_rp->child_mid = ppb_rp->parent_mid = 3171 (uint32_t)(entry->ml_address >> 32); 3172 ppb_rp->child_low = ppb_rp->parent_low = 3173 (uint32_t)entry->ml_address; 3174 ppb_rp->size_high = 3175 (uint32_t)(entry->ml_size >> 32); 3176 ppb_rp->size_low = (uint32_t)entry->ml_size; 3177 *rp = ++ppb_rp; 3178 } else { 3179 pci_rp->child_high = atype; 3180 pci_rp->child_mid = pci_rp->parent_high = 3181 (uint32_t)(entry->ml_address >> 32); 3182 pci_rp->child_low = pci_rp->parent_low = 3183 (uint32_t)entry->ml_address; 3184 pci_rp->size_high = 3185 (uint32_t)(entry->ml_size >> 32); 3186 pci_rp->size_low = (uint32_t)entry->ml_size; 3187 *rp = ++pci_rp; 3188 } 3189 entry = entry->ml_next; 3190 } 3191 } 3192 3193 static void 3194 add_ranges_prop(int bus, int ppb) 3195 { 3196 int total, alloc_size; 3197 void *rp, *next_rp; 3198 struct memlist *iolist, *memlist, *pmemlist; 3199 3200 /* no devinfo node - unused bus, return */ 3201 if (pci_bus_res[bus].dip == NULL) 3202 return; 3203 3204 iolist = memlist = pmemlist = (struct memlist *)NULL; 3205 3206 memlist_merge(&pci_bus_res[bus].io_avail, &iolist); 3207 memlist_merge(&pci_bus_res[bus].io_used, &iolist); 3208 memlist_merge(&pci_bus_res[bus].mem_avail, &memlist); 3209 memlist_merge(&pci_bus_res[bus].mem_used, &memlist); 3210 memlist_merge(&pci_bus_res[bus].pmem_avail, &pmemlist); 3211 memlist_merge(&pci_bus_res[bus].pmem_used, &pmemlist); 3212 3213 total = memlist_count(iolist); 3214 total += memlist_count(memlist); 3215 total += memlist_count(pmemlist); 3216 3217 /* no property is created if no ranges are present */ 3218 if (total == 0) 3219 return; 3220 3221 alloc_size = total * 3222 (ppb ? sizeof (ppb_ranges_t) : sizeof (pci_ranges_t)); 3223 3224 next_rp = rp = kmem_alloc(alloc_size, KM_SLEEP); 3225 3226 memlist_to_ranges(&next_rp, iolist, PCI_ADDR_IO | PCI_REG_REL_M, ppb); 3227 memlist_to_ranges(&next_rp, memlist, 3228 PCI_ADDR_MEM32 | PCI_REG_REL_M, ppb); 3229 memlist_to_ranges(&next_rp, pmemlist, 3230 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M, ppb); 3231 3232 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 3233 "ranges", (int *)rp, alloc_size / sizeof (int)); 3234 3235 kmem_free(rp, alloc_size); 3236 memlist_free_all(&iolist); 3237 memlist_free_all(&memlist); 3238 memlist_free_all(&pmemlist); 3239 } 3240 3241 static void 3242 memlist_remove_list(struct memlist **list, struct memlist *remove_list) 3243 { 3244 while (list && *list && remove_list) { 3245 (void) memlist_remove(list, remove_list->ml_address, 3246 remove_list->ml_size); 3247 remove_list = remove_list->ml_next; 3248 } 3249 } 3250 3251 static int 3252 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 3253 { 3254 int i = 0; 3255 3256 while (list) { 3257 /* assume 32-bit addresses */ 3258 sp->pci_phys_hi = type; 3259 sp->pci_phys_mid = 0; 3260 sp->pci_phys_low = (uint32_t)list->ml_address; 3261 sp->pci_size_hi = 0; 3262 sp->pci_size_low = (uint32_t)list->ml_size; 3263 3264 list = list->ml_next; 3265 sp++, i++; 3266 } 3267 return (i); 3268 } 3269 3270 static void 3271 add_bus_available_prop(int bus) 3272 { 3273 int i, count; 3274 struct pci_phys_spec *sp; 3275 3276 /* no devinfo node - unused bus, return */ 3277 if (pci_bus_res[bus].dip == NULL) 3278 return; 3279 3280 count = memlist_count(pci_bus_res[bus].io_avail) + 3281 memlist_count(pci_bus_res[bus].mem_avail) + 3282 memlist_count(pci_bus_res[bus].pmem_avail); 3283 3284 if (count == 0) /* nothing available */ 3285 return; 3286 3287 sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 3288 i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_avail, 3289 PCI_ADDR_IO | PCI_REG_REL_M); 3290 i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_avail, 3291 PCI_ADDR_MEM32 | PCI_REG_REL_M); 3292 i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_avail, 3293 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 3294 ASSERT(i == count); 3295 3296 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 3297 "available", (int *)sp, 3298 i * sizeof (struct pci_phys_spec) / sizeof (int)); 3299 kmem_free(sp, count * sizeof (*sp)); 3300 } 3301 3302 static void 3303 alloc_res_array(void) 3304 { 3305 static int array_size = 0; 3306 int old_size; 3307 void *old_res; 3308 3309 if (array_size > pci_bios_maxbus + 1) 3310 return; /* array is big enough */ 3311 3312 old_size = array_size; 3313 old_res = pci_bus_res; 3314 3315 if (array_size == 0) 3316 array_size = 16; /* start with a reasonable number */ 3317 3318 while (array_size <= pci_bios_maxbus + 1) 3319 array_size <<= 1; 3320 pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 3321 array_size * sizeof (struct pci_bus_resource), KM_SLEEP); 3322 3323 if (old_res) { /* copy content and free old array */ 3324 bcopy(old_res, pci_bus_res, 3325 old_size * sizeof (struct pci_bus_resource)); 3326 kmem_free(old_res, old_size * sizeof (struct pci_bus_resource)); 3327 } 3328 } 3329 3330 static void 3331 create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 3332 ushort_t deviceid) 3333 { 3334 static dev_info_t *ioapicsnode = NULL; 3335 static int numioapics = 0; 3336 dev_info_t *ioapic_node; 3337 uint64_t physaddr; 3338 uint32_t lobase, hibase = 0; 3339 3340 /* BAR 0 contains the IOAPIC's memory-mapped I/O address */ 3341 lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0); 3342 3343 /* We (and the rest of the world) only support memory-mapped IOAPICs */ 3344 if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM) 3345 return; 3346 3347 if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) 3348 hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4); 3349 3350 lobase &= PCI_BASE_M_ADDR_M; 3351 3352 physaddr = (((uint64_t)hibase) << 32) | lobase; 3353 3354 /* 3355 * Create a nexus node for all IOAPICs under the root node. 3356 */ 3357 if (ioapicsnode == NULL) { 3358 if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME, 3359 (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) { 3360 return; 3361 } 3362 (void) ndi_devi_online(ioapicsnode, 0); 3363 } 3364 3365 /* 3366 * Create a child node for this IOAPIC 3367 */ 3368 ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME, 3369 DEVI_SID_NODEID, numioapics++); 3370 if (ioapic_node == NULL) { 3371 return; 3372 } 3373 3374 /* Vendor and Device ID */ 3375 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 3376 IOAPICS_PROP_VENID, vendorid); 3377 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 3378 IOAPICS_PROP_DEVID, deviceid); 3379 3380 /* device_type */ 3381 (void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node, 3382 "device_type", IOAPICS_DEV_TYPE); 3383 3384 /* reg */ 3385 (void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node, 3386 "reg", physaddr); 3387 } 3388 3389 /* 3390 * NOTE: For PCIe slots, the name is generated from the slot number 3391 * information obtained from Slot Capabilities register. 3392 * For non-PCIe slots, it is generated based on the slot number 3393 * information in the PCI IRQ table. 3394 */ 3395 static void 3396 pciex_slot_names_prop(dev_info_t *dip, ushort_t slot_num) 3397 { 3398 char slotprop[256]; 3399 int len; 3400 3401 bzero(slotprop, sizeof (slotprop)); 3402 3403 /* set mask to 1 as there is only one slot (i.e dev 0) */ 3404 *(uint32_t *)slotprop = 1; 3405 len = 4; 3406 (void) snprintf(slotprop + len, sizeof (slotprop) - len, "pcie%d", 3407 slot_num); 3408 len += strlen(slotprop + len) + 1; 3409 len += len % 4; 3410 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "slot-names", 3411 (int *)slotprop, len / sizeof (int)); 3412 } 3413 3414 /* 3415 * Enable reporting of AER capability next pointer. 3416 * This needs to be done only for CK8-04 devices 3417 * by setting NV_XVR_VEND_CYA1 (offset 0xf40) bit 13 3418 * NOTE: BIOS is disabling this, it needs to be enabled temporarily 3419 * 3420 * This function is adapted from npe_ck804_fix_aer_ptr(), and is 3421 * called from pci_boot.c. 3422 */ 3423 static void 3424 ck804_fix_aer_ptr(dev_info_t *dip, pcie_req_id_t bdf) 3425 { 3426 dev_info_t *rcdip; 3427 ushort_t cya1; 3428 3429 rcdip = pcie_get_rc_dip(dip); 3430 ASSERT(rcdip != NULL); 3431 3432 if ((pci_cfgacc_get16(rcdip, bdf, PCI_CONF_VENID) == 3433 NVIDIA_VENDOR_ID) && 3434 (pci_cfgacc_get16(rcdip, bdf, PCI_CONF_DEVID) == 3435 NVIDIA_CK804_DEVICE_ID) && 3436 (pci_cfgacc_get8(rcdip, bdf, PCI_CONF_REVID) >= 3437 NVIDIA_CK804_AER_VALID_REVID)) { 3438 cya1 = pci_cfgacc_get16(rcdip, bdf, NVIDIA_CK804_VEND_CYA1_OFF); 3439 if (!(cya1 & ~NVIDIA_CK804_VEND_CYA1_ERPT_MASK)) 3440 (void) pci_cfgacc_put16(rcdip, bdf, 3441 NVIDIA_CK804_VEND_CYA1_OFF, 3442 cya1 | NVIDIA_CK804_VEND_CYA1_ERPT_VAL); 3443 } 3444 } 3445