1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/types.h> 27 #include <sys/stat.h> 28 #include <sys/sysmacros.h> 29 #include <sys/sunndi.h> 30 #include <sys/pci.h> 31 #include <sys/pci_impl.h> 32 #include <sys/pci_cfgspace.h> 33 #include <sys/memlist.h> 34 #include <sys/bootconf.h> 35 #include <io/pci/mps_table.h> 36 #include <sys/pci_cfgspace.h> 37 #include <sys/pci_cfgspace_impl.h> 38 #include <sys/psw.h> 39 #include "../../../../common/pci/pci_strings.h" 40 #include <sys/apic.h> 41 #include <io/pciex/pcie_nvidia.h> 42 #include <io/hotplug/pciehpc/pciehpc_acpi.h> 43 #include <sys/acpi/acpi.h> 44 #include <sys/acpica.h> 45 #include <sys/intel_iommu.h> 46 #include <sys/iommulib.h> 47 48 #define pci_getb (*pci_getb_func) 49 #define pci_getw (*pci_getw_func) 50 #define pci_getl (*pci_getl_func) 51 #define pci_putb (*pci_putb_func) 52 #define pci_putw (*pci_putw_func) 53 #define pci_putl (*pci_putl_func) 54 #define dcmn_err if (pci_boot_debug) cmn_err 55 56 #define CONFIG_INFO 0 57 #define CONFIG_UPDATE 1 58 #define CONFIG_NEW 2 59 #define CONFIG_FIX 3 60 #define COMPAT_BUFSIZE 512 61 62 #define PPB_IO_ALIGNMENT 0x1000 /* 4K aligned */ 63 #define PPB_MEM_ALIGNMENT 0x100000 /* 1M aligned */ 64 /* round down to nearest power of two */ 65 #define P2LE(align) \ 66 { \ 67 int i = 0; \ 68 while (align >>= 1) \ 69 i ++; \ 70 align = 1 << i; \ 71 } \ 72 73 /* See AMD-8111 Datasheet Rev 3.03, Page 149: */ 74 #define LPC_IO_CONTROL_REG_1 0x40 75 #define AMD8111_ENABLENMI (uint8_t)0x80 76 #define DEVID_AMD8111_LPC 0x7468 77 78 struct pci_fixundo { 79 uint8_t bus; 80 uint8_t dev; 81 uint8_t fn; 82 void (*undofn)(uint8_t, uint8_t, uint8_t); 83 struct pci_fixundo *next; 84 }; 85 86 struct pci_devfunc { 87 struct pci_devfunc *next; 88 dev_info_t *dip; 89 uchar_t dev; 90 uchar_t func; 91 boolean_t reprogram; /* this device needs to be reprogrammed */ 92 }; 93 94 extern int pseudo_isa; 95 extern int pci_bios_nbus; 96 static uchar_t max_dev_pci = 32; /* PCI standard */ 97 int pci_boot_debug = 0; 98 extern struct memlist *find_bus_res(int, int); 99 static struct pci_fixundo *undolist = NULL; 100 static int num_root_bus = 0; /* count of root buses */ 101 extern volatile int acpi_resource_discovery; 102 103 /* 104 * Module prototypes 105 */ 106 static void enumerate_bus_devs(uchar_t bus, int config_op); 107 static void create_root_bus_dip(uchar_t bus); 108 static void process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t, 109 ushort_t, int); 110 static void add_compatible(dev_info_t *, ushort_t, ushort_t, 111 ushort_t, ushort_t, uchar_t, uint_t, int); 112 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 113 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, 114 ushort_t); 115 static void add_model_prop(dev_info_t *, uint_t); 116 static void add_bus_range_prop(int); 117 static void add_bus_slot_names_prop(int); 118 static void add_ranges_prop(int, int); 119 static void add_bus_available_prop(int); 120 static int get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id); 121 static void fix_ppb_res(uchar_t, boolean_t); 122 static void alloc_res_array(); 123 static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 124 ushort_t deviceid); 125 static void pciex_slot_names_prop(dev_info_t *, ushort_t); 126 static void populate_bus_res(uchar_t bus); 127 static void memlist_remove_list(struct memlist **list, 128 struct memlist *remove_list); 129 130 extern int pci_slot_names_prop(int, char *, int); 131 132 /* set non-zero to force PCI peer-bus renumbering */ 133 int pci_bus_always_renumber = 0; 134 135 /* 136 * used to register ISA resource usage which must not be made 137 * "available" from other PCI node' resource maps 138 */ 139 static struct { 140 struct memlist *io_ports_used; 141 struct memlist *mem_space_used; 142 } isa_res; 143 144 /* 145 * Enumerate all PCI devices 146 */ 147 void 148 pci_setup_tree() 149 { 150 uint_t i, root_bus_addr = 0; 151 152 alloc_res_array(); 153 for (i = 0; i <= pci_bios_nbus; i++) { 154 pci_bus_res[i].par_bus = (uchar_t)-1; 155 pci_bus_res[i].root_addr = (uchar_t)-1; 156 pci_bus_res[i].sub_bus = i; 157 } 158 159 pci_bus_res[0].root_addr = root_bus_addr++; 160 create_root_bus_dip(0); 161 enumerate_bus_devs(0, CONFIG_INFO); 162 163 /* 164 * Now enumerate peer busses 165 * 166 * We loop till pci_bios_nbus. On most systems, there is 167 * one more bus at the high end, which implements the ISA 168 * compatibility bus. We don't care about that. 169 * 170 * Note: In the old (bootconf) enumeration, the peer bus 171 * address did not use the bus number, and there were 172 * too many peer busses created. The root_bus_addr is 173 * used to maintain the old peer bus address assignment. 174 * However, we stop enumerating phantom peers with no 175 * device below. 176 */ 177 for (i = 1; i <= pci_bios_nbus; i++) { 178 if (pci_bus_res[i].dip == NULL) { 179 pci_bus_res[i].root_addr = root_bus_addr++; 180 } 181 enumerate_bus_devs(i, CONFIG_INFO); 182 183 /* add slot-names property for named pci hot-plug slots */ 184 add_bus_slot_names_prop(i); 185 } 186 187 } 188 189 /* 190 * >0 = present, 0 = not present, <0 = error 191 */ 192 static int 193 pci_bbn_present(int bus) 194 { 195 ACPI_HANDLE hdl; 196 int rv; 197 198 /* no dip means no _BBN */ 199 if (pci_bus_res[bus].dip == NULL) 200 return (0); 201 202 rv = -1; /* default return value in case of error below */ 203 if (ACPI_SUCCESS(acpica_get_handle(pci_bus_res[bus].dip, &hdl))) { 204 switch (AcpiEvaluateObject(hdl, "_BBN", NULL, NULL)) { 205 case AE_OK: 206 rv = 1; 207 break; 208 case AE_NOT_FOUND: 209 rv = 0; 210 break; 211 default: 212 break; 213 } 214 } 215 216 return (rv); 217 } 218 219 /* 220 * Return non-zero if any PCI bus in the system has an associated 221 * _BBN object, 0 otherwise. 222 */ 223 static int 224 pci_roots_have_bbn(void) 225 { 226 int i; 227 228 /* 229 * Scan the PCI busses and look for at least 1 _BBN 230 */ 231 for (i = 0; i <= pci_bios_nbus; i++) { 232 /* skip non-root (peer) PCI busses */ 233 if (pci_bus_res[i].par_bus != (uchar_t)-1) 234 continue; 235 236 if (pci_bbn_present(i) > 0) 237 return (1); 238 } 239 return (0); 240 241 } 242 243 /* 244 * return non-zero if the machine is one on which we renumber 245 * the internal pci unit-addresses 246 */ 247 static int 248 pci_bus_renumber() 249 { 250 ACPI_TABLE_HEADER *fadt; 251 252 if (pci_bus_always_renumber) 253 return (1); 254 255 /* get the FADT */ 256 if (AcpiGetTable(ACPI_SIG_FADT, 1, (ACPI_TABLE_HEADER **)&fadt) != 257 AE_OK) 258 return (0); 259 260 /* compare OEM Table ID to "SUNm31" */ 261 if (strncmp("SUNm31", fadt->OemId, 6)) 262 return (0); 263 else 264 return (1); 265 } 266 267 /* 268 * Initial enumeration of the physical PCI bus hierarchy can 269 * leave 'gaps' in the order of peer PCI bus unit-addresses. 270 * Systems with more than one peer PCI bus *must* have an ACPI 271 * _BBN object associated with each peer bus; use the presence 272 * of this object to remove gaps in the numbering of the peer 273 * PCI bus unit-addresses - only peer busses with an associated 274 * _BBN are counted. 275 */ 276 static void 277 pci_renumber_root_busses(void) 278 { 279 int pci_regs[] = {0, 0, 0}; 280 int i, root_addr = 0; 281 282 /* 283 * Currently, we only enable the re-numbering on specific 284 * Sun machines; this is a work-around for the more complicated 285 * issue of upgrade changing physical device paths 286 */ 287 if (!pci_bus_renumber()) 288 return; 289 290 /* 291 * If we find no _BBN objects at all, we either don't need 292 * to do anything or can't do anything anyway 293 */ 294 if (!pci_roots_have_bbn()) 295 return; 296 297 for (i = 0; i <= pci_bios_nbus; i++) { 298 /* skip non-root (peer) PCI busses */ 299 if (pci_bus_res[i].par_bus != (uchar_t)-1) 300 continue; 301 302 if (pci_bbn_present(i) < 1) { 303 pci_bus_res[i].root_addr = (uchar_t)-1; 304 continue; 305 } 306 307 ASSERT(pci_bus_res[i].dip != NULL); 308 if (pci_bus_res[i].root_addr != root_addr) { 309 /* update reg property for node */ 310 pci_bus_res[i].root_addr = root_addr; 311 pci_regs[0] = pci_bus_res[i].root_addr; 312 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 313 pci_bus_res[i].dip, "reg", (int *)pci_regs, 3); 314 } 315 root_addr++; 316 } 317 } 318 319 void 320 pci_register_isa_resources(int type, uint32_t base, uint32_t size) 321 { 322 (void) memlist_insert( 323 (type == 1) ? &isa_res.io_ports_used : &isa_res.mem_space_used, 324 base, size); 325 } 326 327 /* 328 * Remove the resources which are already used by devices under a subtractive 329 * bridge from the bus's resources lists, because they're not available, and 330 * shouldn't be allocated to other buses. This is necessary because tracking 331 * resources for subtractive bridges is not complete. (Subtractive bridges only 332 * track some of their claimed resources, not "the rest of the address space" as 333 * they should, so that allocation to peer non-subtractive PPBs is easier. We 334 * need a fully-capable global resource allocator). 335 */ 336 static void 337 remove_subtractive_res() 338 { 339 int i, j; 340 struct memlist *list; 341 342 for (i = 0; i <= pci_bios_nbus; i++) { 343 if (pci_bus_res[i].subtractive) { 344 /* remove used io ports */ 345 list = pci_bus_res[i].io_ports_used; 346 while (list) { 347 for (j = 0; j <= pci_bios_nbus; j++) 348 (void) memlist_remove( 349 &pci_bus_res[j].io_ports, 350 list->address, list->size); 351 list = list->next; 352 } 353 /* remove used mem resource */ 354 list = pci_bus_res[i].mem_space_used; 355 while (list) { 356 for (j = 0; j <= pci_bios_nbus; j++) { 357 (void) memlist_remove( 358 &pci_bus_res[j].mem_space, 359 list->address, list->size); 360 (void) memlist_remove( 361 &pci_bus_res[j].pmem_space, 362 list->address, list->size); 363 } 364 list = list->next; 365 } 366 /* remove used prefetchable mem resource */ 367 list = pci_bus_res[i].pmem_space_used; 368 while (list) { 369 for (j = 0; j <= pci_bios_nbus; j++) { 370 (void) memlist_remove( 371 &pci_bus_res[j].pmem_space, 372 list->address, list->size); 373 (void) memlist_remove( 374 &pci_bus_res[j].mem_space, 375 list->address, list->size); 376 } 377 list = list->next; 378 } 379 } 380 } 381 } 382 383 /* 384 * Set-up (or complete the set-up) of the bus_space resource list 385 */ 386 static void 387 setup_bus_res(int bus) 388 { 389 uchar_t par_bus; 390 391 if (pci_bus_res[bus].dip == NULL) /* unused bus */ 392 return; 393 394 /* 395 * Setup bus_space if not already filled-in by populate_bus_res(); 396 */ 397 if (pci_bus_res[bus].bus_space == NULL) { 398 ASSERT(pci_bus_res[bus].sub_bus >= bus); 399 memlist_insert(&pci_bus_res[bus].bus_space, bus, 400 pci_bus_res[bus].sub_bus - bus + 1); 401 } 402 403 ASSERT(pci_bus_res[bus].bus_space != NULL); 404 405 /* 406 * Remove resources from parent bus node if this is not a 407 * root bus. 408 */ 409 par_bus = pci_bus_res[bus].par_bus; 410 if (par_bus != (uchar_t)-1) { 411 ASSERT(pci_bus_res[par_bus].bus_space != NULL); 412 memlist_remove_list(&pci_bus_res[par_bus].bus_space, 413 pci_bus_res[bus].bus_space); 414 } 415 416 /* remove self from bus_space */; 417 (void) memlist_remove(&pci_bus_res[bus].bus_space, bus, 1); 418 } 419 420 static uint64_t 421 get_parbus_io_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 422 { 423 uint64_t addr = 0; 424 uchar_t res_bus; 425 426 /* 427 * Skip root(peer) buses in multiple-root-bus systems when 428 * ACPI resource discovery was not successfully done. 429 */ 430 if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 431 (num_root_bus > 1) && (acpi_resource_discovery <= 0)) 432 return (0); 433 434 res_bus = parbus; 435 while (pci_bus_res[res_bus].subtractive) { 436 if (pci_bus_res[res_bus].io_ports) 437 break; 438 res_bus = pci_bus_res[res_bus].par_bus; 439 if (res_bus == (uchar_t)-1) 440 break; /* root bus already */ 441 } 442 443 if (pci_bus_res[res_bus].io_ports) { 444 addr = memlist_find(&pci_bus_res[res_bus].io_ports, 445 size, align); 446 if (addr) { 447 memlist_insert(&pci_bus_res[res_bus].io_ports_used, 448 addr, size); 449 450 /* free the old resource */ 451 memlist_free_all(&pci_bus_res[bus].io_ports); 452 memlist_free_all(&pci_bus_res[bus].io_ports_used); 453 454 /* add the new resource */ 455 memlist_insert(&pci_bus_res[bus].io_ports, addr, size); 456 } 457 } 458 459 return (addr); 460 } 461 462 static uint64_t 463 get_parbus_mem_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 464 { 465 uint64_t addr = 0; 466 uchar_t res_bus; 467 468 /* 469 * Skip root(peer) buses in multiple-root-bus systems when 470 * ACPI resource discovery was not successfully done. 471 */ 472 if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 473 (num_root_bus > 1) && (acpi_resource_discovery <= 0)) 474 return (0); 475 476 res_bus = parbus; 477 while (pci_bus_res[res_bus].subtractive) { 478 if (pci_bus_res[res_bus].mem_space) 479 break; 480 res_bus = pci_bus_res[res_bus].par_bus; 481 if (res_bus == (uchar_t)-1) 482 break; /* root bus already */ 483 } 484 485 if (pci_bus_res[res_bus].mem_space) { 486 addr = memlist_find(&pci_bus_res[res_bus].mem_space, 487 size, align); 488 if (addr) { 489 memlist_insert(&pci_bus_res[res_bus].mem_space_used, 490 addr, size); 491 (void) memlist_remove(&pci_bus_res[res_bus].pmem_space, 492 addr, size); 493 494 /* free the old resource */ 495 memlist_free_all(&pci_bus_res[bus].mem_space); 496 memlist_free_all(&pci_bus_res[bus].mem_space_used); 497 498 /* add the new resource */ 499 memlist_insert(&pci_bus_res[bus].mem_space, addr, size); 500 } 501 } 502 503 return (addr); 504 } 505 506 /* 507 * given a cap_id, return its cap_id location in config space 508 */ 509 static int 510 get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id) 511 { 512 uint8_t curcap, cap_id_loc; 513 uint16_t status; 514 int location = -1; 515 516 /* 517 * Need to check the Status register for ECP support first. 518 * Also please note that for type 1 devices, the 519 * offset could change. Should support type 1 next. 520 */ 521 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 522 if (!(status & PCI_STAT_CAP)) { 523 return (-1); 524 } 525 cap_id_loc = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 526 527 /* Walk the list of capabilities */ 528 while (cap_id_loc && cap_id_loc != (uint8_t)-1) { 529 curcap = pci_getb(bus, dev, func, cap_id_loc); 530 531 if (curcap == cap_id) { 532 location = cap_id_loc; 533 break; 534 } 535 cap_id_loc = pci_getb(bus, dev, func, cap_id_loc + 1); 536 } 537 return (location); 538 } 539 540 /* 541 * Assign valid resources to unconfigured pci(e) bridges. We are trying 542 * to reprogram the bridge when its 543 * i) SECBUS == SUBBUS || 544 * ii) IOBASE > IOLIM || 545 * iii) MEMBASE > MEMLIM 546 * This must be done after one full pass through the PCI tree to collect 547 * all BIOS-configured resources, so that we know what resources are 548 * free and available to assign to the unconfigured PPBs. 549 */ 550 static void 551 fix_ppb_res(uchar_t secbus, boolean_t prog_sub) 552 { 553 uchar_t bus, dev, func; 554 uchar_t parbus, subbus; 555 uint_t io_base, io_limit, mem_base, mem_limit; 556 uint_t io_size, mem_size, io_align, mem_align; 557 uint64_t addr = 0; 558 int *regp = NULL; 559 uint_t reglen; 560 int rv, cap_ptr, physhi; 561 dev_info_t *dip; 562 uint16_t cmd_reg; 563 struct memlist *list; 564 565 /* skip root (peer) PCI busses */ 566 if (pci_bus_res[secbus].par_bus == (uchar_t)-1) 567 return; 568 569 /* skip subtractive PPB when prog_sub is not TRUE */ 570 if (pci_bus_res[secbus].subtractive && !prog_sub) 571 return; 572 573 /* some entries may be empty due to discontiguous bus numbering */ 574 dip = pci_bus_res[secbus].dip; 575 if (dip == NULL) 576 return; 577 578 rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 579 "reg", ®p, ®len); 580 ASSERT(rv == DDI_PROP_SUCCESS && reglen > 0); 581 physhi = regp[0]; 582 ddi_prop_free(regp); 583 584 func = (uchar_t)PCI_REG_FUNC_G(physhi); 585 dev = (uchar_t)PCI_REG_DEV_G(physhi); 586 bus = (uchar_t)PCI_REG_BUS_G(physhi); 587 588 /* 589 * If pcie bridge, check to see if link is enabled 590 */ 591 cap_ptr = get_pci_cap(bus, dev, func, PCI_CAP_ID_PCI_E); 592 if (cap_ptr != -1) { 593 cmd_reg = pci_getw(bus, dev, func, 594 (uint16_t)cap_ptr + PCIE_LINKCTL); 595 if (cmd_reg & PCIE_LINKCTL_LINK_DISABLE) { 596 dcmn_err(CE_NOTE, 597 "!fix_ppb_res: ppb[%x/%x/%x] link is disabled.\n", 598 bus, dev, func); 599 return; 600 } 601 } 602 603 subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 604 parbus = pci_bus_res[secbus].par_bus; 605 ASSERT(parbus == bus); 606 cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 607 608 /* 609 * If we have a Cardbus bridge, but no bus space 610 */ 611 if (pci_bus_res[secbus].num_cbb != 0 && 612 pci_bus_res[secbus].bus_space == NULL) { 613 uchar_t range; 614 615 /* normally there are 2 buses under a cardbus bridge */ 616 range = pci_bus_res[secbus].num_cbb * 2; 617 618 /* 619 * Try to find and allocate a bus-range starting at subbus+1 620 * from the parent of the PPB. 621 */ 622 for (; range != 0; range--) { 623 if (memlist_find_with_startaddr( 624 &pci_bus_res[parbus].bus_space, 625 subbus + 1, range, 1) != NULL) 626 break; /* find bus range resource at parent */ 627 } 628 if (range != 0) { 629 memlist_insert(&pci_bus_res[secbus].bus_space, 630 subbus + 1, range); 631 subbus = subbus + range; 632 pci_bus_res[secbus].sub_bus = subbus; 633 pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus); 634 add_bus_range_prop(secbus); 635 636 cmn_err(CE_NOTE, "!reprogram bus-range on ppb" 637 "[%x/%x/%x]: %x ~ %x\n", bus, dev, func, 638 secbus, subbus); 639 } 640 } 641 642 /* 643 * Calculate required IO size and alignment 644 * If bus io_size is zero, we are going to assign 512 bytes per bus, 645 * otherwise, we'll choose the maximum value of such calculation and 646 * bus io_size. The size needs to be 4K aligned. 647 * 648 * We calculate alignment as the largest power of two less than the 649 * the sum of all children's IO size requirements, because this will 650 * align to the size of the largest child request within that size 651 * (which is always a power of two). 652 */ 653 io_size = (subbus - secbus + 1) * 0x200; 654 if (io_size < pci_bus_res[secbus].io_size) 655 io_size = pci_bus_res[secbus].io_size; 656 io_size = P2ROUNDUP(io_size, PPB_IO_ALIGNMENT); 657 io_align = io_size; 658 P2LE(io_align); 659 660 /* 661 * Calculate required MEM size and alignment 662 * If bus mem_size is zero, we are going to assign 1M bytes per bus, 663 * otherwise, we'll choose the maximum value of such calculation and 664 * bus mem_size. The size needs to be 1M aligned. 665 * 666 * For the alignment, refer to the I/O comment above. 667 */ 668 mem_size = (subbus - secbus + 1) * PPB_MEM_ALIGNMENT; 669 if (mem_size < pci_bus_res[secbus].mem_size) { 670 mem_size = pci_bus_res[secbus].mem_size; 671 mem_size = P2ROUNDUP(mem_size, PPB_MEM_ALIGNMENT); 672 } 673 mem_align = mem_size; 674 P2LE(mem_align); 675 676 /* Subtractive bridge */ 677 if (pci_bus_res[secbus].subtractive && prog_sub) { 678 /* 679 * We program an arbitrary amount of I/O and memory resource 680 * for the subtractive bridge so that child dynamic-resource- 681 * allocating devices (such as Cardbus bridges) have a chance 682 * of success. Until we have full-tree resource rebalancing, 683 * dynamic resource allocation (thru busra) only looks at the 684 * parent bridge, so all PPBs must have some allocatable 685 * resource. For non-subtractive bridges, the resources come 686 * from the base/limit register "windows", but subtractive 687 * bridges often don't program those (since they don't need to). 688 * If we put all the remaining resources on the subtractive 689 * bridge, then peer non-subtractive bridges can't allocate 690 * more space (even though this is probably most correct). 691 * If we put the resources only on the parent, then allocations 692 * from children of subtractive bridges will fail without 693 * special-case code for bypassing the subtractive bridge. 694 * This solution is the middle-ground temporary solution until 695 * we have fully-capable resource allocation. 696 */ 697 698 /* 699 * Add an arbitrary I/O resource to the subtractive PPB 700 */ 701 if (pci_bus_res[secbus].io_ports == NULL) { 702 addr = get_parbus_io_res(parbus, secbus, io_size, 703 io_align); 704 if (addr) { 705 add_ranges_prop(secbus, 1); 706 pci_bus_res[secbus].io_reprogram = 707 pci_bus_res[parbus].io_reprogram; 708 709 cmn_err(CE_NOTE, "!add io-range on subtractive" 710 " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 711 bus, dev, func, (uint32_t)addr, 712 (uint32_t)addr + io_size - 1); 713 } 714 } 715 /* 716 * Add an arbitrary memory resource to the subtractive PPB 717 */ 718 if (pci_bus_res[secbus].mem_space == NULL) { 719 addr = get_parbus_mem_res(parbus, secbus, mem_size, 720 mem_align); 721 if (addr) { 722 add_ranges_prop(secbus, 1); 723 pci_bus_res[secbus].mem_reprogram = 724 pci_bus_res[parbus].mem_reprogram; 725 726 cmn_err(CE_NOTE, "!add mem-range on " 727 "subtractive ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 728 bus, dev, func, (uint32_t)addr, 729 (uint32_t)addr + mem_size - 1); 730 } 731 } 732 733 goto cmd_enable; 734 } 735 736 /* 737 * Check to see if we need to reprogram I/O space, either because the 738 * parent bus needed reprogramming and so do we, or because I/O space is 739 * disabled in base/limit or command register. 740 */ 741 io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 742 io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 743 io_base = (io_base & 0xf0) << 8; 744 io_limit = ((io_limit & 0xf0) << 8) | 0xfff; 745 746 if (pci_bus_res[parbus].io_reprogram || (io_base > io_limit) || 747 (!(cmd_reg & PCI_COMM_IO))) { 748 if (pci_bus_res[secbus].io_ports_used) { 749 memlist_merge(&pci_bus_res[secbus].io_ports_used, 750 &pci_bus_res[secbus].io_ports); 751 } 752 if (pci_bus_res[secbus].io_ports && 753 (!pci_bus_res[parbus].io_reprogram) && 754 (!pci_bus_res[parbus].subtractive)) { 755 /* rechoose old io ports info */ 756 list = pci_bus_res[secbus].io_ports; 757 io_base = (uint_t)list->address; 758 /* 4K aligned */ 759 io_base = io_base & (~(PPB_IO_ALIGNMENT - 1)); 760 io_limit = (uint_t)(list->address + list->size); 761 while (list->next) { 762 list = list->next; 763 if ((list->address + list->size) > io_limit) 764 io_limit = (uint_t) 765 (list->address + list->size); 766 } 767 io_limit = io_limit - 1; 768 /* 4K aligned */ 769 io_limit = (io_limit + PPB_IO_ALIGNMENT) & 770 (~(PPB_IO_ALIGNMENT - 1)); 771 io_size = io_limit - io_base; 772 io_limit = io_limit - 1; 773 ASSERT(io_base <= io_limit); 774 memlist_free_all(&pci_bus_res[secbus].io_ports); 775 memlist_insert(&pci_bus_res[secbus].io_ports, 776 io_base, io_size); 777 memlist_insert(&pci_bus_res[parbus].io_ports_used, 778 io_base, io_size); 779 (void) memlist_remove(&pci_bus_res[parbus].io_ports, 780 io_base, io_size); 781 pci_bus_res[secbus].io_reprogram = B_TRUE; 782 } else { 783 /* get new io ports from parent bus */ 784 addr = get_parbus_io_res(parbus, secbus, io_size, 785 io_align); 786 if (addr) { 787 io_base = addr; 788 io_limit = addr + io_size - 1; 789 pci_bus_res[secbus].io_reprogram = B_TRUE; 790 } 791 } 792 if (pci_bus_res[secbus].io_reprogram) { 793 /* reprogram PPB regs */ 794 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 795 (uchar_t)((io_base>>8) & 0xf0)); 796 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 797 (uchar_t)((io_limit>>8) & 0xf0)); 798 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 799 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 800 add_ranges_prop(secbus, 1); 801 802 cmn_err(CE_NOTE, "!reprogram io-range on" 803 " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 804 bus, dev, func, io_base, io_limit); 805 } 806 } 807 808 /* 809 * Check memory space as we did I/O space. 810 */ 811 mem_base = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 812 mem_base = (mem_base & 0xfff0) << 16; 813 mem_limit = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 814 mem_limit = ((mem_limit & 0xfff0) << 16) | 0xfffff; 815 816 if (pci_bus_res[parbus].mem_reprogram || (mem_base > mem_limit) || 817 (!(cmd_reg & PCI_COMM_MAE))) { 818 if (pci_bus_res[secbus].mem_space_used) { 819 memlist_merge(&pci_bus_res[secbus].mem_space_used, 820 &pci_bus_res[secbus].mem_space); 821 } 822 if (pci_bus_res[secbus].mem_space && 823 (!pci_bus_res[parbus].mem_reprogram) && 824 (!pci_bus_res[parbus].subtractive)) { 825 /* rechoose old mem resource */ 826 list = pci_bus_res[secbus].mem_space; 827 mem_base = (uint_t)list->address; 828 /* 1M aligned */ 829 mem_base = mem_base & (~0xfffff); 830 mem_limit = (uint_t)(list->address + list->size); 831 while (list->next) { 832 list = list->next; 833 if ((list->address + list->size) > mem_limit) 834 mem_limit = (uint_t) 835 (list->address + list->size); 836 } 837 mem_limit = mem_limit - 1; 838 /* 1M aligned */ 839 mem_limit = (mem_limit + PPB_MEM_ALIGNMENT) & 840 (~(PPB_MEM_ALIGNMENT - 1)); 841 mem_size = mem_limit - mem_base; 842 mem_limit = mem_limit - 1; 843 ASSERT(mem_base <= mem_limit); 844 memlist_free_all(&pci_bus_res[secbus].mem_space); 845 memlist_insert(&pci_bus_res[secbus].mem_space, 846 mem_base, mem_size); 847 memlist_insert(&pci_bus_res[parbus].mem_space_used, 848 mem_base, mem_size); 849 (void) memlist_remove(&pci_bus_res[parbus].mem_space, 850 mem_base, mem_size); 851 pci_bus_res[secbus].mem_reprogram = B_TRUE; 852 } else { 853 /* get new mem resource from parent bus */ 854 addr = get_parbus_mem_res(parbus, secbus, mem_size, 855 mem_align); 856 if (addr) { 857 mem_base = addr; 858 mem_limit = addr + mem_size - 1; 859 pci_bus_res[secbus].mem_reprogram = B_TRUE; 860 } 861 } 862 863 if (pci_bus_res[secbus].mem_reprogram) { 864 /* reprogram PPB MEM regs */ 865 pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE, 866 (uint16_t)((mem_base>>16) & 0xfff0)); 867 pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT, 868 (uint16_t)((mem_limit>>16) & 0xfff0)); 869 /* 870 * Disable PMEM window by setting base > limit. 871 * We currently don't reprogram the PMEM like we've 872 * done for I/O and MEM. (Devices that support prefetch 873 * can use non-prefetch MEM.) Anyway, if the MEM access 874 * bit is initially disabled by BIOS, we disable the 875 * PMEM window manually by setting PMEM base > PMEM 876 * limit here, in case there are incorrect values in 877 * them from BIOS, so that we won't get in trouble once 878 * the MEM access bit is enabled at the end of this 879 * function. 880 */ 881 if (!(cmd_reg & PCI_COMM_MAE)) { 882 pci_putw(bus, dev, func, PCI_BCNF_PF_BASE_LOW, 883 0xfff0); 884 pci_putw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW, 885 0x0); 886 pci_putl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH, 887 0xffffffff); 888 pci_putl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH, 889 0x0); 890 } 891 892 add_ranges_prop(secbus, 1); 893 894 cmn_err(CE_NOTE, "!reprogram mem-range on" 895 " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 896 bus, dev, func, mem_base, mem_limit); 897 } 898 } 899 900 cmd_enable: 901 if (pci_bus_res[secbus].io_ports) 902 cmd_reg |= PCI_COMM_IO | PCI_COMM_ME; 903 if (pci_bus_res[secbus].mem_space) 904 cmd_reg |= PCI_COMM_MAE | PCI_COMM_ME; 905 pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 906 } 907 908 void 909 pci_reprogram(void) 910 { 911 int i, pci_reconfig = 1; 912 char *onoff; 913 int bus; 914 915 /* 916 * Excise phantom roots if possible 917 */ 918 pci_renumber_root_busses(); 919 920 /* 921 * Do root-bus resource discovery 922 */ 923 for (bus = 0; bus <= pci_bios_nbus; bus++) { 924 /* skip non-root (peer) PCI busses */ 925 if (pci_bus_res[bus].par_bus != (uchar_t)-1) 926 continue; 927 928 /* 929 * 1. find resources associated with this root bus 930 */ 931 populate_bus_res(bus); 932 933 934 /* 935 * 2. Remove used PCI and ISA resources from bus resource map 936 */ 937 938 memlist_remove_list(&pci_bus_res[bus].io_ports, 939 pci_bus_res[bus].io_ports_used); 940 memlist_remove_list(&pci_bus_res[bus].mem_space, 941 pci_bus_res[bus].mem_space_used); 942 memlist_remove_list(&pci_bus_res[bus].pmem_space, 943 pci_bus_res[bus].pmem_space_used); 944 memlist_remove_list(&pci_bus_res[bus].mem_space, 945 pci_bus_res[bus].pmem_space_used); 946 memlist_remove_list(&pci_bus_res[bus].pmem_space, 947 pci_bus_res[bus].mem_space_used); 948 949 memlist_remove_list(&pci_bus_res[bus].io_ports, 950 isa_res.io_ports_used); 951 memlist_remove_list(&pci_bus_res[bus].mem_space, 952 isa_res.mem_space_used); 953 } 954 955 memlist_free_all(&isa_res.io_ports_used); 956 memlist_free_all(&isa_res.mem_space_used); 957 958 /* add bus-range property for root/peer bus nodes */ 959 for (i = 0; i <= pci_bios_nbus; i++) { 960 /* create bus-range property on root/peer buses */ 961 if (pci_bus_res[i].par_bus == (uchar_t)-1) 962 add_bus_range_prop(i); 963 964 /* setup bus range resource on each bus */ 965 setup_bus_res(i); 966 } 967 968 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 969 DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 970 if (strcmp(onoff, "off") == 0) { 971 pci_reconfig = 0; 972 cmn_err(CE_NOTE, "pci device reprogramming disabled"); 973 } 974 ddi_prop_free(onoff); 975 } 976 977 remove_subtractive_res(); 978 979 /* reprogram the non-subtractive PPB */ 980 if (pci_reconfig) 981 for (i = 0; i <= pci_bios_nbus; i++) 982 fix_ppb_res(i, B_FALSE); 983 984 for (i = 0; i <= pci_bios_nbus; i++) { 985 /* configure devices not configured by BIOS */ 986 if (pci_reconfig) { 987 /* 988 * Reprogram the subtractive PPB. At this time, all its 989 * siblings should have got their resources already. 990 */ 991 if (pci_bus_res[i].subtractive) 992 fix_ppb_res(i, B_TRUE); 993 enumerate_bus_devs(i, CONFIG_NEW); 994 } 995 } 996 997 /* All dev programmed, so we can create available prop */ 998 for (i = 0; i <= pci_bios_nbus; i++) 999 add_bus_available_prop(i); 1000 } 1001 1002 /* 1003 * populate bus resources 1004 */ 1005 static void 1006 populate_bus_res(uchar_t bus) 1007 { 1008 1009 /* scan BIOS structures */ 1010 pci_bus_res[bus].pmem_space = find_bus_res(bus, PREFETCH_TYPE); 1011 pci_bus_res[bus].mem_space = find_bus_res(bus, MEM_TYPE); 1012 pci_bus_res[bus].io_ports = find_bus_res(bus, IO_TYPE); 1013 pci_bus_res[bus].bus_space = find_bus_res(bus, BUSRANGE_TYPE); 1014 1015 /* 1016 * attempt to initialize sub_bus from the largest range-end 1017 * in the bus_space list 1018 */ 1019 if (pci_bus_res[bus].bus_space != NULL) { 1020 struct memlist *entry; 1021 int current; 1022 1023 entry = pci_bus_res[bus].bus_space; 1024 while (entry != NULL) { 1025 current = entry->address + entry->size - 1; 1026 if (current > pci_bus_res[bus].sub_bus) 1027 pci_bus_res[bus].sub_bus = current; 1028 entry = entry->next; 1029 } 1030 } 1031 1032 if (bus == 0) { 1033 /* 1034 * Special treatment of bus 0: 1035 * If no IO/MEM resource from ACPI/MPSPEC/HRT, copy 1036 * pcimem from boot and make I/O space the entire range 1037 * starting at 0x100. 1038 */ 1039 if (pci_bus_res[0].mem_space == NULL) 1040 pci_bus_res[0].mem_space = 1041 memlist_dup(bootops->boot_mem->pcimem); 1042 /* Exclude 0x00 to 0xff of the I/O space, used by all PCs */ 1043 if (pci_bus_res[0].io_ports == NULL) 1044 memlist_insert(&pci_bus_res[0].io_ports, 0x100, 0xffff); 1045 } 1046 1047 /* 1048 * Create 'ranges' property here before any resources are 1049 * removed from the resource lists 1050 */ 1051 add_ranges_prop(bus, 0); 1052 } 1053 1054 1055 /* 1056 * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 1057 */ 1058 static void 1059 create_root_bus_dip(uchar_t bus) 1060 { 1061 int pci_regs[] = {0, 0, 0}; 1062 dev_info_t *dip; 1063 1064 ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 1065 1066 num_root_bus++; 1067 ndi_devi_alloc_sleep(ddi_root_node(), "pci", 1068 (pnode_t)DEVI_SID_NODEID, &dip); 1069 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1070 "#address-cells", 3); 1071 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1072 "#size-cells", 2); 1073 pci_regs[0] = pci_bus_res[bus].root_addr; 1074 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1075 "reg", (int *)pci_regs, 3); 1076 1077 /* 1078 * If system has PCIe bus, then create different properties 1079 */ 1080 if (create_pcie_root_bus(bus, dip) == B_FALSE) 1081 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1082 "device_type", "pci"); 1083 1084 (void) ndi_devi_bind_driver(dip, 0); 1085 pci_bus_res[bus].dip = dip; 1086 } 1087 1088 /* 1089 * For any fixed configuration (often compatability) pci devices 1090 * and those with their own expansion rom, create device nodes 1091 * to hold the already configured device details. 1092 */ 1093 void 1094 enumerate_bus_devs(uchar_t bus, int config_op) 1095 { 1096 uchar_t dev, func, nfunc, header; 1097 ushort_t venid; 1098 struct pci_devfunc *devlist = NULL, *entry; 1099 1100 if (config_op == CONFIG_NEW) { 1101 dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 1102 } else if (config_op == CONFIG_FIX) { 1103 dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus); 1104 } else 1105 dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 1106 1107 if (config_op == CONFIG_NEW) { 1108 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 1109 while (devlist) { 1110 entry = devlist; 1111 devlist = entry->next; 1112 if (entry->reprogram || 1113 pci_bus_res[bus].io_reprogram || 1114 pci_bus_res[bus].mem_reprogram) { 1115 /* reprogram device(s) */ 1116 (void) add_reg_props(entry->dip, bus, 1117 entry->dev, entry->func, CONFIG_NEW, 0); 1118 } 1119 kmem_free(entry, sizeof (*entry)); 1120 } 1121 pci_bus_res[bus].privdata = NULL; 1122 return; 1123 } 1124 1125 for (dev = 0; dev < max_dev_pci; dev++) { 1126 nfunc = 1; 1127 for (func = 0; func < nfunc; func++) { 1128 1129 dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", 1130 dev, func); 1131 1132 venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 1133 1134 if ((venid == 0xffff) || (venid == 0)) { 1135 /* no function at this address */ 1136 continue; 1137 } 1138 1139 header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 1140 if (header == 0xff) { 1141 continue; /* illegal value */ 1142 } 1143 1144 /* 1145 * according to some mail from Microsoft posted 1146 * to the pci-drivers alias, their only requirement 1147 * for a multifunction device is for the 1st 1148 * function to have to PCI_HEADER_MULTI bit set. 1149 */ 1150 if ((func == 0) && (header & PCI_HEADER_MULTI)) { 1151 nfunc = 8; 1152 } 1153 1154 if (config_op == CONFIG_FIX || 1155 config_op == CONFIG_INFO) { 1156 /* 1157 * Create the node, unconditionally, on the 1158 * first pass only. It may still need 1159 * resource assignment, which will be 1160 * done on the second, CONFIG_NEW, pass. 1161 */ 1162 process_devfunc(bus, dev, func, header, 1163 venid, config_op); 1164 1165 } 1166 } 1167 } 1168 1169 /* percolate bus used resources up through parents to root */ 1170 if (config_op == CONFIG_INFO) { 1171 int par_bus; 1172 1173 par_bus = pci_bus_res[bus].par_bus; 1174 while (par_bus != (uchar_t)-1) { 1175 pci_bus_res[par_bus].io_size += 1176 pci_bus_res[bus].io_size; 1177 pci_bus_res[par_bus].mem_size += 1178 pci_bus_res[bus].mem_size; 1179 1180 if (pci_bus_res[bus].io_ports_used) 1181 memlist_merge(&pci_bus_res[bus].io_ports_used, 1182 &pci_bus_res[par_bus].io_ports_used); 1183 1184 if (pci_bus_res[bus].mem_space_used) 1185 memlist_merge(&pci_bus_res[bus].mem_space_used, 1186 &pci_bus_res[par_bus].mem_space_used); 1187 1188 if (pci_bus_res[bus].pmem_space_used) 1189 memlist_merge(&pci_bus_res[bus].pmem_space_used, 1190 &pci_bus_res[par_bus].pmem_space_used); 1191 1192 par_bus = pci_bus_res[par_bus].par_bus; 1193 } 1194 } 1195 } 1196 1197 static int 1198 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 1199 ushort_t subvenid, ushort_t subdevid) 1200 { 1201 static int prop_exist = -1; 1202 static char *pciide_str; 1203 char compat[32]; 1204 1205 if (prop_exist == -1) { 1206 prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 1207 ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 1208 &pciide_str) == DDI_SUCCESS); 1209 } 1210 1211 if (!prop_exist) 1212 return (0); 1213 1214 /* compare property value against various forms of compatible */ 1215 if (subvenid) { 1216 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 1217 venid, devid, subvenid, subdevid, revid); 1218 if (strcmp(pciide_str, compat) == 0) 1219 return (1); 1220 1221 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 1222 venid, devid, subvenid, subdevid); 1223 if (strcmp(pciide_str, compat) == 0) 1224 return (1); 1225 1226 (void) snprintf(compat, sizeof (compat), "pci%x,%x", 1227 subvenid, subdevid); 1228 if (strcmp(pciide_str, compat) == 0) 1229 return (1); 1230 } 1231 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 1232 venid, devid, revid); 1233 if (strcmp(pciide_str, compat) == 0) 1234 return (1); 1235 1236 (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 1237 if (strcmp(pciide_str, compat) == 0) 1238 return (1); 1239 1240 return (0); 1241 } 1242 1243 static int 1244 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 1245 ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 1246 { 1247 struct ide_table { /* table for PCI_MASS_OTHER */ 1248 ushort_t venid; 1249 ushort_t devid; 1250 } *entry; 1251 1252 /* XXX SATA and other devices: need a way to add dynamically */ 1253 static struct ide_table ide_other[] = { 1254 {0x1095, 0x3112}, 1255 {0x1095, 0x3114}, 1256 {0x1095, 0x3512}, 1257 {0x1095, 0x680}, /* Sil0680 */ 1258 {0x1283, 0x8211}, /* ITE 8211F is subcl PCI_MASS_OTHER */ 1259 {0, 0} 1260 }; 1261 1262 if (basecl != PCI_CLASS_MASS) 1263 return (0); 1264 1265 if (subcl == PCI_MASS_IDE) { 1266 return (1); 1267 } 1268 1269 if (check_pciide_prop(revid, venid, devid, subvenid, subdevid)) 1270 return (1); 1271 1272 if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 1273 return (0); 1274 } 1275 1276 entry = &ide_other[0]; 1277 while (entry->venid) { 1278 if (entry->venid == venid && entry->devid == devid) 1279 return (1); 1280 entry++; 1281 } 1282 return (0); 1283 } 1284 1285 static int 1286 is_display(uint_t classcode) 1287 { 1288 static uint_t disp_classes[] = { 1289 0x000100, 1290 0x030000, 1291 0x030001 1292 }; 1293 int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 1294 1295 for (i = 0; i < nclasses; i++) { 1296 if (classcode == disp_classes[i]) 1297 return (1); 1298 } 1299 return (0); 1300 } 1301 1302 static void 1303 add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn, 1304 void (*undofn)(uint8_t, uint8_t, uint8_t)) 1305 { 1306 struct pci_fixundo *newundo; 1307 1308 newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP); 1309 1310 /* 1311 * Adding an item to this list means that we must turn its NMIENABLE 1312 * bit back on at a later time. 1313 */ 1314 newundo->bus = bus; 1315 newundo->dev = dev; 1316 newundo->fn = fn; 1317 newundo->undofn = undofn; 1318 newundo->next = undolist; 1319 1320 /* add to the undo list in LIFO order */ 1321 undolist = newundo; 1322 } 1323 1324 void 1325 add_pci_fixes(void) 1326 { 1327 int i; 1328 1329 for (i = 0; i <= pci_bios_nbus; i++) { 1330 /* 1331 * For each bus, apply needed fixes to the appropriate devices. 1332 * This must be done before the main enumeration loop because 1333 * some fixes must be applied to devices normally encountered 1334 * later in the pci scan (e.g. if a fix to device 7 must be 1335 * applied before scanning device 6, applying fixes in the 1336 * normal enumeration loop would obviously be too late). 1337 */ 1338 enumerate_bus_devs(i, CONFIG_FIX); 1339 } 1340 } 1341 1342 void 1343 undo_pci_fixes(void) 1344 { 1345 struct pci_fixundo *nextundo; 1346 uint8_t bus, dev, fn; 1347 1348 /* 1349 * All fixes in the undo list are performed unconditionally. Future 1350 * fixes may require selective undo. 1351 */ 1352 while (undolist != NULL) { 1353 1354 bus = undolist->bus; 1355 dev = undolist->dev; 1356 fn = undolist->fn; 1357 1358 (*(undolist->undofn))(bus, dev, fn); 1359 1360 nextundo = undolist->next; 1361 kmem_free(undolist, sizeof (struct pci_fixundo)); 1362 undolist = nextundo; 1363 } 1364 } 1365 1366 static void 1367 undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn) 1368 { 1369 uint8_t val8; 1370 1371 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1372 /* 1373 * The NMIONERR bit is turned back on to allow the SMM BIOS 1374 * to handle more critical PCI errors (e.g. PERR#). 1375 */ 1376 val8 |= AMD8111_ENABLENMI; 1377 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1378 } 1379 1380 static void 1381 pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn) 1382 { 1383 uint8_t val8; 1384 1385 val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1386 1387 if ((val8 & AMD8111_ENABLENMI) == 0) 1388 return; 1389 1390 /* 1391 * We reset NMIONERR in the LPC because master-abort on the PCI 1392 * bridge side of the 8111 will cause NMI, which might cause SMI, 1393 * which sometimes prevents all devices from being enumerated. 1394 */ 1395 val8 &= ~AMD8111_ENABLENMI; 1396 1397 pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1398 1399 add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix); 1400 } 1401 1402 static void 1403 set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func) 1404 { 1405 uint16_t status; 1406 uint8_t header; 1407 uint8_t cap_ptr; 1408 uint8_t cap_id; 1409 uint16_t pmcsr; 1410 1411 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 1412 if (!(status & PCI_STAT_CAP)) 1413 return; /* No capabilities list */ 1414 1415 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1416 if (header == PCI_HEADER_CARDBUS) 1417 cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_CAP_PTR); 1418 else 1419 cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 1420 /* 1421 * Walk the capabilities list searching for a PM entry. 1422 */ 1423 while (cap_ptr != PCI_CAP_NEXT_PTR_NULL && cap_ptr >= PCI_CAP_PTR_OFF) { 1424 cap_ptr &= PCI_CAP_PTR_MASK; 1425 cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID); 1426 if (cap_id == PCI_CAP_ID_PM) { 1427 pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR); 1428 pmcsr &= ~(PCI_PMCSR_STATE_MASK); 1429 pmcsr |= PCI_PMCSR_D0; /* D0 state */ 1430 pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr); 1431 break; 1432 } 1433 cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR); 1434 } 1435 1436 } 1437 1438 #define is_isa(bc, sc) \ 1439 (((bc) == PCI_CLASS_BRIDGE) && ((sc) == PCI_BRIDGE_ISA)) 1440 1441 static void 1442 process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 1443 ushort_t vendorid, int config_op) 1444 { 1445 char nodename[32], unitaddr[5]; 1446 dev_info_t *dip; 1447 uchar_t basecl, subcl, progcl, intr, revid; 1448 ushort_t subvenid, subdevid, status; 1449 ushort_t slot_num; 1450 uint_t classcode, revclass; 1451 int reprogram = 0, pciide = 0; 1452 int power[2] = {1, 1}; 1453 int pciex = 0; 1454 ushort_t is_pci_bridge = 0; 1455 struct pci_devfunc *devlist = NULL, *entry = NULL; 1456 iommu_private_t *private; 1457 gfx_entry_t *gfxp; 1458 1459 ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 1460 1461 switch (header & PCI_HEADER_TYPE_M) { 1462 case PCI_HEADER_ZERO: 1463 subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 1464 subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 1465 break; 1466 case PCI_HEADER_CARDBUS: 1467 subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 1468 subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 1469 /* Record the # of cardbus bridges found on the bus */ 1470 if (config_op == CONFIG_INFO) 1471 pci_bus_res[bus].num_cbb++; 1472 break; 1473 default: 1474 subvenid = 0; 1475 subdevid = 0; 1476 break; 1477 } 1478 1479 if (config_op == CONFIG_FIX) { 1480 if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) { 1481 pci_fix_amd8111(bus, dev, func); 1482 } 1483 return; 1484 } 1485 1486 /* XXX should be use generic names? derive from class? */ 1487 revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 1488 classcode = revclass >> 8; 1489 revid = revclass & 0xff; 1490 1491 /* figure out if this is pci-ide */ 1492 basecl = classcode >> 16; 1493 subcl = (classcode >> 8) & 0xff; 1494 progcl = classcode & 0xff; 1495 1496 1497 if (is_display(classcode)) 1498 (void) snprintf(nodename, sizeof (nodename), "display"); 1499 else if (!pseudo_isa && is_isa(basecl, subcl)) 1500 (void) snprintf(nodename, sizeof (nodename), "isa"); 1501 else if (subvenid != 0) 1502 (void) snprintf(nodename, sizeof (nodename), 1503 "pci%x,%x", subvenid, subdevid); 1504 else 1505 (void) snprintf(nodename, sizeof (nodename), 1506 "pci%x,%x", vendorid, deviceid); 1507 1508 /* make sure parent bus dip has been created */ 1509 if (pci_bus_res[bus].dip == NULL) 1510 create_root_bus_dip(bus); 1511 1512 ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 1513 DEVI_SID_NODEID, &dip); 1514 1515 if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num, 1516 &is_pci_bridge) == B_TRUE) 1517 pciex = 1; 1518 1519 /* add properties */ 1520 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 1521 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 1522 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 1523 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1524 "class-code", classcode); 1525 if (func == 0) 1526 (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 1527 else 1528 (void) snprintf(unitaddr, sizeof (unitaddr), 1529 "%x,%x", dev, func); 1530 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1531 "unit-address", unitaddr); 1532 1533 /* add device_type for display nodes */ 1534 if (is_display(classcode)) { 1535 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1536 "device_type", "display"); 1537 } 1538 /* add special stuff for header type */ 1539 if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 1540 uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 1541 uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 1542 1543 if (subvenid != 0) { 1544 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1545 "subsystem-id", subdevid); 1546 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1547 "subsystem-vendor-id", subvenid); 1548 } 1549 if (!pciex) 1550 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1551 "min-grant", mingrant); 1552 if (!pciex) 1553 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1554 "max-latency", maxlatency); 1555 } 1556 1557 /* interrupt, record if not 0 */ 1558 intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 1559 if (intr != 0) 1560 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1561 "interrupts", intr); 1562 1563 /* 1564 * Add support for 133 mhz pci eventually 1565 */ 1566 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 1567 1568 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1569 "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 1570 if (!pciex && (status & PCI_STAT_FBBC)) 1571 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1572 "fast-back-to-back"); 1573 if (!pciex && (status & PCI_STAT_66MHZ)) 1574 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1575 "66mhz-capable"); 1576 if (status & PCI_STAT_UDF) 1577 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 1578 "udf-supported"); 1579 if (pciex && slot_num) { 1580 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1581 "physical-slot#", slot_num); 1582 if (!is_pci_bridge) 1583 pciex_slot_names_prop(dip, slot_num); 1584 } 1585 1586 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1587 "power-consumption", power, 2); 1588 1589 /* Set the device PM state to D0 */ 1590 set_devpm_d0(bus, dev, func); 1591 1592 if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) 1593 add_ppb_props(dip, bus, dev, func, pciex, is_pci_bridge); 1594 else { 1595 /* 1596 * Record the non-PPB devices on the bus for possible 1597 * reprogramming at 2nd bus enumeration. 1598 * Note: PPB reprogramming is done in fix_ppb_res() 1599 */ 1600 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 1601 entry = kmem_zalloc(sizeof (*entry), KM_SLEEP); 1602 entry->dip = dip; 1603 entry->dev = dev; 1604 entry->func = func; 1605 entry->next = devlist; 1606 pci_bus_res[bus].privdata = entry; 1607 } 1608 1609 if (config_op == CONFIG_INFO && 1610 IS_CLASS_IOAPIC(basecl, subcl, progcl)) { 1611 create_ioapic_node(bus, dev, func, vendorid, deviceid); 1612 } 1613 1614 /* check for ck8-04 based PCI ISA bridge only */ 1615 if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) && 1616 (func == 0)) 1617 add_nvidia_isa_bridge_props(dip, bus, dev, func); 1618 1619 if (pciex && is_pci_bridge) 1620 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 1621 (char *)"PCIe-PCI bridge"); 1622 else 1623 add_model_prop(dip, classcode); 1624 1625 add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 1626 revid, classcode, pciex); 1627 1628 /* 1629 * See if this device is a controller that advertises 1630 * itself to be a standard ATA task file controller, or one that 1631 * has been hard coded. 1632 * 1633 * If it is, check if any other higher precedence driver listed in 1634 * driver_aliases will claim the node by calling 1635 * ddi_compatibile_driver_major. If so, clear pciide and do not 1636 * create a pci-ide node or any other special handling. 1637 * 1638 * If another driver does not bind, set the node name to pci-ide 1639 * and then let the special pci-ide handling for registers and 1640 * child pci-ide nodes proceed below. 1641 */ 1642 if (is_pciide(basecl, subcl, revid, vendorid, deviceid, 1643 subvenid, subdevid) == 1) { 1644 if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) { 1645 (void) ndi_devi_set_nodename(dip, "pci-ide", 0); 1646 pciide = 1; 1647 } 1648 } 1649 1650 reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 1651 (void) ndi_devi_bind_driver(dip, 0); 1652 1653 /* special handling for pci-ide */ 1654 if (pciide) { 1655 dev_info_t *cdip; 1656 1657 /* 1658 * Create properties specified by P1275 Working Group 1659 * Proposal #414 Version 1 1660 */ 1661 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1662 "device_type", "pci-ide"); 1663 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1664 "#address-cells", 1); 1665 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1666 "#size-cells", 0); 1667 1668 /* allocate two child nodes */ 1669 ndi_devi_alloc_sleep(dip, "ide", 1670 (pnode_t)DEVI_SID_NODEID, &cdip); 1671 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 1672 "reg", 0); 1673 (void) ndi_devi_bind_driver(cdip, 0); 1674 ndi_devi_alloc_sleep(dip, "ide", 1675 (pnode_t)DEVI_SID_NODEID, &cdip); 1676 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 1677 "reg", 1); 1678 (void) ndi_devi_bind_driver(cdip, 0); 1679 1680 reprogram = 0; /* don't reprogram pci-ide bridge */ 1681 } 1682 1683 /* allocate and set up iommu private */ 1684 private = kmem_alloc(sizeof (iommu_private_t), KM_SLEEP); 1685 private->idp_seg = 0; 1686 private->idp_bus = bus; 1687 private->idp_devfn = (dev << 3) | func; 1688 private->idp_sec = 0; 1689 private->idp_sub = 0; 1690 private->idp_bbp_type = IOMMU_PPB_NONE; 1691 /* record the bridge */ 1692 private->idp_is_bridge = ((basecl == PCI_CLASS_BRIDGE) && 1693 (subcl == PCI_BRIDGE_PCI)); 1694 if (private->idp_is_bridge) { 1695 private->idp_sec = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 1696 private->idp_sub = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 1697 if (pciex && is_pci_bridge) 1698 private->idp_bbp_type = IOMMU_PPB_PCIE_PCI; 1699 else if (pciex) 1700 private->idp_bbp_type = IOMMU_PPB_PCIE_PCIE; 1701 else 1702 private->idp_bbp_type = IOMMU_PPB_PCI_PCI; 1703 } 1704 /* record the special devices */ 1705 private->idp_is_display = (is_display(classcode) ? B_TRUE : B_FALSE); 1706 private->idp_is_lpc = ((basecl == PCI_CLASS_BRIDGE) && 1707 (subcl == PCI_BRIDGE_ISA)); 1708 private->idp_intel_domain = NULL; 1709 /* hook the private to dip */ 1710 DEVI(dip)->devi_iommu_private = private; 1711 1712 if (private->idp_is_display == B_TRUE) { 1713 gfxp = kmem_zalloc(sizeof (*gfxp), KM_SLEEP); 1714 gfxp->g_dip = dip; 1715 gfxp->g_prev = NULL; 1716 gfxp->g_next = gfx_devinfo_list; 1717 gfx_devinfo_list = gfxp; 1718 if (gfxp->g_next) 1719 gfxp->g_next->g_prev = gfxp; 1720 } 1721 1722 /* special handling for isa */ 1723 if (!pseudo_isa && is_isa(basecl, subcl)) { 1724 /* add device_type */ 1725 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1726 "device_type", "isa"); 1727 } 1728 1729 if (reprogram && (entry != NULL)) 1730 entry->reprogram = B_TRUE; 1731 } 1732 1733 /* 1734 * Some vendors do not use unique subsystem IDs in their products, which 1735 * makes the use of form 2 compatible names (pciSSSS,ssss) inappropriate. 1736 * Allow for these compatible forms to be excluded on a per-device basis. 1737 */ 1738 /*ARGSUSED*/ 1739 static boolean_t 1740 subsys_compat_exclude(ushort_t venid, ushort_t devid, ushort_t subvenid, 1741 ushort_t subdevid, uchar_t revid, uint_t classcode) 1742 { 1743 /* Nvidia display adapters */ 1744 if ((venid == 0x10de) && (is_display(classcode))) 1745 return (B_TRUE); 1746 1747 return (B_FALSE); 1748 } 1749 1750 /* 1751 * Set the compatible property to a value compliant with 1752 * rev 2.1 of the IEEE1275 PCI binding. 1753 * (Also used for PCI-Express devices). 1754 * 1755 * pciVVVV,DDDD.SSSS.ssss.RR (0) 1756 * pciVVVV,DDDD.SSSS.ssss (1) 1757 * pciSSSS,ssss (2) 1758 * pciVVVV,DDDD.RR (3) 1759 * pciVVVV,DDDD (4) 1760 * pciclass,CCSSPP (5) 1761 * pciclass,CCSS (6) 1762 * 1763 * The Subsystem (SSSS) forms are not inserted if 1764 * subsystem-vendor-id is 0. 1765 * 1766 * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above 1767 * property 2 is not created as per "1275 bindings for PCI Express Interconnect" 1768 * 1769 * Set with setprop and \x00 between each 1770 * to generate the encoded string array form. 1771 */ 1772 void 1773 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 1774 ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode, 1775 int pciex) 1776 { 1777 int i = 0; 1778 int size = COMPAT_BUFSIZE; 1779 char *compat[13]; 1780 char *buf, *curr; 1781 1782 curr = buf = kmem_alloc(size, KM_SLEEP); 1783 1784 if (pciex) { 1785 if (subvenid) { 1786 compat[i++] = curr; /* form 0 */ 1787 (void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x", 1788 vendorid, deviceid, subvenid, subdevid, revid); 1789 size -= strlen(curr) + 1; 1790 curr += strlen(curr) + 1; 1791 1792 compat[i++] = curr; /* form 1 */ 1793 (void) snprintf(curr, size, "pciex%x,%x.%x.%x", 1794 vendorid, deviceid, subvenid, subdevid); 1795 size -= strlen(curr) + 1; 1796 curr += strlen(curr) + 1; 1797 1798 } 1799 compat[i++] = curr; /* form 3 */ 1800 (void) snprintf(curr, size, "pciex%x,%x.%x", 1801 vendorid, deviceid, revid); 1802 size -= strlen(curr) + 1; 1803 curr += strlen(curr) + 1; 1804 1805 compat[i++] = curr; /* form 4 */ 1806 (void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid); 1807 size -= strlen(curr) + 1; 1808 curr += strlen(curr) + 1; 1809 1810 compat[i++] = curr; /* form 5 */ 1811 (void) snprintf(curr, size, "pciexclass,%06x", classcode); 1812 size -= strlen(curr) + 1; 1813 curr += strlen(curr) + 1; 1814 1815 compat[i++] = curr; /* form 6 */ 1816 (void) snprintf(curr, size, "pciexclass,%04x", 1817 (classcode >> 8)); 1818 size -= strlen(curr) + 1; 1819 curr += strlen(curr) + 1; 1820 } 1821 1822 if (subvenid) { 1823 compat[i++] = curr; /* form 0 */ 1824 (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 1825 vendorid, deviceid, subvenid, subdevid, revid); 1826 size -= strlen(curr) + 1; 1827 curr += strlen(curr) + 1; 1828 1829 compat[i++] = curr; /* form 1 */ 1830 (void) snprintf(curr, size, "pci%x,%x.%x.%x", 1831 vendorid, deviceid, subvenid, subdevid); 1832 size -= strlen(curr) + 1; 1833 curr += strlen(curr) + 1; 1834 1835 if (subsys_compat_exclude(vendorid, deviceid, subvenid, 1836 subdevid, revid, classcode) == B_FALSE) { 1837 compat[i++] = curr; /* form 2 */ 1838 (void) snprintf(curr, size, "pci%x,%x", subvenid, 1839 subdevid); 1840 size -= strlen(curr) + 1; 1841 curr += strlen(curr) + 1; 1842 } 1843 } 1844 compat[i++] = curr; /* form 3 */ 1845 (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 1846 size -= strlen(curr) + 1; 1847 curr += strlen(curr) + 1; 1848 1849 compat[i++] = curr; /* form 4 */ 1850 (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 1851 size -= strlen(curr) + 1; 1852 curr += strlen(curr) + 1; 1853 1854 compat[i++] = curr; /* form 5 */ 1855 (void) snprintf(curr, size, "pciclass,%06x", classcode); 1856 size -= strlen(curr) + 1; 1857 curr += strlen(curr) + 1; 1858 1859 compat[i++] = curr; /* form 6 */ 1860 (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 1861 size -= strlen(curr) + 1; 1862 curr += strlen(curr) + 1; 1863 1864 (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 1865 "compatible", compat, i); 1866 kmem_free(buf, COMPAT_BUFSIZE); 1867 } 1868 1869 /* 1870 * Adjust the reg properties for a dual channel PCI-IDE device. 1871 * 1872 * NOTE: don't do anything that changes the order of the hard-decodes 1873 * and programmed BARs. The kernel driver depends on these values 1874 * being in this order regardless of whether they're for a 'native' 1875 * mode BAR or not. 1876 */ 1877 /* 1878 * config info for pci-ide devices 1879 */ 1880 static struct { 1881 uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 1882 uchar_t bar_offset; /* offset for alt status register */ 1883 ushort_t addr; /* compatibility mode base address */ 1884 ushort_t length; /* number of ports for this BAR */ 1885 } pciide_bar[] = { 1886 { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 1887 { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 1888 { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 1889 { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 1890 }; 1891 1892 static int 1893 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 1894 { 1895 int hard_decode = 0; 1896 1897 /* 1898 * Adjust the base and len for the BARs of the PCI-IDE 1899 * device's primary and secondary controllers. The first 1900 * two BARs are for the primary controller and the next 1901 * two BARs are for the secondary controller. The fifth 1902 * and sixth bars are never adjusted. 1903 */ 1904 if (index >= 0 && index <= 3) { 1905 *lenp = pciide_bar[index].length; 1906 1907 if (progcl & pciide_bar[index].native_mask) { 1908 *basep += pciide_bar[index].bar_offset; 1909 } else { 1910 *basep = pciide_bar[index].addr; 1911 hard_decode = 1; 1912 } 1913 } 1914 1915 /* 1916 * if either base or len is zero make certain both are zero 1917 */ 1918 if (*basep == 0 || *lenp == 0) { 1919 *basep = 0; 1920 *lenp = 0; 1921 hard_decode = 0; 1922 } 1923 1924 return (hard_decode); 1925 } 1926 1927 1928 /* 1929 * Add the "reg" and "assigned-addresses" property 1930 */ 1931 static int 1932 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 1933 int config_op, int pciide) 1934 { 1935 uchar_t baseclass, subclass, progclass, header; 1936 ushort_t bar_sz; 1937 uint_t value = 0, len, devloc; 1938 uint_t base, base_hi, type; 1939 ushort_t offset, end; 1940 int max_basereg, j, reprogram = 0; 1941 uint_t phys_hi; 1942 struct memlist **io_res, **io_res_used; 1943 struct memlist **mem_res, **mem_res_used; 1944 struct memlist **pmem_res, **pmem_res_used; 1945 uchar_t res_bus; 1946 1947 pci_regspec_t regs[16] = {{0}}; 1948 pci_regspec_t assigned[15] = {{0}}; 1949 int nreg, nasgn; 1950 1951 io_res = &pci_bus_res[bus].io_ports; 1952 io_res_used = &pci_bus_res[bus].io_ports_used; 1953 mem_res = &pci_bus_res[bus].mem_space; 1954 mem_res_used = &pci_bus_res[bus].mem_space_used; 1955 pmem_res = &pci_bus_res[bus].pmem_space; 1956 pmem_res_used = &pci_bus_res[bus].pmem_space_used; 1957 1958 devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 1959 regs[0].pci_phys_hi = devloc; 1960 nreg = 1; /* rest of regs[0] is all zero */ 1961 nasgn = 0; 1962 1963 baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 1964 subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 1965 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 1966 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1967 1968 switch (header) { 1969 case PCI_HEADER_ZERO: 1970 max_basereg = PCI_BASE_NUM; 1971 break; 1972 case PCI_HEADER_PPB: 1973 max_basereg = PCI_BCNF_BASE_NUM; 1974 break; 1975 case PCI_HEADER_CARDBUS: 1976 max_basereg = PCI_CBUS_BASE_NUM; 1977 reprogram = 1; 1978 break; 1979 default: 1980 max_basereg = 0; 1981 break; 1982 } 1983 1984 /* 1985 * Create the register property by saving the current 1986 * value of the base register. Write 0xffffffff to the 1987 * base register. Read the value back to determine the 1988 * required size of the address space. Restore the base 1989 * register contents. 1990 * 1991 * Do not disable I/O and memory access; this isn't necessary 1992 * since no driver is yet attached to this device, and disabling 1993 * I/O and memory access has the side-effect of disabling PCI-PCI 1994 * bridge mappings, which makes the bridge transparent to secondary- 1995 * bus activity (see sections 4.1-4.3 of the PCI-PCI Bridge 1996 * Spec V1.2). 1997 */ 1998 end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 1999 for (j = 0, offset = PCI_CONF_BASE0; offset < end; 2000 j++, offset += bar_sz) { 2001 /* determine the size of the address space */ 2002 base = pci_getl(bus, dev, func, offset); 2003 pci_putl(bus, dev, func, offset, 0xffffffff); 2004 value = pci_getl(bus, dev, func, offset); 2005 pci_putl(bus, dev, func, offset, base); 2006 2007 /* construct phys hi,med.lo, size hi, lo */ 2008 if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 2009 int hard_decode = 0; 2010 2011 /* i/o space */ 2012 bar_sz = PCI_BAR_SZ_32; 2013 value &= PCI_BASE_IO_ADDR_M; 2014 len = ((value ^ (value-1)) + 1) >> 1; 2015 2016 /* XXX Adjust first 4 IDE registers */ 2017 if (pciide) { 2018 if (subclass != PCI_MASS_IDE) 2019 progclass = (PCI_IDE_IF_NATIVE_PRI | 2020 PCI_IDE_IF_NATIVE_SEC); 2021 hard_decode = pciIdeAdjustBAR(progclass, j, 2022 &base, &len); 2023 } else if (value == 0) { 2024 /* skip base regs with size of 0 */ 2025 continue; 2026 } 2027 2028 regs[nreg].pci_phys_hi = PCI_ADDR_IO | devloc | 2029 (hard_decode ? PCI_RELOCAT_B : offset); 2030 regs[nreg].pci_phys_low = hard_decode ? 2031 base & PCI_BASE_IO_ADDR_M : 0; 2032 assigned[nasgn].pci_phys_hi = 2033 PCI_RELOCAT_B | regs[nreg].pci_phys_hi; 2034 regs[nreg].pci_size_low = 2035 assigned[nasgn].pci_size_low = len; 2036 type = base & (~PCI_BASE_IO_ADDR_M); 2037 base &= PCI_BASE_IO_ADDR_M; 2038 /* 2039 * A device under a subtractive PPB can allocate 2040 * resources from its parent bus if there is no resource 2041 * available on its own bus. 2042 */ 2043 if ((config_op == CONFIG_NEW) && (*io_res == NULL)) { 2044 res_bus = bus; 2045 while (pci_bus_res[res_bus].subtractive) { 2046 res_bus = pci_bus_res[res_bus].par_bus; 2047 if (res_bus == (uchar_t)-1) 2048 break; /* root bus already */ 2049 if (pci_bus_res[res_bus].io_ports) { 2050 io_res = &pci_bus_res 2051 [res_bus].io_ports; 2052 break; 2053 } 2054 } 2055 } 2056 2057 /* 2058 * first pass - gather what's there 2059 * update/second pass - adjust/allocate regions 2060 * config - allocate regions 2061 */ 2062 if (config_op == CONFIG_INFO) { /* first pass */ 2063 /* take out of the resource map of the bus */ 2064 if (base != 0) { 2065 (void) memlist_remove(io_res, base, 2066 len); 2067 memlist_insert(io_res_used, base, len); 2068 } else { 2069 reprogram = 1; 2070 } 2071 pci_bus_res[bus].io_size += len; 2072 } else if ((*io_res && base == 0) || 2073 pci_bus_res[bus].io_reprogram) { 2074 base = (uint_t)memlist_find(io_res, len, len); 2075 if (base != 0) { 2076 memlist_insert(io_res_used, base, len); 2077 /* XXX need to worry about 64-bit? */ 2078 pci_putl(bus, dev, func, offset, 2079 base | type); 2080 base = pci_getl(bus, dev, func, offset); 2081 base &= PCI_BASE_IO_ADDR_M; 2082 } 2083 if (base == 0) { 2084 cmn_err(CE_WARN, "failed to program" 2085 " IO space [%d/%d/%d] BAR@0x%x" 2086 " length 0x%x", 2087 bus, dev, func, offset, len); 2088 } 2089 } 2090 assigned[nasgn].pci_phys_low = base; 2091 nreg++, nasgn++; 2092 2093 } else { 2094 /* memory space */ 2095 if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 2096 bar_sz = PCI_BAR_SZ_64; 2097 base_hi = pci_getl(bus, dev, func, offset + 4); 2098 phys_hi = PCI_ADDR_MEM64; 2099 } else { 2100 bar_sz = PCI_BAR_SZ_32; 2101 base_hi = 0; 2102 phys_hi = PCI_ADDR_MEM32; 2103 } 2104 2105 /* skip base regs with size of 0 */ 2106 value &= PCI_BASE_M_ADDR_M; 2107 2108 if (value == 0) 2109 continue; 2110 2111 len = ((value ^ (value-1)) + 1) >> 1; 2112 regs[nreg].pci_size_low = 2113 assigned[nasgn].pci_size_low = len; 2114 2115 phys_hi |= (devloc | offset); 2116 if (base & PCI_BASE_PREF_M) 2117 phys_hi |= PCI_PREFETCH_B; 2118 2119 /* 2120 * A device under a subtractive PPB can allocate 2121 * resources from its parent bus if there is no resource 2122 * available on its own bus. 2123 */ 2124 if ((config_op == CONFIG_NEW) && (*mem_res == NULL)) { 2125 res_bus = bus; 2126 while (pci_bus_res[res_bus].subtractive) { 2127 res_bus = pci_bus_res[res_bus].par_bus; 2128 if (res_bus == (uchar_t)-1) 2129 break; /* root bus already */ 2130 mem_res = 2131 &pci_bus_res[res_bus].mem_space; 2132 pmem_res = 2133 &pci_bus_res [res_bus].pmem_space; 2134 /* 2135 * Break out as long as at least 2136 * mem_res is available 2137 */ 2138 if ((*pmem_res && 2139 (phys_hi & PCI_PREFETCH_B)) || 2140 *mem_res) 2141 break; 2142 } 2143 } 2144 2145 regs[nreg].pci_phys_hi = 2146 assigned[nasgn].pci_phys_hi = phys_hi; 2147 assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 2148 assigned[nasgn].pci_phys_mid = base_hi; 2149 type = base & ~PCI_BASE_M_ADDR_M; 2150 base &= PCI_BASE_M_ADDR_M; 2151 2152 if (config_op == CONFIG_INFO) { 2153 /* take out of the resource map of the bus */ 2154 if (base != NULL) { 2155 /* remove from PMEM and MEM space */ 2156 (void) memlist_remove(mem_res, 2157 base, len); 2158 (void) memlist_remove(pmem_res, 2159 base, len); 2160 /* only note as used in correct map */ 2161 if (phys_hi & PCI_PREFETCH_B) 2162 memlist_insert(pmem_res_used, 2163 base, len); 2164 else 2165 memlist_insert(mem_res_used, 2166 base, len); 2167 } else { 2168 reprogram = 1; 2169 } 2170 pci_bus_res[bus].mem_size += len; 2171 } else if ((*mem_res && base == NULL) || 2172 pci_bus_res[bus].mem_reprogram) { 2173 /* 2174 * When desired, attempt a prefetchable 2175 * allocation first 2176 */ 2177 if (phys_hi & PCI_PREFETCH_B) { 2178 base = (uint_t)memlist_find(pmem_res, 2179 len, len); 2180 if (base != NULL) { 2181 memlist_insert(pmem_res_used, 2182 base, len); 2183 (void) memlist_remove(mem_res, 2184 base, len); 2185 } 2186 } 2187 /* 2188 * If prefetchable allocation was not 2189 * desired, or failed, attempt ordinary 2190 * memory allocation 2191 */ 2192 if (base == NULL) { 2193 base = (uint_t)memlist_find(mem_res, 2194 len, len); 2195 if (base != NULL) { 2196 memlist_insert(mem_res_used, 2197 base, len); 2198 (void) memlist_remove(pmem_res, 2199 base, len); 2200 } 2201 } 2202 if (base != NULL) { 2203 pci_putl(bus, dev, func, offset, 2204 base | type); 2205 base = pci_getl(bus, dev, func, offset); 2206 base &= PCI_BASE_M_ADDR_M; 2207 } else 2208 cmn_err(CE_WARN, "failed to program " 2209 "mem space [%d/%d/%d] BAR@0x%x" 2210 " length 0x%x", 2211 bus, dev, func, offset, len); 2212 } 2213 assigned[nasgn].pci_phys_low = base; 2214 nreg++, nasgn++; 2215 } 2216 } 2217 switch (header) { 2218 case PCI_HEADER_ZERO: 2219 offset = PCI_CONF_ROM; 2220 break; 2221 case PCI_HEADER_PPB: 2222 offset = PCI_BCNF_ROM; 2223 break; 2224 default: /* including PCI_HEADER_CARDBUS */ 2225 goto done; 2226 } 2227 2228 /* 2229 * Add the expansion rom memory space 2230 * Determine the size of the ROM base reg; don't write reserved bits 2231 * ROM isn't in the PCI memory space. 2232 */ 2233 base = pci_getl(bus, dev, func, offset); 2234 pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 2235 value = pci_getl(bus, dev, func, offset); 2236 pci_putl(bus, dev, func, offset, base); 2237 if (value & PCI_BASE_ROM_ENABLE) 2238 value &= PCI_BASE_ROM_ADDR_M; 2239 else 2240 value = 0; 2241 2242 if (value != 0) { 2243 regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 2244 assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 2245 PCI_ADDR_MEM32 | devloc) + offset; 2246 base &= PCI_BASE_ROM_ADDR_M; 2247 assigned[nasgn].pci_phys_low = base; 2248 len = ((value ^ (value-1)) + 1) >> 1; 2249 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 2250 nreg++, nasgn++; 2251 /* take it out of the memory resource */ 2252 if (base != NULL) { 2253 (void) memlist_remove(mem_res, base, len); 2254 memlist_insert(mem_res_used, base, len); 2255 } 2256 } 2257 2258 /* 2259 * Account for "legacy" (alias) video adapter resources 2260 */ 2261 2262 /* add the three hard-decode, aliased address spaces for VGA */ 2263 if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 2264 (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 2265 2266 /* VGA hard decode 0x3b0-0x3bb */ 2267 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2268 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2269 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 2270 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 2271 nreg++, nasgn++; 2272 (void) memlist_remove(io_res, 0x3b0, 0xc); 2273 memlist_insert(io_res_used, 0x3b0, 0xc); 2274 2275 /* VGA hard decode 0x3c0-0x3df */ 2276 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2277 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2278 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 2279 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 2280 nreg++, nasgn++; 2281 (void) memlist_remove(io_res, 0x3c0, 0x20); 2282 memlist_insert(io_res_used, 0x3c0, 0x20); 2283 2284 /* Video memory */ 2285 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2286 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_MEM32 | devloc); 2287 regs[nreg].pci_phys_low = 2288 assigned[nasgn].pci_phys_low = 0xa0000; 2289 regs[nreg].pci_size_low = 2290 assigned[nasgn].pci_size_low = 0x20000; 2291 nreg++, nasgn++; 2292 /* remove from MEM and PMEM space */ 2293 (void) memlist_remove(mem_res, 0xa0000, 0x20000); 2294 (void) memlist_remove(pmem_res, 0xa0000, 0x20000); 2295 memlist_insert(mem_res_used, 0xa0000, 0x20000); 2296 } 2297 2298 /* add the hard-decode, aliased address spaces for 8514 */ 2299 if ((baseclass == PCI_CLASS_DISPLAY) && 2300 (subclass == PCI_DISPLAY_VGA) && 2301 (progclass & PCI_DISPLAY_IF_8514)) { 2302 2303 /* hard decode 0x2e8 */ 2304 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2305 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2306 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 2307 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 2308 nreg++, nasgn++; 2309 (void) memlist_remove(io_res, 0x2e8, 0x1); 2310 memlist_insert(io_res_used, 0x2e8, 0x1); 2311 2312 /* hard decode 0x2ea-0x2ef */ 2313 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 2314 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 2315 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 2316 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 2317 nreg++, nasgn++; 2318 (void) memlist_remove(io_res, 0x2ea, 0x6); 2319 memlist_insert(io_res_used, 0x2ea, 0x6); 2320 } 2321 2322 done: 2323 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 2324 (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 2325 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 2326 "assigned-addresses", 2327 (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 2328 2329 return (reprogram); 2330 } 2331 2332 static void 2333 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 2334 int pciex, ushort_t is_pci_bridge) 2335 { 2336 char *dev_type; 2337 int i; 2338 uint_t val, io_range[2], mem_range[2], pmem_range[2]; 2339 uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 2340 uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 2341 uchar_t progclass; 2342 2343 ASSERT(secbus <= subbus); 2344 2345 /* 2346 * Check if it's a subtractive PPB. 2347 */ 2348 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 2349 if (progclass == PCI_BRIDGE_PCI_IF_SUBDECODE) 2350 pci_bus_res[secbus].subtractive = B_TRUE; 2351 2352 /* 2353 * Some BIOSes lie about max pci busses, we allow for 2354 * such mistakes here 2355 */ 2356 if (subbus > pci_bios_nbus) { 2357 pci_bios_nbus = subbus; 2358 alloc_res_array(); 2359 } 2360 2361 ASSERT(pci_bus_res[secbus].dip == NULL); 2362 pci_bus_res[secbus].dip = dip; 2363 pci_bus_res[secbus].par_bus = bus; 2364 2365 dev_type = (pciex && !is_pci_bridge) ? "pciex" : "pci"; 2366 2367 /* setup bus number hierarchy */ 2368 pci_bus_res[secbus].sub_bus = subbus; 2369 /* 2370 * Keep track of the largest subordinate bus number (this is essential 2371 * for peer busses because there is no other way of determining its 2372 * subordinate bus number). 2373 */ 2374 if (subbus > pci_bus_res[bus].sub_bus) 2375 pci_bus_res[bus].sub_bus = subbus; 2376 /* 2377 * Loop through subordinate busses, initializing their parent bus 2378 * field to this bridge's parent. The subordinate busses' parent 2379 * fields may very well be further refined later, as child bridges 2380 * are enumerated. (The value is to note that the subordinate busses 2381 * are not peer busses by changing their par_bus fields to anything 2382 * other than -1.) 2383 */ 2384 for (i = secbus + 1; i <= subbus; i++) 2385 pci_bus_res[i].par_bus = bus; 2386 2387 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 2388 "device_type", dev_type); 2389 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2390 "#address-cells", 3); 2391 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2392 "#size-cells", 2); 2393 2394 /* 2395 * According to PPB spec, the base register should be programmed 2396 * with a value bigger than the limit register when there are 2397 * no resources available. This applies to io, memory, and 2398 * prefetchable memory. 2399 */ 2400 2401 /* 2402 * io range 2403 * We determine i/o windows that are left unconfigured by BIOS 2404 * through its i/o enable bit as Microsoft recommends OEMs to do. 2405 * If it is unset, we disable i/o and mark it for reconfiguration in 2406 * later passes by setting the base > limit 2407 */ 2408 val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM); 2409 if (val & PCI_COMM_IO) { 2410 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 2411 io_range[0] = ((val & 0xf0) << 8); 2412 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 2413 io_range[1] = ((val & 0xf0) << 8) | 0xFFF; 2414 } else { 2415 io_range[0] = 0x9fff; 2416 io_range[1] = 0x1000; 2417 pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 2418 (uint8_t)((io_range[0] >> 8) & 0xf0)); 2419 pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 2420 (uint8_t)((io_range[1] >> 8) & 0xf0)); 2421 pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 2422 pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 2423 } 2424 2425 if (io_range[0] != 0 && io_range[0] < io_range[1]) { 2426 memlist_insert(&pci_bus_res[secbus].io_ports, 2427 (uint64_t)io_range[0], 2428 (uint64_t)(io_range[1] - io_range[0] + 1)); 2429 memlist_insert(&pci_bus_res[bus].io_ports_used, 2430 (uint64_t)io_range[0], 2431 (uint64_t)(io_range[1] - io_range[0] + 1)); 2432 if (pci_bus_res[bus].io_ports != NULL) { 2433 (void) memlist_remove(&pci_bus_res[bus].io_ports, 2434 (uint64_t)io_range[0], 2435 (uint64_t)(io_range[1] - io_range[0] + 1)); 2436 } 2437 dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x", 2438 secbus, io_range[0], io_range[1]); 2439 /* if 32-bit supported, make sure upper bits are not set */ 2440 if ((val & 0xf) == 1 && 2441 pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) { 2442 cmn_err(CE_NOTE, "unsupported 32-bit IO address on" 2443 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 2444 } 2445 } 2446 2447 /* mem range */ 2448 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 2449 mem_range[0] = ((val & 0xFFF0) << 16); 2450 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 2451 mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 2452 if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 2453 memlist_insert(&pci_bus_res[secbus].mem_space, 2454 (uint64_t)mem_range[0], 2455 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2456 memlist_insert(&pci_bus_res[bus].mem_space_used, 2457 (uint64_t)mem_range[0], 2458 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2459 /* remove from parent resource list */ 2460 (void) memlist_remove(&pci_bus_res[bus].mem_space, 2461 (uint64_t)mem_range[0], 2462 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2463 (void) memlist_remove(&pci_bus_res[bus].pmem_space, 2464 (uint64_t)mem_range[0], 2465 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2466 dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x", 2467 secbus, mem_range[0], mem_range[1]); 2468 } 2469 2470 /* prefetchable memory range */ 2471 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 2472 pmem_range[0] = ((val & 0xFFF0) << 16); 2473 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 2474 pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 2475 if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 2476 memlist_insert(&pci_bus_res[secbus].pmem_space, 2477 (uint64_t)pmem_range[0], 2478 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2479 memlist_insert(&pci_bus_res[bus].pmem_space_used, 2480 (uint64_t)pmem_range[0], 2481 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2482 /* remove from parent resource list */ 2483 (void) memlist_remove(&pci_bus_res[bus].pmem_space, 2484 (uint64_t)pmem_range[0], 2485 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2486 (void) memlist_remove(&pci_bus_res[bus].mem_space, 2487 (uint64_t)pmem_range[0], 2488 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2489 dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x", 2490 secbus, pmem_range[0], pmem_range[1]); 2491 /* if 64-bit supported, make sure upper bits are not set */ 2492 if ((val & 0xf) == 1 && 2493 pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) { 2494 cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on" 2495 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 2496 } 2497 } 2498 2499 add_bus_range_prop(secbus); 2500 add_ranges_prop(secbus, 1); 2501 } 2502 2503 extern const struct pci_class_strings_s class_pci[]; 2504 extern int class_pci_items; 2505 2506 static void 2507 add_model_prop(dev_info_t *dip, uint_t classcode) 2508 { 2509 const char *desc; 2510 int i; 2511 uchar_t baseclass = classcode >> 16; 2512 uchar_t subclass = (classcode >> 8) & 0xff; 2513 uchar_t progclass = classcode & 0xff; 2514 2515 if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 2516 desc = "IDE controller"; 2517 } else { 2518 for (desc = 0, i = 0; i < class_pci_items; i++) { 2519 if ((baseclass == class_pci[i].base_class) && 2520 (subclass == class_pci[i].sub_class) && 2521 (progclass == class_pci[i].prog_class)) { 2522 desc = class_pci[i].actual_desc; 2523 break; 2524 } 2525 } 2526 if (i == class_pci_items) 2527 desc = "Unknown class of pci/pnpbios device"; 2528 } 2529 2530 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 2531 (char *)desc); 2532 } 2533 2534 static void 2535 add_bus_range_prop(int bus) 2536 { 2537 int bus_range[2]; 2538 2539 if (pci_bus_res[bus].dip == NULL) 2540 return; 2541 bus_range[0] = bus; 2542 bus_range[1] = pci_bus_res[bus].sub_bus; 2543 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 2544 "bus-range", (int *)bus_range, 2); 2545 } 2546 2547 /* 2548 * Add slot-names property for any named pci hot-plug slots 2549 */ 2550 static void 2551 add_bus_slot_names_prop(int bus) 2552 { 2553 char slotprop[256]; 2554 int len; 2555 2556 if (pci_bus_res[bus].dip != NULL) { 2557 /* simply return if the property is already defined */ 2558 if (ddi_prop_exists(DDI_DEV_T_ANY, pci_bus_res[bus].dip, 2559 DDI_PROP_DONTPASS, "slot-names")) 2560 return; 2561 } 2562 2563 len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); 2564 if (len > 0) { 2565 /* 2566 * Only create a peer bus node if this bus may be a peer bus. 2567 * It may be a peer bus if the dip is NULL and if par_bus is 2568 * -1 (par_bus is -1 if this bus was not found to be 2569 * subordinate to any PCI-PCI bridge). 2570 * If it's not a peer bus, then the ACPI BBN-handling code 2571 * will remove it later. 2572 */ 2573 if (pci_bus_res[bus].par_bus == (uchar_t)-1 && 2574 pci_bus_res[bus].dip == NULL) { 2575 2576 create_root_bus_dip(bus); 2577 } 2578 if (pci_bus_res[bus].dip != NULL) { 2579 ASSERT((len % sizeof (int)) == 0); 2580 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 2581 pci_bus_res[bus].dip, "slot-names", 2582 (int *)slotprop, len / sizeof (int)); 2583 } else { 2584 cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI " 2585 "IRQ routing table; Not adding slot-names " 2586 "property for incorrect bus %d", bus); 2587 } 2588 } 2589 } 2590 2591 /* 2592 * Handle both PCI root and PCI-PCI bridge range properties; 2593 * non-zero 'ppb' argument select PCI-PCI bridges versus root. 2594 */ 2595 static void 2596 memlist_to_ranges(void **rp, struct memlist *entry, int type, int ppb) 2597 { 2598 ppb_ranges_t *ppb_rp = *rp; 2599 pci_ranges_t *pci_rp = *rp; 2600 2601 while (entry != NULL) { 2602 if (ppb) { 2603 ppb_rp->child_high = ppb_rp->parent_high = type; 2604 ppb_rp->child_mid = ppb_rp->parent_mid = 2605 (uint32_t)(entry->address >> 32); /* XXX */ 2606 ppb_rp->child_low = ppb_rp->parent_low = 2607 (uint32_t)entry->address; 2608 ppb_rp->size_high = 2609 (uint32_t)(entry->size >> 32); /* XXX */ 2610 ppb_rp->size_low = (uint32_t)entry->size; 2611 *rp = ++ppb_rp; 2612 } else { 2613 pci_rp->child_high = type; 2614 pci_rp->child_mid = pci_rp->parent_high = 2615 (uint32_t)(entry->address >> 32); /* XXX */ 2616 pci_rp->child_low = pci_rp->parent_low = 2617 (uint32_t)entry->address; 2618 pci_rp->size_high = 2619 (uint32_t)(entry->size >> 32); /* XXX */ 2620 pci_rp->size_low = (uint32_t)entry->size; 2621 *rp = ++pci_rp; 2622 } 2623 entry = entry->next; 2624 } 2625 } 2626 2627 static void 2628 add_ranges_prop(int bus, int ppb) 2629 { 2630 int total, alloc_size; 2631 void *rp, *next_rp; 2632 2633 /* no devinfo node - unused bus, return */ 2634 if (pci_bus_res[bus].dip == NULL) 2635 return; 2636 2637 total = memlist_count(pci_bus_res[bus].io_ports); 2638 total += memlist_count(pci_bus_res[bus].mem_space); 2639 total += memlist_count(pci_bus_res[bus].pmem_space); 2640 2641 /* no property is created if no ranges are present */ 2642 if (total == 0) 2643 return; 2644 2645 alloc_size = total * 2646 (ppb ? sizeof (ppb_ranges_t) : sizeof (pci_ranges_t)); 2647 2648 next_rp = rp = kmem_alloc(alloc_size, KM_SLEEP); 2649 2650 memlist_to_ranges(&next_rp, pci_bus_res[bus].io_ports, 2651 PCI_ADDR_IO | PCI_REG_REL_M, ppb); 2652 memlist_to_ranges(&next_rp, pci_bus_res[bus].mem_space, 2653 PCI_ADDR_MEM32 | PCI_REG_REL_M, ppb); 2654 memlist_to_ranges(&next_rp, pci_bus_res[bus].pmem_space, 2655 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M, ppb); 2656 2657 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 2658 "ranges", (int *)rp, alloc_size / sizeof (int)); 2659 2660 kmem_free(rp, alloc_size); 2661 } 2662 2663 static void 2664 memlist_remove_list(struct memlist **list, struct memlist *remove_list) 2665 { 2666 while (list && *list && remove_list) { 2667 (void) memlist_remove(list, remove_list->address, 2668 remove_list->size); 2669 remove_list = remove_list->next; 2670 } 2671 } 2672 2673 static int 2674 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 2675 { 2676 int i = 0; 2677 2678 while (list) { 2679 /* assume 32-bit addresses */ 2680 sp->pci_phys_hi = type; 2681 sp->pci_phys_mid = 0; 2682 sp->pci_phys_low = (uint32_t)list->address; 2683 sp->pci_size_hi = 0; 2684 sp->pci_size_low = (uint32_t)list->size; 2685 2686 list = list->next; 2687 sp++, i++; 2688 } 2689 return (i); 2690 } 2691 2692 static void 2693 add_bus_available_prop(int bus) 2694 { 2695 int i, count; 2696 struct pci_phys_spec *sp; 2697 2698 /* no devinfo node - unused bus, return */ 2699 if (pci_bus_res[bus].dip == NULL) 2700 return; 2701 2702 count = memlist_count(pci_bus_res[bus].io_ports) + 2703 memlist_count(pci_bus_res[bus].mem_space) + 2704 memlist_count(pci_bus_res[bus].pmem_space); 2705 2706 if (count == 0) /* nothing available */ 2707 return; 2708 2709 sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 2710 i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_ports, 2711 PCI_ADDR_IO | PCI_REG_REL_M); 2712 i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_space, 2713 PCI_ADDR_MEM32 | PCI_REG_REL_M); 2714 i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_space, 2715 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 2716 ASSERT(i == count); 2717 2718 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 2719 "available", (int *)sp, 2720 i * sizeof (struct pci_phys_spec) / sizeof (int)); 2721 kmem_free(sp, count * sizeof (*sp)); 2722 } 2723 2724 static void 2725 alloc_res_array(void) 2726 { 2727 static int array_max = 0; 2728 int old_max; 2729 void *old_res; 2730 2731 if (array_max > pci_bios_nbus + 1) 2732 return; /* array is big enough */ 2733 2734 old_max = array_max; 2735 old_res = pci_bus_res; 2736 2737 if (array_max == 0) 2738 array_max = 16; /* start with a reasonable number */ 2739 2740 while (array_max < pci_bios_nbus + 1) 2741 array_max <<= 1; 2742 pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 2743 array_max * sizeof (struct pci_bus_resource), KM_SLEEP); 2744 2745 if (old_res) { /* copy content and free old array */ 2746 bcopy(old_res, pci_bus_res, 2747 old_max * sizeof (struct pci_bus_resource)); 2748 kmem_free(old_res, old_max * sizeof (struct pci_bus_resource)); 2749 } 2750 } 2751 2752 static void 2753 create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 2754 ushort_t deviceid) 2755 { 2756 static dev_info_t *ioapicsnode = NULL; 2757 static int numioapics = 0; 2758 dev_info_t *ioapic_node; 2759 uint64_t physaddr; 2760 uint32_t lobase, hibase = 0; 2761 2762 /* BAR 0 contains the IOAPIC's memory-mapped I/O address */ 2763 lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0); 2764 2765 /* We (and the rest of the world) only support memory-mapped IOAPICs */ 2766 if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM) 2767 return; 2768 2769 if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) 2770 hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4); 2771 2772 lobase &= PCI_BASE_M_ADDR_M; 2773 2774 physaddr = (((uint64_t)hibase) << 32) | lobase; 2775 2776 /* 2777 * Create a nexus node for all IOAPICs under the root node. 2778 */ 2779 if (ioapicsnode == NULL) { 2780 if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME, 2781 (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) { 2782 return; 2783 } 2784 (void) ndi_devi_online(ioapicsnode, 0); 2785 } 2786 2787 /* 2788 * Create a child node for this IOAPIC 2789 */ 2790 ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME, 2791 DEVI_SID_NODEID, numioapics++); 2792 if (ioapic_node == NULL) { 2793 return; 2794 } 2795 2796 /* Vendor and Device ID */ 2797 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 2798 IOAPICS_PROP_VENID, vendorid); 2799 (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 2800 IOAPICS_PROP_DEVID, deviceid); 2801 2802 /* device_type */ 2803 (void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node, 2804 "device_type", IOAPICS_DEV_TYPE); 2805 2806 /* reg */ 2807 (void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node, 2808 "reg", physaddr); 2809 } 2810 2811 /* 2812 * NOTE: For PCIe slots, the name is generated from the slot number 2813 * information obtained from Slot Capabilities register. 2814 * For non-PCIe slots, it is generated based on the slot number 2815 * information in the PCI IRQ table. 2816 */ 2817 static void 2818 pciex_slot_names_prop(dev_info_t *dip, ushort_t slot_num) 2819 { 2820 char slotprop[256]; 2821 int len; 2822 2823 bzero(slotprop, sizeof (slotprop)); 2824 2825 /* set mask to 1 as there is only one slot (i.e dev 0) */ 2826 *(uint32_t *)slotprop = 1; 2827 len = 4; 2828 (void) snprintf(slotprop + len, sizeof (slotprop) - len, "pcie%d", 2829 slot_num); 2830 len += strlen(slotprop + len) + 1; 2831 len += len % 4; 2832 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "slot-names", 2833 (int *)slotprop, len / sizeof (int)); 2834 } 2835