1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _INTEL_NHM_H 28 #define _INTEL_NHM_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #define NHM_EP_CPU 0x2c408086 35 #define NHM_WS_CPU 0x2c418086 36 #define NHM_CPU_RAS 0x2c1a8086 37 #define NHM_JF_CPU 0x2c588086 38 #define NHM_JF_CPU_RAS 0x2cda8086 39 #define NHM_WM_CPU 0x2c708086 40 #define NHM_WM_CPU_RAS 0x2d9a8086 41 42 #define NHM_INTERCONNECT "Intel QuickPath" 43 44 #define MAX_CPU_NODES 2 45 #define CPU_PCI_DEVS 6 46 #define CPU_PCI_FUNCS 6 47 48 #define MAX_BUS_NUMBER max_bus_number 49 50 #define SOCKET_BUS(cpu) (MAX_BUS_NUMBER - (cpu)) 51 #define CPU_ID_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 0, 0, 0, 0) 52 #define MC_CONTROL_RD(cpu) \ 53 nhm_pci_getl(SOCKET_BUS(cpu), 3, 0, 0x48, 0) 54 #define MC_STATUS_RD(cpu) \ 55 nhm_pci_getl(SOCKET_BUS(cpu), 3, 0, 0x4c, 0) 56 #define MC_SMI_SPARE_DIMM_ERROR_STATUS_RD(cpu) \ 57 nhm_pci_getl(SOCKET_BUS(cpu), 3, 0, 0x50, 0) 58 #define MC_CPU_RAS_RD(cpu) \ 59 nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0, 0) 60 #define MC_SCRUB_CONTROL_RD(cpu) \ 61 nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x4c, 0) 62 #define MC_SCRUB_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, \ 63 0x4c, reg); 64 #define MC_SSR_CONTROL_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x48, 0) 65 #define MC_SSR_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, 0x48, \ 66 reg); 67 #define MC_SSR_SCRUB_CONTROL_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, \ 68 0x4c, 0) 69 #define MC_RAS_ENABLES_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x50, 0) 70 #define MC_RAS_STATUS_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x54, 0) 71 #define MC_SSR_STATUS_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x60, 0) 72 #define MC_CHANNEL_MAPPER_RD(cpu) nhm_pci_getl(SOCKET_BUS(cpu), 3, 0, \ 73 0x60, 0) 74 #define MC_COR_ECC_CNT_RD(cpu, select) \ 75 nhm_pci_getl(SOCKET_BUS(cpu), 3, 2, 0x80 + ((select) * 4), 0) 76 #define MC_CHANNEL_RANK_PRESENT_RD(cpu, channel) \ 77 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 0, 0x7c, 0) 78 #define MC_DOD_RD(cpu, channel, select) \ 79 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 1, 0x48 + ((select) * 4), 0) 80 #define MC_SAG_RD(cpu, channel, select) \ 81 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 1, 0x80 + ((select) * 4), 0) 82 #define MC_RIR_LIMIT_RD(cpu, channel, select) \ 83 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 2, 0x40 + ((select) * 4), 0) 84 #define MC_RIR_WAY_RD(cpu, channel, select) \ 85 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 2, 0x80 + ((select) * 4), 0) 86 #define MC_CHANNEL_DIMM_INIT_PARAMS_RD(cpu, channel) \ 87 nhm_pci_getl(SOCKET_BUS(cpu), (channel) + 4, 0, 0x58, 0) 88 #define SAD_DRAM_RULE_RD(cpu, rule) \ 89 nhm_pci_getl(SOCKET_BUS(cpu), 0, 1, 0x80 + (4 * (rule)), 0) 90 #define SAD_INTERLEAVE_LIST_RD(cpu, rule) \ 91 nhm_pci_getl(SOCKET_BUS(cpu), 0, 1, 0xc0 + (4 * (rule)), 0) 92 #define TAD_DRAM_RULE_RD(cpu, rule) \ 93 nhm_pci_getl(SOCKET_BUS(cpu), 3, 1, 0x80 + (4 * (rule)), 0) 94 #define TAD_INTERLEAVE_LIST_RD(cpu, rule) \ 95 nhm_pci_getl(SOCKET_BUS(cpu), 3, 1, 0xc0 + (4 * (rule)), 0) 96 #define MC_DIMM_CLK_RATIO_STATUS(cpu) \ 97 nhm_pci_getl(SOCKET_BUS(cpu), 3, 4, 0x50, 0) 98 99 /* 100 * MC_CONTROL 101 */ 102 #define MC_CONTROL_CHANNEL_ACTIVE(reg, channel) \ 103 ((reg) & (1 << (8 + (channel))) != 0) 104 #define MC_CONTROL_ECCEN(reg) (((reg) >> 1) & 1) 105 #define MC_CONTROL_CLOSED_PAGE(reg) ((reg) & 1) 106 /* 107 * MC_STATUS 108 */ 109 #define CHANNEL_DISABLED(reg, channel) ((reg) & (1 << (channel))) 110 #define WS_ECC_ENABLED 0x10 111 /* 112 * MC_CHANNEL_DIMM_INIT_PARAMS 113 */ 114 #define THREE_DIMMS_PRESENT (1 << 24) /* not quad rank */ 115 #define SINGLE_QUAD_RANK_PRESENT (1 << 23) 116 #define QUAD_RANK_PRESENT (1 << 22) /* 1 or 2 quad rank dimms */ 117 #define REGISTERED_DIMM (1 << 15) 118 119 /* 120 * MC_DOD_CH 121 */ 122 #define RANKOFFSET(reg) (((reg) >> 10) & 7) 123 #define DIMMPRESENT(reg) (((reg) & (1 << 9)) != 0) 124 #define NUMBANK(reg) (((reg) & (3 << 7)) == 0 ? 4 : (((reg) >> 7) & 3) * 8) 125 #define NUMRANK(reg) (((reg) & (3 << 5)) == 0 ? 1 : (((reg) >> 5) & 3) * 2) 126 #define NUMROW(reg) ((((reg) >> 2) & 7) + 12) 127 #define NUMCOL(reg) (((reg) & 3) + 10) 128 #define DIMMWIDTH 8 129 #define DIMMSIZE(reg) ((1ULL << (NUMCOL(reg) + NUMROW(reg))) * NUMRANK(reg) \ 130 * NUMBANK(reg) * DIMMWIDTH) 131 132 /* 133 * MC_SAG_CH 134 */ 135 #define DIVBY3(reg) (((reg) >> 27) & 1) /* 3 or 6 way interleave */ 136 #define REMOVE_6(reg) (((reg) >> 24) & 1) 137 #define REMOVE_7(reg) (((reg) >> 25) & 1) 138 #define REMOVE_8(reg) (((reg) >> 26) & 1) 139 #define CH_ADDRESS_OFFSET(reg) \ 140 ((int64_t)(((uint64_t)(reg) & 0x00ffffff) << 40) >> 40) 141 /* 142 * MC_RIR_LIMIT_CH 143 */ 144 #define RIR_LIMIT(reg) ((((uint64_t)(reg) & 0x000003ff) + 1) << 28) 145 /* 146 * MC_RIR_WAY_CH 147 */ 148 #define RIR_OFFSET(reg) ((int64_t)(((uint64_t)(reg) & 0x3ff0) << 50) >> 54) 149 #define RIR_RANK(reg) ((reg) & 0xf) 150 151 #define MAX_RIR_WAY 4 152 153 /* 154 * MC_RAS_ENABLES 155 */ 156 #define RAS_LOCKSTEP_ENABLE(reg) (((reg) & 2) != 0) 157 #define RAS_MIRROR_MEM_ENABLE(reg) (((reg) & 1) != 0) 158 /* 159 * MC_RAS_STATUS 160 */ 161 #define REDUNDANCY_LOSS(reg) (((reg) & 1) != 0) 162 /* 163 * MC_SSRSTATUS 164 */ 165 #define SPAREING_IN_PROGRESS(reg) (((reg) & 2) != 0) 166 #define SPAREING_COMPLETE(reg) (((reg) & 1) != 0) 167 168 /* 169 * MC_SSR_CONTROL 170 */ 171 #define SSR_MODE(reg) ((reg) & 3) 172 #define SSR_IDLE 0 173 #define SSR_SCRUB 1 174 #define SSR_SPARE 2 175 #define DEMAND_SCRUB_ENABLE (1 << 6) 176 /* 177 * MC_SCRUB_CONTROL 178 */ 179 #define STARTSCRUB (1 << 24) 180 /* 181 * MC_DIMM_CLK_RATIO_STATUS 182 */ 183 #define MAX_DIMM_CLK_RATIO(reg) (((reg) >> 24) & 0x1f) 184 /* 185 * MC_SMI_SPARE_DIMM_ERROR_STATUS_RD 186 */ 187 #define REDUNDANCY_LOSS_FAILING_DIMM(status) (((status) >> 12) & 3) 188 #define DIMM_ERROR_OVERFLOW_STATUS(status) ((status) & 0xfff) 189 190 #define MAX_MEMORY_CONTROLLERS MAX_CPU_NODES 191 #define CHANNELS_PER_MEMORY_CONTROLLER 3 192 #define MAX_DIMMS_PER_CHANNEL 3 193 194 /* 195 * SAD_DRAM_RULE 196 */ 197 #define SAD_DRAM_LIMIT(sad) ((((uint64_t)(sad) & 0x000fffc0ULL) + 0x40) << 20) 198 #define SAD_DRAM_MODE(sad) (((sad) >> 1) & 3) 199 #define SAD_DRAM_RULE_ENABLE(sad) ((sad) & 1) 200 201 #define SAD_INTERLEAVE(list, num) (((list) >> ((num) * 4)) & 0x3) 202 #define INTERLEAVE_NWAY 8 203 #define MAX_SAD_DRAM_RULE 8 204 205 /* 206 * TAD_DRAM_RULE 207 */ 208 #define TAD_DRAM_LIMIT(tad) ((((uint64_t)(tad) & 0x000fffc0ULL) + 0x40) << 20) 209 #define TAD_DRAM_MODE(tad) (((tad) >> 1) & 3) 210 #define TAD_DRAM_RULE_ENABLE(tad) ((tad) & 1) 211 212 #define TAD_INTERLEAVE(list, channel) (((list) >> ((channel) * 4)) & 3) 213 214 #define MAX_TAD_DRAM_RULE 8 215 216 #define VRANK_SZ 0x40000000 217 218 /* 219 * MC_CHANNEL_MAPPER 220 */ 221 #define CHANNEL_MAP(reg, channel, write) (((reg) >> ((channel) * 6 + \ 222 ((write) ? 0 : 3))) & 7) 223 224 extern int max_bus_number; 225 226 #ifdef __cplusplus 227 } 228 #endif 229 230 #endif /* _INTEL_NHM_H */ 231