1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright (c) 2019, Joyent, Inc. 24 */ 25 26 /* 27 * PCI configurator (pcicfg) 28 */ 29 30 #include <sys/sysmacros.h> 31 #include <sys/conf.h> 32 #include <sys/kmem.h> 33 #include <sys/debug.h> 34 #include <sys/modctl.h> 35 #include <sys/autoconf.h> 36 #include <sys/hwconf.h> 37 #include <sys/pcie.h> 38 #include <sys/pcie_impl.h> 39 #include <sys/pci_cap.h> 40 #include <sys/ddi.h> 41 #include <sys/sunndi.h> 42 #include <sys/hotplug/pci/pcicfg.h> 43 #include <sys/ndi_impldefs.h> 44 #include <sys/pci_cfgacc.h> 45 #include <sys/pcie_impl.h> 46 47 /* 48 * ************************************************************************ 49 * *** Implementation specific local data structures/definitions. *** 50 * ************************************************************************ 51 */ 52 53 static int pcicfg_start_devno = 0; /* for Debug only */ 54 55 #define PCICFG_MAX_ARI_FUNCTION 256 56 57 #define PCICFG_NODEVICE 42 58 #define PCICFG_NOMEMORY 43 59 #define PCICFG_NOMULTI 44 60 #define PCICFG_NORESRC 45 61 62 #define PCICFG_HIADDR(n) ((uint32_t)(((uint64_t)(n) & \ 63 0xFFFFFFFF00000000ULL)>> 32)) 64 #define PCICFG_LOADDR(n) ((uint32_t)((uint64_t)(n) & 0x00000000FFFFFFFF)) 65 #define PCICFG_LADDR(lo, hi) (((uint64_t)(hi) << 32) | (uint32_t)(lo)) 66 67 #define PCICFG_HIWORD(n) ((uint16_t)(((uint32_t)(n) & 0xFFFF0000)>> 16)) 68 #define PCICFG_LOWORD(n) ((uint16_t)((uint32_t)(n) & 0x0000FFFF)) 69 #define PCICFG_HIBYTE(n) ((uint8_t)(((uint16_t)(n) & 0xFF00)>> 8)) 70 #define PCICFG_LOBYTE(n) ((uint8_t)((uint16_t)(n) & 0x00FF)) 71 72 #define PCICFG_ROUND_UP(addr, gran) ((uintptr_t)((gran+addr-1)&(~(gran-1)))) 73 #define PCICFG_ROUND_DOWN(addr, gran) ((uintptr_t)((addr) & ~(gran-1))) 74 75 #define PCICFG_MEMGRAN 0x100000 76 #define PCICFG_IOGRAN 0x1000 77 #define PCICFG_4GIG_LIMIT 0xFFFFFFFFUL 78 79 #define PCICFG_MEM_MULT 4 80 #define PCICFG_IO_MULT 4 81 #define PCICFG_RANGE_LEN 3 /* Number of range entries */ 82 83 static int pcicfg_slot_busnums = 8; 84 static int pcicfg_slot_memsize = 32 * PCICFG_MEMGRAN; /* 32MB per slot */ 85 static int pcicfg_slot_pf_memsize = 32 * PCICFG_MEMGRAN; /* 32MB per slot */ 86 static int pcicfg_slot_iosize = 64 * PCICFG_IOGRAN; /* 64K per slot */ 87 static int pcicfg_sec_reset_delay = 3000000; 88 static int pcicfg_do_legacy_props = 1; /* create legacy compatible prop */ 89 90 typedef struct hole hole_t; 91 92 struct hole { 93 uint64_t start; 94 uint64_t len; 95 hole_t *next; 96 }; 97 98 typedef struct pcicfg_phdl pcicfg_phdl_t; 99 100 struct pcicfg_phdl { 101 102 dev_info_t *dip; /* Associated with the bridge */ 103 dev_info_t *top_dip; /* top node of the attach point */ 104 pcicfg_phdl_t *next; 105 106 /* non-prefetchable memory space */ 107 uint64_t memory_base; /* Memory base for this attach point */ 108 uint64_t memory_last; 109 uint64_t memory_len; 110 111 /* prefetchable memory space */ 112 uint64_t pf_memory_base; /* PF Memory base for this Connection */ 113 uint64_t pf_memory_last; 114 uint64_t pf_memory_len; 115 116 /* io space */ 117 uint32_t io_base; /* I/O base for this attach point */ 118 uint32_t io_last; 119 uint32_t io_len; 120 121 int error; 122 uint_t highest_bus; /* Highest bus seen on the probe */ 123 124 hole_t mem_hole; /* Memory hole linked list. */ 125 hole_t pf_mem_hole; /* PF Memory hole linked list. */ 126 hole_t io_hole; /* IO hole linked list */ 127 128 ndi_ra_request_t mem_req; /* allocator request for memory */ 129 ndi_ra_request_t pf_mem_req; /* allocator request for PF memory */ 130 ndi_ra_request_t io_req; /* allocator request for I/O */ 131 }; 132 133 struct pcicfg_standard_prop_entry { 134 uchar_t *name; 135 uint_t config_offset; 136 uint_t size; 137 }; 138 139 140 struct pcicfg_name_entry { 141 uint32_t class_code; 142 char *name; 143 }; 144 145 struct pcicfg_find_ctrl { 146 uint_t device; 147 uint_t function; 148 dev_info_t *dip; 149 }; 150 151 /* 152 * List of Indirect Config Map Devices. At least the intent of the 153 * design is to look for a device in this list during the configure 154 * operation, and if the device is listed here, then it is a nontransparent 155 * bridge, hence load the driver and avail the config map services from 156 * the driver. Class and Subclass should be as defined in the PCI specs 157 * ie. class is 0x6, and subclass is 0x9. 158 */ 159 static struct { 160 uint8_t mem_range_bar_offset; 161 uint8_t io_range_bar_offset; 162 uint8_t prefetch_mem_range_bar_offset; 163 } pcicfg_indirect_map_devs[] = { 164 PCI_CONF_BASE3, PCI_CONF_BASE2, PCI_CONF_BASE3, 165 0, 0, 0, 166 }; 167 168 #define PCICFG_MAKE_REG_HIGH(busnum, devnum, funcnum, register)\ 169 (\ 170 ((ulong_t)(busnum & 0xff) << 16) |\ 171 ((ulong_t)(devnum & 0x1f) << 11) |\ 172 ((ulong_t)(funcnum & 0x7) << 8) |\ 173 ((ulong_t)(register & 0x3f))) 174 175 /* 176 * debug macros: 177 */ 178 #if defined(DEBUG) 179 extern void prom_printf(const char *, ...); 180 181 /* 182 * Following values are defined for this debug flag. 183 * 184 * 1 = dump configuration header only. 185 * 2 = dump generic debug data only (no config header dumped) 186 * 3 = dump everything (both 1 and 2) 187 */ 188 int pcicfg_debug = 0; 189 190 static void debug(char *, uintptr_t, uintptr_t, 191 uintptr_t, uintptr_t, uintptr_t); 192 193 #define DEBUG0(fmt)\ 194 debug(fmt, 0, 0, 0, 0, 0); 195 #define DEBUG1(fmt, a1)\ 196 debug(fmt, (uintptr_t)(a1), 0, 0, 0, 0); 197 #define DEBUG2(fmt, a1, a2)\ 198 debug(fmt, (uintptr_t)(a1), (uintptr_t)(a2), 0, 0, 0); 199 #define DEBUG3(fmt, a1, a2, a3)\ 200 debug(fmt, (uintptr_t)(a1), (uintptr_t)(a2),\ 201 (uintptr_t)(a3), 0, 0); 202 #define DEBUG4(fmt, a1, a2, a3, a4)\ 203 debug(fmt, (uintptr_t)(a1), (uintptr_t)(a2),\ 204 (uintptr_t)(a3), (uintptr_t)(a4), 0); 205 #define DEBUG5(fmt, a1, a2, a3, a4, a5)\ 206 debug(fmt, (uintptr_t)(a1), (uintptr_t)(a2),\ 207 (uintptr_t)(a3), (uintptr_t)(a4), (uintptr_t)(a5)); 208 #else 209 #define DEBUG0(fmt) 210 #define DEBUG1(fmt, a1) 211 #define DEBUG2(fmt, a1, a2) 212 #define DEBUG3(fmt, a1, a2, a3) 213 #define DEBUG4(fmt, a1, a2, a3, a4) 214 #define DEBUG5(fmt, a1, a2, a3, a4, a5) 215 #endif 216 217 /* 218 * forward declarations for routines defined in this module (called here) 219 */ 220 221 static int pcicfg_add_config_reg(dev_info_t *, 222 uint_t, uint_t, uint_t); 223 static int pcicfg_probe_children(dev_info_t *, uint_t, uint_t, uint_t, 224 uint_t *, pcicfg_flags_t, boolean_t); 225 static int pcicfg_match_dev(dev_info_t *, void *); 226 static dev_info_t *pcicfg_devi_find(dev_info_t *, uint_t, uint_t); 227 static pcicfg_phdl_t *pcicfg_find_phdl(dev_info_t *); 228 static pcicfg_phdl_t *pcicfg_create_phdl(dev_info_t *); 229 static int pcicfg_destroy_phdl(dev_info_t *); 230 static int pcicfg_sum_resources(dev_info_t *, void *); 231 static int pcicfg_device_assign(dev_info_t *); 232 static int pcicfg_bridge_assign(dev_info_t *, void *); 233 static int pcicfg_device_assign_readonly(dev_info_t *); 234 static int pcicfg_free_resources(dev_info_t *, pcicfg_flags_t); 235 static void pcicfg_setup_bridge(pcicfg_phdl_t *, ddi_acc_handle_t); 236 static void pcicfg_update_bridge(pcicfg_phdl_t *, ddi_acc_handle_t); 237 static int pcicfg_update_assigned_prop(dev_info_t *, pci_regspec_t *); 238 static void pcicfg_device_on(ddi_acc_handle_t); 239 static void pcicfg_device_off(ddi_acc_handle_t); 240 static int pcicfg_set_busnode_props(dev_info_t *, uint8_t); 241 static int pcicfg_free_bridge_resources(dev_info_t *); 242 static int pcicfg_free_device_resources(dev_info_t *); 243 static int pcicfg_teardown_device(dev_info_t *, pcicfg_flags_t, boolean_t); 244 static void pcicfg_reparent_node(dev_info_t *, dev_info_t *); 245 static int pcicfg_config_setup(dev_info_t *, ddi_acc_handle_t *); 246 static void pcicfg_config_teardown(ddi_acc_handle_t *); 247 static void pcicfg_get_mem(pcicfg_phdl_t *, uint32_t, uint64_t *); 248 static void pcicfg_get_pf_mem(pcicfg_phdl_t *, uint32_t, uint64_t *); 249 static void pcicfg_get_io(pcicfg_phdl_t *, uint32_t, uint32_t *); 250 static int pcicfg_update_ranges_prop(dev_info_t *, ppb_ranges_t *); 251 static int pcicfg_configure_ntbridge(dev_info_t *, uint_t, uint_t); 252 static uint_t pcicfg_ntbridge_child(dev_info_t *); 253 static uint_t pcicfg_get_ntbridge_child_range(dev_info_t *, uint64_t *, 254 uint64_t *, uint_t); 255 static int pcicfg_is_ntbridge(dev_info_t *); 256 static int pcicfg_ntbridge_allocate_resources(dev_info_t *); 257 static int pcicfg_ntbridge_configure_done(dev_info_t *); 258 static int pcicfg_ntbridge_program_child(dev_info_t *); 259 static uint_t pcicfg_ntbridge_unconfigure(dev_info_t *); 260 static int pcicfg_ntbridge_unconfigure_child(dev_info_t *, uint_t); 261 static void pcicfg_free_hole(hole_t *); 262 static uint64_t pcicfg_alloc_hole(hole_t *, uint64_t *, uint32_t); 263 static int pcicfg_device_type(dev_info_t *, ddi_acc_handle_t *); 264 static void pcicfg_update_phdl(dev_info_t *, uint8_t, uint8_t); 265 static int pcicfg_get_cap(ddi_acc_handle_t, uint8_t); 266 static uint8_t pcicfg_get_nslots(dev_info_t *, ddi_acc_handle_t); 267 static int pcicfg_pcie_dev(dev_info_t *, ddi_acc_handle_t); 268 static int pcicfg_pcie_device_type(dev_info_t *, ddi_acc_handle_t); 269 static int pcicfg_pcie_port_type(dev_info_t *, ddi_acc_handle_t); 270 static int pcicfg_probe_bridge(dev_info_t *, ddi_acc_handle_t, uint_t, 271 uint_t *, boolean_t); 272 static int pcicfg_find_resource_end(dev_info_t *, void *); 273 static boolean_t is_pcie_fabric(dev_info_t *); 274 275 static int pcicfg_populate_reg_props(dev_info_t *, ddi_acc_handle_t); 276 static int pcicfg_populate_props_from_bar(dev_info_t *, ddi_acc_handle_t); 277 static int pcicfg_update_assigned_prop_value(dev_info_t *, uint32_t, 278 uint32_t, uint32_t, uint_t); 279 static int pcicfg_ari_configure(dev_info_t *); 280 281 #ifdef DEBUG 282 static void pcicfg_dump_common_config(ddi_acc_handle_t config_handle); 283 static void pcicfg_dump_device_config(ddi_acc_handle_t); 284 static void pcicfg_dump_bridge_config(ddi_acc_handle_t config_handle); 285 static uint64_t pcicfg_unused_space(hole_t *, uint32_t *); 286 287 #define PCICFG_DUMP_COMMON_CONFIG(hdl) (void)pcicfg_dump_common_config(hdl) 288 #define PCICFG_DUMP_DEVICE_CONFIG(hdl) (void)pcicfg_dump_device_config(hdl) 289 #define PCICFG_DUMP_BRIDGE_CONFIG(hdl) (void)pcicfg_dump_bridge_config(hdl) 290 #else 291 #define PCICFG_DUMP_COMMON_CONFIG(handle) 292 #define PCICFG_DUMP_DEVICE_CONFIG(handle) 293 #define PCICFG_DUMP_BRIDGE_CONFIG(handle) 294 #endif 295 296 static kmutex_t pcicfg_list_mutex; /* Protects the probe handle list */ 297 static pcicfg_phdl_t *pcicfg_phdl_list = NULL; 298 299 #ifndef _DONT_USE_1275_GENERIC_NAMES 300 /* 301 * Class code table 302 */ 303 static struct pcicfg_name_entry pcicfg_class_lookup [] = { 304 305 { 0x001, "display" }, 306 { 0x100, "scsi" }, 307 { 0x101, "ide" }, 308 { 0x102, "fdc" }, 309 { 0x103, "ipi" }, 310 { 0x104, "raid" }, 311 { 0x105, "ata" }, 312 { 0x106, "sata" }, 313 { 0x200, "ethernet" }, 314 { 0x201, "token-ring" }, 315 { 0x202, "fddi" }, 316 { 0x203, "atm" }, 317 { 0x204, "isdn" }, 318 { 0x206, "mcd" }, 319 { 0x300, "display" }, 320 { 0x400, "video" }, 321 { 0x401, "sound" }, 322 { 0x500, "memory" }, 323 { 0x501, "flash" }, 324 { 0x600, "host" }, 325 { 0x601, "isa" }, 326 { 0x602, "eisa" }, 327 { 0x603, "mca" }, 328 { 0x604, "pci" }, 329 { 0x605, "pcmcia" }, 330 { 0x606, "nubus" }, 331 { 0x607, "cardbus" }, 332 { 0x609, "pci" }, 333 { 0x60a, "ib-pci" }, 334 { 0x700, "serial" }, 335 { 0x701, "parallel" }, 336 { 0x800, "interrupt-controller" }, 337 { 0x801, "dma-controller" }, 338 { 0x802, "timer" }, 339 { 0x803, "rtc" }, 340 { 0x900, "keyboard" }, 341 { 0x901, "pen" }, 342 { 0x902, "mouse" }, 343 { 0xa00, "dock" }, 344 { 0xb00, "cpu" }, 345 { 0xb01, "cpu" }, 346 { 0xb02, "cpu" }, 347 { 0xb10, "cpu" }, 348 { 0xb20, "cpu" }, 349 { 0xb30, "cpu" }, 350 { 0xb40, "coproc" }, 351 { 0xc00, "firewire" }, 352 { 0xc01, "access-bus" }, 353 { 0xc02, "ssa" }, 354 { 0xc03, "usb" }, 355 { 0xc04, "fibre-channel" }, 356 { 0xc05, "smbus" }, 357 { 0xc06, "ib" }, 358 { 0xd00, "irda" }, 359 { 0xd01, "ir" }, 360 { 0xd10, "rf" }, 361 { 0xd11, "btooth" }, 362 { 0xd12, "brdband" }, 363 { 0xd20, "802.11a" }, 364 { 0xd21, "802.11b" }, 365 { 0xe00, "i2o" }, 366 { 0xf01, "tv" }, 367 { 0xf02, "audio" }, 368 { 0xf03, "voice" }, 369 { 0xf04, "data" }, 370 { 0, 0 } 371 }; 372 #endif /* _DONT_USE_1275_GENERIC_NAMES */ 373 374 /* 375 * Module control operations 376 */ 377 378 extern struct mod_ops mod_miscops; 379 380 static struct modlmisc modlmisc = { 381 &mod_miscops, /* Type of module */ 382 "PCI configurator" 383 }; 384 385 static struct modlinkage modlinkage = { 386 MODREV_1, (void *)&modlmisc, NULL 387 }; 388 389 390 #ifdef DEBUG 391 392 static void 393 pcicfg_dump_common_config(ddi_acc_handle_t config_handle) 394 { 395 if ((pcicfg_debug & 1) == 0) 396 return; 397 prom_printf(" Vendor ID = [0x%x]\n", 398 pci_config_get16(config_handle, PCI_CONF_VENID)); 399 prom_printf(" Device ID = [0x%x]\n", 400 pci_config_get16(config_handle, PCI_CONF_DEVID)); 401 prom_printf(" Command REG = [0x%x]\n", 402 pci_config_get16(config_handle, PCI_CONF_COMM)); 403 prom_printf(" Status REG = [0x%x]\n", 404 pci_config_get16(config_handle, PCI_CONF_STAT)); 405 prom_printf(" Revision ID = [0x%x]\n", 406 pci_config_get8(config_handle, PCI_CONF_REVID)); 407 prom_printf(" Prog Class = [0x%x]\n", 408 pci_config_get8(config_handle, PCI_CONF_PROGCLASS)); 409 prom_printf(" Dev Class = [0x%x]\n", 410 pci_config_get8(config_handle, PCI_CONF_SUBCLASS)); 411 prom_printf(" Base Class = [0x%x]\n", 412 pci_config_get8(config_handle, PCI_CONF_BASCLASS)); 413 prom_printf(" Device ID = [0x%x]\n", 414 pci_config_get8(config_handle, PCI_CONF_CACHE_LINESZ)); 415 prom_printf(" Header Type = [0x%x]\n", 416 pci_config_get8(config_handle, PCI_CONF_HEADER)); 417 prom_printf(" BIST = [0x%x]\n", 418 pci_config_get8(config_handle, PCI_CONF_BIST)); 419 prom_printf(" BASE 0 = [0x%x]\n", 420 pci_config_get32(config_handle, PCI_CONF_BASE0)); 421 prom_printf(" BASE 1 = [0x%x]\n", 422 pci_config_get32(config_handle, PCI_CONF_BASE1)); 423 424 } 425 426 static void 427 pcicfg_dump_device_config(ddi_acc_handle_t config_handle) 428 { 429 if ((pcicfg_debug & 1) == 0) 430 return; 431 pcicfg_dump_common_config(config_handle); 432 433 prom_printf(" BASE 2 = [0x%x]\n", 434 pci_config_get32(config_handle, PCI_CONF_BASE2)); 435 prom_printf(" BASE 3 = [0x%x]\n", 436 pci_config_get32(config_handle, PCI_CONF_BASE3)); 437 prom_printf(" BASE 4 = [0x%x]\n", 438 pci_config_get32(config_handle, PCI_CONF_BASE4)); 439 prom_printf(" BASE 5 = [0x%x]\n", 440 pci_config_get32(config_handle, PCI_CONF_BASE5)); 441 prom_printf(" Cardbus CIS = [0x%x]\n", 442 pci_config_get32(config_handle, PCI_CONF_CIS)); 443 prom_printf(" Sub VID = [0x%x]\n", 444 pci_config_get16(config_handle, PCI_CONF_SUBVENID)); 445 prom_printf(" Sub SID = [0x%x]\n", 446 pci_config_get16(config_handle, PCI_CONF_SUBSYSID)); 447 prom_printf(" ROM = [0x%x]\n", 448 pci_config_get32(config_handle, PCI_CONF_ROM)); 449 prom_printf(" I Line = [0x%x]\n", 450 pci_config_get8(config_handle, PCI_CONF_ILINE)); 451 prom_printf(" I Pin = [0x%x]\n", 452 pci_config_get8(config_handle, PCI_CONF_IPIN)); 453 prom_printf(" Max Grant = [0x%x]\n", 454 pci_config_get8(config_handle, PCI_CONF_MIN_G)); 455 prom_printf(" Max Latent = [0x%x]\n", 456 pci_config_get8(config_handle, PCI_CONF_MAX_L)); 457 } 458 459 static void 460 pcicfg_dump_bridge_config(ddi_acc_handle_t config_handle) 461 { 462 if ((pcicfg_debug & 1) == 0) 463 return; 464 pcicfg_dump_common_config(config_handle); 465 466 prom_printf("........................................\n"); 467 468 prom_printf(" Pri Bus = [0x%x]\n", 469 pci_config_get8(config_handle, PCI_BCNF_PRIBUS)); 470 prom_printf(" Sec Bus = [0x%x]\n", 471 pci_config_get8(config_handle, PCI_BCNF_SECBUS)); 472 prom_printf(" Sub Bus = [0x%x]\n", 473 pci_config_get8(config_handle, PCI_BCNF_SUBBUS)); 474 prom_printf(" Latency = [0x%x]\n", 475 pci_config_get8(config_handle, PCI_BCNF_LATENCY_TIMER)); 476 prom_printf(" I/O Base LO = [0x%x]\n", 477 pci_config_get8(config_handle, PCI_BCNF_IO_BASE_LOW)); 478 prom_printf(" I/O Lim LO = [0x%x]\n", 479 pci_config_get8(config_handle, PCI_BCNF_IO_LIMIT_LOW)); 480 prom_printf(" Sec. Status = [0x%x]\n", 481 pci_config_get16(config_handle, PCI_BCNF_SEC_STATUS)); 482 prom_printf(" Mem Base = [0x%x]\n", 483 pci_config_get16(config_handle, PCI_BCNF_MEM_BASE)); 484 prom_printf(" Mem Limit = [0x%x]\n", 485 pci_config_get16(config_handle, PCI_BCNF_MEM_LIMIT)); 486 prom_printf(" PF Mem Base = [0x%x]\n", 487 pci_config_get16(config_handle, PCI_BCNF_PF_BASE_LOW)); 488 prom_printf(" PF Mem Lim = [0x%x]\n", 489 pci_config_get16(config_handle, PCI_BCNF_PF_LIMIT_LOW)); 490 prom_printf(" PF Base HI = [0x%x]\n", 491 pci_config_get32(config_handle, PCI_BCNF_PF_BASE_HIGH)); 492 prom_printf(" PF Lim HI = [0x%x]\n", 493 pci_config_get32(config_handle, PCI_BCNF_PF_LIMIT_HIGH)); 494 prom_printf(" I/O Base HI = [0x%x]\n", 495 pci_config_get16(config_handle, PCI_BCNF_IO_BASE_HI)); 496 prom_printf(" I/O Lim HI = [0x%x]\n", 497 pci_config_get16(config_handle, PCI_BCNF_IO_LIMIT_HI)); 498 prom_printf(" ROM addr = [0x%x]\n", 499 pci_config_get32(config_handle, PCI_BCNF_ROM)); 500 prom_printf(" Intr Line = [0x%x]\n", 501 pci_config_get8(config_handle, PCI_BCNF_ILINE)); 502 prom_printf(" Intr Pin = [0x%x]\n", 503 pci_config_get8(config_handle, PCI_BCNF_IPIN)); 504 prom_printf(" Bridge Ctrl = [0x%x]\n", 505 pci_config_get16(config_handle, PCI_BCNF_BCNTRL)); 506 } 507 #endif 508 509 int 510 _init() 511 { 512 DEBUG0(" PCI configurator installed\n"); 513 mutex_init(&pcicfg_list_mutex, NULL, MUTEX_DRIVER, NULL); 514 return (mod_install(&modlinkage)); 515 } 516 517 int 518 _fini(void) 519 { 520 int error; 521 522 error = mod_remove(&modlinkage); 523 if (error != 0) { 524 return (error); 525 } 526 mutex_destroy(&pcicfg_list_mutex); 527 return (0); 528 } 529 530 int 531 _info(struct modinfo *modinfop) 532 { 533 return (mod_info(&modlinkage, modinfop)); 534 } 535 536 /* 537 * In the following functions ndi_devi_enter() without holding the 538 * parent dip is sufficient. This is because pci dr is driven through 539 * opens on the nexus which is in the device tree path above the node 540 * being operated on, and implicitly held due to the open. 541 */ 542 543 /* 544 * This entry point is called to configure a device (and 545 * all its children) on the given bus. It is called when 546 * a new device is added to the PCI domain. This routine 547 * will create the device tree and program the devices 548 * registers. 549 */ 550 int 551 pcicfg_configure(dev_info_t *devi, uint_t device, uint_t function, 552 pcicfg_flags_t flags) 553 { 554 uint_t bus; 555 int len; 556 int func; 557 dev_info_t *attach_point; 558 pci_bus_range_t pci_bus_range; 559 int rv; 560 int circ; 561 uint_t highest_bus, visited = 0; 562 int ari_mode = B_FALSE; 563 int max_function = PCI_MAX_FUNCTIONS; 564 int trans_device; 565 dev_info_t *new_device; 566 boolean_t is_pcie; 567 568 if (flags == PCICFG_FLAG_ENABLE_ARI) 569 return (pcicfg_ari_configure(devi)); 570 571 /* 572 * Start probing at the device specified in "device" on the 573 * "bus" specified. 574 */ 575 len = sizeof (pci_bus_range_t); 576 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, devi, 0, "bus-range", 577 (caddr_t)&pci_bus_range, &len) != DDI_SUCCESS) { 578 DEBUG0("no bus-range property\n"); 579 return (PCICFG_FAILURE); 580 } 581 582 bus = pci_bus_range.lo; /* primary bus number of this bus node */ 583 584 attach_point = devi; 585 586 is_pcie = is_pcie_fabric(devi); 587 588 ndi_devi_enter(devi, &circ); 589 for (func = 0; func < max_function; ) { 590 591 if ((function != PCICFG_ALL_FUNC) && (function != func)) 592 goto next; 593 594 if (ari_mode) 595 trans_device = func >> 3; 596 else 597 trans_device = device; 598 599 switch (rv = pcicfg_probe_children(attach_point, 600 bus, trans_device, func & 7, &highest_bus, 601 flags, is_pcie)) { 602 case PCICFG_NORESRC: 603 case PCICFG_FAILURE: 604 DEBUG2("configure failed: bus [0x%x] device " 605 "[0x%x]\n", bus, trans_device); 606 goto cleanup; 607 case PCICFG_NODEVICE: 608 DEBUG3("no device : bus " 609 "[0x%x] slot [0x%x] func [0x%x]\n", 610 bus, trans_device, func &7); 611 612 /* 613 * When walking the list of ARI functions 614 * we don't expect to see a non-present 615 * function, so we will stop walking 616 * the function list. 617 */ 618 if (ari_mode == B_TRUE) 619 break; 620 621 if (func) 622 goto next; 623 break; 624 default: 625 DEBUG3("configure: bus => [%d] " 626 "slot => [%d] func => [%d]\n", 627 bus, trans_device, func & 7); 628 break; 629 } 630 631 if (rv != PCICFG_SUCCESS) 632 break; 633 634 if ((new_device = pcicfg_devi_find(attach_point, 635 trans_device, func & 7)) == NULL) { 636 DEBUG0("Did'nt find device node just created\n"); 637 goto cleanup; 638 } 639 640 /* 641 * Up until now, we have detected a non transparent bridge 642 * (ntbridge) as a part of the generic probe code and 643 * configured only one configuration 644 * header which is the side facing the host bus. 645 * Now, configure the other side and create children. 646 * 647 * In order to make the process simpler, lets load the device 648 * driver for the non transparent bridge as this is a 649 * Solaris bundled driver, and use its configuration map 650 * services rather than programming it here. 651 * If the driver is not bundled into Solaris, it must be 652 * first loaded and configured before performing any 653 * hotplug operations. 654 * 655 * This not only makes the code here simpler but also more 656 * generic. 657 * 658 * So here we go. 659 */ 660 661 /* 662 * check if this is a bridge in nontransparent mode 663 */ 664 if (pcicfg_is_ntbridge(new_device) != DDI_FAILURE) { 665 DEBUG0("pcicfg: Found nontransparent bridge.\n"); 666 667 rv = pcicfg_configure_ntbridge(new_device, bus, 668 trans_device); 669 if (rv != PCICFG_SUCCESS) 670 goto cleanup; 671 } 672 673 /* 674 * Note that we've successfully gone through and visited at 675 * least one node. 676 */ 677 visited++; 678 next: 679 /* 680 * Determine if ARI Forwarding should be enabled. 681 */ 682 if (func == 0) { 683 if ((pcie_ari_supported(devi) 684 == PCIE_ARI_FORW_SUPPORTED) && 685 (pcie_ari_device(new_device) == PCIE_ARI_DEVICE)) { 686 if (pcie_ari_enable(devi) == DDI_SUCCESS) { 687 (void) ddi_prop_create(DDI_DEV_T_NONE, 688 devi, DDI_PROP_CANSLEEP, 689 "ari-enabled", NULL, 0); 690 691 ari_mode = B_TRUE; 692 max_function = PCICFG_MAX_ARI_FUNCTION; 693 } 694 } 695 } 696 if (ari_mode == B_TRUE) { 697 int next_function; 698 699 DEBUG0("Next Function - ARI Device\n"); 700 if (pcie_ari_get_next_function(new_device, 701 &next_function) != DDI_SUCCESS) 702 goto cleanup; 703 704 /* 705 * Check if there are more functions to probe. 706 */ 707 if (next_function == 0) { 708 DEBUG0("Next Function - " 709 "No more ARI Functions\n"); 710 break; 711 } 712 func = next_function; 713 } else { 714 func++; 715 } 716 DEBUG1("Next Function - %x\n", func); 717 } 718 719 ndi_devi_exit(devi, circ); 720 721 if (visited == 0) 722 return (PCICFG_FAILURE); /* probe failed */ 723 else 724 return (PCICFG_SUCCESS); 725 726 cleanup: 727 /* 728 * Clean up a partially created "probe state" tree. 729 * There are no resources allocated to the in the 730 * probe state. 731 */ 732 733 for (func = 0; func < PCI_MAX_FUNCTIONS; func++) { 734 if ((function != PCICFG_ALL_FUNC) && (function != func)) 735 continue; 736 737 if ((new_device = pcicfg_devi_find(devi, device, func)) 738 == NULL) { 739 continue; 740 } 741 742 DEBUG2("Cleaning up device [0x%x] function [0x%x]\n", 743 device, func); 744 /* 745 * If this was a bridge device it will have a 746 * probe handle - if not, no harm in calling this. 747 */ 748 (void) pcicfg_destroy_phdl(new_device); 749 if (is_pcie) { 750 /* 751 * free pcie_bus_t for the sub-tree 752 */ 753 if (ddi_get_child(new_device) != NULL) 754 pcie_fab_fini_bus(new_device, PCIE_BUS_ALL); 755 756 pcie_fini_bus(new_device, PCIE_BUS_ALL); 757 } 758 /* 759 * This will free up the node 760 */ 761 (void) ndi_devi_offline(new_device, NDI_DEVI_REMOVE); 762 } 763 ndi_devi_exit(devi, circ); 764 765 /* 766 * Use private return codes to help identify issues without debugging 767 * enabled. Resource limitations and mis-configurations are 768 * probably the most likely caue of configuration failures on x86. 769 * Convert return code back to values expected by the external 770 * consumer before returning so we will warn only once on the first 771 * encountered failure. 772 */ 773 if (rv == PCICFG_NORESRC) { 774 char *path = kmem_alloc(MAXPATHLEN, KM_SLEEP); 775 776 (void) ddi_pathname(devi, path); 777 cmn_err(CE_CONT, "?Not enough PCI resources to " 778 "configure: %s\n", path); 779 780 kmem_free(path, MAXPATHLEN); 781 rv = PCICFG_FAILURE; 782 } 783 784 return (rv); 785 } 786 787 /* 788 * configure the child nodes of ntbridge. new_device points to ntbridge itself 789 */ 790 /*ARGSUSED*/ 791 static int 792 pcicfg_configure_ntbridge(dev_info_t *new_device, uint_t bus, uint_t device) 793 { 794 int bus_range[2], rc = PCICFG_FAILURE, rc1, max_devs = 0; 795 int devno; 796 dev_info_t *new_ntbridgechild; 797 ddi_acc_handle_t config_handle; 798 uint16_t vid; 799 uint64_t next_bus; 800 uint64_t blen; 801 ndi_ra_request_t req; 802 uint8_t pcie_device_type = 0; 803 804 /* 805 * If we need to do indirect config, lets create a property here 806 * to let the child conf map routine know that it has to 807 * go through the DDI calls, and not assume the devices are 808 * mapped directly under the host. 809 */ 810 if ((rc = ndi_prop_update_int(DDI_DEV_T_NONE, new_device, 811 PCI_DEV_CONF_MAP_PROP, (int)DDI_SUCCESS)) != DDI_SUCCESS) { 812 DEBUG0("Cannot create indirect conf map property.\n"); 813 return ((int)PCICFG_FAILURE); 814 } 815 816 if (pci_config_setup(new_device, &config_handle) != DDI_SUCCESS) 817 return (PCICFG_FAILURE); 818 /* check if we are PCIe device */ 819 if (pcicfg_pcie_device_type(new_device, config_handle) == DDI_SUCCESS) { 820 DEBUG0("PCIe device detected\n"); 821 pcie_device_type = 1; 822 } 823 pci_config_teardown(&config_handle); 824 /* create Bus node properties for ntbridge. */ 825 if (pcicfg_set_busnode_props(new_device, pcie_device_type) 826 != PCICFG_SUCCESS) { 827 DEBUG0("Failed to set busnode props\n"); 828 return (rc); 829 } 830 831 /* For now: Lets only support one layer of child */ 832 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 833 req.ra_len = 1; 834 if (ndi_ra_alloc(ddi_get_parent(new_device), &req, &next_bus, &blen, 835 NDI_RA_TYPE_PCI_BUSNUM, NDI_RA_PASS) != NDI_SUCCESS) { 836 DEBUG0("ntbridge: Failed to get a bus number\n"); 837 return (PCICFG_NORESRC); 838 } 839 840 DEBUG1("ntbridge bus range start ->[%d]\n", next_bus); 841 842 /* 843 * Following will change, as we detect more bridges 844 * on the way. 845 */ 846 bus_range[0] = (int)next_bus; 847 bus_range[1] = (int)next_bus; 848 849 if (ndi_prop_update_int_array(DDI_DEV_T_NONE, new_device, "bus-range", 850 bus_range, 2) != DDI_SUCCESS) { 851 DEBUG0("Cannot set ntbridge bus-range property"); 852 return (rc); 853 } 854 855 /* 856 * The other interface (away from the host) will be 857 * initialized by the nexus driver when it loads. 858 * We just have to set the registers and the nexus driver 859 * figures out the rest. 860 */ 861 862 /* 863 * finally, lets load and attach the driver 864 * before configuring children of ntbridge. 865 */ 866 rc = ndi_devi_online(new_device, NDI_ONLINE_ATTACH|NDI_CONFIG); 867 if (rc != NDI_SUCCESS) { 868 cmn_err(CE_WARN, 869 "pcicfg: Fail:cant load nontransparent bridgd driver..\n"); 870 rc = PCICFG_FAILURE; 871 return (rc); 872 } 873 DEBUG0("pcicfg: Success loading nontransparent bridge nexus driver.."); 874 875 /* Now set aside pci resource allocation requests for our children */ 876 if (pcicfg_ntbridge_allocate_resources(new_device) != PCICFG_SUCCESS) { 877 max_devs = 0; 878 rc = PCICFG_FAILURE; 879 } else 880 max_devs = PCI_MAX_DEVICES; 881 882 /* Probe devices on 2nd bus */ 883 rc = PCICFG_SUCCESS; 884 for (devno = pcicfg_start_devno; devno < max_devs; devno++) { 885 886 ndi_devi_alloc_sleep(new_device, DEVI_PSEUDO_NEXNAME, 887 (pnode_t)DEVI_SID_NODEID, &new_ntbridgechild); 888 889 if (pcicfg_add_config_reg(new_ntbridgechild, next_bus, devno, 0) 890 != DDI_PROP_SUCCESS) { 891 cmn_err(CE_WARN, 892 "Failed to add conf reg for ntbridge child.\n"); 893 (void) ndi_devi_free(new_ntbridgechild); 894 rc = PCICFG_FAILURE; 895 break; 896 } 897 898 if (pci_config_setup(new_ntbridgechild, &config_handle) 899 != DDI_SUCCESS) { 900 cmn_err(CE_WARN, 901 "Cannot map ntbridge child %x\n", devno); 902 (void) ndi_devi_free(new_ntbridgechild); 903 rc = PCICFG_FAILURE; 904 break; 905 } 906 907 /* 908 * See if there is any PCI HW at this location 909 * by reading the Vendor ID. If it returns with 0xffff 910 * then there is no hardware at this location. 911 */ 912 vid = pci_config_get16(config_handle, PCI_CONF_VENID); 913 914 pci_config_teardown(&config_handle); 915 (void) ndi_devi_free(new_ntbridgechild); 916 if (vid == 0xffff) 917 continue; 918 919 /* Lets fake attachments points for each child, */ 920 rc = pcicfg_configure(new_device, devno, PCICFG_ALL_FUNC, 0); 921 if (rc != PCICFG_SUCCESS) { 922 int old_dev = pcicfg_start_devno; 923 924 cmn_err(CE_WARN, 925 "Error configuring ntbridge child dev=%d\n", devno); 926 927 while (old_dev != devno) { 928 if (pcicfg_ntbridge_unconfigure_child( 929 new_device, old_dev) == PCICFG_FAILURE) 930 cmn_err(CE_WARN, "Unconfig Error " 931 "ntbridge child dev=%d\n", old_dev); 932 old_dev++; 933 } 934 break; 935 } 936 } /* devno loop */ 937 DEBUG1("ntbridge: finish probing 2nd bus, rc=%d\n", rc); 938 939 if (rc == PCICFG_SUCCESS) 940 rc = pcicfg_ntbridge_configure_done(new_device); 941 else { 942 pcicfg_phdl_t *entry = pcicfg_find_phdl(new_device); 943 uint_t *bus; 944 int k; 945 946 if (ddi_getlongprop(DDI_DEV_T_ANY, new_device, 947 DDI_PROP_DONTPASS, "bus-range", (caddr_t)&bus, &k) 948 != DDI_PROP_SUCCESS) { 949 DEBUG0("Failed to read bus-range property\n"); 950 rc = PCICFG_FAILURE; 951 return (rc); 952 } 953 954 DEBUG2("Need to free bus [%d] range [%d]\n", 955 bus[0], bus[1] - bus[0] + 1); 956 957 if (ndi_ra_free(ddi_get_parent(new_device), (uint64_t)bus[0], 958 (uint64_t)(bus[1] - bus[0] + 1), NDI_RA_TYPE_PCI_BUSNUM, 959 NDI_RA_PASS) != NDI_SUCCESS) { 960 DEBUG0("Failed to free a bus number\n"); 961 rc = PCICFG_FAILURE; 962 kmem_free(bus, k); 963 return (rc); 964 } 965 966 /* 967 * Since no memory allocations are done for non transparent 968 * bridges (but instead we just set the handle with the 969 * already allocated memory, we just need to reset the 970 * following values before calling the destroy_phdl() 971 * function next, otherwise the it will try to free 972 * memory allocated as in case of a transparent bridge. 973 */ 974 entry->memory_len = 0; 975 entry->pf_memory_len = 0; 976 entry->io_len = 0; 977 kmem_free(bus, k); 978 /* the following will free hole data. */ 979 (void) pcicfg_destroy_phdl(new_device); 980 } 981 982 /* 983 * Unload driver just in case child configure failed! 984 */ 985 rc1 = ndi_devi_offline(new_device, 0); 986 DEBUG1("pcicfg: now unloading the ntbridge driver. rc1=%d\n", rc1); 987 if (rc1 != NDI_SUCCESS) { 988 cmn_err(CE_WARN, 989 "pcicfg: cant unload ntbridge driver..children.\n"); 990 rc = PCICFG_FAILURE; 991 } 992 993 return (rc); 994 } 995 996 static int 997 pcicfg_ntbridge_allocate_resources(dev_info_t *dip) 998 { 999 pcicfg_phdl_t *phdl; 1000 ndi_ra_request_t *mem_request; 1001 ndi_ra_request_t *pf_mem_request; 1002 ndi_ra_request_t *io_request; 1003 uint64_t boundbase, boundlen; 1004 1005 phdl = pcicfg_find_phdl(dip); 1006 ASSERT(phdl); 1007 1008 mem_request = &phdl->mem_req; 1009 pf_mem_request = &phdl->pf_mem_req; 1010 io_request = &phdl->io_req; 1011 1012 phdl->error = PCICFG_SUCCESS; 1013 1014 /* Set Memory space handle for ntbridge */ 1015 if (pcicfg_get_ntbridge_child_range(dip, &boundbase, &boundlen, 1016 PCI_BASE_SPACE_MEM) != DDI_SUCCESS) { 1017 cmn_err(CE_WARN, 1018 "ntbridge: Mem resource information failure\n"); 1019 phdl->memory_len = 0; 1020 return (PCICFG_FAILURE); 1021 } 1022 mem_request->ra_boundbase = boundbase; 1023 mem_request->ra_boundlen = boundbase + boundlen; 1024 mem_request->ra_len = boundlen; 1025 mem_request->ra_align_mask = 1026 PCICFG_MEMGRAN - 1; /* 1M alignment on memory space */ 1027 mem_request->ra_flags |= NDI_RA_ALLOC_BOUNDED; 1028 1029 /* 1030 * mem_request->ra_len = 1031 * PCICFG_ROUND_UP(mem_request->ra_len, PCICFG_MEMGRAN); 1032 */ 1033 1034 phdl->memory_base = phdl->memory_last = boundbase; 1035 phdl->memory_len = boundlen; 1036 phdl->mem_hole.start = phdl->memory_base; 1037 phdl->mem_hole.len = mem_request->ra_len; 1038 phdl->mem_hole.next = (hole_t *)NULL; 1039 1040 DEBUG2("Connector requested [0x%llx], needs [0x%llx] bytes of memory\n", 1041 boundlen, mem_request->ra_len); 1042 1043 /* Set IO space handle for ntbridge */ 1044 if (pcicfg_get_ntbridge_child_range(dip, &boundbase, &boundlen, 1045 PCI_BASE_SPACE_IO) != DDI_SUCCESS) { 1046 cmn_err(CE_WARN, "ntbridge: IO resource information failure\n"); 1047 phdl->io_len = 0; 1048 return (PCICFG_FAILURE); 1049 } 1050 io_request->ra_len = boundlen; 1051 io_request->ra_align_mask = 1052 PCICFG_IOGRAN - 1; /* 4K alignment on I/O space */ 1053 io_request->ra_boundbase = boundbase; 1054 io_request->ra_boundlen = boundbase + boundlen; 1055 io_request->ra_flags |= NDI_RA_ALLOC_BOUNDED; 1056 1057 /* 1058 * io_request->ra_len = 1059 * PCICFG_ROUND_UP(io_request->ra_len, PCICFG_IOGRAN); 1060 */ 1061 1062 phdl->io_base = phdl->io_last = (uint32_t)boundbase; 1063 phdl->io_len = (uint32_t)boundlen; 1064 phdl->io_hole.start = phdl->io_base; 1065 phdl->io_hole.len = io_request->ra_len; 1066 phdl->io_hole.next = (hole_t *)NULL; 1067 1068 DEBUG2("Connector requested [0x%llx], needs [0x%llx] bytes of IO\n", 1069 boundlen, io_request->ra_len); 1070 1071 /* Set Prefetchable Memory space handle for ntbridge */ 1072 if (pcicfg_get_ntbridge_child_range(dip, &boundbase, &boundlen, 1073 PCI_BASE_SPACE_MEM | PCI_BASE_PREF_M) != DDI_SUCCESS) { 1074 cmn_err(CE_WARN, 1075 "ntbridge: PF Mem resource information failure\n"); 1076 phdl->pf_memory_len = 0; 1077 return (PCICFG_FAILURE); 1078 } 1079 pf_mem_request->ra_boundbase = boundbase; 1080 pf_mem_request->ra_boundlen = boundbase + boundlen; 1081 pf_mem_request->ra_len = boundlen; 1082 pf_mem_request->ra_align_mask = 1083 PCICFG_MEMGRAN - 1; /* 1M alignment on memory space */ 1084 pf_mem_request->ra_flags |= NDI_RA_ALLOC_BOUNDED; 1085 1086 /* 1087 * pf_mem_request->ra_len = 1088 * PCICFG_ROUND_UP(pf_mem_request->ra_len, PCICFG_MEMGRAN); 1089 */ 1090 1091 phdl->pf_memory_base = phdl->pf_memory_last = boundbase; 1092 phdl->pf_memory_len = boundlen; 1093 phdl->pf_mem_hole.start = phdl->pf_memory_base; 1094 phdl->pf_mem_hole.len = pf_mem_request->ra_len; 1095 phdl->pf_mem_hole.next = (hole_t *)NULL; 1096 1097 DEBUG2("Connector requested [0x%llx], needs [0x%llx] bytes of PF " 1098 "memory\n", boundlen, pf_mem_request->ra_len); 1099 1100 DEBUG2("MEMORY BASE = [0x%lx] length [0x%lx]\n", 1101 phdl->memory_base, phdl->memory_len); 1102 DEBUG2("IO BASE = [0x%x] length [0x%x]\n", 1103 phdl->io_base, phdl->io_len); 1104 DEBUG2("PF MEMORY BASE = [0x%lx] length [0x%lx]\n", 1105 phdl->pf_memory_base, phdl->pf_memory_len); 1106 1107 return (PCICFG_SUCCESS); 1108 } 1109 1110 static int 1111 pcicfg_ntbridge_configure_done(dev_info_t *dip) 1112 { 1113 ppb_ranges_t range[PCICFG_RANGE_LEN]; 1114 pcicfg_phdl_t *entry; 1115 uint_t len; 1116 pci_bus_range_t bus_range; 1117 int new_bus_range[2]; 1118 1119 DEBUG1("Configuring children for %p\n", dip); 1120 1121 entry = pcicfg_find_phdl(dip); 1122 ASSERT(entry); 1123 1124 bzero((caddr_t)range, sizeof (ppb_ranges_t) * PCICFG_RANGE_LEN); 1125 range[1].child_high = range[1].parent_high |= 1126 (PCI_REG_REL_M | PCI_ADDR_MEM32); 1127 range[1].child_low = range[1].parent_low = (uint32_t)entry->memory_base; 1128 1129 range[0].child_high = range[0].parent_high |= 1130 (PCI_REG_REL_M | PCI_ADDR_IO); 1131 range[0].child_low = range[0].parent_low = (uint32_t)entry->io_base; 1132 1133 range[2].child_high = range[2].parent_high |= 1134 (PCI_REG_REL_M | PCI_ADDR_MEM32 | PCI_REG_PF_M); 1135 range[2].child_low = range[2].parent_low = 1136 (uint32_t)entry->pf_memory_base; 1137 1138 len = sizeof (pci_bus_range_t); 1139 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1140 "bus-range", (caddr_t)&bus_range, (int *)&len) != DDI_SUCCESS) { 1141 DEBUG0("no bus-range property\n"); 1142 return (PCICFG_FAILURE); 1143 } 1144 1145 new_bus_range[0] = bus_range.lo; /* primary bus number */ 1146 if (entry->highest_bus) { /* secondary bus number */ 1147 if (entry->highest_bus < bus_range.lo) { 1148 cmn_err(CE_WARN, 1149 "ntbridge bus range invalid !(%d,%d)\n", 1150 bus_range.lo, entry->highest_bus); 1151 new_bus_range[1] = bus_range.lo + entry->highest_bus; 1152 } 1153 else 1154 new_bus_range[1] = entry->highest_bus; 1155 } 1156 else 1157 new_bus_range[1] = bus_range.hi; 1158 1159 DEBUG2("ntbridge: bus range lo=%x, hi=%x\n", new_bus_range[0], 1160 new_bus_range[1]); 1161 1162 if (ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "bus-range", 1163 new_bus_range, 2) != DDI_SUCCESS) { 1164 DEBUG0("Failed to set bus-range property"); 1165 entry->error = PCICFG_FAILURE; 1166 return (PCICFG_FAILURE); 1167 } 1168 1169 #ifdef DEBUG 1170 { 1171 uint64_t unused; 1172 unused = pcicfg_unused_space(&entry->io_hole, &len); 1173 DEBUG2("ntbridge: Unused IO space %llx bytes over %d holes\n", 1174 unused, len); 1175 } 1176 #endif 1177 1178 range[0].size_low = entry->io_len; 1179 if (pcicfg_update_ranges_prop(dip, &range[0])) { 1180 DEBUG0("Failed to update ranges (i/o)\n"); 1181 entry->error = PCICFG_FAILURE; 1182 return (PCICFG_FAILURE); 1183 } 1184 1185 #ifdef DEBUG 1186 { 1187 uint64_t unused; 1188 unused = pcicfg_unused_space(&entry->mem_hole, &len); 1189 DEBUG2("ntbridge: Unused Mem space %llx bytes over %d holes\n", 1190 unused, len); 1191 } 1192 #endif 1193 1194 range[1].size_low = entry->memory_len; 1195 if (pcicfg_update_ranges_prop(dip, &range[1])) { 1196 DEBUG0("Failed to update ranges (memory)\n"); 1197 entry->error = PCICFG_FAILURE; 1198 return (PCICFG_FAILURE); 1199 } 1200 1201 #ifdef DEBUG 1202 { 1203 uint64_t unused; 1204 unused = pcicfg_unused_space(&entry->pf_mem_hole, &len); 1205 DEBUG2("ntbridge: Unused PF Mem space %llx bytes over" 1206 " %d holes\n", unused, len); 1207 } 1208 #endif 1209 1210 range[2].size_low = entry->pf_memory_len; 1211 if (pcicfg_update_ranges_prop(dip, &range[2])) { 1212 DEBUG0("Failed to update ranges (PF memory)\n"); 1213 entry->error = PCICFG_FAILURE; 1214 return (PCICFG_FAILURE); 1215 } 1216 1217 return (PCICFG_SUCCESS); 1218 } 1219 1220 static int 1221 pcicfg_ntbridge_program_child(dev_info_t *dip) 1222 { 1223 pcicfg_phdl_t *entry; 1224 int rc = PCICFG_SUCCESS; 1225 dev_info_t *anode = dip; 1226 1227 /* Find the Hotplug Connection (CN) node */ 1228 while ((anode != NULL) && 1229 (strcmp(ddi_binding_name(anode), "hp_attachment") != 0)) { 1230 anode = ddi_get_parent(anode); 1231 } 1232 1233 if (anode == NULL) { 1234 DEBUG0("ntbridge child tree not in PROBE state\n"); 1235 return (PCICFG_FAILURE); 1236 } 1237 entry = pcicfg_find_phdl(ddi_get_parent(anode)); 1238 ASSERT(entry); 1239 1240 if (pcicfg_bridge_assign(dip, entry) == DDI_WALK_TERMINATE) { 1241 cmn_err(CE_WARN, 1242 "ntbridge: Error assigning range for child %s\n", 1243 ddi_get_name(dip)); 1244 rc = PCICFG_FAILURE; 1245 } 1246 return (rc); 1247 } 1248 1249 static int 1250 pcicfg_ntbridge_unconfigure_child(dev_info_t *new_device, uint_t devno) 1251 { 1252 1253 dev_info_t *new_ntbridgechild; 1254 int len, bus; 1255 uint16_t vid; 1256 ddi_acc_handle_t config_handle; 1257 pci_bus_range_t pci_bus_range; 1258 1259 len = sizeof (pci_bus_range_t); 1260 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, new_device, DDI_PROP_DONTPASS, 1261 "bus-range", (caddr_t)&pci_bus_range, &len) != DDI_SUCCESS) { 1262 DEBUG0("no bus-range property\n"); 1263 return (PCICFG_FAILURE); 1264 } 1265 1266 bus = pci_bus_range.lo; /* primary bus number of this bus node */ 1267 1268 ndi_devi_alloc_sleep(new_device, DEVI_PSEUDO_NEXNAME, 1269 (pnode_t)DEVI_SID_NODEID, &new_ntbridgechild); 1270 1271 if (pcicfg_add_config_reg(new_ntbridgechild, bus, devno, 0) 1272 != DDI_PROP_SUCCESS) { 1273 cmn_err(CE_WARN, "Unconfigure: Failed to add conf reg prop for " 1274 "ntbridge child.\n"); 1275 (void) ndi_devi_free(new_ntbridgechild); 1276 return (PCICFG_FAILURE); 1277 } 1278 1279 if (pci_config_setup(new_ntbridgechild, &config_handle) 1280 != DDI_SUCCESS) { 1281 cmn_err(CE_WARN, "pcicfg: Cannot map ntbridge child %x\n", 1282 devno); 1283 (void) ndi_devi_free(new_ntbridgechild); 1284 return (PCICFG_FAILURE); 1285 } 1286 1287 /* 1288 * See if there is any PCI HW at this location 1289 * by reading the Vendor ID. If it returns with 0xffff 1290 * then there is no hardware at this location. 1291 */ 1292 vid = pci_config_get16(config_handle, PCI_CONF_VENID); 1293 1294 pci_config_teardown(&config_handle); 1295 (void) ndi_devi_free(new_ntbridgechild); 1296 if (vid == 0xffff) 1297 return (PCICFG_NODEVICE); 1298 1299 return (pcicfg_unconfigure(new_device, devno, PCICFG_ALL_FUNC, 0)); 1300 } 1301 1302 static uint_t 1303 pcicfg_ntbridge_unconfigure(dev_info_t *dip) 1304 { 1305 pcicfg_phdl_t *entry = pcicfg_find_phdl(dip); 1306 uint_t *bus; 1307 int k, rc = DDI_FAILURE; 1308 1309 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "bus-range", 1310 (caddr_t)&bus, &k) != DDI_PROP_SUCCESS) { 1311 DEBUG0("ntbridge: Failed to read bus-range property\n"); 1312 return (rc); 1313 } 1314 1315 DEBUG2("ntbridge: Need to free bus [%d] range [%d]\n", 1316 bus[0], bus[1] - bus[0] + 1); 1317 1318 if (ndi_ra_free(ddi_get_parent(dip), (uint64_t)bus[0], 1319 (uint64_t)(bus[1] - bus[0] + 1), 1320 NDI_RA_TYPE_PCI_BUSNUM, NDI_RA_PASS) != NDI_SUCCESS) { 1321 DEBUG0("ntbridge: Failed to free a bus number\n"); 1322 kmem_free(bus, k); 1323 return (rc); 1324 } 1325 1326 /* 1327 * Since our resources will be freed at the parent level, 1328 * just reset these values. 1329 */ 1330 entry->memory_len = 0; 1331 entry->io_len = 0; 1332 entry->pf_memory_len = 0; 1333 1334 kmem_free(bus, k); 1335 1336 /* the following will also free hole data. */ 1337 return (pcicfg_destroy_phdl(dip)); 1338 1339 } 1340 1341 static int 1342 pcicfg_is_ntbridge(dev_info_t *dip) 1343 { 1344 ddi_acc_handle_t config_handle; 1345 uint8_t class, subclass; 1346 int rc = DDI_SUCCESS; 1347 1348 if (pci_config_setup(dip, &config_handle) != DDI_SUCCESS) { 1349 cmn_err(CE_WARN, 1350 "pcicfg: cannot map config space, to get map type\n"); 1351 return (DDI_FAILURE); 1352 } 1353 class = pci_config_get8(config_handle, PCI_CONF_BASCLASS); 1354 subclass = pci_config_get8(config_handle, PCI_CONF_SUBCLASS); 1355 1356 /* check for class=6, subclass=9, for non transparent bridges. */ 1357 if ((class != PCI_CLASS_BRIDGE) || (subclass != PCI_BRIDGE_STBRIDGE)) 1358 rc = DDI_FAILURE; 1359 1360 DEBUG3("pcicfg: checking device %x,%x for indirect map. rc=%d\n", 1361 pci_config_get16(config_handle, PCI_CONF_VENID), 1362 pci_config_get16(config_handle, PCI_CONF_DEVID), 1363 rc); 1364 pci_config_teardown(&config_handle); 1365 return (rc); 1366 } 1367 1368 static uint_t 1369 pcicfg_ntbridge_child(dev_info_t *dip) 1370 { 1371 int len, val, rc = DDI_FAILURE; 1372 dev_info_t *anode = dip; 1373 1374 /* 1375 * Find the Hotplug Connection (CN) node 1376 */ 1377 while ((anode != NULL) && (strcmp(ddi_binding_name(anode), 1378 "hp_attachment") != 0)) { 1379 anode = ddi_get_parent(anode); 1380 } 1381 1382 if (anode == NULL) { 1383 DEBUG0("ntbridge child tree not in PROBE state\n"); 1384 return (rc); 1385 } 1386 len = sizeof (int); 1387 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, ddi_get_parent(anode), 1388 DDI_PROP_DONTPASS, PCI_DEV_CONF_MAP_PROP, (caddr_t)&val, &len) 1389 != DDI_SUCCESS) { 1390 1391 DEBUG1("ntbridge child: no \"%s\" property\n", 1392 PCI_DEV_CONF_MAP_PROP); 1393 return (rc); 1394 } 1395 DEBUG0("ntbridge child: success\n"); 1396 return (DDI_SUCCESS); 1397 } 1398 1399 static uint_t 1400 pcicfg_get_ntbridge_child_range(dev_info_t *dip, uint64_t *boundbase, 1401 uint64_t *boundlen, uint_t space_type) 1402 { 1403 int length, found = DDI_FAILURE, acount, i, ibridge; 1404 pci_regspec_t *assigned; 1405 1406 if ((ibridge = pcicfg_is_ntbridge(dip)) == DDI_FAILURE) 1407 return (found); 1408 1409 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1410 "assigned-addresses", (caddr_t)&assigned, &length) 1411 != DDI_PROP_SUCCESS) { 1412 DEBUG1("Failed to get assigned-addresses property %llx\n", dip); 1413 return (found); 1414 } 1415 DEBUG1("pcicfg: ntbridge child range: dip = %s\n", 1416 ddi_driver_name(dip)); 1417 1418 acount = length / sizeof (pci_regspec_t); 1419 1420 for (i = 0; i < acount; i++) { 1421 if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) == 1422 pcicfg_indirect_map_devs[ibridge].mem_range_bar_offset) && 1423 (space_type == PCI_BASE_SPACE_MEM)) { 1424 found = DDI_SUCCESS; 1425 break; 1426 } else if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) == 1427 pcicfg_indirect_map_devs[ibridge].io_range_bar_offset) && 1428 (space_type == PCI_BASE_SPACE_IO)) { 1429 found = DDI_SUCCESS; 1430 break; 1431 } else if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) == 1432 pcicfg_indirect_map_devs[ibridge]. 1433 prefetch_mem_range_bar_offset) && 1434 (space_type == (PCI_BASE_SPACE_MEM | 1435 PCI_BASE_PREF_M))) { 1436 found = DDI_SUCCESS; 1437 break; 1438 } 1439 } 1440 DEBUG3("pcicfg: ntbridge child range: space=%x, base=%lx, len=%lx\n", 1441 space_type, assigned[i].pci_phys_low, assigned[i].pci_size_low); 1442 1443 if (found == DDI_SUCCESS) { 1444 *boundbase = assigned[i].pci_phys_low; 1445 *boundlen = assigned[i].pci_size_low; 1446 } 1447 1448 kmem_free(assigned, length); 1449 return (found); 1450 } 1451 1452 /* 1453 * This will turn resources allocated by pcicfg_configure() 1454 * and remove the device tree from the Hotplug Connection (CN) 1455 * and below. The routine assumes the devices have their 1456 * drivers detached. 1457 */ 1458 int 1459 pcicfg_unconfigure(dev_info_t *devi, uint_t device, uint_t function, 1460 pcicfg_flags_t flags) 1461 { 1462 dev_info_t *child_dip; 1463 int func; 1464 int i; 1465 int max_function, trans_device; 1466 int circ; 1467 boolean_t is_pcie; 1468 1469 if (pcie_ari_is_enabled(devi) == PCIE_ARI_FORW_ENABLED) 1470 max_function = PCICFG_MAX_ARI_FUNCTION; 1471 else 1472 max_function = PCI_MAX_FUNCTIONS; 1473 1474 /* 1475 * Cycle through devices to make sure none are busy. 1476 * If a single device is busy fail the whole unconfigure. 1477 */ 1478 is_pcie = is_pcie_fabric(devi); 1479 1480 ndi_devi_enter(devi, &circ); 1481 for (func = 0; func < max_function; func++) { 1482 if ((function != PCICFG_ALL_FUNC) && (function != func)) 1483 continue; 1484 1485 if (max_function == PCICFG_MAX_ARI_FUNCTION) 1486 trans_device = func >> 3; /* ARI Device */ 1487 else 1488 trans_device = device; 1489 1490 if ((child_dip = pcicfg_devi_find(devi, trans_device, 1491 func & 7)) == NULL) 1492 continue; 1493 1494 if (ndi_devi_offline(child_dip, NDI_UNCONFIG) == NDI_SUCCESS) 1495 continue; 1496 1497 /* 1498 * Device function is busy. Before returning we have to 1499 * put all functions back online which were taken 1500 * offline during the process. 1501 */ 1502 DEBUG2("Device [0x%x] function [0x%x] is busy\n", 1503 trans_device, func & 7); 1504 /* 1505 * If we are only asked to offline one specific function, 1506 * and that fails, we just simply return. 1507 */ 1508 if (function != PCICFG_ALL_FUNC) 1509 return (PCICFG_FAILURE); 1510 1511 for (i = 0; i < func; i++) { 1512 if (max_function == PCICFG_MAX_ARI_FUNCTION) 1513 trans_device = i >> 3; 1514 1515 if ((child_dip = pcicfg_devi_find(devi, trans_device, 1516 i & 7)) == NULL) { 1517 DEBUG0("No more devices to put back " 1518 "on line!!\n"); 1519 /* 1520 * Made it through all functions 1521 */ 1522 continue; 1523 } 1524 if (ndi_devi_online(child_dip, NDI_CONFIG) 1525 != NDI_SUCCESS) { 1526 DEBUG0("Failed to put back devices state\n"); 1527 goto fail; 1528 } 1529 } 1530 goto fail; 1531 } 1532 1533 /* 1534 * Now, tear down all devinfo nodes for this Connector. 1535 */ 1536 for (func = 0; func < max_function; func++) { 1537 if ((function != PCICFG_ALL_FUNC) && (function != func)) 1538 continue; 1539 1540 if (max_function == PCICFG_MAX_ARI_FUNCTION) 1541 trans_device = func >> 3; /* ARI Device */ 1542 else 1543 trans_device = device; 1544 1545 if ((child_dip = pcicfg_devi_find(devi, trans_device, func & 7)) 1546 == NULL) { 1547 DEBUG2("No device at %x,%x\n", trans_device, func & 7); 1548 continue; 1549 } 1550 1551 DEBUG2("Tearing down device [0x%x] function [0x%x]\n", 1552 trans_device, func & 7); 1553 1554 if (pcicfg_is_ntbridge(child_dip) != DDI_FAILURE) 1555 if (pcicfg_ntbridge_unconfigure(child_dip) != 1556 PCICFG_SUCCESS) { 1557 cmn_err(CE_WARN, 1558 "ntbridge: unconfigure failed\n"); 1559 goto fail; 1560 } 1561 1562 if (pcicfg_teardown_device(child_dip, flags, is_pcie) 1563 != PCICFG_SUCCESS) { 1564 DEBUG2("Failed to tear down device [0x%x]" 1565 "function [0x%x]\n", trans_device, func & 7); 1566 goto fail; 1567 } 1568 } 1569 1570 if (pcie_ari_is_enabled(devi) == PCIE_ARI_FORW_ENABLED) { 1571 (void) ddi_prop_remove(DDI_DEV_T_NONE, devi, "ari-enabled"); 1572 (void) pcie_ari_disable(devi); 1573 } 1574 1575 ndi_devi_exit(devi, circ); 1576 return (PCICFG_SUCCESS); 1577 1578 fail: 1579 ndi_devi_exit(devi, circ); 1580 return (PCICFG_FAILURE); 1581 } 1582 1583 static int 1584 pcicfg_teardown_device(dev_info_t *dip, pcicfg_flags_t flags, boolean_t is_pcie) 1585 { 1586 ddi_acc_handle_t handle; 1587 1588 /* 1589 * Free up resources associated with 'dip' 1590 */ 1591 if (pcicfg_free_resources(dip, flags) != PCICFG_SUCCESS) { 1592 DEBUG0("Failed to free resources\n"); 1593 return (PCICFG_FAILURE); 1594 } 1595 1596 /* 1597 * disable the device 1598 */ 1599 if (pcicfg_config_setup(dip, &handle) != PCICFG_SUCCESS) 1600 return (PCICFG_FAILURE); 1601 pcicfg_device_off(handle); 1602 pcicfg_config_teardown(&handle); 1603 1604 if (is_pcie) { 1605 /* 1606 * free pcie_bus_t for the sub-tree 1607 */ 1608 if (ddi_get_child(dip) != NULL) 1609 pcie_fab_fini_bus(dip, PCIE_BUS_ALL); 1610 1611 pcie_fini_bus(dip, PCIE_BUS_ALL); 1612 } 1613 1614 /* 1615 * The framework provides this routine which can 1616 * tear down a sub-tree. 1617 */ 1618 if (ndi_devi_offline(dip, NDI_DEVI_REMOVE) != NDI_SUCCESS) { 1619 DEBUG0("Failed to offline and remove node\n"); 1620 return (PCICFG_FAILURE); 1621 } 1622 1623 return (PCICFG_SUCCESS); 1624 } 1625 1626 /* 1627 * BEGIN GENERIC SUPPORT ROUTINES 1628 */ 1629 static pcicfg_phdl_t * 1630 pcicfg_find_phdl(dev_info_t *dip) 1631 { 1632 pcicfg_phdl_t *entry; 1633 mutex_enter(&pcicfg_list_mutex); 1634 for (entry = pcicfg_phdl_list; entry != NULL; entry = entry->next) { 1635 if (entry->dip == dip) { 1636 mutex_exit(&pcicfg_list_mutex); 1637 return (entry); 1638 } 1639 } 1640 mutex_exit(&pcicfg_list_mutex); 1641 1642 /* 1643 * Did'nt find entry - create one 1644 */ 1645 return (pcicfg_create_phdl(dip)); 1646 } 1647 1648 static pcicfg_phdl_t * 1649 pcicfg_create_phdl(dev_info_t *dip) 1650 { 1651 pcicfg_phdl_t *new; 1652 1653 new = (pcicfg_phdl_t *)kmem_zalloc(sizeof (pcicfg_phdl_t), KM_SLEEP); 1654 1655 new->dip = dip; 1656 mutex_enter(&pcicfg_list_mutex); 1657 new->next = pcicfg_phdl_list; 1658 pcicfg_phdl_list = new; 1659 mutex_exit(&pcicfg_list_mutex); 1660 1661 return (new); 1662 } 1663 1664 static int 1665 pcicfg_destroy_phdl(dev_info_t *dip) 1666 { 1667 pcicfg_phdl_t *entry; 1668 pcicfg_phdl_t *follow = NULL; 1669 1670 mutex_enter(&pcicfg_list_mutex); 1671 for (entry = pcicfg_phdl_list; entry != NULL; follow = entry, 1672 entry = entry->next) { 1673 if (entry->dip == dip) { 1674 if (entry == pcicfg_phdl_list) { 1675 pcicfg_phdl_list = entry->next; 1676 } else { 1677 follow->next = entry->next; 1678 } 1679 /* 1680 * If this entry has any allocated memory 1681 * or IO space associated with it, that 1682 * must be freed up. 1683 */ 1684 if (entry->memory_len > 0) { 1685 (void) ndi_ra_free(ddi_get_parent(dip), 1686 entry->memory_base, entry->memory_len, 1687 NDI_RA_TYPE_MEM, NDI_RA_PASS); 1688 } 1689 pcicfg_free_hole(&entry->mem_hole); 1690 1691 if (entry->io_len > 0) { 1692 (void) ndi_ra_free(ddi_get_parent(dip), 1693 entry->io_base, entry->io_len, 1694 NDI_RA_TYPE_IO, NDI_RA_PASS); 1695 } 1696 pcicfg_free_hole(&entry->io_hole); 1697 1698 if (entry->pf_memory_len > 0) { 1699 (void) ndi_ra_free(ddi_get_parent(dip), 1700 entry->pf_memory_base, entry->pf_memory_len, 1701 NDI_RA_TYPE_PCI_PREFETCH_MEM, NDI_RA_PASS); 1702 } 1703 pcicfg_free_hole(&entry->pf_mem_hole); 1704 1705 /* 1706 * Destroy this entry 1707 */ 1708 kmem_free((caddr_t)entry, sizeof (pcicfg_phdl_t)); 1709 mutex_exit(&pcicfg_list_mutex); 1710 return (PCICFG_SUCCESS); 1711 } 1712 } 1713 mutex_exit(&pcicfg_list_mutex); 1714 /* 1715 * Did'nt find the entry 1716 */ 1717 return (PCICFG_FAILURE); 1718 } 1719 1720 static int 1721 pcicfg_bridge_assign(dev_info_t *dip, void *hdl) 1722 { 1723 ddi_acc_handle_t handle; 1724 pci_regspec_t *reg; 1725 int length; 1726 int rcount; 1727 int i; 1728 int offset; 1729 uint64_t mem_answer; 1730 uint32_t io_answer; 1731 int count; 1732 uint8_t header_type; 1733 ppb_ranges_t range[PCICFG_RANGE_LEN]; 1734 int bus_range[2]; 1735 uint64_t mem_residual; 1736 uint64_t pf_mem_residual; 1737 uint64_t io_residual; 1738 1739 pcicfg_phdl_t *entry = (pcicfg_phdl_t *)hdl; 1740 1741 DEBUG1("bridge assign: assigning addresses to %s\n", ddi_get_name(dip)); 1742 1743 entry->error = PCICFG_SUCCESS; 1744 1745 if (entry == NULL) { 1746 DEBUG0("Failed to get entry\n"); 1747 entry->error = PCICFG_FAILURE; 1748 return (DDI_WALK_TERMINATE); 1749 } 1750 1751 if (pcicfg_config_setup(dip, &handle) != DDI_SUCCESS) { 1752 DEBUG0("Failed to map config space!\n"); 1753 entry->error = PCICFG_FAILURE; 1754 return (DDI_WALK_TERMINATE); 1755 } 1756 1757 header_type = pci_config_get8(handle, PCI_CONF_HEADER); 1758 1759 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) { 1760 1761 bzero((caddr_t)range, sizeof (ppb_ranges_t) * PCICFG_RANGE_LEN); 1762 1763 (void) pcicfg_setup_bridge(entry, handle); 1764 1765 range[0].child_high = range[0].parent_high |= 1766 (PCI_REG_REL_M | PCI_ADDR_IO); 1767 range[0].child_low = range[0].parent_low = entry->io_last; 1768 range[1].child_high = range[1].parent_high |= 1769 (PCI_REG_REL_M | PCI_ADDR_MEM32); 1770 range[1].child_low = range[1].parent_low = 1771 entry->memory_last; 1772 range[2].child_high = range[2].parent_high |= 1773 (PCI_REG_REL_M | PCI_ADDR_MEM32 | PCI_REG_PF_M); 1774 range[2].child_low = range[2].parent_low = 1775 entry->pf_memory_last; 1776 1777 ndi_devi_enter(dip, &count); 1778 ddi_walk_devs(ddi_get_child(dip), 1779 pcicfg_bridge_assign, (void *)entry); 1780 ndi_devi_exit(dip, count); 1781 1782 (void) pcicfg_update_bridge(entry, handle); 1783 1784 bus_range[0] = pci_config_get8(handle, PCI_BCNF_SECBUS); 1785 bus_range[1] = pci_config_get8(handle, PCI_BCNF_SUBBUS); 1786 1787 if (ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1788 "bus-range", bus_range, 2) != DDI_SUCCESS) { 1789 DEBUG0("Failed to set bus-range property"); 1790 entry->error = PCICFG_FAILURE; 1791 (void) pcicfg_config_teardown(&handle); 1792 return (DDI_WALK_TERMINATE); 1793 } 1794 1795 /* 1796 * Put back memory and I/O space not allocated 1797 * under the bridge. 1798 */ 1799 mem_residual = entry->memory_len - 1800 (entry->memory_last - entry->memory_base); 1801 if (mem_residual > 0) { 1802 (void) ndi_ra_free(ddi_get_parent(dip), 1803 entry->memory_last, mem_residual, 1804 NDI_RA_TYPE_MEM, NDI_RA_PASS); 1805 } 1806 1807 io_residual = entry->io_len - (entry->io_last - entry->io_base); 1808 if (io_residual > 0) { 1809 (void) ndi_ra_free(ddi_get_parent(dip), entry->io_last, 1810 io_residual, NDI_RA_TYPE_IO, NDI_RA_PASS); 1811 } 1812 1813 pf_mem_residual = entry->pf_memory_len - 1814 (entry->pf_memory_last - entry->pf_memory_base); 1815 if (pf_mem_residual > 0) { 1816 (void) ndi_ra_free(ddi_get_parent(dip), 1817 entry->pf_memory_last, pf_mem_residual, 1818 NDI_RA_TYPE_PCI_PREFETCH_MEM, NDI_RA_PASS); 1819 } 1820 1821 if (entry->io_len > 0) { 1822 range[0].size_low = entry->io_last - entry->io_base; 1823 if (pcicfg_update_ranges_prop(dip, &range[0])) { 1824 DEBUG0("Failed to update ranges (i/o)\n"); 1825 entry->error = PCICFG_FAILURE; 1826 (void) pcicfg_config_teardown(&handle); 1827 return (DDI_WALK_TERMINATE); 1828 } 1829 } 1830 if (entry->memory_len > 0) { 1831 range[1].size_low = 1832 entry->memory_last - entry->memory_base; 1833 if (pcicfg_update_ranges_prop(dip, &range[1])) { 1834 DEBUG0("Failed to update ranges (memory)\n"); 1835 entry->error = PCICFG_FAILURE; 1836 (void) pcicfg_config_teardown(&handle); 1837 return (DDI_WALK_TERMINATE); 1838 } 1839 } 1840 if (entry->pf_memory_len > 0) { 1841 range[2].size_low = 1842 entry->pf_memory_last - entry->pf_memory_base; 1843 if (pcicfg_update_ranges_prop(dip, &range[2])) { 1844 DEBUG0("Failed to update ranges (PF memory)\n"); 1845 entry->error = PCICFG_FAILURE; 1846 (void) pcicfg_config_teardown(&handle); 1847 return (DDI_WALK_TERMINATE); 1848 } 1849 } 1850 1851 (void) pcicfg_device_on(handle); 1852 1853 PCICFG_DUMP_BRIDGE_CONFIG(handle); 1854 1855 (void) pcicfg_config_teardown(&handle); 1856 1857 return (DDI_WALK_PRUNECHILD); 1858 } 1859 1860 /* 1861 * If there is an interrupt pin set program 1862 * interrupt line with default values. 1863 */ 1864 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 1865 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 1866 } 1867 1868 /* 1869 * A single device (under a bridge). 1870 * For each "reg" property with a length, allocate memory 1871 * and program the base registers. 1872 */ 1873 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "reg", 1874 (caddr_t)®, &length) != DDI_PROP_SUCCESS) { 1875 DEBUG0("Failed to read reg property\n"); 1876 entry->error = PCICFG_FAILURE; 1877 (void) pcicfg_config_teardown(&handle); 1878 return (DDI_WALK_TERMINATE); 1879 } 1880 1881 rcount = length / sizeof (pci_regspec_t); 1882 offset = PCI_CONF_BASE0; 1883 for (i = 0; i < rcount; i++) { 1884 if ((reg[i].pci_size_low != 0) || (reg[i].pci_size_hi != 0)) { 1885 1886 offset = PCI_REG_REG_G(reg[i].pci_phys_hi); 1887 1888 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) { 1889 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 1890 1891 if (reg[i].pci_phys_hi & PCI_REG_PF_M) { 1892 /* allocate prefetchable memory */ 1893 pcicfg_get_pf_mem(entry, 1894 reg[i].pci_size_low, &mem_answer); 1895 } else { /* get non prefetchable memory */ 1896 pcicfg_get_mem(entry, 1897 reg[i].pci_size_low, &mem_answer); 1898 } 1899 pci_config_put64(handle, offset, mem_answer); 1900 DEBUG2("REGISTER off %x (64)LO ----> [0x%x]\n", 1901 offset, pci_config_get32(handle, offset)); 1902 DEBUG2("REGISTER off %x (64)HI ----> [0x%x]\n", 1903 offset + 4, 1904 pci_config_get32(handle, offset + 4)); 1905 1906 reg[i].pci_phys_hi |= PCI_REG_REL_M; 1907 reg[i].pci_phys_low = PCICFG_LOADDR(mem_answer); 1908 reg[i].pci_phys_mid = PCICFG_HIADDR(mem_answer); 1909 break; 1910 1911 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 1912 if (reg[i].pci_phys_hi & PCI_REG_PF_M) { 1913 /* allocate prefetchable memory */ 1914 pcicfg_get_pf_mem(entry, 1915 reg[i].pci_size_low, &mem_answer); 1916 } else { 1917 /* get non prefetchable memory */ 1918 pcicfg_get_mem(entry, 1919 reg[i].pci_size_low, &mem_answer); 1920 } 1921 1922 pci_config_put32(handle, offset, 1923 (uint32_t)mem_answer); 1924 1925 DEBUG2("REGISTER off %x(32)LO ----> [0x%x]\n", 1926 offset, pci_config_get32(handle, offset)); 1927 1928 reg[i].pci_phys_hi |= PCI_REG_REL_M; 1929 reg[i].pci_phys_low = (uint32_t)mem_answer; 1930 1931 break; 1932 case PCI_REG_ADDR_G(PCI_ADDR_IO): 1933 /* allocate I/O space from the allocator */ 1934 1935 (void) pcicfg_get_io(entry, reg[i].pci_size_low, 1936 &io_answer); 1937 pci_config_put32(handle, offset, io_answer); 1938 1939 DEBUG2("REGISTER off %x (I/O)LO ----> [0x%x]\n", 1940 offset, pci_config_get32(handle, offset)); 1941 1942 reg[i].pci_phys_hi |= PCI_REG_REL_M; 1943 reg[i].pci_phys_low = io_answer; 1944 1945 break; 1946 default: 1947 DEBUG0("Unknown register type\n"); 1948 kmem_free(reg, length); 1949 (void) pcicfg_config_teardown(&handle); 1950 entry->error = PCICFG_FAILURE; 1951 return (DDI_WALK_TERMINATE); 1952 } /* switch */ 1953 1954 /* 1955 * Now that memory locations are assigned, 1956 * update the assigned address property. 1957 */ 1958 if (pcicfg_update_assigned_prop(dip, ®[i]) 1959 != PCICFG_SUCCESS) { 1960 kmem_free(reg, length); 1961 (void) pcicfg_config_teardown(&handle); 1962 entry->error = PCICFG_FAILURE; 1963 return (DDI_WALK_TERMINATE); 1964 } 1965 } 1966 } 1967 (void) pcicfg_device_on(handle); 1968 1969 PCICFG_DUMP_DEVICE_CONFIG(handle); 1970 1971 (void) pcicfg_config_teardown(&handle); 1972 kmem_free((caddr_t)reg, length); 1973 return (DDI_WALK_CONTINUE); 1974 } 1975 1976 static int 1977 pcicfg_device_assign(dev_info_t *dip) 1978 { 1979 ddi_acc_handle_t handle; 1980 pci_regspec_t *reg; 1981 int length; 1982 int rcount; 1983 int i; 1984 int offset; 1985 ndi_ra_request_t request; 1986 uint64_t answer; 1987 uint64_t alen; 1988 1989 DEBUG1("%llx now under configuration\n", dip); 1990 1991 /* request.ra_len = PCICFG_ROUND_UP(request.ra_len, PCICFG_IOGRAN); */ 1992 if (pcicfg_ntbridge_child(dip) == DDI_SUCCESS) { 1993 1994 return (pcicfg_ntbridge_program_child(dip)); 1995 } 1996 /* 1997 * XXX Failure here should be noted 1998 */ 1999 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "reg", 2000 (caddr_t)®, &length) != DDI_PROP_SUCCESS) { 2001 DEBUG0("Failed to read reg property\n"); 2002 return (PCICFG_FAILURE); 2003 } 2004 2005 if (pcicfg_config_setup(dip, &handle) != DDI_SUCCESS) { 2006 DEBUG0("Failed to map config space!\n"); 2007 kmem_free(reg, length); 2008 return (PCICFG_FAILURE); 2009 } 2010 2011 /* 2012 * A single device 2013 * 2014 * For each "reg" property with a length, allocate memory 2015 * and program the base registers. 2016 */ 2017 2018 /* 2019 * If there is an interrupt pin set program 2020 * interrupt line with default values. 2021 */ 2022 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 2023 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 2024 } 2025 2026 bzero((caddr_t)&request, sizeof (ndi_ra_request_t)); 2027 2028 /* 2029 * Note: Both non-prefetchable and prefetchable memory space 2030 * allocations are made within 32bit space. Currently, BIOSs 2031 * allocate device memory for PCI devices within the 32bit space 2032 * so this will not be a problem. 2033 */ 2034 request.ra_flags |= NDI_RA_ALIGN_SIZE | NDI_RA_ALLOC_BOUNDED; 2035 request.ra_boundbase = 0; 2036 request.ra_boundlen = PCICFG_4GIG_LIMIT; 2037 2038 rcount = length / sizeof (pci_regspec_t); 2039 offset = PCI_CONF_BASE0; 2040 for (i = 0; i < rcount; i++) { 2041 char *mem_type; 2042 2043 if ((reg[i].pci_size_low != 0)|| (reg[i].pci_size_hi != 0)) { 2044 2045 offset = PCI_REG_REG_G(reg[i].pci_phys_hi); 2046 request.ra_len = reg[i].pci_size_low; 2047 2048 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) { 2049 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 2050 if (reg[i].pci_phys_hi & PCI_REG_PF_M) { 2051 mem_type = NDI_RA_TYPE_PCI_PREFETCH_MEM; 2052 } else { 2053 mem_type = NDI_RA_TYPE_MEM; 2054 } 2055 /* allocate memory space from the allocator */ 2056 if (ndi_ra_alloc(ddi_get_parent(dip), &request, 2057 &answer, &alen, mem_type, NDI_RA_PASS) 2058 != NDI_SUCCESS) { 2059 DEBUG0("Failed to allocate 64b mem\n"); 2060 kmem_free(reg, length); 2061 (void) pcicfg_config_teardown(&handle); 2062 return (PCICFG_NORESRC); 2063 } 2064 DEBUG3("64 addr = [0x%x.0x%x] len [0x%x]\n", 2065 PCICFG_HIADDR(answer), 2066 PCICFG_LOADDR(answer), alen); 2067 /* program the low word */ 2068 pci_config_put32(handle, offset, 2069 PCICFG_LOADDR(answer)); 2070 /* program the high word */ 2071 pci_config_put32(handle, offset + 4, 2072 PCICFG_HIADDR(answer)); 2073 2074 reg[i].pci_phys_hi |= PCI_REG_REL_M; 2075 reg[i].pci_phys_low = PCICFG_LOADDR(answer); 2076 reg[i].pci_phys_mid = PCICFG_HIADDR(answer); 2077 /* 2078 * currently support 32b address space 2079 * assignments only. 2080 */ 2081 reg[i].pci_phys_hi ^= 2082 PCI_ADDR_MEM64 ^ PCI_ADDR_MEM32; 2083 2084 offset += 8; 2085 break; 2086 2087 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 2088 if (reg[i].pci_phys_hi & PCI_REG_PF_M) 2089 mem_type = NDI_RA_TYPE_PCI_PREFETCH_MEM; 2090 else 2091 mem_type = NDI_RA_TYPE_MEM; 2092 /* allocate memory space from the allocator */ 2093 if (ndi_ra_alloc(ddi_get_parent(dip), &request, 2094 &answer, &alen, mem_type, NDI_RA_PASS) 2095 != NDI_SUCCESS) { 2096 DEBUG0("Failed to allocate 32b mem\n"); 2097 kmem_free(reg, length); 2098 (void) pcicfg_config_teardown(&handle); 2099 return (PCICFG_NORESRC); 2100 } 2101 DEBUG3("32 addr = [0x%x.0x%x] len [0x%x]\n", 2102 PCICFG_HIADDR(answer), 2103 PCICFG_LOADDR(answer), 2104 alen); 2105 /* program the low word */ 2106 pci_config_put32(handle, offset, 2107 PCICFG_LOADDR(answer)); 2108 2109 reg[i].pci_phys_hi |= PCI_REG_REL_M; 2110 reg[i].pci_phys_low = PCICFG_LOADDR(answer); 2111 reg[i].pci_phys_mid = 0; 2112 2113 offset += 4; 2114 break; 2115 case PCI_REG_ADDR_G(PCI_ADDR_IO): 2116 /* 2117 * Try to allocate I/O space. If it fails, 2118 * continue here instead of returning failure 2119 * so that the hotplug for drivers that don't 2120 * use I/O space can succeed, For drivers 2121 * that need to use I/O space, the hotplug 2122 * will still fail later during driver attach. 2123 */ 2124 if (ndi_ra_alloc(ddi_get_parent(dip), &request, 2125 &answer, &alen, NDI_RA_TYPE_IO, NDI_RA_PASS) 2126 != NDI_SUCCESS) { 2127 DEBUG0("Failed to allocate I/O\n"); 2128 continue; 2129 } 2130 DEBUG3("I/O addr = [0x%x.0x%x] len [0x%x]\n", 2131 PCICFG_HIADDR(answer), 2132 PCICFG_LOADDR(answer), alen); 2133 pci_config_put32(handle, offset, 2134 PCICFG_LOADDR(answer)); 2135 2136 reg[i].pci_phys_hi |= PCI_REG_REL_M; 2137 reg[i].pci_phys_low = PCICFG_LOADDR(answer); 2138 2139 offset += 4; 2140 break; 2141 default: 2142 DEBUG0("Unknown register type\n"); 2143 kmem_free(reg, length); 2144 (void) pcicfg_config_teardown(&handle); 2145 return (PCICFG_FAILURE); 2146 } /* switch */ 2147 2148 /* 2149 * Now that memory locations are assigned, 2150 * update the assigned address property. 2151 */ 2152 2153 if (pcicfg_update_assigned_prop(dip, ®[i]) 2154 != PCICFG_SUCCESS) { 2155 kmem_free(reg, length); 2156 (void) pcicfg_config_teardown(&handle); 2157 return (PCICFG_FAILURE); 2158 } 2159 } 2160 } 2161 2162 (void) pcicfg_device_on(handle); 2163 kmem_free(reg, length); 2164 2165 PCICFG_DUMP_DEVICE_CONFIG(handle); 2166 2167 (void) pcicfg_config_teardown(&handle); 2168 return (PCICFG_SUCCESS); 2169 } 2170 2171 static int 2172 pcicfg_device_assign_readonly(dev_info_t *dip) 2173 { 2174 ddi_acc_handle_t handle; 2175 pci_regspec_t *assigned; 2176 int length; 2177 int acount; 2178 int i; 2179 ndi_ra_request_t request; 2180 uint64_t answer; 2181 uint64_t alen; 2182 2183 DEBUG1("%llx now under configuration\n", dip); 2184 2185 /* 2186 * we don't support ntbridges for readonly probe. 2187 */ 2188 if (pcicfg_ntbridge_child(dip) == DDI_SUCCESS) { 2189 return (PCICFG_FAILURE); 2190 } 2191 2192 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 2193 DDI_PROP_DONTPASS, "assigned-addresses", (caddr_t)&assigned, 2194 &length) != DDI_PROP_SUCCESS) { 2195 DEBUG0("Failed to read assigned-addresses property\n"); 2196 return (PCICFG_FAILURE); 2197 } 2198 2199 if (pcicfg_config_setup(dip, &handle) != DDI_SUCCESS) { 2200 DEBUG0("Failed to map config space!\n"); 2201 kmem_free(assigned, length); 2202 return (PCICFG_FAILURE); 2203 } 2204 2205 /* 2206 * If there is an interrupt pin set program 2207 * interrupt line with default values. 2208 */ 2209 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 2210 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 2211 } 2212 /* 2213 * Note: Both non-prefetchable and prefetchable memory space 2214 * allocations are made within 32bit space. Currently, BIOSs 2215 * allocate device memory for PCI devices within the 32bit space 2216 * so this will not be a problem. 2217 */ 2218 bzero((caddr_t)&request, sizeof (ndi_ra_request_t)); 2219 2220 request.ra_flags = NDI_RA_ALLOC_SPECIFIED; /* specified addr */ 2221 request.ra_boundbase = 0; 2222 request.ra_boundlen = PCICFG_4GIG_LIMIT; 2223 2224 acount = length / sizeof (pci_regspec_t); 2225 for (i = 0; i < acount; i++) { 2226 char *mem_type; 2227 2228 if ((assigned[i].pci_size_low != 0)|| 2229 (assigned[i].pci_size_hi != 0)) { 2230 2231 request.ra_len = assigned[i].pci_size_low; 2232 2233 switch (PCI_REG_ADDR_G(assigned[i].pci_phys_hi)) { 2234 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 2235 request.ra_addr = (uint64_t)PCICFG_LADDR( 2236 assigned[i].pci_phys_low, 2237 assigned[i].pci_phys_mid); 2238 2239 if (assigned[i].pci_phys_hi & PCI_REG_PF_M) { 2240 mem_type = NDI_RA_TYPE_PCI_PREFETCH_MEM; 2241 } else { 2242 mem_type = NDI_RA_TYPE_MEM; 2243 } 2244 /* allocate memory space from the allocator */ 2245 if (ndi_ra_alloc(ddi_get_parent(dip), &request, 2246 &answer, &alen, mem_type, NDI_RA_PASS) 2247 != NDI_SUCCESS) { 2248 DEBUG0("Failed to allocate 64b mem\n"); 2249 kmem_free(assigned, length); 2250 return (PCICFG_NORESRC); 2251 } 2252 2253 break; 2254 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 2255 request.ra_addr = (uint64_t) 2256 assigned[i].pci_phys_low; 2257 2258 if (assigned[i].pci_phys_hi & PCI_REG_PF_M) 2259 mem_type = NDI_RA_TYPE_PCI_PREFETCH_MEM; 2260 else 2261 mem_type = NDI_RA_TYPE_MEM; 2262 /* allocate memory space from the allocator */ 2263 if (ndi_ra_alloc(ddi_get_parent(dip), &request, 2264 &answer, &alen, mem_type, NDI_RA_PASS) 2265 != NDI_SUCCESS) { 2266 DEBUG0("Failed to allocate 32b mem\n"); 2267 kmem_free(assigned, length); 2268 return (PCICFG_NORESRC); 2269 } 2270 2271 break; 2272 case PCI_REG_ADDR_G(PCI_ADDR_IO): 2273 request.ra_addr = (uint64_t) 2274 assigned[i].pci_phys_low; 2275 2276 /* allocate I/O space from the allocator */ 2277 if (ndi_ra_alloc(ddi_get_parent(dip), &request, 2278 &answer, &alen, NDI_RA_TYPE_IO, NDI_RA_PASS) 2279 != NDI_SUCCESS) { 2280 DEBUG0("Failed to allocate I/O\n"); 2281 kmem_free(assigned, length); 2282 return (PCICFG_NORESRC); 2283 } 2284 2285 break; 2286 default: 2287 DEBUG0("Unknown register type\n"); 2288 kmem_free(assigned, length); 2289 return (PCICFG_FAILURE); 2290 } /* switch */ 2291 } 2292 } 2293 2294 (void) pcicfg_device_on(handle); 2295 kmem_free(assigned, length); 2296 2297 PCICFG_DUMP_DEVICE_CONFIG(handle); 2298 2299 (void) pcicfg_config_teardown(&handle); 2300 return (PCICFG_SUCCESS); 2301 } 2302 2303 #ifdef DEBUG 2304 /* 2305 * This function is useful in debug mode, where we can measure how 2306 * much memory was wasted/unallocated in bridge device's domain. 2307 */ 2308 static uint64_t 2309 pcicfg_unused_space(hole_t *hole, uint32_t *hole_count) 2310 { 2311 uint64_t len = 0; 2312 uint32_t count = 0; 2313 2314 do { 2315 len += hole->len; 2316 hole = hole->next; 2317 count++; 2318 } while (hole); 2319 *hole_count = count; 2320 return (len); 2321 } 2322 #endif 2323 2324 /* 2325 * This function frees data structures that hold the hole information 2326 * which are allocated in pcicfg_alloc_hole(). This is not freeing 2327 * any memory allocated through NDI calls. 2328 */ 2329 static void 2330 pcicfg_free_hole(hole_t *addr_hole) 2331 { 2332 hole_t *nhole, *hole = addr_hole->next; 2333 2334 while (hole) { 2335 nhole = hole->next; 2336 kmem_free(hole, sizeof (hole_t)); 2337 hole = nhole; 2338 } 2339 } 2340 2341 static uint64_t 2342 pcicfg_alloc_hole(hole_t *addr_hole, uint64_t *alast, uint32_t length) 2343 { 2344 uint64_t actual_hole_start, ostart, olen; 2345 hole_t *hole = addr_hole, *thole, *nhole; 2346 2347 do { 2348 actual_hole_start = PCICFG_ROUND_UP(hole->start, length); 2349 if (((actual_hole_start - hole->start) + length) <= hole->len) { 2350 DEBUG3("hole found. start %llx, len %llx, req=0x%x\n", 2351 hole->start, hole->len, length); 2352 ostart = hole->start; 2353 olen = hole->len; 2354 /* current hole parameters adjust */ 2355 if ((actual_hole_start - hole->start) == 0) { 2356 hole->start += length; 2357 hole->len -= length; 2358 if (hole->start > *alast) 2359 *alast = hole->start; 2360 } else { 2361 hole->len = actual_hole_start - hole->start; 2362 nhole = (hole_t *)kmem_zalloc(sizeof (hole_t), 2363 KM_SLEEP); 2364 nhole->start = actual_hole_start + length; 2365 nhole->len = (ostart + olen) - nhole->start; 2366 nhole->next = NULL; 2367 thole = hole->next; 2368 hole->next = nhole; 2369 nhole->next = thole; 2370 if (nhole->start > *alast) 2371 *alast = nhole->start; 2372 DEBUG2("put new hole to %llx, %llx\n", 2373 nhole->start, nhole->len); 2374 } 2375 DEBUG2("adjust current hole to %llx, %llx\n", 2376 hole->start, hole->len); 2377 break; 2378 } 2379 actual_hole_start = 0; 2380 hole = hole->next; 2381 } while (hole); 2382 2383 DEBUG1("return hole at %llx\n", actual_hole_start); 2384 return (actual_hole_start); 2385 } 2386 2387 static void 2388 pcicfg_get_mem(pcicfg_phdl_t *entry, uint32_t length, uint64_t *ans) 2389 { 2390 uint64_t new_mem; 2391 2392 /* See if there is a hole, that can hold this request. */ 2393 new_mem = pcicfg_alloc_hole(&entry->mem_hole, &entry->memory_last, 2394 length); 2395 if (new_mem) { /* if non-zero, found a hole. */ 2396 if (ans != NULL) 2397 *ans = new_mem; 2398 } else 2399 cmn_err(CE_WARN, "No %u bytes memory window for %s\n", 2400 length, ddi_get_name(entry->dip)); 2401 } 2402 2403 static void 2404 pcicfg_get_io(pcicfg_phdl_t *entry, 2405 uint32_t length, uint32_t *ans) 2406 { 2407 uint32_t new_io; 2408 uint64_t io_last; 2409 2410 /* 2411 * See if there is a hole, that can hold this request. 2412 * Pass 64 bit parameters and then truncate to 32 bit. 2413 */ 2414 io_last = entry->io_last; 2415 new_io = (uint32_t)pcicfg_alloc_hole(&entry->io_hole, &io_last, length); 2416 if (new_io) { /* if non-zero, found a hole. */ 2417 entry->io_last = (uint32_t)io_last; 2418 if (ans != NULL) 2419 *ans = new_io; 2420 } else 2421 cmn_err(CE_WARN, "No %u bytes IO space window for %s\n", 2422 length, ddi_get_name(entry->dip)); 2423 } 2424 2425 static void 2426 pcicfg_get_pf_mem(pcicfg_phdl_t *entry, uint32_t length, uint64_t *ans) 2427 { 2428 uint64_t new_mem; 2429 2430 /* See if there is a hole, that can hold this request. */ 2431 new_mem = pcicfg_alloc_hole(&entry->pf_mem_hole, &entry->pf_memory_last, 2432 length); 2433 if (new_mem) { /* if non-zero, found a hole. */ 2434 if (ans != NULL) 2435 *ans = new_mem; 2436 } else 2437 cmn_err(CE_WARN, "No %u bytes PF memory window for %s\n", 2438 length, ddi_get_name(entry->dip)); 2439 } 2440 2441 static int 2442 pcicfg_sum_resources(dev_info_t *dip, void *hdl) 2443 { 2444 pcicfg_phdl_t *entry = (pcicfg_phdl_t *)hdl; 2445 pci_regspec_t *pci_rp; 2446 int length; 2447 int rcount; 2448 int i; 2449 ndi_ra_request_t *pf_mem_request; 2450 ndi_ra_request_t *mem_request; 2451 ndi_ra_request_t *io_request; 2452 uint8_t header_type; 2453 ddi_acc_handle_t handle; 2454 2455 entry->error = PCICFG_SUCCESS; 2456 2457 pf_mem_request = &entry->pf_mem_req; 2458 mem_request = &entry->mem_req; 2459 io_request = &entry->io_req; 2460 2461 if (pcicfg_config_setup(dip, &handle) != DDI_SUCCESS) { 2462 DEBUG0("Failed to map config space!\n"); 2463 entry->error = PCICFG_FAILURE; 2464 return (DDI_WALK_TERMINATE); 2465 } 2466 2467 header_type = pci_config_get8(handle, PCI_CONF_HEADER); 2468 2469 /* 2470 * If its a bridge - just record the highest bus seen 2471 */ 2472 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) { 2473 2474 if (entry->highest_bus < pci_config_get8(handle, 2475 PCI_BCNF_SECBUS)) { 2476 entry->highest_bus = 2477 pci_config_get8(handle, PCI_BCNF_SECBUS); 2478 } 2479 (void) pcicfg_config_teardown(&handle); 2480 entry->error = PCICFG_FAILURE; 2481 return (DDI_WALK_CONTINUE); 2482 } else { 2483 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 2484 "reg", (caddr_t)&pci_rp, &length) != DDI_PROP_SUCCESS) { 2485 /* 2486 * If one node in (the subtree of nodes) 2487 * doesn't have a "reg" property fail the 2488 * allocation. 2489 */ 2490 entry->memory_len = 0; 2491 entry->io_len = 0; 2492 entry->pf_memory_len = 0; 2493 entry->error = PCICFG_FAILURE; 2494 (void) pcicfg_config_teardown(&handle); 2495 return (DDI_WALK_TERMINATE); 2496 } 2497 /* 2498 * For each "reg" property with a length, add that to the 2499 * total memory (or I/O) to allocate. 2500 */ 2501 rcount = length / sizeof (pci_regspec_t); 2502 2503 for (i = 0; i < rcount; i++) { 2504 2505 switch (PCI_REG_ADDR_G(pci_rp[i].pci_phys_hi)) { 2506 2507 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 2508 if (pci_rp[i].pci_phys_hi & PCI_REG_PF_M) { 2509 pf_mem_request->ra_len = 2510 pci_rp[i].pci_size_low + 2511 PCICFG_ROUND_UP( 2512 pf_mem_request->ra_len, 2513 pci_rp[i].pci_size_low); 2514 DEBUG1("ADDING 32 --->0x%x\n", 2515 pci_rp[i].pci_size_low); 2516 } else { 2517 mem_request->ra_len = 2518 pci_rp[i].pci_size_low + 2519 PCICFG_ROUND_UP(mem_request->ra_len, 2520 pci_rp[i].pci_size_low); 2521 DEBUG1("ADDING 32 --->0x%x\n", 2522 pci_rp[i].pci_size_low); 2523 } 2524 2525 break; 2526 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 2527 if (pci_rp[i].pci_phys_hi & PCI_REG_PF_M) { 2528 pf_mem_request->ra_len = 2529 pci_rp[i].pci_size_low + 2530 PCICFG_ROUND_UP( 2531 pf_mem_request->ra_len, 2532 pci_rp[i].pci_size_low); 2533 DEBUG1("ADDING 64 --->0x%x\n", 2534 pci_rp[i].pci_size_low); 2535 } else { 2536 mem_request->ra_len = 2537 pci_rp[i].pci_size_low + 2538 PCICFG_ROUND_UP(mem_request->ra_len, 2539 pci_rp[i].pci_size_low); 2540 DEBUG1("ADDING 64 --->0x%x\n", 2541 pci_rp[i].pci_size_low); 2542 } 2543 2544 break; 2545 case PCI_REG_ADDR_G(PCI_ADDR_IO): 2546 io_request->ra_len = 2547 pci_rp[i].pci_size_low + 2548 PCICFG_ROUND_UP(io_request->ra_len, 2549 pci_rp[i].pci_size_low); 2550 DEBUG1("ADDING I/O --->0x%x\n", 2551 pci_rp[i].pci_size_low); 2552 break; 2553 default: 2554 /* Config space register - not included */ 2555 break; 2556 } 2557 } 2558 2559 /* 2560 * free the memory allocated by ddi_getlongprop 2561 */ 2562 kmem_free(pci_rp, length); 2563 2564 /* 2565 * continue the walk to the next sibling to sum memory 2566 */ 2567 2568 (void) pcicfg_config_teardown(&handle); 2569 2570 return (DDI_WALK_CONTINUE); 2571 } 2572 } 2573 2574 static int 2575 pcicfg_free_bridge_resources(dev_info_t *dip) 2576 { 2577 ppb_ranges_t *ranges; 2578 uint_t *bus; 2579 int k; 2580 int length = 0; 2581 int i; 2582 2583 2584 if ((i = ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 2585 "ranges", (caddr_t)&ranges, &length)) != DDI_PROP_SUCCESS) { 2586 DEBUG0("Failed to read ranges property\n"); 2587 if (ddi_get_child(dip)) { 2588 cmn_err(CE_WARN, "No ranges property found for %s", 2589 ddi_get_name(dip)); 2590 /* 2591 * strictly speaking, we can check for children with 2592 * assigned-addresses but for now it is better to 2593 * be conservative and assume that if there are child 2594 * nodes, then they do consume PCI memory or IO 2595 * resources, Hence return failure. 2596 */ 2597 return (PCICFG_FAILURE); 2598 } 2599 length = 0; 2600 } 2601 2602 for (i = 0; i < length / sizeof (ppb_ranges_t); i++) { 2603 char *mem_type; 2604 2605 if (ranges[i].size_low != 0 || ranges[i].size_high != 0) { 2606 switch (ranges[i].parent_high & PCI_REG_ADDR_M) { 2607 case PCI_ADDR_IO: 2608 DEBUG2("Free I/O base/length = " 2609 "[0x%x]/[0x%x]\n", ranges[i].child_low, 2610 ranges[i].size_low); 2611 if (ndi_ra_free(ddi_get_parent(dip), 2612 (uint64_t)ranges[i].child_low, 2613 (uint64_t)ranges[i].size_low, 2614 NDI_RA_TYPE_IO, NDI_RA_PASS) 2615 != NDI_SUCCESS) { 2616 DEBUG0("Trouble freeing " 2617 "PCI i/o space\n"); 2618 kmem_free(ranges, length); 2619 return (PCICFG_FAILURE); 2620 } 2621 break; 2622 case PCI_ADDR_MEM32: 2623 case PCI_ADDR_MEM64: 2624 if (ranges[i].parent_high & PCI_REG_PF_M) { 2625 DEBUG3("Free PF Memory base/length = " 2626 "[0x%x.0x%x]/[0x%x]\n", 2627 ranges[i].child_mid, 2628 ranges[i].child_low, 2629 ranges[i].size_low); 2630 mem_type = NDI_RA_TYPE_PCI_PREFETCH_MEM; 2631 } else { 2632 DEBUG3("Free Memory base/length" 2633 " = [0x%x.0x%x]/[0x%x]\n", 2634 ranges[i].child_mid, 2635 ranges[i].child_low, 2636 ranges[i].size_low) 2637 mem_type = NDI_RA_TYPE_MEM; 2638 } 2639 if (ndi_ra_free(ddi_get_parent(dip), 2640 PCICFG_LADDR(ranges[i].child_low, 2641 ranges[i].child_mid), 2642 (uint64_t)ranges[i].size_low, 2643 mem_type, NDI_RA_PASS) != NDI_SUCCESS) { 2644 DEBUG0("Trouble freeing " 2645 "PCI memory space\n"); 2646 kmem_free(ranges, length); 2647 return (PCICFG_FAILURE); 2648 } 2649 break; 2650 default: 2651 DEBUG0("Unknown memory space\n"); 2652 break; 2653 } 2654 } 2655 } 2656 2657 if (length) 2658 kmem_free(ranges, length); 2659 2660 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 2661 "bus-range", (caddr_t)&bus, &k) != DDI_PROP_SUCCESS) { 2662 DEBUG0("Failed to read bus-range property\n"); 2663 return (PCICFG_FAILURE); 2664 } 2665 2666 DEBUG2("Need to free bus [%d] range [%d]\n", 2667 bus[0], bus[1] - bus[0] + 1); 2668 2669 if (ndi_ra_free(ddi_get_parent(dip), (uint64_t)bus[0], 2670 (uint64_t)(bus[1] - bus[0] + 1), NDI_RA_TYPE_PCI_BUSNUM, 2671 NDI_RA_PASS) != NDI_SUCCESS) { 2672 DEBUG0("Failed to free a bus number\n"); 2673 kmem_free(bus, k); 2674 return (PCICFG_FAILURE); 2675 } 2676 2677 kmem_free(bus, k); 2678 return (PCICFG_SUCCESS); 2679 } 2680 2681 static int 2682 pcicfg_free_device_resources(dev_info_t *dip) 2683 { 2684 pci_regspec_t *assigned; 2685 2686 int length; 2687 int acount; 2688 int i; 2689 2690 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 2691 "assigned-addresses", (caddr_t)&assigned, &length) 2692 != DDI_PROP_SUCCESS) { 2693 DEBUG0("Failed to read assigned-addresses property\n"); 2694 return (PCICFG_FAILURE); 2695 } 2696 2697 /* 2698 * For each "assigned-addresses" property entry with a length, 2699 * call the memory allocation routines to return the 2700 * resource. 2701 */ 2702 acount = length / sizeof (pci_regspec_t); 2703 for (i = 0; i < acount; i++) { 2704 char *mem_type; 2705 2706 /* 2707 * Free the resource if the size of it is not zero. 2708 */ 2709 if ((assigned[i].pci_size_low != 0)|| 2710 (assigned[i].pci_size_hi != 0)) { 2711 switch (PCI_REG_ADDR_G(assigned[i].pci_phys_hi)) { 2712 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 2713 /* 2714 * Check the assigned address for zero. 2715 * (Workaround for Devconf (x86) bug to 2716 * skip bogus entry for ROM base address 2717 * register. If the assigned address is 2718 * zero then ignore the entry 2719 * (see bugid 4281306)). 2720 */ 2721 if (assigned[i].pci_phys_low == 0) 2722 break; /* ignore the entry */ 2723 2724 if (assigned[i].pci_phys_hi & PCI_REG_PF_M) 2725 mem_type = NDI_RA_TYPE_PCI_PREFETCH_MEM; 2726 else 2727 mem_type = NDI_RA_TYPE_MEM; 2728 2729 if (ndi_ra_free(ddi_get_parent(dip), 2730 (uint64_t)assigned[i].pci_phys_low, 2731 (uint64_t)assigned[i].pci_size_low, 2732 mem_type, NDI_RA_PASS) != NDI_SUCCESS) { 2733 DEBUG0("Trouble freeing " 2734 "PCI memory space\n"); 2735 kmem_free(assigned, length); 2736 return (PCICFG_FAILURE); 2737 } 2738 2739 DEBUG4("Returned 0x%x of 32 bit %s space" 2740 " @ 0x%x from register 0x%x\n", 2741 assigned[i].pci_size_low, mem_type, 2742 assigned[i].pci_phys_low, 2743 PCI_REG_REG_G(assigned[i].pci_phys_hi)); 2744 2745 break; 2746 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 2747 if (assigned[i].pci_phys_hi & PCI_REG_PF_M) 2748 mem_type = NDI_RA_TYPE_PCI_PREFETCH_MEM; 2749 else 2750 mem_type = NDI_RA_TYPE_MEM; 2751 2752 if (ndi_ra_free(ddi_get_parent(dip), 2753 PCICFG_LADDR(assigned[i].pci_phys_low, 2754 assigned[i].pci_phys_mid), 2755 (uint64_t)assigned[i].pci_size_low, 2756 mem_type, NDI_RA_PASS) != NDI_SUCCESS) { 2757 DEBUG0("Trouble freeing " 2758 "PCI memory space\n"); 2759 kmem_free(assigned, length); 2760 return (PCICFG_FAILURE); 2761 } 2762 2763 DEBUG5("Returned 0x%x of 64 bit %s space" 2764 " @ 0x%x.0x%x from register 0x%x\n", 2765 assigned[i].pci_size_low, 2766 mem_type, assigned[i].pci_phys_mid, 2767 assigned[i].pci_phys_low, 2768 PCI_REG_REG_G(assigned[i].pci_phys_hi)); 2769 2770 break; 2771 case PCI_REG_ADDR_G(PCI_ADDR_IO): 2772 if (ndi_ra_free(ddi_get_parent(dip), 2773 (uint64_t)assigned[i].pci_phys_low, 2774 (uint64_t)assigned[i].pci_size_low, 2775 NDI_RA_TYPE_IO, NDI_RA_PASS) != 2776 NDI_SUCCESS) { 2777 DEBUG0("Trouble freeing " 2778 "PCI IO space\n"); 2779 kmem_free(assigned, length); 2780 return (PCICFG_FAILURE); 2781 } 2782 DEBUG3("Returned 0x%x of IO space @ 0x%x from " 2783 "register 0x%x\n", assigned[i].pci_size_low, 2784 assigned[i].pci_phys_low, 2785 PCI_REG_REG_G(assigned[i].pci_phys_hi)); 2786 break; 2787 default: 2788 DEBUG0("Unknown register type\n"); 2789 kmem_free(assigned, length); 2790 return (PCICFG_FAILURE); 2791 } /* switch */ 2792 } 2793 } 2794 kmem_free(assigned, length); 2795 return (PCICFG_SUCCESS); 2796 } 2797 2798 static int 2799 pcicfg_free_resources(dev_info_t *dip, pcicfg_flags_t flags) 2800 { 2801 ddi_acc_handle_t handle; 2802 uint8_t header_type; 2803 2804 if (pci_config_setup(dip, &handle) != DDI_SUCCESS) { 2805 DEBUG0("Failed to map config space!\n"); 2806 return (PCICFG_FAILURE); 2807 } 2808 2809 header_type = pci_config_get8(handle, PCI_CONF_HEADER); 2810 2811 (void) pci_config_teardown(&handle); 2812 2813 /* 2814 * A different algorithm is used for bridges and leaf devices. 2815 */ 2816 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) { 2817 /* 2818 * We only support readonly probing for leaf devices. 2819 */ 2820 if (flags & PCICFG_FLAG_READ_ONLY) 2821 return (PCICFG_FAILURE); 2822 2823 if (pcicfg_free_bridge_resources(dip) != PCICFG_SUCCESS) { 2824 DEBUG0("Failed freeing up bridge resources\n"); 2825 return (PCICFG_FAILURE); 2826 } 2827 } else { 2828 if (pcicfg_free_device_resources(dip) != PCICFG_SUCCESS) { 2829 DEBUG0("Failed freeing up device resources\n"); 2830 return (PCICFG_FAILURE); 2831 } 2832 } 2833 2834 return (PCICFG_SUCCESS); 2835 } 2836 2837 #ifndef _DONT_USE_1275_GENERIC_NAMES 2838 static char * 2839 pcicfg_get_class_name(uint32_t classcode) 2840 { 2841 struct pcicfg_name_entry *ptr; 2842 2843 for (ptr = &pcicfg_class_lookup[0]; ptr->name != NULL; ptr++) { 2844 if (ptr->class_code == classcode) { 2845 return (ptr->name); 2846 } 2847 } 2848 return (NULL); 2849 } 2850 #endif /* _DONT_USE_1275_GENERIC_NAMES */ 2851 2852 static dev_info_t * 2853 pcicfg_devi_find(dev_info_t *dip, uint_t device, uint_t function) 2854 { 2855 struct pcicfg_find_ctrl ctrl; 2856 int count; 2857 2858 ctrl.device = device; 2859 ctrl.function = function; 2860 ctrl.dip = NULL; 2861 2862 ndi_devi_enter(dip, &count); 2863 ddi_walk_devs(ddi_get_child(dip), pcicfg_match_dev, (void *)&ctrl); 2864 ndi_devi_exit(dip, count); 2865 2866 return (ctrl.dip); 2867 } 2868 2869 static int 2870 pcicfg_match_dev(dev_info_t *dip, void *hdl) 2871 { 2872 struct pcicfg_find_ctrl *ctrl = (struct pcicfg_find_ctrl *)hdl; 2873 pci_regspec_t *pci_rp; 2874 int length; 2875 int pci_dev; 2876 int pci_func; 2877 2878 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 2879 "reg", (int **)&pci_rp, (uint_t *)&length) != DDI_PROP_SUCCESS) { 2880 ctrl->dip = NULL; 2881 return (DDI_WALK_TERMINATE); 2882 } 2883 2884 /* get the PCI device address info */ 2885 pci_dev = PCI_REG_DEV_G(pci_rp->pci_phys_hi); 2886 pci_func = PCI_REG_FUNC_G(pci_rp->pci_phys_hi); 2887 2888 /* 2889 * free the memory allocated by ddi_prop_lookup_int_array 2890 */ 2891 ddi_prop_free(pci_rp); 2892 2893 2894 if ((pci_dev == ctrl->device) && (pci_func == ctrl->function)) { 2895 /* found the match for the specified device address */ 2896 ctrl->dip = dip; 2897 return (DDI_WALK_TERMINATE); 2898 } 2899 2900 /* 2901 * continue the walk to the next sibling to look for a match. 2902 */ 2903 return (DDI_WALK_PRUNECHILD); 2904 } 2905 2906 static int 2907 pcicfg_update_assigned_prop(dev_info_t *dip, pci_regspec_t *newone) 2908 { 2909 int alen; 2910 pci_regspec_t *assigned; 2911 caddr_t newreg; 2912 uint_t status; 2913 2914 status = ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 2915 "assigned-addresses", (caddr_t)&assigned, &alen); 2916 switch (status) { 2917 case DDI_PROP_SUCCESS: 2918 break; 2919 case DDI_PROP_NO_MEMORY: 2920 DEBUG0("no memory for assigned-addresses property\n"); 2921 return (PCICFG_FAILURE); 2922 default: 2923 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 2924 "assigned-addresses", (int *)newone, 2925 sizeof (*newone)/sizeof (int)); 2926 return (PCICFG_SUCCESS); 2927 } 2928 2929 /* 2930 * Allocate memory for the existing 2931 * assigned-addresses(s) plus one and then 2932 * build it. 2933 */ 2934 2935 newreg = kmem_zalloc(alen+sizeof (*newone), KM_SLEEP); 2936 2937 bcopy(assigned, newreg, alen); 2938 bcopy(newone, newreg + alen, sizeof (*newone)); 2939 2940 /* 2941 * Write out the new "assigned-addresses" spec 2942 */ 2943 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 2944 "assigned-addresses", (int *)newreg, 2945 (alen + sizeof (*newone))/sizeof (int)); 2946 2947 kmem_free((caddr_t)newreg, alen+sizeof (*newone)); 2948 kmem_free(assigned, alen); 2949 2950 return (PCICFG_SUCCESS); 2951 } 2952 2953 static int 2954 pcicfg_update_ranges_prop(dev_info_t *dip, ppb_ranges_t *addition) 2955 { 2956 int rlen; 2957 ppb_ranges_t *ranges; 2958 caddr_t newreg; 2959 uint_t status; 2960 2961 status = ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 2962 "ranges", (caddr_t)&ranges, &rlen); 2963 2964 2965 switch (status) { 2966 case DDI_PROP_SUCCESS: 2967 break; 2968 case DDI_PROP_NO_MEMORY: 2969 DEBUG0("ranges present, but unable to get memory\n"); 2970 return (PCICFG_FAILURE); 2971 default: 2972 DEBUG0("no ranges property - creating one\n"); 2973 if (ndi_prop_update_int_array(DDI_DEV_T_NONE, 2974 dip, "ranges", (int *)addition, 2975 sizeof (ppb_ranges_t)/sizeof (int)) 2976 != DDI_SUCCESS) { 2977 DEBUG0("Did'nt create ranges property\n"); 2978 return (PCICFG_FAILURE); 2979 } 2980 return (PCICFG_SUCCESS); 2981 } 2982 2983 /* 2984 * Allocate memory for the existing ranges plus one and then 2985 * build it. 2986 */ 2987 newreg = kmem_zalloc(rlen+sizeof (ppb_ranges_t), KM_SLEEP); 2988 2989 bcopy(ranges, newreg, rlen); 2990 bcopy(addition, newreg + rlen, sizeof (ppb_ranges_t)); 2991 2992 /* 2993 * Write out the new "ranges" property 2994 */ 2995 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "ranges", 2996 (int *)newreg, (rlen + sizeof (ppb_ranges_t))/sizeof (int)); 2997 2998 DEBUG1("Updating ranges property for %d entries", 2999 rlen / sizeof (ppb_ranges_t) + 1); 3000 3001 kmem_free((caddr_t)newreg, rlen+sizeof (ppb_ranges_t)); 3002 3003 kmem_free((caddr_t)ranges, rlen); 3004 3005 return (PCICFG_SUCCESS); 3006 } 3007 3008 static int 3009 pcicfg_update_reg_prop(dev_info_t *dip, uint32_t regvalue, uint_t reg_offset) 3010 { 3011 int rlen; 3012 pci_regspec_t *reg; 3013 caddr_t newreg; 3014 uint32_t hiword; 3015 pci_regspec_t addition; 3016 uint32_t size; 3017 uint_t status; 3018 3019 status = ddi_getlongprop(DDI_DEV_T_ANY, 3020 dip, DDI_PROP_DONTPASS, "reg", (caddr_t)®, &rlen); 3021 3022 switch (status) { 3023 case DDI_PROP_SUCCESS: 3024 break; 3025 case DDI_PROP_NO_MEMORY: 3026 DEBUG0("reg present, but unable to get memory\n"); 3027 return (PCICFG_FAILURE); 3028 default: 3029 DEBUG0("no reg property\n"); 3030 return (PCICFG_FAILURE); 3031 } 3032 3033 /* 3034 * Allocate memory for the existing reg(s) plus one and then 3035 * build it. 3036 */ 3037 newreg = kmem_zalloc(rlen+sizeof (pci_regspec_t), KM_SLEEP); 3038 3039 /* 3040 * Build the regspec, then add it to the existing one(s) 3041 */ 3042 3043 hiword = PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi), 3044 PCI_REG_DEV_G(reg->pci_phys_hi), 3045 PCI_REG_FUNC_G(reg->pci_phys_hi), reg_offset); 3046 3047 if (reg_offset == PCI_CONF_ROM) { 3048 size = (~(PCI_BASE_ROM_ADDR_M & regvalue))+1; 3049 hiword |= PCI_ADDR_MEM32; 3050 } else { 3051 size = (~(PCI_BASE_M_ADDR_M & regvalue))+1; 3052 3053 if ((PCI_BASE_SPACE_M & regvalue) == PCI_BASE_SPACE_MEM) { 3054 if ((PCI_BASE_TYPE_M & regvalue) == PCI_BASE_TYPE_MEM) { 3055 hiword |= PCI_ADDR_MEM32; 3056 } else if ((PCI_BASE_TYPE_M & regvalue) 3057 == PCI_BASE_TYPE_ALL) { 3058 hiword |= PCI_ADDR_MEM64; 3059 } 3060 if (regvalue & PCI_BASE_PREF_M) 3061 hiword |= PCI_REG_PF_M; 3062 } else { 3063 hiword |= PCI_ADDR_IO; 3064 } 3065 } 3066 3067 addition.pci_phys_hi = hiword; 3068 addition.pci_phys_mid = 0; 3069 addition.pci_phys_low = 0; 3070 addition.pci_size_hi = 0; 3071 addition.pci_size_low = size; 3072 3073 bcopy(reg, newreg, rlen); 3074 bcopy(&addition, newreg + rlen, sizeof (pci_regspec_t)); 3075 3076 DEBUG3("updating BAR@off %x with %x,%x\n", reg_offset, hiword, size); 3077 /* 3078 * Write out the new "reg" property 3079 */ 3080 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 3081 (int *)newreg, (rlen + sizeof (pci_regspec_t))/sizeof (int)); 3082 3083 kmem_free((caddr_t)newreg, rlen+sizeof (pci_regspec_t)); 3084 kmem_free((caddr_t)reg, rlen); 3085 3086 return (PCICFG_SUCCESS); 3087 } 3088 3089 static int 3090 pcicfg_update_assigned_prop_value(dev_info_t *dip, uint32_t size, 3091 uint32_t base, uint32_t base_hi, uint_t reg_offset) 3092 { 3093 int rlen; 3094 pci_regspec_t *reg; 3095 uint32_t hiword; 3096 pci_regspec_t addition; 3097 uint_t status; 3098 3099 status = ddi_getlongprop(DDI_DEV_T_ANY, 3100 dip, DDI_PROP_DONTPASS, "reg", (caddr_t)®, &rlen); 3101 3102 switch (status) { 3103 case DDI_PROP_SUCCESS: 3104 break; 3105 case DDI_PROP_NO_MEMORY: 3106 DEBUG0("reg present, but unable to get memory\n"); 3107 return (PCICFG_FAILURE); 3108 default: 3109 /* 3110 * Since the config space "reg" entry should have been 3111 * created, we expect a "reg" property already 3112 * present here. 3113 */ 3114 DEBUG0("no reg property\n"); 3115 return (PCICFG_FAILURE); 3116 } 3117 3118 /* 3119 * Build the regspec, then add it to the existing one(s) 3120 */ 3121 3122 hiword = PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi), 3123 PCI_REG_DEV_G(reg->pci_phys_hi), 3124 PCI_REG_FUNC_G(reg->pci_phys_hi), reg_offset); 3125 3126 hiword |= PCI_REG_REL_M; 3127 3128 if (reg_offset == PCI_CONF_ROM) { 3129 hiword |= PCI_ADDR_MEM32; 3130 3131 base = PCI_BASE_ROM_ADDR_M & base; 3132 } else { 3133 if ((PCI_BASE_SPACE_M & base) == PCI_BASE_SPACE_MEM) { 3134 if ((PCI_BASE_TYPE_M & base) == PCI_BASE_TYPE_MEM) { 3135 hiword |= PCI_ADDR_MEM32; 3136 } else if ((PCI_BASE_TYPE_M & base) 3137 == PCI_BASE_TYPE_ALL) { 3138 hiword |= PCI_ADDR_MEM64; 3139 } 3140 if (base & PCI_BASE_PREF_M) 3141 hiword |= PCI_REG_PF_M; 3142 3143 base = PCI_BASE_M_ADDR_M & base; 3144 } else { 3145 hiword |= PCI_ADDR_IO; 3146 3147 base = PCI_BASE_IO_ADDR_M & base; 3148 base_hi = 0; 3149 } 3150 } 3151 3152 addition.pci_phys_hi = hiword; 3153 addition.pci_phys_mid = base_hi; 3154 addition.pci_phys_low = base; 3155 addition.pci_size_hi = 0; 3156 addition.pci_size_low = size; 3157 3158 DEBUG3("updating BAR@off %x with %x,%x\n", reg_offset, hiword, size); 3159 3160 kmem_free((caddr_t)reg, rlen); 3161 3162 return (pcicfg_update_assigned_prop(dip, &addition)); 3163 } 3164 3165 static void 3166 pcicfg_device_on(ddi_acc_handle_t config_handle) 3167 { 3168 /* 3169 * Enable memory, IO, and bus mastership 3170 * XXX should we enable parity, SERR#, 3171 * fast back-to-back, and addr. stepping? 3172 */ 3173 pci_config_put16(config_handle, PCI_CONF_COMM, 3174 pci_config_get16(config_handle, PCI_CONF_COMM) | 0x7); 3175 } 3176 3177 static void 3178 pcicfg_device_off(ddi_acc_handle_t config_handle) 3179 { 3180 /* 3181 * Disable I/O and memory traffic through the bridge 3182 */ 3183 pci_config_put16(config_handle, PCI_CONF_COMM, 0x0); 3184 } 3185 3186 /* 3187 * Setup the basic 1275 properties based on information found in the config 3188 * header of the PCI device 3189 */ 3190 static int 3191 pcicfg_set_standard_props(dev_info_t *dip, ddi_acc_handle_t config_handle, 3192 uint8_t pcie_dev) 3193 { 3194 int ret; 3195 uint16_t cap_id_loc, val; 3196 uint32_t wordval; 3197 uint8_t byteval; 3198 3199 /* These two exists only for non-bridges */ 3200 if (((pci_config_get8(config_handle, PCI_CONF_HEADER) & 3201 PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) && !pcie_dev) { 3202 byteval = pci_config_get8(config_handle, PCI_CONF_MIN_G); 3203 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3204 "min-grant", byteval)) != DDI_SUCCESS) { 3205 return (ret); 3206 } 3207 3208 byteval = pci_config_get8(config_handle, PCI_CONF_MAX_L); 3209 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3210 "max-latency", byteval)) != DDI_SUCCESS) { 3211 return (ret); 3212 } 3213 } 3214 3215 /* 3216 * These should always exist and have the value of the 3217 * corresponding register value 3218 */ 3219 val = pci_config_get16(config_handle, PCI_CONF_VENID); 3220 3221 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", val)) 3222 != DDI_SUCCESS) { 3223 return (ret); 3224 } 3225 val = pci_config_get16(config_handle, PCI_CONF_DEVID); 3226 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", val)) 3227 != DDI_SUCCESS) { 3228 return (ret); 3229 } 3230 byteval = pci_config_get8(config_handle, PCI_CONF_REVID); 3231 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3232 "revision-id", byteval)) != DDI_SUCCESS) { 3233 return (ret); 3234 } 3235 3236 wordval = (pci_config_get16(config_handle, PCI_CONF_SUBCLASS)<< 8) | 3237 (pci_config_get8(config_handle, PCI_CONF_PROGCLASS)); 3238 3239 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3240 "class-code", wordval)) != DDI_SUCCESS) { 3241 return (ret); 3242 } 3243 val = (pci_config_get16(config_handle, PCI_CONF_STAT) & 3244 PCI_STAT_DEVSELT); 3245 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3246 "devsel-speed", val)) != DDI_SUCCESS) { 3247 return (ret); 3248 } 3249 3250 /* 3251 * The next three are bits set in the status register. The property is 3252 * present (but with no value other than its own existence) if the bit 3253 * is set, non-existent otherwise 3254 */ 3255 if ((!pcie_dev) && 3256 (pci_config_get16(config_handle, PCI_CONF_STAT) & PCI_STAT_FBBC)) { 3257 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3258 "fast-back-to-back", 0)) != DDI_SUCCESS) { 3259 return (ret); 3260 } 3261 } 3262 if ((!pcie_dev) && 3263 (pci_config_get16(config_handle, PCI_CONF_STAT) & PCI_STAT_66MHZ)) { 3264 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3265 "66mhz-capable", 0)) != DDI_SUCCESS) { 3266 return (ret); 3267 } 3268 } 3269 if (pci_config_get16(config_handle, PCI_CONF_STAT) & PCI_STAT_UDF) { 3270 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3271 "udf-supported", 0)) != DDI_SUCCESS) { 3272 return (ret); 3273 } 3274 } 3275 3276 /* 3277 * These next three are optional and are not present 3278 * if the corresponding register is zero. If the value 3279 * is non-zero then the property exists with the value 3280 * of the register. 3281 */ 3282 if ((val = pci_config_get16(config_handle, PCI_CONF_SUBVENID)) != 0) { 3283 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3284 "subsystem-vendor-id", val)) != DDI_SUCCESS) { 3285 return (ret); 3286 } 3287 } 3288 if ((val = pci_config_get16(config_handle, PCI_CONF_SUBSYSID)) != 0) { 3289 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3290 "subsystem-id", val)) != DDI_SUCCESS) { 3291 return (ret); 3292 } 3293 } 3294 if ((val = pci_config_get16(config_handle, PCI_CONF_CACHE_LINESZ)) 3295 != 0) { 3296 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3297 "cache-line-size", val)) != DDI_SUCCESS) { 3298 return (ret); 3299 } 3300 } 3301 3302 /* 3303 * If the Interrupt Pin register is non-zero then the 3304 * interrupts property exists 3305 */ 3306 if ((byteval = pci_config_get8(config_handle, PCI_CONF_IPIN)) != 0) { 3307 /* 3308 * If interrupt pin is non-zero, 3309 * record the interrupt line used 3310 */ 3311 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3312 "interrupts", byteval)) != DDI_SUCCESS) { 3313 return (ret); 3314 } 3315 } 3316 (void) PCI_CAP_LOCATE(config_handle, PCI_CAP_ID_PCI_E, &cap_id_loc); 3317 if (pcie_dev && cap_id_loc != PCI_CAP_NEXT_PTR_NULL) { 3318 val = pci_config_get16(config_handle, cap_id_loc + PCIE_PCIECAP) 3319 & PCIE_PCIECAP_SLOT_IMPL; 3320 /* if slot implemented, get physical slot number */ 3321 if (val) { 3322 wordval = pci_config_get32(config_handle, cap_id_loc + 3323 PCIE_SLOTCAP); 3324 /* create the property only if slotnum set correctly? */ 3325 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3326 "physical-slot#", PCIE_SLOTCAP_PHY_SLOT_NUM( 3327 wordval))) != DDI_SUCCESS) { 3328 return (ret); 3329 } 3330 } 3331 } 3332 3333 return (PCICFG_SUCCESS); 3334 } 3335 3336 static int 3337 pcicfg_set_busnode_props(dev_info_t *dip, uint8_t pcie_device_type) 3338 { 3339 int ret; 3340 char device_type[8]; 3341 3342 if (pcie_device_type) 3343 (void) strcpy(device_type, "pciex"); 3344 else 3345 (void) strcpy(device_type, "pci"); 3346 3347 if ((ret = ndi_prop_update_string(DDI_DEV_T_NONE, dip, 3348 "device_type", device_type)) != DDI_SUCCESS) { 3349 return (ret); 3350 } 3351 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3352 "#address-cells", 3)) != DDI_SUCCESS) { 3353 return (ret); 3354 } 3355 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, "#size-cells", 2)) 3356 != DDI_SUCCESS) { 3357 return (ret); 3358 } 3359 return (PCICFG_SUCCESS); 3360 } 3361 3362 static int 3363 pcicfg_set_childnode_props(dev_info_t *dip, ddi_acc_handle_t config_handle, 3364 uint8_t pcie_dev) 3365 { 3366 3367 int ret; 3368 char *name; 3369 char buffer[64], pprefix[8], nprefix[8]; 3370 uint16_t classcode; 3371 uint8_t revid, pif, pclass, psubclass; 3372 char *compat[24]; 3373 int i; 3374 int n; 3375 uint16_t sub_vid, sub_sid, vid, did; 3376 /* set the property prefix based on the device type */ 3377 if (pcie_dev) { 3378 (void) sprintf(pprefix, "pciex"); 3379 } else 3380 (void) sprintf(pprefix, "pci"); 3381 3382 /* set the prefix right for name property */ 3383 /* x86 platforms need to go with pci for upgrade purposes */ 3384 (void) sprintf(nprefix, "pci"); 3385 3386 /* 3387 * NOTE: These are for both a child and PCI-PCI bridge node 3388 */ 3389 sub_vid = pci_config_get16(config_handle, PCI_CONF_SUBVENID); 3390 sub_sid = pci_config_get16(config_handle, PCI_CONF_SUBSYSID); 3391 vid = pci_config_get16(config_handle, PCI_CONF_VENID); 3392 did = pci_config_get16(config_handle, PCI_CONF_DEVID); 3393 revid = pci_config_get8(config_handle, PCI_CONF_REVID); 3394 pif = pci_config_get8(config_handle, PCI_CONF_PROGCLASS); 3395 classcode = pci_config_get16(config_handle, PCI_CONF_SUBCLASS); 3396 pclass = pci_config_get8(config_handle, PCI_CONF_BASCLASS); 3397 psubclass = pci_config_get8(config_handle, PCI_CONF_SUBCLASS); 3398 3399 if (!sub_vid) 3400 (void) sprintf(buffer, "%s%x,%x", nprefix, vid, did); 3401 else 3402 (void) sprintf(buffer, "%s%x,%x", nprefix, sub_vid, sub_sid); 3403 3404 /* 3405 * In some environments, trying to use "generic" 1275 names is 3406 * not the convention. In those cases use the name as created 3407 * above. In all the rest of the cases, check to see if there 3408 * is a generic name first. 3409 */ 3410 #ifdef _DONT_USE_1275_GENERIC_NAMES 3411 name = buffer; 3412 #else 3413 if ((name = pcicfg_get_class_name(classcode)) == NULL) { 3414 /* 3415 * Set name to the above fabricated name 3416 */ 3417 name = buffer; 3418 } 3419 #endif 3420 3421 /* 3422 * The node name field needs to be filled in with the name 3423 */ 3424 if (ndi_devi_set_nodename(dip, name, 0) != NDI_SUCCESS) { 3425 DEBUG0("Failed to set nodename for node\n"); 3426 return (PCICFG_FAILURE); 3427 } 3428 3429 /* 3430 * Create the compatible property as an array of pointers 3431 * to strings. Start with the buffer created above. 3432 */ 3433 n = 0; 3434 3435 /* 3436 * Setup 'compatible' as per the PCI2.1 bindings document. 3437 * pci[ex]VVVV,DDDD.SSSS.ssss.RR 3438 * pci[ex]VVVV,DDDD.SSSS.ssss 3439 * pciSSSS.ssss -> not created for PCIe as per PCIe bindings 3440 * pci[ex]VVVV,DDDD.RR 3441 * pci[ex]VVVV,DDDD 3442 * pci[ex]class,CCSSPP 3443 * pci[ex]class,CCSS 3444 * Add legacy entries for compatibility with legacy devices and OS 3445 * for x86. 3446 * pciVVVV,DDDD.SSSS.ssss.RR 3447 * pciVVVV,DDDD.SSSS.ssss 3448 * pciSSSS.ssss 3449 * pciVVVV,DDDD.RR 3450 * pciVVVV,DDDD 3451 * pciclass,CCSSPP 3452 * pciclass,CCSS 3453 */ 3454 3455 do { 3456 if (sub_vid) { 3457 /* pci[ex]VVVV,DDDD.SSSS.ssss.RR */ 3458 (void) sprintf(buffer, "%s%x,%x.%x.%x.%x", pprefix, vid, 3459 did, sub_vid, sub_sid, revid); 3460 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3461 (void) strcpy(compat[n++], buffer); 3462 3463 /* pci[ex]VVVV,DDDD.SSSS.ssss */ 3464 (void) sprintf(buffer, "%s%x,%x.%x.%x", pprefix, vid, 3465 did, sub_vid, sub_sid); 3466 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3467 (void) strcpy(compat[n++], buffer); 3468 3469 /* pciSSSS.ssss -> not created for PCIe as per PCIe */ 3470 /* binding to IEEE 1275 spec. */ 3471 if (!pcie_dev && pcicfg_do_legacy_props) { 3472 (void) sprintf(buffer, "pci%x,%x", sub_vid, 3473 sub_sid); 3474 compat[n] = kmem_alloc(strlen(buffer) + 1, 3475 KM_SLEEP); 3476 (void) strcpy(compat[n++], buffer); 3477 } 3478 } 3479 3480 /* pci[ex]VVVV,DDDD.RR */ 3481 (void) sprintf(buffer, "%s%x,%x.%x", pprefix, vid, did, revid); 3482 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3483 (void) strcpy(compat[n++], buffer); 3484 3485 /* pci[ex]VVVV,DDDD */ 3486 (void) sprintf(buffer, "%s%x,%x", pprefix, vid, did); 3487 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3488 (void) strcpy(compat[n++], buffer); 3489 3490 /* pci[ex]class,CCSSPP */ 3491 (void) sprintf(buffer, "%sclass,%02x%02x%02x", pprefix, pclass, 3492 psubclass, pif); 3493 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3494 (void) strcpy(compat[n++], buffer); 3495 3496 /* pci[ex]class,CCSS */ 3497 (void) sprintf(buffer, "%sclass,%04x", pprefix, classcode); 3498 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3499 (void) strcpy(compat[n++], buffer); 3500 3501 if (!pcie_dev) 3502 break; 3503 3504 /* also add compatible names using "pci" prefix */ 3505 (void) sprintf(pprefix, "pci"); 3506 pcie_dev = 0; 3507 3508 } while (pcicfg_do_legacy_props); 3509 3510 ret = ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, "compatible", 3511 (char **)compat, n); 3512 3513 for (i = 0; i < n; i++) { 3514 kmem_free(compat[i], strlen(compat[i]) + 1); 3515 } 3516 3517 return (ret); 3518 } 3519 3520 /* 3521 * Program the bus numbers into the bridge 3522 */ 3523 static void 3524 pcicfg_set_bus_numbers(ddi_acc_handle_t config_handle, 3525 uint_t primary, uint_t secondary, uint_t subordinate) 3526 { 3527 DEBUG3("Setting bridge bus-range %d,%d,%d\n", primary, secondary, 3528 subordinate); 3529 /* 3530 * Primary bus# 3531 */ 3532 pci_config_put8(config_handle, PCI_BCNF_PRIBUS, primary); 3533 3534 /* 3535 * Secondary bus# 3536 */ 3537 pci_config_put8(config_handle, PCI_BCNF_SECBUS, secondary); 3538 3539 /* 3540 * Set the subordinate bus number to ff in order to pass through any 3541 * type 1 cycle with a bus number higher than the secondary bus# 3542 */ 3543 pci_config_put8(config_handle, PCI_BCNF_SUBBUS, subordinate); 3544 } 3545 3546 /* 3547 * Put bridge registers into initial state 3548 */ 3549 static void 3550 pcicfg_setup_bridge(pcicfg_phdl_t *entry, 3551 ddi_acc_handle_t handle) 3552 { 3553 /* 3554 * The highest bus seen during probing is the max-subordinate bus 3555 */ 3556 pci_config_put8(handle, PCI_BCNF_SUBBUS, entry->highest_bus); 3557 3558 /* 3559 * Reset the secondary bus 3560 */ 3561 pci_config_put16(handle, PCI_BCNF_BCNTRL, 3562 pci_config_get16(handle, PCI_BCNF_BCNTRL) | 0x40); 3563 drv_usecwait(1000); 3564 pci_config_put16(handle, PCI_BCNF_BCNTRL, 3565 pci_config_get16(handle, PCI_BCNF_BCNTRL) & ~0x40); 3566 drv_usecwait(1000); 3567 3568 /* 3569 * Program the memory base register with the 3570 * start of the memory range 3571 */ 3572 pci_config_put16(handle, PCI_BCNF_MEM_BASE, 3573 PCICFG_HIWORD(PCICFG_LOADDR(entry->memory_last))); 3574 3575 /* 3576 * Program the I/O base register with the start of the I/O range 3577 */ 3578 pci_config_put8(handle, PCI_BCNF_IO_BASE_LOW, 3579 PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(entry->io_last)))); 3580 pci_config_put16(handle, PCI_BCNF_IO_BASE_HI, 3581 PCICFG_HIWORD(PCICFG_LOADDR(entry->io_last))); 3582 3583 /* 3584 * Program the PF memory base register with the start of 3585 * PF memory range 3586 */ 3587 pci_config_put16(handle, PCI_BCNF_PF_BASE_LOW, 3588 PCICFG_HIWORD(PCICFG_LOADDR(entry->pf_memory_last))); 3589 pci_config_put32(handle, PCI_BCNF_PF_BASE_HIGH, 3590 PCICFG_HIADDR(entry->pf_memory_last)); 3591 3592 /* 3593 * Clear status bits 3594 */ 3595 pci_config_put16(handle, PCI_BCNF_SEC_STATUS, 0xffff); 3596 3597 /* 3598 * Needs to be set to this value 3599 */ 3600 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 3601 3602 /* 3603 * XXX - may be delay should be used since noone configures 3604 * devices in the interrupt context 3605 */ 3606 drv_usecwait(pcicfg_sec_reset_delay); /* 1 sec wait */ 3607 } 3608 3609 static void 3610 pcicfg_update_bridge(pcicfg_phdl_t *entry, 3611 ddi_acc_handle_t handle) 3612 { 3613 uint_t length; 3614 3615 /* 3616 * Program the memory limit register with the end of the memory range 3617 */ 3618 3619 DEBUG1("DOWN ROUNDED ===>[0x%x]\n", 3620 PCICFG_ROUND_DOWN(entry->memory_last, PCICFG_MEMGRAN)); 3621 3622 pci_config_put16(handle, PCI_BCNF_MEM_LIMIT, 3623 PCICFG_HIWORD(PCICFG_LOADDR( 3624 PCICFG_ROUND_DOWN(entry->memory_last, PCICFG_MEMGRAN)))); 3625 /* 3626 * Since this is a bridge, the rest of this range will 3627 * be responded to by the bridge. We have to round up 3628 * so no other device claims it. 3629 */ 3630 if ((length = (PCICFG_ROUND_UP(entry->memory_last, PCICFG_MEMGRAN) 3631 - entry->memory_last)) > 0) { 3632 (void) pcicfg_get_mem(entry, length, NULL); 3633 DEBUG1("Added [0x%x]at the top of the bridge (mem)\n", length); 3634 } 3635 3636 /* 3637 * Program the PF memory limit register with the end of the memory range 3638 */ 3639 3640 DEBUG1("DOWN ROUNDED ===>[0x%x]\n", 3641 PCICFG_ROUND_DOWN(entry->pf_memory_last, PCICFG_MEMGRAN)); 3642 3643 pci_config_put16(handle, PCI_BCNF_PF_LIMIT_LOW, 3644 PCICFG_HIWORD(PCICFG_LOADDR(PCICFG_ROUND_DOWN( 3645 entry->pf_memory_last, PCICFG_MEMGRAN)))); 3646 pci_config_put32(handle, PCI_BCNF_PF_LIMIT_HIGH, PCICFG_HIADDR( 3647 PCICFG_ROUND_DOWN(entry->pf_memory_last, PCICFG_MEMGRAN))); 3648 if ((length = (PCICFG_ROUND_UP(entry->pf_memory_last, PCICFG_MEMGRAN) 3649 - entry->pf_memory_last)) > 0) { 3650 (void) pcicfg_get_pf_mem(entry, length, NULL); 3651 DEBUG1("Added [0x%x]at the top of the bridge (PF mem)\n", 3652 length); 3653 } 3654 3655 /* 3656 * Program the I/O limit register with the end of the I/O range 3657 */ 3658 pci_config_put8(handle, PCI_BCNF_IO_LIMIT_LOW, 3659 PCICFG_HIBYTE(PCICFG_LOWORD( 3660 PCICFG_LOADDR(PCICFG_ROUND_DOWN(entry->io_last, PCICFG_IOGRAN))))); 3661 3662 pci_config_put16(handle, PCI_BCNF_IO_LIMIT_HI, PCICFG_HIWORD( 3663 PCICFG_LOADDR(PCICFG_ROUND_DOWN(entry->io_last, PCICFG_IOGRAN)))); 3664 3665 /* 3666 * Same as above for I/O space. Since this is a 3667 * bridge, the rest of this range will be responded 3668 * to by the bridge. We have to round up so no 3669 * other device claims it. 3670 */ 3671 if ((length = (PCICFG_ROUND_UP(entry->io_last, PCICFG_IOGRAN) 3672 - entry->io_last)) > 0) { 3673 (void) pcicfg_get_io(entry, length, NULL); 3674 DEBUG1("Added [0x%x]at the top of the bridge (I/O)\n", length); 3675 } 3676 } 3677 3678 static int 3679 pcicfg_probe_children(dev_info_t *parent, uint_t bus, uint_t device, 3680 uint_t func, uint_t *highest_bus, pcicfg_flags_t flags, boolean_t is_pcie) 3681 { 3682 dev_info_t *new_child; 3683 ddi_acc_handle_t config_handle; 3684 uint8_t header_type, pcie_dev = 0; 3685 int ret = PCICFG_FAILURE; 3686 3687 /* 3688 * This node will be put immediately below 3689 * "parent". Allocate a blank device node. It will either 3690 * be filled in or freed up based on further probing. 3691 */ 3692 3693 ndi_devi_alloc_sleep(parent, DEVI_PSEUDO_NEXNAME, 3694 (pnode_t)DEVI_SID_NODEID, &new_child); 3695 3696 if (pcicfg_add_config_reg(new_child, bus, device, func) 3697 != DDI_SUCCESS) { 3698 DEBUG0("pcicfg_probe_children():Failed to add candidate REG\n"); 3699 goto failedconfig; 3700 } 3701 3702 if ((ret = pcicfg_config_setup(new_child, &config_handle)) 3703 != PCICFG_SUCCESS) { 3704 if (ret == PCICFG_NODEVICE) { 3705 (void) ndi_devi_free(new_child); 3706 return (ret); 3707 } 3708 DEBUG0("pcicfg_probe_children():" 3709 "Failed to setup config space\n"); 3710 goto failedconfig; 3711 } 3712 3713 if (is_pcie) 3714 (void) pcie_init_bus(new_child, PCI_GETBDF(bus, device, func), 3715 PCIE_BUS_INITIAL); 3716 3717 /* 3718 * As soon as we have access to config space, 3719 * turn off device. It will get turned on 3720 * later (after memory is assigned). 3721 */ 3722 (void) pcicfg_device_off(config_handle); 3723 3724 /* check if we are PCIe device */ 3725 if (pcicfg_pcie_dev(new_child, config_handle) == DDI_SUCCESS) { 3726 DEBUG0("PCIe device detected\n"); 3727 pcie_dev = 1; 3728 } 3729 3730 /* 3731 * Set 1275 properties common to all devices 3732 */ 3733 if (pcicfg_set_standard_props(new_child, config_handle, pcie_dev) 3734 != PCICFG_SUCCESS) { 3735 DEBUG0("Failed to set standard properties\n"); 3736 goto failedchild; 3737 } 3738 3739 /* 3740 * Child node properties NOTE: Both for PCI-PCI bridge and child node 3741 */ 3742 if (pcicfg_set_childnode_props(new_child, config_handle, pcie_dev) 3743 != PCICFG_SUCCESS) { 3744 goto failedchild; 3745 } 3746 3747 header_type = pci_config_get8(config_handle, PCI_CONF_HEADER); 3748 3749 /* 3750 * If this is not a multi-function card only probe function zero. 3751 */ 3752 if ((!(header_type & PCI_HEADER_MULTI)) && (func != 0)) { 3753 3754 ret = PCICFG_NODEVICE; 3755 goto failedchild; 3756 } 3757 3758 /* 3759 * Attach the child to its parent 3760 */ 3761 (void) i_ndi_config_node(new_child, DS_LINKED, 0); 3762 3763 DEVI_SET_PCI(new_child); 3764 3765 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) { 3766 3767 DEBUG3("--Bridge found bus [0x%x] device[0x%x] func [0x%x]\n", 3768 bus, device, func); 3769 3770 /* Only support read-only probe for leaf device */ 3771 if (flags & PCICFG_FLAG_READ_ONLY) 3772 goto failedchild; 3773 3774 ret = pcicfg_probe_bridge(new_child, config_handle, bus, 3775 highest_bus, is_pcie); 3776 if (ret != PCICFG_SUCCESS) { 3777 (void) pcicfg_free_bridge_resources(new_child); 3778 goto failedchild; 3779 } 3780 3781 } else { 3782 3783 DEBUG3("--Leaf device found bus [0x%x] device" 3784 "[0x%x] func [0x%x]\n", bus, device, func); 3785 3786 if (flags & PCICFG_FLAG_READ_ONLY) { 3787 /* 3788 * with read-only probe, don't do any resource 3789 * allocation, just read the BARs and update props. 3790 */ 3791 ret = pcicfg_populate_props_from_bar(new_child, 3792 config_handle); 3793 if (ret != PCICFG_SUCCESS) 3794 goto failedchild; 3795 3796 /* 3797 * now allocate the resources, just remove the 3798 * resources from the parent busra pool. 3799 */ 3800 ret = pcicfg_device_assign_readonly(new_child); 3801 if (ret != PCICFG_SUCCESS) { 3802 (void) pcicfg_free_device_resources(new_child); 3803 goto failedchild; 3804 } 3805 3806 } else { 3807 /* 3808 * update "reg" property by sizing the BARs. 3809 */ 3810 ret = pcicfg_populate_reg_props(new_child, 3811 config_handle); 3812 if (ret != PCICFG_SUCCESS) 3813 goto failedchild; 3814 3815 /* now allocate & program the resources */ 3816 ret = pcicfg_device_assign(new_child); 3817 if (ret != PCICFG_SUCCESS) { 3818 (void) pcicfg_free_device_resources(new_child); 3819 goto failedchild; 3820 } 3821 } 3822 3823 (void) ndi_devi_bind_driver(new_child, 0); 3824 } 3825 3826 (void) pcicfg_config_teardown(&config_handle); 3827 3828 /* 3829 * Properties have been setted up, so initialize the remaining 3830 * bus_t fields 3831 */ 3832 if (is_pcie) 3833 (void) pcie_init_bus(new_child, 0, PCIE_BUS_FINAL); 3834 3835 return (PCICFG_SUCCESS); 3836 3837 failedchild: 3838 /* 3839 * XXX check if it should be taken offline (if online) 3840 */ 3841 (void) pcicfg_config_teardown(&config_handle); 3842 3843 if (is_pcie) 3844 pcie_fini_bus(new_child, PCIE_BUS_FINAL); 3845 3846 failedconfig: 3847 3848 (void) ndi_devi_free(new_child); 3849 return (ret); 3850 } 3851 3852 /* 3853 * Sizing the BARs and update "reg" property 3854 */ 3855 static int 3856 pcicfg_populate_reg_props(dev_info_t *new_child, 3857 ddi_acc_handle_t config_handle) 3858 { 3859 int i; 3860 uint32_t request; 3861 3862 i = PCI_CONF_BASE0; 3863 3864 while (i <= PCI_CONF_BASE5) { 3865 3866 pci_config_put32(config_handle, i, 0xffffffff); 3867 3868 request = pci_config_get32(config_handle, i); 3869 /* 3870 * If its a zero length, don't do 3871 * any programming. 3872 */ 3873 if (request != 0) { 3874 /* 3875 * Add to the "reg" property 3876 */ 3877 if (pcicfg_update_reg_prop(new_child, 3878 request, i) != PCICFG_SUCCESS) { 3879 goto failedchild; 3880 } 3881 } else { 3882 DEBUG1("BASE register [0x%x] asks for " 3883 "[0x0]=[0x0](32)\n", i); 3884 i += 4; 3885 continue; 3886 } 3887 3888 /* 3889 * Increment by eight if it is 64 bit address space 3890 */ 3891 if ((PCI_BASE_TYPE_M & request) == PCI_BASE_TYPE_ALL) { 3892 DEBUG3("BASE register [0x%x] asks for " 3893 "[0x%x]=[0x%x] (64)\n", 3894 i, request, (~(PCI_BASE_M_ADDR_M & request))+1); 3895 i += 8; 3896 } else { 3897 DEBUG3("BASE register [0x%x] asks for " 3898 "[0x%x]=[0x%x](32)\n", 3899 i, request, (~(PCI_BASE_M_ADDR_M & request))+1); 3900 i += 4; 3901 } 3902 } 3903 3904 /* 3905 * Get the ROM size and create register for it 3906 */ 3907 pci_config_put32(config_handle, PCI_CONF_ROM, 0xfffffffe); 3908 3909 request = pci_config_get32(config_handle, PCI_CONF_ROM); 3910 /* 3911 * If its a zero length, don't do 3912 * any programming. 3913 */ 3914 3915 if (request != 0) { 3916 DEBUG3("BASE register [0x%x] asks for [0x%x]=[0x%x]\n", 3917 PCI_CONF_ROM, request, 3918 (~(PCI_BASE_ROM_ADDR_M & request)) + 1); 3919 /* 3920 * Add to the "reg" property 3921 */ 3922 if (pcicfg_update_reg_prop(new_child, request, PCI_CONF_ROM) 3923 != PCICFG_SUCCESS) { 3924 goto failedchild; 3925 } 3926 } 3927 3928 return (PCICFG_SUCCESS); 3929 3930 failedchild: 3931 return (PCICFG_FAILURE); 3932 } 3933 3934 /* 3935 * Read the BARs and update properties. Used in virtual hotplug. 3936 */ 3937 static int 3938 pcicfg_populate_props_from_bar(dev_info_t *new_child, 3939 ddi_acc_handle_t config_handle) 3940 { 3941 uint32_t request, base, base_hi, size; 3942 int i; 3943 3944 i = PCI_CONF_BASE0; 3945 3946 while (i <= PCI_CONF_BASE5) { 3947 /* 3948 * determine the size of the address space 3949 */ 3950 base = pci_config_get32(config_handle, i); 3951 pci_config_put32(config_handle, i, 0xffffffff); 3952 request = pci_config_get32(config_handle, i); 3953 pci_config_put32(config_handle, i, base); 3954 3955 /* 3956 * If its a zero length, don't do any programming. 3957 */ 3958 if (request != 0) { 3959 /* 3960 * Add to the "reg" property 3961 */ 3962 if (pcicfg_update_reg_prop(new_child, 3963 request, i) != PCICFG_SUCCESS) { 3964 goto failedchild; 3965 } 3966 3967 if ((PCI_BASE_SPACE_IO & request) == 0 && 3968 (PCI_BASE_TYPE_M & request) == PCI_BASE_TYPE_ALL) { 3969 base_hi = pci_config_get32(config_handle, i+4); 3970 } else { 3971 base_hi = 0; 3972 } 3973 /* 3974 * Add to "assigned-addresses" property 3975 */ 3976 size = (~(PCI_BASE_M_ADDR_M & request))+1; 3977 if (pcicfg_update_assigned_prop_value(new_child, 3978 size, base, base_hi, i) != PCICFG_SUCCESS) { 3979 goto failedchild; 3980 } 3981 } else { 3982 DEBUG1("BASE register [0x%x] asks for [0x0]=[0x0]" 3983 "(32)\n", i); 3984 i += 4; 3985 continue; 3986 } 3987 3988 /* 3989 * Increment by eight if it is 64 bit address space 3990 */ 3991 if ((PCI_BASE_TYPE_M & request) == PCI_BASE_TYPE_ALL) { 3992 DEBUG3("BASE register [0x%x] asks for [0x%x]=[0x%x]" 3993 "(64)\n", i, request, 3994 (~(PCI_BASE_M_ADDR_M & request)) + 1); 3995 i += 8; 3996 } else { 3997 DEBUG3("BASE register [0x%x] asks for [0x%x]=[0x%x]" 3998 "(32)\n", i, request, 3999 (~(PCI_BASE_M_ADDR_M & request)) + 1); 4000 i += 4; 4001 } 4002 } 4003 4004 /* 4005 * Get the ROM size and create register for it 4006 */ 4007 base = pci_config_get32(config_handle, PCI_CONF_ROM); 4008 pci_config_put32(config_handle, PCI_CONF_ROM, 0xfffffffe); 4009 request = pci_config_get32(config_handle, PCI_CONF_ROM); 4010 pci_config_put32(config_handle, PCI_CONF_ROM, base); 4011 4012 /* 4013 * If its a zero length, don't do 4014 * any programming. 4015 */ 4016 if (request != 0) { 4017 DEBUG3("BASE register [0x%x] asks for [0x%x]=[0x%x]\n", 4018 PCI_CONF_ROM, request, 4019 (~(PCI_BASE_ROM_ADDR_M & request)) + 1); 4020 /* 4021 * Add to the "reg" property 4022 */ 4023 if (pcicfg_update_reg_prop(new_child, request, PCI_CONF_ROM) 4024 != PCICFG_SUCCESS) { 4025 goto failedchild; 4026 } 4027 /* 4028 * Add to "assigned-addresses" property 4029 */ 4030 size = (~(PCI_BASE_ROM_ADDR_M & request))+1; 4031 if (pcicfg_update_assigned_prop_value(new_child, size, 4032 base, 0, PCI_CONF_ROM) != PCICFG_SUCCESS) { 4033 goto failedchild; 4034 } 4035 } 4036 4037 return (PCICFG_SUCCESS); 4038 4039 failedchild: 4040 return (PCICFG_FAILURE); 4041 } 4042 4043 static int 4044 pcicfg_probe_bridge(dev_info_t *new_child, ddi_acc_handle_t h, uint_t bus, 4045 uint_t *highest_bus, boolean_t is_pcie) 4046 { 4047 uint64_t next_bus; 4048 uint_t new_bus, num_slots; 4049 ndi_ra_request_t req; 4050 int rval, i, j; 4051 uint64_t mem_answer, io_answer, mem_base, io_base, mem_alen, io_alen; 4052 uint64_t pf_mem_answer, pf_mem_base, pf_mem_alen; 4053 uint64_t mem_size, io_size, pf_mem_size; 4054 uint64_t mem_end, pf_mem_end, io_end; 4055 uint64_t round_answer, round_len; 4056 ppb_ranges_t range[PCICFG_RANGE_LEN]; 4057 int bus_range[2]; 4058 pcicfg_phdl_t phdl; 4059 int count; 4060 uint64_t pcibus_base, pcibus_alen; 4061 uint64_t max_bus; 4062 uint8_t pcie_device_type = 0; 4063 uint_t pf_mem_supported = 0; 4064 dev_info_t *new_device; 4065 int trans_device; 4066 int ari_mode = B_FALSE; 4067 int max_function = PCI_MAX_FUNCTIONS; 4068 4069 io_answer = io_base = io_alen = io_size = 0; 4070 pf_mem_answer = pf_mem_base = pf_mem_size = pf_mem_alen = 0; 4071 4072 /* 4073 * Set "device_type" to "pci", the actual type will be set later 4074 * by pcicfg_set_busnode_props() below. This is needed as the 4075 * pcicfg_ra_free() below would update "available" property based 4076 * on "device_type". 4077 * 4078 * This code can be removed later after PCI configurator is changed 4079 * to use PCIRM, which automatically update properties upon allocation 4080 * and free, at that time we'll be able to remove the code inside 4081 * ndi_ra_alloc/free() which currently updates "available" property 4082 * for pci/pcie devices in pcie fabric. 4083 */ 4084 if (ndi_prop_update_string(DDI_DEV_T_NONE, new_child, 4085 "device_type", "pci") != DDI_SUCCESS) { 4086 DEBUG0("Failed to set \"device_type\" props\n"); 4087 return (PCICFG_FAILURE); 4088 } 4089 4090 /* 4091 * setup resource maps for the bridge node 4092 */ 4093 if (ndi_ra_map_setup(new_child, NDI_RA_TYPE_PCI_BUSNUM) 4094 == NDI_FAILURE) { 4095 DEBUG0("Can not setup resource map - NDI_RA_TYPE_PCI_BUSNUM\n"); 4096 rval = PCICFG_FAILURE; 4097 goto cleanup; 4098 } 4099 if (ndi_ra_map_setup(new_child, NDI_RA_TYPE_MEM) == NDI_FAILURE) { 4100 DEBUG0("Can not setup resource map - NDI_RA_TYPE_MEM\n"); 4101 rval = PCICFG_FAILURE; 4102 goto cleanup; 4103 } 4104 if (ndi_ra_map_setup(new_child, NDI_RA_TYPE_IO) == NDI_FAILURE) { 4105 DEBUG0("Can not setup resource map - NDI_RA_TYPE_IO\n"); 4106 rval = PCICFG_FAILURE; 4107 goto cleanup; 4108 } 4109 if (ndi_ra_map_setup(new_child, NDI_RA_TYPE_PCI_PREFETCH_MEM) == 4110 NDI_FAILURE) { 4111 DEBUG0("Can not setup resource map -" 4112 " NDI_RA_TYPE_PCI_PREFETCH_MEM\n"); 4113 rval = PCICFG_FAILURE; 4114 goto cleanup; 4115 } 4116 4117 /* 4118 * Allocate bus range pool for the bridge. 4119 */ 4120 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 4121 req.ra_flags = (NDI_RA_ALLOC_BOUNDED | NDI_RA_ALLOC_PARTIAL_OK); 4122 req.ra_boundbase = 0; 4123 req.ra_boundlen = req.ra_len = (PCI_MAX_BUS_NUM -1); 4124 req.ra_align_mask = 0; /* no alignment needed */ 4125 4126 rval = ndi_ra_alloc(ddi_get_parent(new_child), &req, 4127 &pcibus_base, &pcibus_alen, NDI_RA_TYPE_PCI_BUSNUM, NDI_RA_PASS); 4128 4129 if (rval != NDI_SUCCESS) { 4130 if (rval == NDI_RA_PARTIAL_REQ) { 4131 /*EMPTY*/ 4132 DEBUG0("NDI_RA_PARTIAL_REQ returned for bus range\n"); 4133 } else { 4134 DEBUG0( 4135 "Failed to allocate bus range for bridge\n"); 4136 rval = PCICFG_NORESRC; 4137 goto cleanup; 4138 } 4139 } 4140 4141 DEBUG2("Bus Range Allocated [base=%d] [len=%d]\n", 4142 pcibus_base, pcibus_alen); 4143 4144 /* 4145 * Put available bus range into the pool. 4146 * Take the first one for this bridge to use and don't give 4147 * to child. 4148 */ 4149 (void) ndi_ra_free(new_child, pcibus_base+1, pcibus_alen-1, 4150 NDI_RA_TYPE_PCI_BUSNUM, NDI_RA_PASS); 4151 4152 next_bus = pcibus_base; 4153 max_bus = pcibus_base + pcibus_alen - 1; 4154 4155 new_bus = next_bus; 4156 4157 DEBUG1("NEW bus found ->[%d]\n", new_bus); 4158 4159 /* Keep track of highest bus for subordinate bus programming */ 4160 *highest_bus = new_bus; 4161 4162 /* 4163 * Allocate (non-prefetchable) Memory Space for Bridge 4164 */ 4165 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 4166 req.ra_flags = (NDI_RA_ALLOC_BOUNDED | NDI_RA_ALLOC_PARTIAL_OK); 4167 req.ra_boundbase = 0; 4168 /* 4169 * limit the boundlen,len to a 32b quantity. It should be Ok to 4170 * lose alignment-based-size of resource due to this. 4171 */ 4172 req.ra_boundlen = PCICFG_4GIG_LIMIT; 4173 req.ra_len = PCICFG_4GIG_LIMIT; /* Get as big as possible */ 4174 req.ra_align_mask = 4175 PCICFG_MEMGRAN - 1; /* 1M alignment on memory space */ 4176 4177 rval = ndi_ra_alloc(ddi_get_parent(new_child), &req, 4178 &mem_answer, &mem_alen, NDI_RA_TYPE_MEM, NDI_RA_PASS); 4179 4180 if (rval != NDI_SUCCESS) { 4181 if (rval == NDI_RA_PARTIAL_REQ) { 4182 /*EMPTY*/ 4183 DEBUG0("NDI_RA_PARTIAL_REQ returned\n"); 4184 } else { 4185 DEBUG0( 4186 "Failed to allocate memory for bridge\n"); 4187 rval = PCICFG_NORESRC; 4188 goto cleanup; 4189 } 4190 } 4191 4192 DEBUG3("Bridge Memory Allocated [0x%x.%x] len [0x%x]\n", 4193 PCICFG_HIADDR(mem_answer), 4194 PCICFG_LOADDR(mem_answer), 4195 mem_alen); 4196 4197 /* 4198 * Put available memory into the pool. 4199 */ 4200 (void) ndi_ra_free(new_child, mem_answer, mem_alen, NDI_RA_TYPE_MEM, 4201 NDI_RA_PASS); 4202 4203 mem_base = mem_answer; 4204 4205 /* 4206 * Allocate I/O Space for Bridge 4207 */ 4208 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 4209 req.ra_align_mask = PCICFG_IOGRAN - 1; /* 4k alignment */ 4210 req.ra_boundbase = 0; 4211 req.ra_boundlen = PCICFG_4GIG_LIMIT; 4212 req.ra_flags = (NDI_RA_ALLOC_BOUNDED | NDI_RA_ALLOC_PARTIAL_OK); 4213 req.ra_len = PCICFG_4GIG_LIMIT; /* Get as big as possible */ 4214 4215 rval = ndi_ra_alloc(ddi_get_parent(new_child), &req, &io_answer, 4216 &io_alen, NDI_RA_TYPE_IO, NDI_RA_PASS); 4217 4218 if (rval != NDI_SUCCESS) { 4219 if (rval == NDI_RA_PARTIAL_REQ) { 4220 /*EMPTY*/ 4221 DEBUG0("NDI_RA_PARTIAL_REQ returned\n"); 4222 } else { 4223 DEBUG0("Failed to allocate io space for bridge\n"); 4224 /* i/o space is an optional requirement so continue */ 4225 } 4226 } 4227 4228 DEBUG3("Bridge IO Space Allocated [0x%x.%x] len [0x%x]\n", 4229 PCICFG_HIADDR(io_answer), PCICFG_LOADDR(io_answer), io_alen); 4230 4231 /* 4232 * Put available I/O into the pool. 4233 */ 4234 (void) ndi_ra_free(new_child, io_answer, io_alen, NDI_RA_TYPE_IO, 4235 NDI_RA_PASS); 4236 4237 io_base = io_answer; 4238 4239 /* 4240 * Check if the bridge supports Prefetchable memory range. 4241 * If it does, then we setup PF memory range for the bridge. 4242 * Otherwise, we skip the step of setting up PF memory 4243 * range for it. This could cause config operation to 4244 * fail if any devices under the bridge need PF memory. 4245 */ 4246 /* write a non zero value to the PF BASE register */ 4247 pci_config_put16(h, PCI_BCNF_PF_BASE_LOW, 0xfff0); 4248 /* if the read returns zero then PF range is not supported */ 4249 if (pci_config_get16(h, PCI_BCNF_PF_BASE_LOW) == 0) { 4250 /* bridge doesn't support PF memory range */ 4251 goto pf_setup_end; 4252 } else { 4253 pf_mem_supported = 1; 4254 /* reset the PF BASE register */ 4255 pci_config_put16(h, PCI_BCNF_PF_BASE_LOW, 0); 4256 } 4257 4258 /* 4259 * Bridge supports PF mem range; Allocate PF Memory Space for it. 4260 * 4261 * Note: Both non-prefetchable and prefetchable memory space 4262 * allocations are made within 32bit space. Currently, BIOSs 4263 * allocate device memory for PCI devices within the 32bit space 4264 * so this will not be a problem. 4265 */ 4266 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 4267 req.ra_flags = NDI_RA_ALLOC_PARTIAL_OK | NDI_RA_ALLOC_BOUNDED; 4268 req.ra_boundbase = 0; 4269 req.ra_len = PCICFG_4GIG_LIMIT; /* Get as big as possible */ 4270 req.ra_align_mask = 4271 PCICFG_MEMGRAN - 1; /* 1M alignment on memory space */ 4272 4273 rval = ndi_ra_alloc(ddi_get_parent(new_child), &req, 4274 &pf_mem_answer, &pf_mem_alen, NDI_RA_TYPE_PCI_PREFETCH_MEM, 4275 NDI_RA_PASS); 4276 4277 if (rval != NDI_SUCCESS) { 4278 if (rval == NDI_RA_PARTIAL_REQ) { 4279 /*EMPTY*/ 4280 DEBUG0("NDI_RA_PARTIAL_REQ returned\n"); 4281 } else { 4282 DEBUG0( 4283 "Failed to allocate PF memory for bridge\n"); 4284 /* PF mem is an optional requirement so continue */ 4285 } 4286 } 4287 4288 DEBUG3("Bridge PF Memory Allocated [0x%x.%x] len [0x%x]\n", 4289 PCICFG_HIADDR(pf_mem_answer), 4290 PCICFG_LOADDR(pf_mem_answer), 4291 pf_mem_alen); 4292 4293 /* 4294 * Put available PF memory into the pool. 4295 */ 4296 (void) ndi_ra_free(new_child, pf_mem_answer, pf_mem_alen, 4297 NDI_RA_TYPE_PCI_PREFETCH_MEM, NDI_RA_PASS); 4298 4299 pf_mem_base = pf_mem_answer; 4300 4301 /* 4302 * Program the PF memory base register with the 4303 * start of the memory range 4304 */ 4305 pci_config_put16(h, PCI_BCNF_PF_BASE_LOW, 4306 PCICFG_HIWORD(PCICFG_LOADDR(pf_mem_answer))); 4307 pci_config_put32(h, PCI_BCNF_PF_BASE_HIGH, 4308 PCICFG_HIADDR(pf_mem_answer)); 4309 4310 /* 4311 * Program the PF memory limit register with the 4312 * end of the memory range. 4313 */ 4314 pci_config_put16(h, PCI_BCNF_PF_LIMIT_LOW, 4315 PCICFG_HIWORD(PCICFG_LOADDR( 4316 PCICFG_ROUND_DOWN((pf_mem_answer + pf_mem_alen), 4317 PCICFG_MEMGRAN) - 1))); 4318 pci_config_put32(h, PCI_BCNF_PF_LIMIT_HIGH, 4319 PCICFG_HIADDR(PCICFG_ROUND_DOWN((pf_mem_answer + pf_mem_alen), 4320 PCICFG_MEMGRAN) - 1)); 4321 4322 /* 4323 * Allocate the chunk of PF memory (if any) not programmed into the 4324 * bridge because of the round down. 4325 */ 4326 if (PCICFG_ROUND_DOWN((pf_mem_answer + pf_mem_alen), PCICFG_MEMGRAN) 4327 != (pf_mem_answer + pf_mem_alen)) { 4328 DEBUG0("Need to allocate Memory round off chunk\n"); 4329 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 4330 req.ra_flags = NDI_RA_ALLOC_SPECIFIED; 4331 req.ra_addr = PCICFG_ROUND_DOWN((pf_mem_answer + pf_mem_alen), 4332 PCICFG_MEMGRAN); 4333 req.ra_len = (pf_mem_answer + pf_mem_alen) - 4334 (PCICFG_ROUND_DOWN((pf_mem_answer + pf_mem_alen), 4335 PCICFG_MEMGRAN)); 4336 4337 (void) ndi_ra_alloc(new_child, &req, 4338 &round_answer, &round_len, NDI_RA_TYPE_PCI_PREFETCH_MEM, 4339 NDI_RA_PASS); 4340 } 4341 4342 pf_setup_end: 4343 4344 /* 4345 * Program the memory base register with the 4346 * start of the memory range 4347 */ 4348 pci_config_put16(h, PCI_BCNF_MEM_BASE, 4349 PCICFG_HIWORD(PCICFG_LOADDR(mem_answer))); 4350 4351 /* 4352 * Program the memory limit register with the 4353 * end of the memory range. 4354 */ 4355 4356 pci_config_put16(h, PCI_BCNF_MEM_LIMIT, 4357 PCICFG_HIWORD(PCICFG_LOADDR( 4358 PCICFG_ROUND_DOWN((mem_answer + mem_alen), PCICFG_MEMGRAN) - 1))); 4359 4360 /* 4361 * Allocate the chunk of memory (if any) not programmed into the 4362 * bridge because of the round down. 4363 */ 4364 if (PCICFG_ROUND_DOWN((mem_answer + mem_alen), PCICFG_MEMGRAN) 4365 != (mem_answer + mem_alen)) { 4366 DEBUG0("Need to allocate Memory round off chunk\n"); 4367 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 4368 req.ra_flags = NDI_RA_ALLOC_SPECIFIED; 4369 req.ra_addr = PCICFG_ROUND_DOWN((mem_answer + mem_alen), 4370 PCICFG_MEMGRAN); 4371 req.ra_len = (mem_answer + mem_alen) - 4372 (PCICFG_ROUND_DOWN((mem_answer + mem_alen), 4373 PCICFG_MEMGRAN)); 4374 4375 (void) ndi_ra_alloc(new_child, &req, 4376 &round_answer, &round_len, NDI_RA_TYPE_MEM, NDI_RA_PASS); 4377 } 4378 4379 /* 4380 * Program the I/O Space Base 4381 */ 4382 pci_config_put8(h, PCI_BCNF_IO_BASE_LOW, 4383 PCICFG_HIBYTE(PCICFG_LOWORD( 4384 PCICFG_LOADDR(io_answer)))); 4385 4386 pci_config_put16(h, PCI_BCNF_IO_BASE_HI, 4387 PCICFG_HIWORD(PCICFG_LOADDR(io_answer))); 4388 4389 /* 4390 * Program the I/O Space Limit 4391 */ 4392 pci_config_put8(h, PCI_BCNF_IO_LIMIT_LOW, 4393 PCICFG_HIBYTE(PCICFG_LOWORD( 4394 PCICFG_LOADDR(PCICFG_ROUND_DOWN(io_answer + io_alen, 4395 PCICFG_IOGRAN)))) - 1); 4396 4397 pci_config_put16(h, PCI_BCNF_IO_LIMIT_HI, 4398 PCICFG_HIWORD(PCICFG_LOADDR( 4399 PCICFG_ROUND_DOWN(io_answer + io_alen, PCICFG_IOGRAN))) 4400 - 1); 4401 4402 /* 4403 * Allocate the chunk of I/O (if any) not programmed into the 4404 * bridge because of the round down. 4405 */ 4406 if (PCICFG_ROUND_DOWN((io_answer + io_alen), PCICFG_IOGRAN) 4407 != (io_answer + io_alen)) { 4408 DEBUG0("Need to allocate I/O round off chunk\n"); 4409 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 4410 req.ra_flags = NDI_RA_ALLOC_SPECIFIED; 4411 req.ra_addr = PCICFG_ROUND_DOWN((io_answer + io_alen), 4412 PCICFG_IOGRAN); 4413 req.ra_len = (io_answer + io_alen) - 4414 (PCICFG_ROUND_DOWN((io_answer + io_alen), 4415 PCICFG_IOGRAN)); 4416 4417 (void) ndi_ra_alloc(new_child, &req, 4418 &round_answer, &round_len, NDI_RA_TYPE_IO, NDI_RA_PASS); 4419 } 4420 4421 (void) pcicfg_set_bus_numbers(h, bus, new_bus, max_bus); 4422 4423 /* 4424 * Setup "ranges" and "bus-range" properties before onlining 4425 * the bridge. 4426 */ 4427 bzero((caddr_t)range, sizeof (ppb_ranges_t) * PCICFG_RANGE_LEN); 4428 4429 range[0].child_high = range[0].parent_high |= (PCI_REG_REL_M | 4430 PCI_ADDR_IO); 4431 range[0].child_low = range[0].parent_low = io_base; 4432 range[1].child_high = range[1].parent_high |= 4433 (PCI_REG_REL_M | PCI_ADDR_MEM32); 4434 range[1].child_low = range[1].parent_low = mem_base; 4435 range[2].child_high = range[2].parent_high |= 4436 (PCI_REG_REL_M | PCI_ADDR_MEM64 | PCI_REG_PF_M); 4437 range[2].child_low = range[2].parent_low = pf_mem_base; 4438 4439 range[0].size_low = io_alen; 4440 (void) pcicfg_update_ranges_prop(new_child, &range[0]); 4441 range[1].size_low = mem_alen; 4442 (void) pcicfg_update_ranges_prop(new_child, &range[1]); 4443 range[2].size_low = pf_mem_alen; 4444 (void) pcicfg_update_ranges_prop(new_child, &range[2]); 4445 4446 bus_range[0] = new_bus; 4447 bus_range[1] = max_bus; 4448 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, new_child, 4449 "bus-range", bus_range, 2); 4450 4451 /* 4452 * Reset the secondary bus 4453 */ 4454 pci_config_put16(h, PCI_BCNF_BCNTRL, 4455 pci_config_get16(h, PCI_BCNF_BCNTRL) | 0x40); 4456 4457 drv_usecwait(100); 4458 4459 pci_config_put16(h, PCI_BCNF_BCNTRL, 4460 pci_config_get16(h, PCI_BCNF_BCNTRL) & ~0x40); 4461 4462 /* 4463 * Clear status bits 4464 */ 4465 pci_config_put16(h, PCI_BCNF_SEC_STATUS, 0xffff); 4466 4467 /* 4468 * Needs to be set to this value 4469 */ 4470 pci_config_put8(h, PCI_CONF_ILINE, 0xf); 4471 4472 /* check our device_type as defined by Open Firmware */ 4473 if (pcicfg_pcie_device_type(new_child, h) == DDI_SUCCESS) 4474 pcie_device_type = 1; 4475 4476 /* 4477 * Set bus properties 4478 */ 4479 if (pcicfg_set_busnode_props(new_child, pcie_device_type) 4480 != PCICFG_SUCCESS) { 4481 DEBUG0("Failed to set busnode props\n"); 4482 rval = PCICFG_FAILURE; 4483 goto cleanup; 4484 } 4485 4486 (void) pcicfg_device_on(h); 4487 4488 if (is_pcie) 4489 (void) pcie_init_bus(new_child, 0, PCIE_BUS_FINAL); 4490 if (ndi_devi_online(new_child, NDI_NO_EVENT|NDI_CONFIG) 4491 != NDI_SUCCESS) { 4492 DEBUG0("Unable to online bridge\n"); 4493 rval = PCICFG_FAILURE; 4494 goto cleanup; 4495 } 4496 4497 DEBUG0("Bridge is ONLINE\n"); 4498 4499 /* 4500 * After a Reset, we need to wait 2^25 clock cycles before the 4501 * first Configuration access. The worst case is 33MHz, which 4502 * is a 1 second wait. 4503 */ 4504 drv_usecwait(pcicfg_sec_reset_delay); 4505 4506 /* 4507 * Probe all children devices 4508 */ 4509 DEBUG0("Bridge Programming Complete - probe children\n"); 4510 ndi_devi_enter(new_child, &count); 4511 for (i = 0; ((i < PCI_MAX_DEVICES) && (ari_mode == B_FALSE)); 4512 i++) { 4513 for (j = 0; j < max_function; ) { 4514 if (ari_mode) 4515 trans_device = j >> 3; 4516 else 4517 trans_device = i; 4518 4519 if ((rval = pcicfg_probe_children(new_child, 4520 new_bus, trans_device, j & 7, highest_bus, 4521 0, is_pcie)) != PCICFG_SUCCESS) { 4522 if (rval == PCICFG_NODEVICE) { 4523 DEBUG3("No Device at bus [0x%x]" 4524 "device [0x%x] " 4525 "func [0x%x]\n", new_bus, 4526 trans_device, j & 7); 4527 4528 if (j) 4529 goto next; 4530 } else 4531 /*EMPTY*/ 4532 DEBUG3("Failed to configure bus " 4533 "[0x%x] device [0x%x] " 4534 "func [0x%x]\n", new_bus, 4535 trans_device, j & 7); 4536 break; 4537 } 4538 next: 4539 new_device = pcicfg_devi_find(new_child, trans_device, 4540 (j & 7)); 4541 4542 /* 4543 * Determine if ARI Forwarding should be enabled. 4544 */ 4545 if (j == 0) { 4546 if (new_device == NULL) 4547 break; 4548 4549 if ((pcie_ari_supported(new_child) == 4550 PCIE_ARI_FORW_SUPPORTED) && 4551 (pcie_ari_device(new_device) == 4552 PCIE_ARI_DEVICE)) { 4553 if (pcie_ari_enable(new_child) == 4554 DDI_SUCCESS) { 4555 (void) ddi_prop_create( 4556 DDI_DEV_T_NONE, 4557 new_child, 4558 DDI_PROP_CANSLEEP, 4559 "ari-enabled", NULL, 0); 4560 ari_mode = B_TRUE; 4561 max_function = 4562 PCICFG_MAX_ARI_FUNCTION; 4563 } 4564 } 4565 } 4566 if (ari_mode == B_TRUE) { 4567 int next_function; 4568 4569 if (new_device == NULL) 4570 break; 4571 4572 if (pcie_ari_get_next_function(new_device, 4573 &next_function) != DDI_SUCCESS) 4574 break; 4575 4576 j = next_function; 4577 4578 if (next_function == 0) 4579 break; 4580 } else 4581 j++; 4582 4583 } 4584 /* if any function fails to be configured, no need to proceed */ 4585 if (rval != PCICFG_NODEVICE) 4586 break; 4587 } 4588 ndi_devi_exit(new_child, count); 4589 4590 /* 4591 * Offline the bridge to allow reprogramming of resources. 4592 * 4593 * This should always succeed since nobody else has started to 4594 * use it yet, failing to detach the driver would indicate a bug. 4595 * Also in that case it's better just panic than allowing the 4596 * configurator to proceed with BAR reprogramming without bridge 4597 * driver detached. 4598 */ 4599 VERIFY(ndi_devi_offline(new_child, NDI_NO_EVENT|NDI_UNCONFIG) 4600 == NDI_SUCCESS); 4601 if (is_pcie) 4602 pcie_fini_bus(new_child, PCIE_BUS_INITIAL); 4603 4604 phdl.dip = new_child; 4605 phdl.memory_base = mem_answer; 4606 phdl.io_base = io_answer; 4607 phdl.pf_memory_base = pf_mem_answer; 4608 phdl.error = PCICFG_SUCCESS; /* in case of empty child tree */ 4609 4610 ndi_devi_enter(ddi_get_parent(new_child), &count); 4611 ddi_walk_devs(new_child, pcicfg_find_resource_end, (void *)&phdl); 4612 ndi_devi_exit(ddi_get_parent(new_child), count); 4613 4614 num_slots = pcicfg_get_nslots(new_child, h); 4615 mem_end = PCICFG_ROUND_UP(phdl.memory_base, PCICFG_MEMGRAN); 4616 io_end = PCICFG_ROUND_UP(phdl.io_base, PCICFG_IOGRAN); 4617 pf_mem_end = PCICFG_ROUND_UP(phdl.pf_memory_base, PCICFG_MEMGRAN); 4618 4619 DEBUG4("Start of Unallocated Bridge(%d slots) Resources Mem=0x%lx " 4620 "I/O=0x%lx PF_mem=%x%lx\n", num_slots, mem_end, io_end, pf_mem_end); 4621 4622 /* 4623 * Before probing the children we've allocated maximum MEM/IO 4624 * resources from parent, and updated "available" property 4625 * accordingly. Later we'll be giving up unused resources to 4626 * the parent, thus we need to destroy "available" property 4627 * here otherwise it will be out-of-sync with the actual free 4628 * resources this bridge has. This property will be rebuilt below 4629 * with the actual free resources reserved for hotplug slots 4630 * (if any). 4631 */ 4632 (void) ndi_prop_remove(DDI_DEV_T_NONE, new_child, "available"); 4633 /* 4634 * if the bridge a slots, then preallocate. If not, assume static 4635 * configuration. Also check for preallocation limits and spit 4636 * warning messages appropriately (perhaps some can be in debug mode). 4637 */ 4638 if (num_slots) { 4639 uint64_t mem_reqd = mem_answer + 4640 (num_slots * pcicfg_slot_memsize); 4641 uint64_t io_reqd = io_answer + 4642 (num_slots * pcicfg_slot_iosize); 4643 uint64_t pf_mem_reqd = pf_mem_answer + 4644 (num_slots * pcicfg_slot_pf_memsize); 4645 uint8_t highest_bus_reqd = new_bus + 4646 (num_slots * pcicfg_slot_busnums); 4647 #ifdef DEBUG 4648 if (mem_end > mem_reqd) 4649 DEBUG3("Memory space consumed by bridge more " 4650 "than planned for %d slot(s)(%" PRIx64 ",%" 4651 PRIx64 ")", num_slots, mem_answer, mem_end); 4652 if (io_end > io_reqd) 4653 DEBUG3("IO space consumed by bridge more than" 4654 " planned for %d slot(s)(%" PRIx64 ",%" PRIx64 ")", 4655 num_slots, io_answer, io_end); 4656 if (pf_mem_end > pf_mem_reqd) 4657 DEBUG3("PF Memory space consumed by bridge" 4658 " more than planned for %d slot(s)(%" PRIx64 ",%" 4659 PRIx64 ")", num_slots, pf_mem_answer, pf_mem_end); 4660 if (*highest_bus > highest_bus_reqd) 4661 DEBUG3("Buses consumed by bridge more " 4662 "than planned for %d slot(s)(%x, %x)", 4663 num_slots, new_bus, *highest_bus); 4664 4665 if (mem_reqd > (mem_answer + mem_alen)) 4666 DEBUG3("Memory space required by bridge more " 4667 "than available for %d slot(s)(%" PRIx64 ",%" 4668 PRIx64 ")", num_slots, mem_answer, mem_end); 4669 if (io_reqd > (io_answer + io_alen)) 4670 DEBUG3("IO space required by bridge more than" 4671 "available for %d slot(s)(%" PRIx64 ",%" PRIx64 ")", 4672 num_slots, io_answer, io_end); 4673 if (pf_mem_reqd > (pf_mem_answer + pf_mem_alen)) 4674 DEBUG3("PF Memory space required by bridge" 4675 " more than available for %d slot(s)(%" PRIx64 ",%" 4676 PRIx64 ")", num_slots, pf_mem_answer, pf_mem_end); 4677 if (highest_bus_reqd > max_bus) 4678 DEBUG3("Bus numbers required by bridge more " 4679 "than available for %d slot(s)(%x, %x)", 4680 num_slots, new_bus, *highest_bus); 4681 #endif 4682 mem_end = MAX((MIN(mem_reqd, (mem_answer + mem_alen))), 4683 mem_end); 4684 io_end = MAX((MIN(io_reqd, (io_answer + io_alen))), io_end); 4685 pf_mem_end = MAX((MIN(pf_mem_reqd, (pf_mem_answer + 4686 pf_mem_alen))), pf_mem_end); 4687 *highest_bus = MAX((MIN(highest_bus_reqd, max_bus)), 4688 *highest_bus); 4689 DEBUG4("mem_end %lx, io_end %lx, pf_mem_end %lx" 4690 " highest_bus %x\n", mem_end, io_end, pf_mem_end, 4691 *highest_bus); 4692 } 4693 4694 /* 4695 * Give back unused memory space to parent. 4696 */ 4697 (void) ndi_ra_free(ddi_get_parent(new_child), mem_end, 4698 (mem_answer + mem_alen) - mem_end, NDI_RA_TYPE_MEM, NDI_RA_PASS); 4699 4700 if (mem_end == mem_answer) { 4701 DEBUG0("No memory resources used\n"); 4702 /* 4703 * To prevent the bridge from forwarding any Memory 4704 * transactions, the Memory Limit will be programmed 4705 * with a smaller value than the Memory Base. 4706 */ 4707 pci_config_put16(h, PCI_BCNF_MEM_BASE, 0xffff); 4708 pci_config_put16(h, PCI_BCNF_MEM_LIMIT, 0); 4709 4710 mem_size = 0; 4711 } else { 4712 /* 4713 * Reprogram the end of the memory. 4714 */ 4715 pci_config_put16(h, PCI_BCNF_MEM_LIMIT, 4716 PCICFG_HIWORD(mem_end) - 1); 4717 mem_size = mem_end - mem_base; 4718 } 4719 4720 /* 4721 * Give back unused io space to parent. 4722 */ 4723 (void) ndi_ra_free(ddi_get_parent(new_child), 4724 io_end, (io_answer + io_alen) - io_end, 4725 NDI_RA_TYPE_IO, NDI_RA_PASS); 4726 4727 if (io_end == io_answer) { 4728 DEBUG0("No IO Space resources used\n"); 4729 4730 /* 4731 * To prevent the bridge from forwarding any I/O 4732 * transactions, the I/O Limit will be programmed 4733 * with a smaller value than the I/O Base. 4734 */ 4735 pci_config_put8(h, PCI_BCNF_IO_LIMIT_LOW, 0); 4736 pci_config_put16(h, PCI_BCNF_IO_LIMIT_HI, 0); 4737 pci_config_put8(h, PCI_BCNF_IO_BASE_LOW, 0xff); 4738 pci_config_put16(h, PCI_BCNF_IO_BASE_HI, 0); 4739 4740 io_size = 0; 4741 } else { 4742 /* 4743 * Reprogram the end of the io space. 4744 */ 4745 pci_config_put8(h, PCI_BCNF_IO_LIMIT_LOW, 4746 PCICFG_HIBYTE(PCICFG_LOWORD( 4747 PCICFG_LOADDR(io_end) - 1))); 4748 4749 pci_config_put16(h, PCI_BCNF_IO_LIMIT_HI, 4750 PCICFG_HIWORD(PCICFG_LOADDR(io_end - 1))); 4751 4752 io_size = io_end - io_base; 4753 } 4754 4755 /* 4756 * Give back unused PF memory space to parent. 4757 */ 4758 if (pf_mem_supported) { 4759 (void) ndi_ra_free(ddi_get_parent(new_child), 4760 pf_mem_end, (pf_mem_answer + pf_mem_alen) - pf_mem_end, 4761 NDI_RA_TYPE_PCI_PREFETCH_MEM, NDI_RA_PASS); 4762 4763 if (pf_mem_end == pf_mem_answer) { 4764 DEBUG0("No PF memory resources used\n"); 4765 /* 4766 * To prevent the bridge from forwarding any PF Memory 4767 * transactions, the PF Memory Limit will be programmed 4768 * with a smaller value than the Memory Base. 4769 */ 4770 pci_config_put16(h, PCI_BCNF_PF_BASE_LOW, 0xfff0); 4771 pci_config_put32(h, PCI_BCNF_PF_BASE_HIGH, 0xffffffff); 4772 pci_config_put16(h, PCI_BCNF_PF_LIMIT_LOW, 0); 4773 pci_config_put32(h, PCI_BCNF_PF_LIMIT_HIGH, 0); 4774 4775 pf_mem_size = 0; 4776 } else { 4777 /* 4778 * Reprogram the end of the PF memory range. 4779 */ 4780 pci_config_put16(h, PCI_BCNF_PF_LIMIT_LOW, 4781 PCICFG_HIWORD(PCICFG_LOADDR(pf_mem_end - 1))); 4782 pci_config_put32(h, PCI_BCNF_PF_LIMIT_HIGH, 4783 PCICFG_HIADDR(pf_mem_end - 1)); 4784 pf_mem_size = pf_mem_end - pf_mem_base; 4785 } 4786 } 4787 4788 if ((max_bus - *highest_bus) > 0) { 4789 /* 4790 * Give back unused bus numbers 4791 */ 4792 (void) ndi_ra_free(ddi_get_parent(new_child), 4793 *highest_bus+1, max_bus - *highest_bus, 4794 NDI_RA_TYPE_PCI_BUSNUM, NDI_RA_PASS); 4795 } 4796 4797 /* 4798 * Set bus numbers to ranges encountered during scan 4799 */ 4800 (void) pcicfg_set_bus_numbers(h, bus, new_bus, *highest_bus); 4801 4802 /* 4803 * Remove the ranges property if it exists since we will create 4804 * a new one. 4805 */ 4806 (void) ndi_prop_remove(DDI_DEV_T_NONE, new_child, "ranges"); 4807 4808 DEBUG2("Creating Ranges property - Mem Address %lx Mem Size %x\n", 4809 mem_base, mem_size); 4810 DEBUG2(" - I/O Address %lx I/O Size %x\n", 4811 io_base, io_size); 4812 DEBUG2(" - PF Mem address %lx PF Mem Size %x\n", 4813 pf_mem_base, pf_mem_size); 4814 4815 bzero((caddr_t)range, sizeof (ppb_ranges_t) * PCICFG_RANGE_LEN); 4816 4817 range[0].child_high = range[0].parent_high |= (PCI_REG_REL_M | 4818 PCI_ADDR_IO); 4819 range[0].child_low = range[0].parent_low = io_base; 4820 range[1].child_high = range[1].parent_high |= 4821 (PCI_REG_REL_M | PCI_ADDR_MEM32); 4822 range[1].child_low = range[1].parent_low = mem_base; 4823 range[2].child_high = range[2].parent_high |= 4824 (PCI_REG_REL_M | PCI_ADDR_MEM64 | PCI_REG_PF_M); 4825 range[2].child_low = range[2].parent_low = pf_mem_base; 4826 4827 if (io_size > 0) { 4828 range[0].size_low = io_size; 4829 (void) pcicfg_update_ranges_prop(new_child, &range[0]); 4830 } 4831 if (mem_size > 0) { 4832 range[1].size_low = mem_size; 4833 (void) pcicfg_update_ranges_prop(new_child, &range[1]); 4834 } 4835 if (pf_mem_size > 0) { 4836 range[2].size_low = pf_mem_size; 4837 (void) pcicfg_update_ranges_prop(new_child, &range[2]); 4838 } 4839 4840 bus_range[0] = pci_config_get8(h, PCI_BCNF_SECBUS); 4841 bus_range[1] = pci_config_get8(h, PCI_BCNF_SUBBUS); 4842 DEBUG1("End of bridge probe: bus_range[0] = %d\n", bus_range[0]); 4843 DEBUG1("End of bridge probe: bus_range[1] = %d\n", bus_range[1]); 4844 4845 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, new_child, 4846 "bus-range", bus_range, 2); 4847 4848 rval = PCICFG_SUCCESS; 4849 4850 PCICFG_DUMP_BRIDGE_CONFIG(h); 4851 4852 cleanup: 4853 /* free up resources (for error return case only) */ 4854 if (rval != PCICFG_SUCCESS) { 4855 if (mem_alen) 4856 (void) ndi_ra_free(ddi_get_parent(new_child), mem_base, 4857 mem_alen, NDI_RA_TYPE_MEM, NDI_RA_PASS); 4858 if (io_alen) 4859 (void) ndi_ra_free(ddi_get_parent(new_child), io_base, 4860 io_alen, NDI_RA_TYPE_IO, NDI_RA_PASS); 4861 if (pf_mem_alen) 4862 (void) ndi_ra_free(ddi_get_parent(new_child), 4863 pf_mem_base, pf_mem_alen, 4864 NDI_RA_TYPE_PCI_PREFETCH_MEM, NDI_RA_PASS); 4865 if (pcibus_alen) 4866 (void) ndi_ra_free(ddi_get_parent(new_child), 4867 pcibus_base, pcibus_alen, NDI_RA_TYPE_PCI_BUSNUM, 4868 NDI_RA_PASS); 4869 } 4870 4871 /* free up any resource maps setup for the bridge node */ 4872 (void) ndi_ra_map_destroy(new_child, NDI_RA_TYPE_PCI_BUSNUM); 4873 (void) ndi_ra_map_destroy(new_child, NDI_RA_TYPE_IO); 4874 (void) ndi_ra_map_destroy(new_child, NDI_RA_TYPE_MEM); 4875 (void) ndi_ra_map_destroy(new_child, NDI_RA_TYPE_PCI_PREFETCH_MEM); 4876 4877 return (rval); 4878 } 4879 4880 static int 4881 pcicfg_find_resource_end(dev_info_t *dip, void *hdl) 4882 { 4883 pcicfg_phdl_t *entry = (pcicfg_phdl_t *)hdl; 4884 pci_regspec_t *pci_ap; 4885 int length; 4886 int rcount; 4887 int i; 4888 4889 entry->error = PCICFG_SUCCESS; 4890 4891 if (dip == entry->dip) { 4892 DEBUG0("Don't include parent bridge node\n"); 4893 return (DDI_WALK_CONTINUE); 4894 } else { 4895 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 4896 DDI_PROP_DONTPASS, "assigned-addresses", 4897 (caddr_t)&pci_ap, &length) != DDI_PROP_SUCCESS) { 4898 DEBUG0("Node doesn't have assigned-addresses\n"); 4899 return (DDI_WALK_CONTINUE); 4900 } 4901 4902 rcount = length / sizeof (pci_regspec_t); 4903 4904 for (i = 0; i < rcount; i++) { 4905 4906 switch (PCI_REG_ADDR_G(pci_ap[i].pci_phys_hi)) { 4907 4908 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 4909 if (pci_ap[i].pci_phys_hi & PCI_REG_PF_M) { 4910 if ((pci_ap[i].pci_phys_low + 4911 pci_ap[i].pci_size_low) > 4912 entry->pf_memory_base) { 4913 entry->pf_memory_base = 4914 pci_ap[i].pci_phys_low + 4915 pci_ap[i].pci_size_low; 4916 } 4917 } else { 4918 if ((pci_ap[i].pci_phys_low + 4919 pci_ap[i].pci_size_low) > 4920 entry->memory_base) { 4921 entry->memory_base = 4922 pci_ap[i].pci_phys_low + 4923 pci_ap[i].pci_size_low; 4924 } 4925 } 4926 break; 4927 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 4928 if (pci_ap[i].pci_phys_hi & PCI_REG_PF_M) { 4929 if ((PCICFG_LADDR( 4930 pci_ap[i].pci_phys_low, 4931 pci_ap[i].pci_phys_mid) + 4932 pci_ap[i].pci_size_low) > 4933 entry->pf_memory_base) { 4934 entry->pf_memory_base = 4935 PCICFG_LADDR( 4936 pci_ap[i].pci_phys_low, 4937 pci_ap[i].pci_phys_mid) + 4938 pci_ap[i].pci_size_low; 4939 } 4940 } else { 4941 if ((PCICFG_LADDR( 4942 pci_ap[i].pci_phys_low, 4943 pci_ap[i].pci_phys_mid) + 4944 pci_ap[i].pci_size_low) > 4945 entry->memory_base) { 4946 entry->memory_base = 4947 PCICFG_LADDR( 4948 pci_ap[i].pci_phys_low, 4949 pci_ap[i].pci_phys_mid) + 4950 pci_ap[i].pci_size_low; 4951 } 4952 } 4953 break; 4954 case PCI_REG_ADDR_G(PCI_ADDR_IO): 4955 if ((pci_ap[i].pci_phys_low + 4956 pci_ap[i].pci_size_low) > 4957 entry->io_base) { 4958 entry->io_base = 4959 pci_ap[i].pci_phys_low + 4960 pci_ap[i].pci_size_low; 4961 } 4962 break; 4963 } 4964 } 4965 4966 /* 4967 * free the memory allocated by ddi_getlongprop 4968 */ 4969 kmem_free(pci_ap, length); 4970 4971 /* 4972 * continue the walk to the next sibling to sum memory 4973 */ 4974 return (DDI_WALK_CONTINUE); 4975 } 4976 } 4977 4978 /* 4979 * Make "parent" be the parent of the "child" dip 4980 */ 4981 static void 4982 pcicfg_reparent_node(dev_info_t *child, dev_info_t *parent) 4983 { 4984 int circ; 4985 dev_info_t *opdip; 4986 4987 ASSERT(i_ddi_node_state(child) <= DS_LINKED); 4988 /* 4989 * Unlink node from tree before reparenting 4990 */ 4991 opdip = ddi_get_parent(child); 4992 ndi_devi_enter(opdip, &circ); 4993 (void) i_ndi_unconfig_node(child, DS_PROTO, 0); 4994 ndi_devi_exit(opdip, circ); 4995 4996 DEVI(child)->devi_parent = DEVI(parent); 4997 DEVI(child)->devi_bus_ctl = DEVI(parent); 4998 (void) ndi_devi_bind_driver(child, 0); 4999 } 5000 5001 /* 5002 * Return PCICFG_SUCCESS if device exists at the specified address. 5003 * Return PCICFG_NODEVICE is no device exists at the specified address. 5004 */ 5005 int 5006 pcicfg_config_setup(dev_info_t *dip, ddi_acc_handle_t *handle) 5007 { 5008 caddr_t cfgaddr; 5009 ddi_device_acc_attr_t attr; 5010 dev_info_t *anode; 5011 int status; 5012 int rlen; 5013 pci_regspec_t *reg; 5014 int ret = DDI_SUCCESS; 5015 int16_t tmp; 5016 5017 /* 5018 * Get the pci register spec from the node 5019 */ 5020 status = ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "reg", 5021 (caddr_t)®, &rlen); 5022 5023 switch (status) { 5024 case DDI_PROP_SUCCESS: 5025 break; 5026 case DDI_PROP_NO_MEMORY: 5027 DEBUG0("reg present, but unable to get memory\n"); 5028 return (PCICFG_FAILURE); 5029 default: 5030 DEBUG0("no reg property\n"); 5031 return (PCICFG_FAILURE); 5032 } 5033 5034 anode = dip; 5035 DEBUG2("conf_map: dip=%p, anode=%p\n", dip, anode); 5036 5037 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 5038 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 5039 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 5040 5041 if (ddi_regs_map_setup(anode, 0, &cfgaddr, 0, 0, &attr, handle) 5042 != DDI_SUCCESS) { 5043 DEBUG0("Failed to setup registers\n"); 5044 kmem_free((caddr_t)reg, rlen); 5045 return (PCICFG_FAILURE); 5046 } 5047 5048 /* 5049 * need to use DDI interfaces as the conf space is 5050 * cannot be directly accessed by the host. 5051 */ 5052 tmp = (int16_t)ddi_get16(*handle, (uint16_t *)cfgaddr); 5053 if ((tmp == (int16_t)0xffff) || (tmp == -1)) { 5054 DEBUG1("NO DEVICEFOUND, read %x\n", tmp); 5055 ret = PCICFG_NODEVICE; 5056 } else { 5057 if (tmp == 0) { 5058 DEBUG0("Device Not Ready yet ?"); 5059 ret = PCICFG_NODEVICE; 5060 } else { 5061 DEBUG1("DEVICEFOUND, read %x\n", tmp); 5062 ret = PCICFG_SUCCESS; 5063 } 5064 } 5065 5066 if (ret == PCICFG_NODEVICE) 5067 ddi_regs_map_free(handle); 5068 kmem_free((caddr_t)reg, rlen); 5069 5070 return (ret); 5071 5072 } 5073 5074 static void 5075 pcicfg_config_teardown(ddi_acc_handle_t *handle) 5076 { 5077 (void) ddi_regs_map_free(handle); 5078 } 5079 5080 static int 5081 pcicfg_add_config_reg(dev_info_t *dip, 5082 uint_t bus, uint_t device, uint_t func) 5083 { 5084 int reg[10] = { PCI_ADDR_CONFIG, 0, 0, 0, 0}; 5085 5086 reg[0] = PCICFG_MAKE_REG_HIGH(bus, device, func, 0); 5087 5088 return (ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", reg, 5)); 5089 } 5090 5091 static int 5092 pcicfg_ari_configure(dev_info_t *dip) 5093 { 5094 if (pcie_ari_supported(dip) == PCIE_ARI_FORW_NOT_SUPPORTED) 5095 return (DDI_FAILURE); 5096 5097 /* 5098 * Until we have resource balancing, dynamically configure 5099 * ARI functions without firmware assistamce. 5100 */ 5101 return (DDI_FAILURE); 5102 } 5103 5104 5105 #ifdef DEBUG 5106 static void 5107 debug(char *fmt, uintptr_t a1, uintptr_t a2, uintptr_t a3, 5108 uintptr_t a4, uintptr_t a5) 5109 { 5110 if (pcicfg_debug > 1) { 5111 prom_printf("pcicfg: "); 5112 prom_printf(fmt, a1, a2, a3, a4, a5); 5113 } 5114 } 5115 #endif 5116 5117 /*ARGSUSED*/ 5118 static uint8_t 5119 pcicfg_get_nslots(dev_info_t *dip, ddi_acc_handle_t handle) 5120 { 5121 uint16_t cap_id_loc, slot_id_loc; 5122 uint8_t num_slots = 0; 5123 5124 /* just depend on the pcie_cap for now. */ 5125 (void) PCI_CAP_LOCATE(handle, PCI_CAP_ID_PCI_E, &cap_id_loc); 5126 (void) PCI_CAP_LOCATE(handle, PCI_CAP_ID_SLOT_ID, &slot_id_loc); 5127 if (cap_id_loc != PCI_CAP_NEXT_PTR_NULL) { 5128 if (pci_config_get8(handle, cap_id_loc + PCI_CAP_ID_REGS_OFF) & 5129 PCIE_PCIECAP_SLOT_IMPL) 5130 num_slots = 1; 5131 } else /* not a PCIe switch/bridge. Must be a PCI-PCI[-X] bridge */ 5132 if (slot_id_loc != PCI_CAP_NEXT_PTR_NULL) { 5133 uint8_t esr_reg = pci_config_get8(handle, slot_id_loc + 2); 5134 num_slots = PCI_CAPSLOT_NSLOTS(esr_reg); 5135 } 5136 /* XXX - need to cover PCI-PCIe bridge with n slots */ 5137 return (num_slots); 5138 } 5139 5140 /*ARGSUSED*/ 5141 static int 5142 pcicfg_pcie_dev(dev_info_t *dip, ddi_acc_handle_t handle) 5143 { 5144 /* get parent device's device_type property */ 5145 char *device_type; 5146 int val; 5147 dev_info_t *pdip = ddi_get_parent(dip); 5148 5149 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pdip, DDI_PROP_DONTPASS, 5150 "device_type", &device_type) != DDI_PROP_SUCCESS) { 5151 DEBUG2("device_type property missing for %s#%d", 5152 ddi_get_name(pdip), ddi_get_instance(pdip)); 5153 return (DDI_FAILURE); 5154 } 5155 DEBUG1("device_type=<%s>\n", device_type); 5156 5157 val = DDI_FAILURE; 5158 if (strcmp(device_type, "pciex") == 0) 5159 val = DDI_SUCCESS; 5160 ddi_prop_free(device_type); 5161 return (val); 5162 } 5163 5164 static int 5165 pcicfg_pcie_device_type(dev_info_t *dip, ddi_acc_handle_t handle) 5166 { 5167 int port_type = pcicfg_pcie_port_type(dip, handle); 5168 5169 DEBUG1("device port_type = %x\n", port_type); 5170 /* No PCIe CAP regs, we are not PCIe device_type */ 5171 if (port_type < 0) 5172 return (DDI_FAILURE); 5173 5174 /* check for all PCIe device_types */ 5175 if ((port_type == PCIE_PCIECAP_DEV_TYPE_UP) || 5176 (port_type == PCIE_PCIECAP_DEV_TYPE_DOWN) || 5177 (port_type == PCIE_PCIECAP_DEV_TYPE_ROOT) || 5178 (port_type == PCIE_PCIECAP_DEV_TYPE_PCI2PCIE)) 5179 return (DDI_SUCCESS); 5180 5181 return (DDI_FAILURE); 5182 5183 } 5184 5185 /*ARGSUSED*/ 5186 static int 5187 pcicfg_pcie_port_type(dev_info_t *dip, ddi_acc_handle_t handle) 5188 { 5189 int port_type = -1; 5190 uint16_t cap_loc; 5191 5192 /* Note: need to look at the port type information here */ 5193 (void) PCI_CAP_LOCATE(handle, PCI_CAP_ID_PCI_E, &cap_loc); 5194 if (cap_loc != PCI_CAP_NEXT_PTR_NULL) 5195 port_type = pci_config_get16(handle, 5196 cap_loc + PCIE_PCIECAP) & PCIE_PCIECAP_DEV_TYPE_MASK; 5197 5198 return (port_type); 5199 } 5200 5201 /* 5202 * Return true if the devinfo node is in a PCI Express hierarchy. 5203 */ 5204 static boolean_t 5205 is_pcie_fabric(dev_info_t *dip) 5206 { 5207 dev_info_t *root = ddi_root_node(); 5208 dev_info_t *pdip; 5209 boolean_t found = B_FALSE; 5210 char *bus; 5211 5212 /* 5213 * Does this device reside in a pcie fabric ? 5214 */ 5215 for (pdip = dip; pdip && (pdip != root) && !found; 5216 pdip = ddi_get_parent(pdip)) { 5217 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pdip, 5218 DDI_PROP_DONTPASS, "device_type", &bus) != 5219 DDI_PROP_SUCCESS) 5220 break; 5221 5222 if (strcmp(bus, "pciex") == 0) 5223 found = B_TRUE; 5224 5225 ddi_prop_free(bus); 5226 } 5227 5228 return (found); 5229 } 5230