1*507c3241Smlf /* 2*507c3241Smlf * CDDL HEADER START 3*507c3241Smlf * 4*507c3241Smlf * The contents of this file are subject to the terms of the 5*507c3241Smlf * Common Development and Distribution License (the "License"). 6*507c3241Smlf * You may not use this file except in compliance with the License. 7*507c3241Smlf * 8*507c3241Smlf * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*507c3241Smlf * or http://www.opensolaris.org/os/licensing. 10*507c3241Smlf * See the License for the specific language governing permissions 11*507c3241Smlf * and limitations under the License. 12*507c3241Smlf * 13*507c3241Smlf * When distributing Covered Code, include this CDDL HEADER in each 14*507c3241Smlf * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*507c3241Smlf * If applicable, add the following below this CDDL HEADER, with the 16*507c3241Smlf * fields enclosed by brackets "[]" replaced with your own identifying 17*507c3241Smlf * information: Portions Copyright [yyyy] [name of copyright owner] 18*507c3241Smlf * 19*507c3241Smlf * CDDL HEADER END 20*507c3241Smlf */ 21*507c3241Smlf 22*507c3241Smlf /* 23*507c3241Smlf * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24*507c3241Smlf * Use is subject to license terms. 25*507c3241Smlf */ 26*507c3241Smlf 27*507c3241Smlf #ifndef _SIL3XXX_H 28*507c3241Smlf #define _SIL3XXX_H 29*507c3241Smlf 30*507c3241Smlf #ifdef __cplusplus 31*507c3241Smlf extern "C" { 32*507c3241Smlf #endif 33*507c3241Smlf 34*507c3241Smlf /* 35*507c3241Smlf * PCI IDs 36*507c3241Smlf */ 37*507c3241Smlf #define SILICON_IMAGE_VENDOR_ID 0x1095 38*507c3241Smlf #define SIL3112_DEVICE_ID 0x3112 39*507c3241Smlf #define SIL3114_DEVICE_ID 0x3114 40*507c3241Smlf #define SIL3512_DEVICE_ID 0x3512 41*507c3241Smlf 42*507c3241Smlf /* Base Register 5 Indirect Address Offset */ 43*507c3241Smlf 44*507c3241Smlf #define PCI_CONF_BA5_IND_ADDRESS 0xc0 45*507c3241Smlf #define PCI_CONF_BA5_IND_ACCESS 0xc4 46*507c3241Smlf 47*507c3241Smlf /* 48*507c3241Smlf * FIS Configuration channel offsets 49*507c3241Smlf * Sil3114 has 4 channels 50*507c3241Smlf * Sil3112 has 2 channels 51*507c3241Smlf * Sil3512 has 2 channels 52*507c3241Smlf */ 53*507c3241Smlf #define SFISCFG_0 0x14c /* SFISCfg Channel 0 */ 54*507c3241Smlf #define SFISCFG_1 0x1cc /* SFISCfg Channel 1 */ 55*507c3241Smlf #define SFISCFG_2 0x34c /* SFISCfg Channel 2 */ 56*507c3241Smlf #define SFISCFG_3 0x3cc /* SFISCfg Channel 3 */ 57*507c3241Smlf 58*507c3241Smlf /* 59*507c3241Smlf * FIFO count and contrl offsets for channel 0-4 60*507c3241Smlf */ 61*507c3241Smlf #define FIFO_CNTCTL_0 0x40 62*507c3241Smlf #define FIFO_CNTCTL_1 0x44 63*507c3241Smlf #define FIFO_CNTCTL_2 0x240 64*507c3241Smlf #define FIFO_CNTCTL_3 0x244 65*507c3241Smlf 66*507c3241Smlf /* 67*507c3241Smlf * Errata Sil-AN-0028-C (Sil3512 Rev 0.3) 68*507c3241Smlf * Errata Sil-AN-0109-B2 (Sil3114 Rev 0.3) 69*507c3241Smlf * To prevent erroneous ERR set for queued DMA transfers 70*507c3241Smlf * greater then 8k, FIS reception for FIS0cfg needs to be set 71*507c3241Smlf * to Accept FIS without Interlock 72*507c3241Smlf * Default SFISCfg value of 0x10401555 in channel SFISCfg 73*507c3241Smlf * register need to be changed to 0x10401554. 74*507c3241Smlf */ 75*507c3241Smlf #define SFISCFG_ERRATA 0x10401554 76*507c3241Smlf 77*507c3241Smlf 78*507c3241Smlf #define PUT_BAR5_INDIRECT(handle, address, value) \ 79*507c3241Smlf {\ 80*507c3241Smlf pci_config_put32(handle, PCI_CONF_BA5_IND_ADDRESS, address); \ 81*507c3241Smlf pci_config_put32(handle, PCI_CONF_BA5_IND_ACCESS, value); \ 82*507c3241Smlf } 83*507c3241Smlf 84*507c3241Smlf #define GET_BAR5_INDIRECT(handle, address, rval) \ 85*507c3241Smlf {\ 86*507c3241Smlf pci_config_put32(handle, PCI_CONF_BA5_IND_ADDRESS, address); \ 87*507c3241Smlf rval = pci_config_get32(handle, PCI_CONF_BA5_IND_ACCESS); \ 88*507c3241Smlf } 89*507c3241Smlf 90*507c3241Smlf uint_t sil3xxx_init_controller(dev_info_t *, ushort_t, ushort_t); 91*507c3241Smlf 92*507c3241Smlf #ifdef __cplusplus 93*507c3241Smlf } 94*507c3241Smlf #endif 95*507c3241Smlf 96*507c3241Smlf #endif /* _SIL3XXX_H */ 97