1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _PCIIDE_H 28 #define _PCIIDE_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 35 /* 36 * Bus Mastering devices have a PCI class-code of 0x010180 to 0x0101ff 37 */ 38 #define PCIIDE_BM_CAP_MASK 0x80 39 #define PCIIDE_BM_CLASS ((PCI_CLASS_MASS << 16) | (PCI_MASS_IDE << 8) | 0x80) 40 #define PCIIDE_BM_CLASS_MASK 0xffffff80 41 42 43 #define PCIIDE_BMICX_REG 0 /* Bus Master IDE Command Register */ 44 45 #define PCIIDE_BMICX_SSBM 0x01 /* Start/Stop Bus Master */ 46 #define PCIIDE_BMICX_SSBM_E 0x01 /* 1=Start (Enable) */ 47 /* 0=Start (Disable) */ 48 49 /* 50 * NOTE: "read" and "write" are the actions of the DMA 51 * engine on the PCI bus. Not the DMA engine's action on the ATA 52 * BUS. Therefore for a ATA READ command, program the DMA engine to 53 * "write to memory" mode (and vice versa). 54 */ 55 #define PCIIDE_BMICX_RWCON 0x08 /* Read/Write Control */ 56 #define PCIIDE_BMICX_RWCON_WRITE_TO_MEMORY 0x08 /* 1=Write (dev to host) */ 57 #define PCIIDE_BMICX_RWCON_READ_FROM_MEMORY 0x00 /* 0=Read (host to dev) */ 58 59 /* preserve these bits during updates */ 60 #define PCIIDE_BMICX_MASK (~(PCIIDE_BMICX_SSBM | PCIIDE_BMICX_RWCON)) 61 62 63 64 #define PCIIDE_BMISX_REG 2 /* Bus Master IDE Status Register */ 65 66 #define PCIIDE_BMISX_BMIDEA 0x01 /* Bus Master IDE Active */ 67 #define PCIIDE_BMISX_IDERR 0x02 /* IDE DMA Error */ 68 #define PCIIDE_BMISX_IDEINTS 0x04 /* IDE Interrupt Status */ 69 #define PCIIDE_BMISX_DMA0CAP 0x20 /* Drive 0 DMA Capable */ 70 #define PCIIDE_BMISX_DMA1CAP 0x40 /* Drive 1 DMA Capable */ 71 #define PCIIDE_BMISX_SIMPLEX 0x80 /* Simplex only */ 72 73 /* preserve these bits during updates */ 74 #define PCIIDE_BMISX_MASK 0xf8 75 76 #define PCIIDE_BMIDTPX_REG 4 /* Bus Master IDE Desc. Table Ptr */ 77 #define PCIIDE_BMIDTPX_MASK 0x00000003 /* must be zeros */ 78 79 80 typedef struct PhysicalRegionDescriptorTableEntry { 81 uint_t p_address; /* physical address */ 82 uint_t p_count; /* byte count, EOT in high order bit */ 83 } prde_t; 84 85 /* 86 * Some specs say the p_address must 32-bit aligned, and some claim 87 * 16-bit alignment. Use 32-bit alignment just to be safe. 88 */ 89 #ifdef __not_yet__ 90 #define PCIIDE_PRDE_ADDR_MASK ((uint_t)(sizeof (short) -1)) 91 #else 92 #define PCIIDE_PRDE_ADDR_MASK ((uint_t)(sizeof (int) -1)) 93 #endif 94 95 #define PCIIDE_PRDE_CNT_MASK ((uint_t)0x0001) /* must be even */ 96 #define PCIIDE_PRDE_CNT_MAX ((uint_t)0x10000) /* 0 == 64k */ 97 #define PCIIDE_PRDE_EOT ((uint_t)0x80000000) 98 99 #ifdef __cplusplus 100 } 101 #endif 102 103 #endif /* _PCIIDE_H */ 104