1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/modctl.h> 31 #include <sys/debug.h> 32 #include <sys/promif.h> 33 #include <sys/pci.h> 34 #include <sys/errno.h> 35 #include <sys/open.h> 36 #include <sys/uio.h> 37 #include <sys/cred.h> 38 39 #include "ata_common.h" 40 #include "ata_disk.h" 41 #include "atapi.h" 42 #include "ata_blacklist.h" 43 #include "sil3xxx.h" 44 45 /* 46 * Solaris Entry Points. 47 */ 48 49 static int ata_probe(dev_info_t *dip); 50 static int ata_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 51 static int ata_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 52 static int ata_bus_ctl(dev_info_t *d, dev_info_t *r, ddi_ctl_enum_t o, 53 void *a, void *v); 54 static uint_t ata_intr(caddr_t arg); 55 56 /* 57 * GHD Entry points 58 */ 59 60 static int ata_get_status(void *hba_handle, void *intr_status); 61 static void ata_process_intr(void *hba_handle, void *intr_status); 62 static int ata_hba_start(void *handle, gcmd_t *gcmdp); 63 static void ata_hba_complete(void *handle, gcmd_t *gcmdp, int do_callback); 64 static int ata_timeout_func(void *hba_handle, gcmd_t *gcmdp, 65 gtgt_t *gtgtp, gact_t action, int calltype); 66 67 /* 68 * Local Function Prototypes 69 */ 70 static int ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip, 71 uint_t flags, char *name, int defvalue); 72 static int ata_ctlr_fsm(uchar_t fsm_func, ata_ctl_t *ata_ctlp, 73 ata_drv_t *ata_drvp, ata_pkt_t *ata_pktp, 74 int *DoneFlgp); 75 static void ata_destroy_controller(dev_info_t *dip); 76 static int ata_drive_type(uchar_t drvhd, 77 ddi_acc_handle_t io_hdl1, caddr_t ioaddr1, 78 ddi_acc_handle_t io_hdl2, caddr_t ioaddr2, 79 struct ata_id *ata_id_bufp); 80 static ata_ctl_t *ata_init_controller(dev_info_t *dip); 81 static ata_drv_t *ata_init_drive(ata_ctl_t *ata_ctlp, 82 uchar_t targ, uchar_t lun); 83 static int ata_init_drive_pcidma(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 84 dev_info_t *tdip); 85 static int ata_flush_cache(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp); 86 static void ata_init_pciide(dev_info_t *dip, ata_ctl_t *ata_ctlp); 87 static int ata_reset_bus(ata_ctl_t *ata_ctlp); 88 static int ata_setup_ioaddr(dev_info_t *dip, 89 ddi_acc_handle_t *iohandle1, caddr_t *ioaddr1p, 90 ddi_acc_handle_t *iohandle2, caddr_t *ioaddr2p, 91 ddi_acc_handle_t *bm_hdlp, caddr_t *bm_addrp); 92 static int ata_software_reset(ata_ctl_t *ata_ctlp); 93 static int ata_start_arq(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 94 ata_pkt_t *ata_pktp); 95 static int ata_strncmp(char *p1, char *p2, int cnt); 96 static void ata_uninit_drive(ata_drv_t *ata_drvp); 97 98 static int ata_check_pciide_blacklist(dev_info_t *dip, uint_t flags); 99 static int ata_check_revert_to_defaults(ata_drv_t *ata_drvp); 100 static void ata_show_transfer_mode(ata_ctl_t *, ata_drv_t *); 101 static int ata_spec_init_controller(dev_info_t *dip); 102 103 104 /* 105 * Local static data 106 */ 107 static void *ata_state; 108 109 static tmr_t ata_timer_conf; /* single timeout list for all instances */ 110 static int ata_watchdog_usec = 100000; /* check timeouts every 100 ms */ 111 112 int ata_hba_start_watchdog = 1000; 113 int ata_process_intr_watchdog = 1000; 114 int ata_reset_bus_watchdog = 1000; 115 116 117 /* 118 * number of seconds to wait during various operations 119 */ 120 int ata_flush_delay = 5 * 1000000; 121 uint_t ata_set_feature_wait = 4 * 1000000; 122 uint_t ata_flush_cache_wait = 60 * 1000000; /* may take a long time */ 123 124 /* 125 * Change this for SFF-8070i support. Currently SFF-8070i is 126 * using a field in the IDENTIFY PACKET DEVICE response which 127 * already seems to be in use by some vendor's drives. I suspect 128 * SFF will either move their laslun field or provide a reliable 129 * way to validate it. 130 */ 131 int ata_enable_atapi_luns = FALSE; 132 133 /* 134 * set this to disable all DMA requests 135 */ 136 int ata_dma_disabled = FALSE; 137 138 /* 139 * set this to TRUE to enable storing the IDENTIFY DEVICE result in the 140 * "ata" or "atapi" property. 141 */ 142 int ata_id_debug = FALSE; 143 144 /* 145 * set this to TRUE to enable logging device-capability data 146 */ 147 int ata_capability_data = FALSE; 148 149 #define ATAPRT(fmt) ghd_err fmt 150 151 /* 152 * DMA selection message pointers 153 */ 154 char *ata_cntrl_DMA_sel_msg; 155 char *ata_dev_DMA_sel_msg; 156 157 /* 158 * bus nexus operations 159 */ 160 static struct bus_ops ata_bus_ops; 161 static struct bus_ops *scsa_bus_ops_p; 162 163 /* ARGSUSED */ 164 static int 165 ata_open(dev_t *devp, int flag, int otyp, cred_t *cred_p) 166 { 167 if (ddi_get_soft_state(ata_state, getminor(*devp)) == NULL) 168 return (ENXIO); 169 170 return (0); 171 } 172 173 /* 174 * The purpose of this function is to pass the ioaddress of the controller 175 * to the caller, specifically used for upgrade from pre-pciide 176 * to pciide nodes 177 */ 178 /* ARGSUSED */ 179 static int 180 ata_read(dev_t dev, struct uio *uio_p, cred_t *cred_p) 181 { 182 ata_ctl_t *ata_ctlp; 183 char buf[18]; 184 long len; 185 186 ata_ctlp = ddi_get_soft_state(ata_state, getminor(dev)); 187 188 if (ata_ctlp == NULL) 189 return (ENXIO); 190 191 (void) sprintf(buf, "%p\n", (void *) ata_ctlp->ac_ioaddr1); 192 193 len = strlen(buf) - uio_p->uio_offset; 194 len = min(uio_p->uio_resid, len); 195 if (len <= 0) 196 return (0); 197 198 return (uiomove((caddr_t)(buf + uio_p->uio_offset), len, 199 UIO_READ, uio_p)); 200 } 201 202 int 203 ata_devo_reset( 204 dev_info_t *dip, 205 ddi_reset_cmd_t cmd) 206 { 207 ata_ctl_t *ata_ctlp; 208 ata_drv_t *ata_drvp; 209 int instance; 210 int i; 211 int rc; 212 int flush_okay; 213 214 if (cmd != DDI_RESET_FORCE) 215 return (0); 216 217 instance = ddi_get_instance(dip); 218 ata_ctlp = ddi_get_soft_state(ata_state, instance); 219 220 if (!ata_ctlp) 221 return (0); 222 223 /* 224 * reset ATA drives and flush the write cache of any drives 225 */ 226 flush_okay = TRUE; 227 for (i = 0; i < ATA_MAXTARG; i++) { 228 if ((ata_drvp = CTL2DRV(ata_ctlp, i, 0)) == 0) 229 continue; 230 /* Don't revert to defaults for certain IBM drives */ 231 if ((ata_drvp->ad_flags & AD_DISK) != 0 && 232 ((ata_drvp->ad_flags & AD_NORVRT) == 0)) { 233 /* Enable revert to defaults when reset */ 234 (void) ata_set_feature(ata_ctlp, ata_drvp, 0xCC, 0); 235 } 236 237 /* 238 * skip flush cache if device type is cdrom 239 * 240 * notes: the structure definitions for ata_drvp->ad_id are 241 * defined for the ATA IDENTIFY_DEVICE, but if AD_ATAPI is set 242 * the struct holds data for the ATAPI IDENTIFY_PACKET_DEVICE 243 */ 244 if (!IS_CDROM(ata_drvp)) { 245 246 /* 247 * Try the ATA/ATAPI flush write cache command 248 */ 249 rc = ata_flush_cache(ata_ctlp, ata_drvp); 250 ADBG_WARN(("ata_flush_cache %s\n", 251 rc ? "okay" : "failed")); 252 253 if (!rc) 254 flush_okay = FALSE; 255 } 256 257 258 /* 259 * do something else if flush cache not supported 260 */ 261 } 262 263 /* 264 * just busy wait if any drive doesn't support FLUSH CACHE 265 */ 266 if (!flush_okay) 267 drv_usecwait(ata_flush_delay); 268 return (0); 269 } 270 271 272 static struct cb_ops ata_cb_ops = { 273 ata_open, /* open */ 274 nulldev, /* close */ 275 nodev, /* strategy */ 276 nodev, /* print */ 277 nodev, /* dump */ 278 ata_read, /* read */ 279 nodev, /* write */ 280 nodev, /* ioctl */ 281 nodev, /* devmap */ 282 nodev, /* mmap */ 283 nodev, /* segmap */ 284 nochpoll, /* chpoll */ 285 ddi_prop_op, /* prop_op */ 286 NULL, /* stream info */ 287 D_MP, /* driver compatibility flag */ 288 CB_REV, /* cb_ops revision */ 289 nodev, /* aread */ 290 nodev /* awrite */ 291 }; 292 293 static struct dev_ops ata_ops = { 294 DEVO_REV, /* devo_rev, */ 295 0, /* refcnt */ 296 ddi_getinfo_1to1, /* info */ 297 nulldev, /* identify */ 298 ata_probe, /* probe */ 299 ata_attach, /* attach */ 300 ata_detach, /* detach */ 301 ata_devo_reset, /* reset */ 302 &ata_cb_ops, /* driver operations */ 303 NULL /* bus operations */ 304 }; 305 306 /* driver loadable module wrapper */ 307 static struct modldrv modldrv = { 308 &mod_driverops, /* Type of module. This one is a driver */ 309 "ATA AT-bus attachment disk controller Driver", /* module name */ 310 &ata_ops, /* driver ops */ 311 }; 312 313 static struct modlinkage modlinkage = { 314 MODREV_1, (void *)&modldrv, NULL 315 }; 316 317 #ifdef ATA_DEBUG 318 int ata_debug_init = FALSE; 319 int ata_debug_probe = FALSE; 320 int ata_debug_attach = FALSE; 321 322 int ata_debug = ADBG_FLAG_ERROR 323 /* | ADBG_FLAG_ARQ */ 324 /* | ADBG_FLAG_INIT */ 325 /* | ADBG_FLAG_TRACE */ 326 /* | ADBG_FLAG_TRANSPORT */ 327 /* | ADBG_FLAG_WARN */ 328 ; 329 #endif 330 331 int 332 _init(void) 333 { 334 int err; 335 336 #ifdef ATA_DEBUG 337 if (ata_debug_init) 338 debug_enter("\nATA _INIT\n"); 339 #endif 340 341 if ((err = ddi_soft_state_init(&ata_state, sizeof (ata_ctl_t), 0)) != 0) 342 return (err); 343 344 if ((err = scsi_hba_init(&modlinkage)) != 0) { 345 ddi_soft_state_fini(&ata_state); 346 return (err); 347 } 348 349 /* save pointer to SCSA provided bus_ops struct */ 350 scsa_bus_ops_p = ata_ops.devo_bus_ops; 351 352 /* make a copy of SCSA bus_ops */ 353 ata_bus_ops = *(ata_ops.devo_bus_ops); 354 355 /* 356 * Modify our bus_ops to call our routines. Our implementation 357 * will determine if the device is ATA or ATAPI/SCSA and react 358 * accordingly. 359 */ 360 ata_bus_ops.bus_ctl = ata_bus_ctl; 361 362 /* patch our bus_ops into the dev_ops struct */ 363 ata_ops.devo_bus_ops = &ata_bus_ops; 364 365 if ((err = mod_install(&modlinkage)) != 0) { 366 scsi_hba_fini(&modlinkage); 367 ddi_soft_state_fini(&ata_state); 368 } 369 370 /* 371 * Initialize the per driver timer info. 372 */ 373 374 ghd_timer_init(&ata_timer_conf, drv_usectohz(ata_watchdog_usec)); 375 376 return (err); 377 } 378 379 int 380 _fini(void) 381 { 382 int err; 383 384 if ((err = mod_remove(&modlinkage)) == 0) { 385 ghd_timer_fini(&ata_timer_conf); 386 scsi_hba_fini(&modlinkage); 387 ddi_soft_state_fini(&ata_state); 388 } 389 390 return (err); 391 } 392 393 int 394 _info(struct modinfo *modinfop) 395 { 396 return (mod_info(&modlinkage, modinfop)); 397 } 398 399 400 /* driver probe entry point */ 401 402 static int 403 ata_probe( 404 dev_info_t *dip) 405 { 406 ddi_acc_handle_t io_hdl1 = NULL; 407 ddi_acc_handle_t io_hdl2 = NULL; 408 ddi_acc_handle_t bm_hdl = NULL; 409 caddr_t ioaddr1; 410 caddr_t ioaddr2; 411 caddr_t bm_addr; 412 int drive; 413 struct ata_id *ata_id_bufp; 414 int rc = DDI_PROBE_FAILURE; 415 416 ADBG_TRACE(("ata_probe entered\n")); 417 #ifdef ATA_DEBUG 418 if (ata_debug_probe) 419 debug_enter("\nATA_PROBE\n"); 420 #endif 421 422 if (!ata_setup_ioaddr(dip, &io_hdl1, &ioaddr1, &io_hdl2, &ioaddr2, 423 &bm_hdl, &bm_addr)) 424 return (rc); 425 426 ata_id_bufp = kmem_zalloc(sizeof (*ata_id_bufp), KM_SLEEP); 427 428 for (drive = 0; drive < ATA_MAXTARG; drive++) { 429 uchar_t drvhd; 430 431 /* set up drv/hd and feature registers */ 432 433 drvhd = (drive == 0 ? ATDH_DRIVE0 : ATDH_DRIVE1); 434 435 436 if (ata_drive_type(drvhd, io_hdl1, ioaddr1, io_hdl2, ioaddr2, 437 ata_id_bufp) != ATA_DEV_NONE) { 438 rc = (DDI_PROBE_SUCCESS); 439 break; 440 } 441 } 442 443 /* always leave the controller set to drive 0 */ 444 if (drive != 0) { 445 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_DRVHD, ATDH_DRIVE0); 446 ATA_DELAY_400NSEC(io_hdl2, ioaddr2); 447 } 448 449 out2: 450 kmem_free(ata_id_bufp, sizeof (*ata_id_bufp)); 451 452 if (io_hdl1) 453 ddi_regs_map_free(&io_hdl1); 454 if (io_hdl2) 455 ddi_regs_map_free(&io_hdl2); 456 if (bm_hdl) 457 ddi_regs_map_free(&bm_hdl); 458 return (rc); 459 } 460 461 /* 462 * 463 * driver attach entry point 464 * 465 */ 466 467 static int 468 ata_attach( 469 dev_info_t *dip, 470 ddi_attach_cmd_t cmd) 471 { 472 ata_ctl_t *ata_ctlp; 473 ata_drv_t *ata_drvp; 474 ata_drv_t *first_drvp = NULL; 475 uchar_t targ; 476 uchar_t lun; 477 uchar_t lastlun; 478 int atapi_count = 0; 479 int disk_count = 0; 480 481 ADBG_TRACE(("ata_attach entered\n")); 482 #ifdef ATA_DEBUG 483 if (ata_debug_attach) 484 debug_enter("\nATA_ATTACH\n\n"); 485 #endif 486 487 if (cmd != DDI_ATTACH) 488 return (DDI_FAILURE); 489 490 /* initialize controller */ 491 ata_ctlp = ata_init_controller(dip); 492 493 if (ata_ctlp == NULL) 494 goto errout; 495 496 mutex_enter(&ata_ctlp->ac_ccc.ccc_hba_mutex); 497 498 /* initialize drives */ 499 500 for (targ = 0; targ < ATA_MAXTARG; targ++) { 501 502 ata_drvp = ata_init_drive(ata_ctlp, targ, 0); 503 if (ata_drvp == NULL) 504 continue; 505 506 if (first_drvp == NULL) 507 first_drvp = ata_drvp; 508 509 if (ATAPIDRV(ata_drvp)) { 510 atapi_count++; 511 lastlun = ata_drvp->ad_id.ai_lastlun; 512 } else { 513 disk_count++; 514 lastlun = 0; 515 } 516 517 /* 518 * LUN support is currently disabled. Check with SFF-8070i 519 * before enabling. 520 */ 521 if (!ata_enable_atapi_luns) 522 lastlun = 0; 523 524 /* Initialize higher LUNs, if there are any */ 525 for (lun = 1; lun <= lastlun && lun < ATA_MAXLUN; lun++) { 526 if ((ata_drvp = 527 ata_init_drive(ata_ctlp, targ, lun)) != NULL) { 528 ata_show_transfer_mode(ata_ctlp, ata_drvp); 529 } 530 } 531 } 532 533 if ((atapi_count == 0) && (disk_count == 0)) { 534 ADBG_WARN(("ata_attach: no drives detected\n")); 535 goto errout1; 536 } 537 538 /* 539 * Always make certain that a valid drive is selected so 540 * that routines which poll the status register don't get 541 * confused by non-existent drives. 542 */ 543 ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd, 544 first_drvp->ad_drive_bits); 545 ATA_DELAY_400NSEC(ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2); 546 547 /* 548 * make certain the drive selected 549 */ 550 if (!ata_wait(ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2, 551 0, ATS_BSY, 5000000)) { 552 ADBG_ERROR(("ata_attach: select failed\n")); 553 } 554 555 /* 556 * initialize atapi/ata_dsk modules if we have at least 557 * one drive of that type. 558 */ 559 560 if (atapi_count) { 561 if (!atapi_attach(ata_ctlp)) 562 goto errout1; 563 ata_ctlp->ac_flags |= AC_ATAPI_INIT; 564 } 565 566 if (disk_count) { 567 if (!ata_disk_attach(ata_ctlp)) 568 goto errout1; 569 ata_ctlp->ac_flags |= AC_DISK_INIT; 570 } 571 572 /* 573 * make certain the interrupt and error latches are clear 574 */ 575 if (ata_ctlp->ac_pciide) { 576 577 int instance = ddi_get_instance(dip); 578 if (ddi_create_minor_node(dip, "control", S_IFCHR, instance, 579 DDI_PSEUDO, 0) != DDI_SUCCESS) { 580 goto errout1; 581 } 582 583 (void) ata_pciide_status_clear(ata_ctlp); 584 585 } 586 587 /* 588 * enable the interrupt handler and drop the mutex 589 */ 590 ata_ctlp->ac_flags |= AC_ATTACHED; 591 mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex); 592 593 ddi_report_dev(dip); 594 return (DDI_SUCCESS); 595 596 errout1: 597 mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex); 598 errout: 599 (void) ata_detach(dip, DDI_DETACH); 600 return (DDI_FAILURE); 601 } 602 603 /* driver detach entry point */ 604 605 static int 606 ata_detach( 607 dev_info_t *dip, 608 ddi_detach_cmd_t cmd) 609 { 610 ata_ctl_t *ata_ctlp; 611 ata_drv_t *ata_drvp; 612 int instance; 613 int i; 614 int j; 615 616 ADBG_TRACE(("ata_detach entered\n")); 617 618 if (cmd != DDI_DETACH) 619 return (DDI_FAILURE); 620 621 instance = ddi_get_instance(dip); 622 ata_ctlp = ddi_get_soft_state(ata_state, instance); 623 624 if (!ata_ctlp) 625 return (DDI_SUCCESS); 626 627 ata_ctlp->ac_flags &= ~AC_ATTACHED; 628 629 /* destroy ata module */ 630 if (ata_ctlp->ac_flags & AC_DISK_INIT) 631 ata_disk_detach(ata_ctlp); 632 633 /* destroy atapi module */ 634 if (ata_ctlp->ac_flags & AC_ATAPI_INIT) 635 atapi_detach(ata_ctlp); 636 637 ddi_remove_minor_node(dip, NULL); 638 639 /* destroy drives */ 640 for (i = 0; i < ATA_MAXTARG; i++) { 641 for (j = 0; j < ATA_MAXLUN; j++) { 642 ata_drvp = CTL2DRV(ata_ctlp, i, j); 643 if (ata_drvp != NULL) 644 ata_uninit_drive(ata_drvp); 645 } 646 } 647 648 if (ata_ctlp->ac_iohandle1) 649 ddi_regs_map_free(&ata_ctlp->ac_iohandle1); 650 if (ata_ctlp->ac_iohandle2) 651 ddi_regs_map_free(&ata_ctlp->ac_iohandle2); 652 if (ata_ctlp->ac_bmhandle) 653 ddi_regs_map_free(&ata_ctlp->ac_bmhandle); 654 655 ddi_prop_remove_all(dip); 656 657 /* destroy controller */ 658 ata_destroy_controller(dip); 659 660 return (DDI_SUCCESS); 661 } 662 663 /* 664 * Nexus driver bus_ctl entry point 665 */ 666 /*ARGSUSED*/ 667 static int 668 ata_bus_ctl( 669 dev_info_t *d, 670 dev_info_t *r, 671 ddi_ctl_enum_t o, 672 void *a, 673 void *v) 674 { 675 dev_info_t *tdip; 676 int target_type; 677 int rc; 678 char *bufp; 679 680 ADBG_TRACE(("ata_bus_ctl entered\n")); 681 682 switch (o) { 683 684 case DDI_CTLOPS_SIDDEV: 685 return (DDI_FAILURE); 686 687 case DDI_CTLOPS_IOMIN: 688 689 /* 690 * Since we use PIO, we return a minimum I/O size of 691 * one byte. This will need to be updated when we 692 * implement DMA support 693 */ 694 695 *((int *)v) = 1; 696 return (DDI_SUCCESS); 697 698 case DDI_CTLOPS_DMAPMAPC: 699 case DDI_CTLOPS_REPORTINT: 700 case DDI_CTLOPS_REGSIZE: 701 case DDI_CTLOPS_NREGS: 702 case DDI_CTLOPS_SLAVEONLY: 703 case DDI_CTLOPS_AFFINITY: 704 case DDI_CTLOPS_POKE: 705 case DDI_CTLOPS_PEEK: 706 707 /* These ops shouldn't be called by a target driver */ 708 ADBG_ERROR(("ata_bus_ctl: %s%d: invalid op (%d) from %s%d\n", 709 ddi_driver_name(d), ddi_get_instance(d), o, 710 ddi_driver_name(r), ddi_get_instance(r))); 711 712 return (DDI_FAILURE); 713 714 case DDI_CTLOPS_REPORTDEV: 715 case DDI_CTLOPS_INITCHILD: 716 case DDI_CTLOPS_UNINITCHILD: 717 718 /* these require special handling below */ 719 break; 720 721 default: 722 return (ddi_ctlops(d, r, o, a, v)); 723 } 724 725 /* get targets dip */ 726 727 if (o == DDI_CTLOPS_INITCHILD || o == DDI_CTLOPS_UNINITCHILD) 728 tdip = (dev_info_t *)a; 729 else 730 tdip = r; 731 732 /* 733 * XXX - Get class of target 734 * Before the "class" entry in a conf file becomes 735 * a real property, we use an additional property 736 * tentatively called "class_prop". We will require that 737 * new classes (ie. direct) export "class_prop". 738 * SCSA target drivers will not have this property, so 739 * no property implies SCSA. 740 */ 741 if ((ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 742 "class", &bufp) == DDI_PROP_SUCCESS) || 743 (ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 744 "class_prop", &bufp) == DDI_PROP_SUCCESS)) { 745 if (strcmp(bufp, "dada") == 0) 746 target_type = ATA_DEV_DISK; 747 else if (strcmp(bufp, "scsi") == 0) 748 target_type = ATA_DEV_ATAPI; 749 else { 750 ADBG_WARN(("ata_bus_ctl: invalid target class %s\n", 751 bufp)); 752 ddi_prop_free(bufp); 753 return (DDI_FAILURE); 754 } 755 ddi_prop_free(bufp); 756 } else { 757 target_type = ATA_DEV_ATAPI; /* no class prop, assume SCSI */ 758 } 759 760 if (o == DDI_CTLOPS_INITCHILD) { 761 int instance = ddi_get_instance(d); 762 ata_ctl_t *ata_ctlp = ddi_get_soft_state(ata_state, instance); 763 ata_drv_t *ata_drvp; 764 int targ; 765 int lun; 766 int drive_type; 767 char *disk_prop; 768 char *class_prop; 769 770 if (ata_ctlp == NULL) { 771 ADBG_WARN(("ata_bus_ctl: failed to find ctl struct\n")); 772 return (DDI_FAILURE); 773 } 774 775 /* get (target,lun) of child device */ 776 777 targ = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 778 "target", -1); 779 if (targ == -1) { 780 ADBG_WARN(("ata_bus_ctl: failed to get targ num\n")); 781 return (DDI_FAILURE); 782 } 783 784 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 785 "lun", 0); 786 787 if ((targ < 0) || (targ >= ATA_MAXTARG) || 788 (lun < 0) || (lun >= ATA_MAXLUN)) { 789 return (DDI_FAILURE); 790 } 791 792 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 793 794 if (ata_drvp == NULL) 795 return (DDI_FAILURE); /* no drive */ 796 797 /* get type of device */ 798 799 if (ATAPIDRV(ata_drvp)) 800 drive_type = ATA_DEV_ATAPI; 801 else 802 drive_type = ATA_DEV_DISK; 803 804 /* 805 * Check for special handling when child driver is 806 * cmdk (which morphs to the correct interface) 807 */ 808 if (strcmp(ddi_get_name(tdip), "cmdk") == 0) { 809 810 if ((target_type == ATA_DEV_DISK) && 811 (target_type != drive_type)) 812 return (DDI_FAILURE); 813 814 target_type = drive_type; 815 816 if (drive_type == ATA_DEV_ATAPI) { 817 class_prop = "scsi"; 818 } else { 819 disk_prop = "dadk"; 820 class_prop = "dada"; 821 822 if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip, 823 "disk", disk_prop) != DDI_PROP_SUCCESS) { 824 ADBG_WARN(("ata_bus_ctl: failed to " 825 "create disk prop\n")); 826 return (DDI_FAILURE); 827 } 828 } 829 830 if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip, 831 "class_prop", class_prop) != DDI_PROP_SUCCESS) { 832 ADBG_WARN(("ata_bus_ctl: failed to " 833 "create class prop\n")); 834 return (DDI_FAILURE); 835 } 836 } 837 838 /* Check that target class matches the device */ 839 840 if (target_type != drive_type) 841 return (DDI_FAILURE); 842 843 /* save pointer to drive struct for ata_disk_bus_ctl */ 844 ddi_set_driver_private(tdip, ata_drvp); 845 846 /* 847 * Determine whether to enable DMA support for this drive. This 848 * check is deferred to this point so that the various dma 849 * properties could reside on the devinfo node should finer 850 * grained dma control be required. 851 */ 852 ata_drvp->ad_pciide_dma = ata_init_drive_pcidma(ata_ctlp, 853 ata_drvp, tdip); 854 ata_show_transfer_mode(ata_ctlp, ata_drvp); 855 } 856 857 if (target_type == ATA_DEV_ATAPI) { 858 rc = scsa_bus_ops_p->bus_ctl(d, r, o, a, v); 859 } else { 860 rc = ata_disk_bus_ctl(d, r, o, a, v); 861 } 862 863 return (rc); 864 } 865 866 /* 867 * 868 * GHD ccc_hba_complete callback 869 * 870 */ 871 872 /* ARGSUSED */ 873 static void 874 ata_hba_complete( 875 void *hba_handle, 876 gcmd_t *gcmdp, 877 int do_callback) 878 { 879 ata_drv_t *ata_drvp; 880 ata_pkt_t *ata_pktp; 881 882 ADBG_TRACE(("ata_hba_complete entered\n")); 883 884 ata_drvp = GCMD2DRV(gcmdp); 885 ata_pktp = GCMD2APKT(gcmdp); 886 if (ata_pktp->ap_complete) 887 (*ata_pktp->ap_complete)(ata_drvp, ata_pktp, 888 do_callback); 889 } 890 891 /* GHD ccc_timeout_func callback */ 892 893 /* ARGSUSED */ 894 static int 895 ata_timeout_func( 896 void *hba_handle, 897 gcmd_t *gcmdp, 898 gtgt_t *gtgtp, 899 gact_t action, 900 int calltype) 901 { 902 ata_ctl_t *ata_ctlp; 903 ata_pkt_t *ata_pktp; 904 905 ADBG_TRACE(("ata_timeout_func entered\n")); 906 907 ata_ctlp = (ata_ctl_t *)hba_handle; 908 909 if (gcmdp != NULL) 910 ata_pktp = GCMD2APKT(gcmdp); 911 else 912 ata_pktp = NULL; 913 914 switch (action) { 915 case GACTION_EARLY_ABORT: 916 /* abort before request was started */ 917 if (ata_pktp != NULL) { 918 ata_pktp->ap_flags |= AP_ABORT; 919 } 920 ghd_complete(&ata_ctlp->ac_ccc, gcmdp); 921 return (TRUE); 922 923 case GACTION_EARLY_TIMEOUT: 924 /* timeout before request was started */ 925 if (ata_pktp != NULL) { 926 ata_pktp->ap_flags |= AP_TIMEOUT; 927 } 928 ghd_complete(&ata_ctlp->ac_ccc, gcmdp); 929 return (TRUE); 930 931 case GACTION_RESET_TARGET: 932 /* 933 * Reset a device is not supported. Resetting a specific 934 * device can't be done at all to an ATA device and if 935 * you send a RESET to an ATAPI device you have to 936 * reset the whole bus to make certain both devices 937 * on the bus stay in sync regarding which device is 938 * the currently selected one. 939 */ 940 return (FALSE); 941 942 case GACTION_RESET_BUS: 943 /* 944 * Issue bus reset and reinitialize both drives. 945 * But only if this is a timed-out request. Target 946 * driver reset requests are ignored because ATA 947 * and ATAPI devices shouldn't be gratuitously reset. 948 */ 949 if (gcmdp == NULL) 950 break; 951 return (ata_reset_bus(ata_ctlp)); 952 default: 953 break; 954 } 955 return (FALSE); 956 } 957 958 /* 959 * 960 * Initialize controller's soft-state structure 961 * 962 */ 963 964 static ata_ctl_t * 965 ata_init_controller( 966 dev_info_t *dip) 967 { 968 ata_ctl_t *ata_ctlp; 969 int instance; 970 caddr_t ioaddr1; 971 caddr_t ioaddr2; 972 973 ADBG_TRACE(("ata_init_controller entered\n")); 974 975 instance = ddi_get_instance(dip); 976 977 /* allocate controller structure */ 978 if (ddi_soft_state_zalloc(ata_state, instance) != DDI_SUCCESS) { 979 ADBG_WARN(("ata_init_controller: soft_state_zalloc failed\n")); 980 return (NULL); 981 } 982 983 ata_ctlp = ddi_get_soft_state(ata_state, instance); 984 985 if (ata_ctlp == NULL) { 986 ADBG_WARN(("ata_init_controller: failed to find " 987 "controller struct\n")); 988 return (NULL); 989 } 990 991 /* 992 * initialize per-controller data 993 */ 994 ata_ctlp->ac_dip = dip; 995 ata_ctlp->ac_arq_pktp = kmem_zalloc(sizeof (ata_pkt_t), KM_SLEEP); 996 997 /* 998 * map the device registers 999 */ 1000 if (!ata_setup_ioaddr(dip, &ata_ctlp->ac_iohandle1, &ioaddr1, 1001 &ata_ctlp->ac_iohandle2, &ioaddr2, 1002 &ata_ctlp->ac_bmhandle, &ata_ctlp->ac_bmaddr)) { 1003 (void) ata_detach(dip, DDI_DETACH); 1004 return (NULL); 1005 } 1006 1007 ADBG_INIT(("ata_init_controller: ioaddr1 = 0x%p, ioaddr2 = 0x%p\n", 1008 ioaddr1, ioaddr2)); 1009 1010 /* 1011 * Do ARQ setup 1012 */ 1013 atapi_init_arq(ata_ctlp); 1014 1015 /* 1016 * Do PCI-IDE setup 1017 */ 1018 ata_init_pciide(dip, ata_ctlp); 1019 1020 /* 1021 * port addresses associated with ioaddr1 1022 */ 1023 ata_ctlp->ac_ioaddr1 = ioaddr1; 1024 ata_ctlp->ac_data = (ushort_t *)ioaddr1 + AT_DATA; 1025 ata_ctlp->ac_error = (uchar_t *)ioaddr1 + AT_ERROR; 1026 ata_ctlp->ac_feature = (uchar_t *)ioaddr1 + AT_FEATURE; 1027 ata_ctlp->ac_count = (uchar_t *)ioaddr1 + AT_COUNT; 1028 ata_ctlp->ac_sect = (uchar_t *)ioaddr1 + AT_SECT; 1029 ata_ctlp->ac_lcyl = (uchar_t *)ioaddr1 + AT_LCYL; 1030 ata_ctlp->ac_hcyl = (uchar_t *)ioaddr1 + AT_HCYL; 1031 ata_ctlp->ac_drvhd = (uchar_t *)ioaddr1 + AT_DRVHD; 1032 ata_ctlp->ac_status = (uchar_t *)ioaddr1 + AT_STATUS; 1033 ata_ctlp->ac_cmd = (uchar_t *)ioaddr1 + AT_CMD; 1034 1035 /* 1036 * port addresses associated with ioaddr2 1037 */ 1038 ata_ctlp->ac_ioaddr2 = ioaddr2; 1039 ata_ctlp->ac_altstatus = (uchar_t *)ioaddr2 + AT_ALTSTATUS; 1040 ata_ctlp->ac_devctl = (uchar_t *)ioaddr2 + AT_DEVCTL; 1041 1042 /* 1043 * If AC_BSY_WAIT needs to be set for laptops that do 1044 * suspend/resume but do not correctly wait for the busy bit to 1045 * drop after a resume. 1046 */ 1047 ata_ctlp->ac_timing_flags = ddi_prop_get_int(DDI_DEV_T_ANY, 1048 dip, DDI_PROP_DONTPASS, "timing_flags", 0); 1049 /* 1050 * get max transfer size, default to 256 sectors 1051 */ 1052 ata_ctlp->ac_max_transfer = ddi_prop_get_int(DDI_DEV_T_ANY, 1053 dip, DDI_PROP_DONTPASS, "max_transfer", 0x100); 1054 if (ata_ctlp->ac_max_transfer < 1) 1055 ata_ctlp->ac_max_transfer = 1; 1056 if (ata_ctlp->ac_max_transfer > 0x100) 1057 ata_ctlp->ac_max_transfer = 0x100; 1058 1059 /* 1060 * Get the standby timer value 1061 */ 1062 ata_ctlp->ac_standby_time = ddi_prop_get_int(DDI_DEV_T_ANY, 1063 dip, DDI_PROP_DONTPASS, "standby", -1); 1064 1065 /* 1066 * If this is a /pci/pci-ide instance check to see if 1067 * it's supposed to be attached as an /isa/ata 1068 */ 1069 if (ata_ctlp->ac_pciide) { 1070 static char prop_buf[] = "SUNW-ata-ffff-isa"; 1071 int addr1 = (intptr_t)ioaddr1; 1072 1073 1074 if (addr1 < 0 || addr1 > 0xffff) { 1075 (void) ata_detach(dip, DDI_DETACH); 1076 return (NULL); 1077 } 1078 (void) sprintf(prop_buf, "SUNW-ata-%04x-isa", 1079 addr1); 1080 if (ddi_prop_exists(DDI_DEV_T_ANY, ddi_root_node(), 1081 DDI_PROP_DONTPASS, prop_buf)) { 1082 (void) ata_detach(dip, DDI_DETACH); 1083 return (NULL); 1084 } 1085 } 1086 1087 /* Init controller specific stuff */ 1088 (void) ata_spec_init_controller(dip); 1089 1090 /* 1091 * initialize GHD 1092 */ 1093 1094 GHD_WAITQ_INIT(&ata_ctlp->ac_ccc.ccc_waitq, NULL, 1); 1095 1096 if (!ghd_register("ata", &ata_ctlp->ac_ccc, dip, 0, ata_ctlp, 1097 atapi_ccballoc, atapi_ccbfree, 1098 ata_pciide_dma_sg_func, ata_hba_start, 1099 ata_hba_complete, ata_intr, 1100 ata_get_status, ata_process_intr, ata_timeout_func, 1101 &ata_timer_conf, NULL)) { 1102 (void) ata_detach(dip, DDI_DETACH); 1103 return (NULL); 1104 } 1105 1106 ata_ctlp->ac_flags |= AC_GHD_INIT; 1107 return (ata_ctlp); 1108 } 1109 1110 /* destroy a controller */ 1111 1112 static void 1113 ata_destroy_controller( 1114 dev_info_t *dip) 1115 { 1116 ata_ctl_t *ata_ctlp; 1117 int instance; 1118 1119 ADBG_TRACE(("ata_destroy_controller entered\n")); 1120 1121 instance = ddi_get_instance(dip); 1122 ata_ctlp = ddi_get_soft_state(ata_state, instance); 1123 1124 if (ata_ctlp == NULL) 1125 return; 1126 1127 /* destroy ghd */ 1128 if (ata_ctlp->ac_flags & AC_GHD_INIT) 1129 ghd_unregister(&ata_ctlp->ac_ccc); 1130 1131 /* free the pciide buffer (if any) */ 1132 ata_pciide_free(ata_ctlp); 1133 1134 /* destroy controller struct */ 1135 kmem_free(ata_ctlp->ac_arq_pktp, sizeof (ata_pkt_t)); 1136 ddi_soft_state_free(ata_state, instance); 1137 1138 } 1139 1140 1141 /* 1142 * 1143 * initialize a drive 1144 * 1145 */ 1146 1147 static ata_drv_t * 1148 ata_init_drive( 1149 ata_ctl_t *ata_ctlp, 1150 uchar_t targ, 1151 uchar_t lun) 1152 { 1153 static char nec_260[] = "NEC CD-ROM DRIVE"; 1154 ata_drv_t *ata_drvp; 1155 struct ata_id *aidp; 1156 char buf[80]; 1157 int drive_type; 1158 int i; 1159 int valid_version = 0; 1160 1161 ADBG_TRACE(("ata_init_drive entered, targ = %d, lun = %d\n", 1162 targ, lun)); 1163 1164 /* check if device already exists */ 1165 1166 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 1167 1168 if (ata_drvp != NULL) 1169 return (ata_drvp); 1170 1171 /* allocate new device structure */ 1172 1173 ata_drvp = kmem_zalloc(sizeof (ata_drv_t), KM_SLEEP); 1174 aidp = &ata_drvp->ad_id; 1175 1176 /* 1177 * set up drive struct 1178 */ 1179 ata_drvp->ad_ctlp = ata_ctlp; 1180 ata_drvp->ad_targ = targ; 1181 ata_drvp->ad_drive_bits = 1182 (ata_drvp->ad_targ == 0 ? ATDH_DRIVE0 : ATDH_DRIVE1); 1183 /* 1184 * Add the LUN for SFF-8070i support 1185 */ 1186 ata_drvp->ad_lun = lun; 1187 ata_drvp->ad_drive_bits |= ata_drvp->ad_lun; 1188 1189 /* 1190 * get drive type, side effect is to collect 1191 * IDENTIFY DRIVE data 1192 */ 1193 1194 drive_type = ata_drive_type(ata_drvp->ad_drive_bits, 1195 ata_ctlp->ac_iohandle1, 1196 ata_ctlp->ac_ioaddr1, 1197 ata_ctlp->ac_iohandle2, 1198 ata_ctlp->ac_ioaddr2, 1199 aidp); 1200 1201 switch (drive_type) { 1202 case ATA_DEV_NONE: 1203 /* no drive found */ 1204 goto errout; 1205 case ATA_DEV_ATAPI: 1206 ata_drvp->ad_flags |= AD_ATAPI; 1207 break; 1208 case ATA_DEV_DISK: 1209 ata_drvp->ad_flags |= AD_DISK; 1210 break; 1211 } 1212 1213 /* 1214 * swap bytes of all text fields 1215 */ 1216 if (!ata_strncmp(nec_260, aidp->ai_model, sizeof (aidp->ai_model))) { 1217 swab(aidp->ai_drvser, aidp->ai_drvser, 1218 sizeof (aidp->ai_drvser)); 1219 swab(aidp->ai_fw, aidp->ai_fw, 1220 sizeof (aidp->ai_fw)); 1221 swab(aidp->ai_model, aidp->ai_model, 1222 sizeof (aidp->ai_model)); 1223 } 1224 1225 /* 1226 * Check if this drive has the Single Sector bug 1227 */ 1228 1229 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_1SECTOR)) 1230 ata_drvp->ad_flags |= AD_1SECTOR; 1231 else 1232 ata_drvp->ad_flags &= ~AD_1SECTOR; 1233 1234 /* Check if this drive has the "revert to defaults" bug */ 1235 if (!ata_check_revert_to_defaults(ata_drvp)) 1236 ata_drvp->ad_flags |= AD_NORVRT; 1237 1238 /* Dump the drive info */ 1239 (void) strncpy(buf, aidp->ai_model, sizeof (aidp->ai_model)); 1240 buf[sizeof (aidp->ai_model)-1] = '\0'; 1241 for (i = sizeof (aidp->ai_model) - 2; buf[i] == ' '; i--) 1242 buf[i] = '\0'; 1243 1244 ATAPRT(("?\t%s device at targ %d, lun %d lastlun 0x%x\n", 1245 (ATAPIDRV(ata_drvp) ? "ATAPI":"IDE"), 1246 ata_drvp->ad_targ, ata_drvp->ad_lun, aidp->ai_lastlun)); 1247 1248 ATAPRT(("?\tmodel %s\n", buf)); 1249 1250 if (aidp->ai_majorversion != 0 && aidp->ai_majorversion != 0xffff) { 1251 for (i = 14; i >= 2; i--) { 1252 if (aidp->ai_majorversion & (1 << i)) { 1253 valid_version = i; 1254 break; 1255 } 1256 } 1257 ATAPRT(( 1258 "?\tATA/ATAPI-%d supported, majver 0x%x minver 0x%x\n", 1259 valid_version, 1260 aidp->ai_majorversion, 1261 aidp->ai_minorversion)); 1262 } 1263 1264 if (ata_capability_data) { 1265 1266 ATAPRT(("?\t\tstat %x, err %x\n", 1267 ddi_get8(ata_ctlp->ac_iohandle2, 1268 ata_ctlp->ac_altstatus), 1269 ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_error))); 1270 1271 ATAPRT(("?\t\tcfg 0x%x, cap 0x%x\n", 1272 aidp->ai_config, 1273 aidp->ai_cap)); 1274 1275 /* 1276 * Be aware that ATA-6 and later drives may not provide valid 1277 * geometry information and other obsoleted info. 1278 * Select what is printed based on supported ATA model (skip 1279 * anything below ATA/ATAPI-3) 1280 */ 1281 1282 if (valid_version == 0 || aidp->ai_majorversion < 1283 ATAC_MAJVER_6) { 1284 /* 1285 * Supported version less then ATA-6 1286 */ 1287 ATAPRT(("?\t\tcyl %d, hd %d, sec/trk %d\n", 1288 aidp->ai_fixcyls, 1289 aidp->ai_heads, 1290 aidp->ai_sectors)); 1291 } 1292 ATAPRT(("?\t\tmult1 0x%x, mult2 0x%x\n", 1293 aidp->ai_mult1, 1294 aidp->ai_mult2)); 1295 if (valid_version && aidp->ai_majorversion < ATAC_MAJVER_4) { 1296 ATAPRT(( 1297 "?\t\tpiomode 0x%x, dmamode 0x%x, advpiomode 0x%x\n", 1298 aidp->ai_piomode, 1299 aidp->ai_dmamode, 1300 aidp->ai_advpiomode)); 1301 } else { 1302 ATAPRT(("?\t\tadvpiomode 0x%x\n", 1303 aidp->ai_advpiomode)); 1304 } 1305 ATAPRT(("?\t\tminpio %d, minpioflow %d\n", 1306 aidp->ai_minpio, 1307 aidp->ai_minpioflow)); 1308 if (valid_version && aidp->ai_majorversion >= ATAC_MAJVER_4 && 1309 (aidp->ai_validinfo & ATAC_VALIDINFO_83)) { 1310 ATAPRT(("?\t\tdwdma 0x%x, ultradma 0x%x\n", 1311 aidp->ai_dworddma, 1312 aidp->ai_ultradma)); 1313 } else { 1314 ATAPRT(("?\t\tdwdma 0x%x\n", 1315 aidp->ai_dworddma)); 1316 } 1317 } 1318 1319 if (ATAPIDRV(ata_drvp)) { 1320 if (!atapi_init_drive(ata_drvp)) 1321 goto errout; 1322 } else { 1323 if (!ata_disk_init_drive(ata_drvp)) 1324 goto errout; 1325 } 1326 1327 /* 1328 * store pointer in controller struct 1329 */ 1330 CTL2DRV(ata_ctlp, targ, lun) = ata_drvp; 1331 1332 /* 1333 * lock the drive's current settings in case I have to 1334 * reset the drive due to some sort of error 1335 */ 1336 (void) ata_set_feature(ata_ctlp, ata_drvp, 0x66, 0); 1337 1338 return (ata_drvp); 1339 1340 errout: 1341 ata_uninit_drive(ata_drvp); 1342 return (NULL); 1343 } 1344 1345 /* destroy a drive */ 1346 1347 static void 1348 ata_uninit_drive( 1349 ata_drv_t *ata_drvp) 1350 { 1351 #if 0 1352 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 1353 #endif 1354 1355 ADBG_TRACE(("ata_uninit_drive entered\n")); 1356 1357 #if 0 1358 /* 1359 * DON'T DO THIS. disabling interrupts floats the IRQ line 1360 * which generates spurious interrupts 1361 */ 1362 1363 /* 1364 * Select the correct drive 1365 */ 1366 ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd, 1367 ata_drvp->ad_drive_bits); 1368 ATA_DELAY_400NSEC(ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2); 1369 1370 /* 1371 * Disable interrupts from the drive 1372 */ 1373 ddi_put8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_devctl, 1374 (ATDC_D3 | ATDC_NIEN)); 1375 #endif 1376 1377 /* interface specific clean-ups */ 1378 1379 if (ata_drvp->ad_flags & AD_ATAPI) 1380 atapi_uninit_drive(ata_drvp); 1381 else if (ata_drvp->ad_flags & AD_DISK) 1382 ata_disk_uninit_drive(ata_drvp); 1383 1384 /* free drive struct */ 1385 1386 kmem_free(ata_drvp, sizeof (ata_drv_t)); 1387 } 1388 1389 1390 /* 1391 * ata_drive_type() 1392 * 1393 * The timeout values and exact sequence of checking is critical 1394 * especially for atapi device detection, and should not be changed lightly. 1395 * 1396 */ 1397 static int 1398 ata_drive_type( 1399 uchar_t drvhd, 1400 ddi_acc_handle_t io_hdl1, 1401 caddr_t ioaddr1, 1402 ddi_acc_handle_t io_hdl2, 1403 caddr_t ioaddr2, 1404 struct ata_id *ata_id_bufp) 1405 { 1406 uchar_t status; 1407 1408 ADBG_TRACE(("ata_drive_type entered\n")); 1409 1410 /* 1411 * select the appropriate drive and LUN 1412 */ 1413 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_DRVHD, drvhd); 1414 ATA_DELAY_400NSEC(io_hdl2, ioaddr2); 1415 1416 /* 1417 * make certain the drive is selected, and wait for not busy 1418 */ 1419 (void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY, 0x7f, 0, 0x7f, 0, 1420 5 * 1000000); 1421 1422 status = ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS); 1423 1424 if (status & ATS_BSY) { 1425 ADBG_TRACE(("ata_drive_type BUSY 0x%p 0x%x\n", 1426 ioaddr1, status)); 1427 return (ATA_DEV_NONE); 1428 } 1429 1430 if (ata_disk_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) 1431 return (ATA_DEV_DISK); 1432 1433 /* 1434 * No disk, check for atapi unit. 1435 */ 1436 if (!atapi_signature(io_hdl1, ioaddr1)) { 1437 #ifndef ATA_DISABLE_ATAPI_1_7 1438 /* 1439 * Check for old (but prevalent) atapi 1.7B 1440 * spec device, the only known example is the 1441 * NEC CDR-260 (not 260R which is (mostly) ATAPI 1.2 1442 * compliant). This device has no signature 1443 * and requires conversion from hex to BCD 1444 * for some scsi audio commands. 1445 */ 1446 if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) { 1447 return (ATA_DEV_ATAPI); 1448 } 1449 #endif 1450 return (ATA_DEV_NONE); 1451 } 1452 1453 if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) { 1454 return (ATA_DEV_ATAPI); 1455 } 1456 1457 return (ATA_DEV_NONE); 1458 1459 } 1460 1461 /* 1462 * Wait for a register of a controller to achieve a specific state. 1463 * To return normally, all the bits in the first sub-mask must be ON, 1464 * all the bits in the second sub-mask must be OFF. 1465 * If timeout_usec microseconds pass without the controller achieving 1466 * the desired bit configuration, we return TRUE, else FALSE. 1467 */ 1468 1469 int ata_usec_delay = 10; 1470 1471 int 1472 ata_wait( 1473 ddi_acc_handle_t io_hdl, 1474 caddr_t ioaddr, 1475 uchar_t onbits, 1476 uchar_t offbits, 1477 uint_t timeout_usec) 1478 { 1479 ushort_t val; 1480 1481 do { 1482 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS); 1483 if ((val & onbits) == onbits && (val & offbits) == 0) 1484 return (TRUE); 1485 drv_usecwait(ata_usec_delay); 1486 timeout_usec -= ata_usec_delay; 1487 } while (timeout_usec > 0); 1488 1489 return (FALSE); 1490 } 1491 1492 1493 1494 /* 1495 * 1496 * This is a slightly more complicated version that checks 1497 * for error conditions and bails-out rather than looping 1498 * until the timeout expires 1499 */ 1500 int 1501 ata_wait3( 1502 ddi_acc_handle_t io_hdl, 1503 caddr_t ioaddr, 1504 uchar_t onbits1, 1505 uchar_t offbits1, 1506 uchar_t failure_onbits2, 1507 uchar_t failure_offbits2, 1508 uchar_t failure_onbits3, 1509 uchar_t failure_offbits3, 1510 uint_t timeout_usec) 1511 { 1512 ushort_t val; 1513 1514 do { 1515 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS); 1516 1517 /* 1518 * check for expected condition 1519 */ 1520 if ((val & onbits1) == onbits1 && (val & offbits1) == 0) 1521 return (TRUE); 1522 1523 /* 1524 * check for error conditions 1525 */ 1526 if ((val & failure_onbits2) == failure_onbits2 && 1527 (val & failure_offbits2) == 0) { 1528 return (FALSE); 1529 } 1530 1531 if ((val & failure_onbits3) == failure_onbits3 && 1532 (val & failure_offbits3) == 0) { 1533 return (FALSE); 1534 } 1535 1536 drv_usecwait(ata_usec_delay); 1537 timeout_usec -= ata_usec_delay; 1538 } while (timeout_usec > 0); 1539 1540 return (FALSE); 1541 } 1542 1543 1544 /* 1545 * 1546 * low level routine for ata_disk_id() and atapi_id() 1547 * 1548 */ 1549 1550 int 1551 ata_id_common( 1552 uchar_t id_cmd, 1553 int expect_drdy, 1554 ddi_acc_handle_t io_hdl1, 1555 caddr_t ioaddr1, 1556 ddi_acc_handle_t io_hdl2, 1557 caddr_t ioaddr2, 1558 struct ata_id *aidp) 1559 { 1560 uchar_t status; 1561 1562 ADBG_TRACE(("ata_id_common entered\n")); 1563 1564 bzero(aidp, sizeof (struct ata_id)); 1565 1566 /* 1567 * clear the features register 1568 */ 1569 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_FEATURE, 0); 1570 1571 /* 1572 * enable interrupts from the device 1573 */ 1574 ddi_put8(io_hdl2, (uchar_t *)ioaddr2 + AT_DEVCTL, ATDC_D3); 1575 1576 /* 1577 * issue IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command 1578 */ 1579 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_CMD, id_cmd); 1580 1581 /* wait for the busy bit to settle */ 1582 ATA_DELAY_400NSEC(io_hdl2, ioaddr2); 1583 1584 /* 1585 * According to the ATA specification, some drives may have 1586 * to read the media to complete this command. We need to 1587 * make sure we give them enough time to respond. 1588 */ 1589 1590 (void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY, 1591 ATS_ERR, ATS_BSY, 0x7f, 0, 5 * 1000000); 1592 1593 /* 1594 * read the status byte and clear the pending interrupt 1595 */ 1596 status = ddi_get8(io_hdl2, (uchar_t *)ioaddr1 + AT_STATUS); 1597 1598 /* 1599 * this happens if there's no drive present 1600 */ 1601 if (status == 0xff || status == 0x7f) { 1602 /* invalid status, can't be an ATA or ATAPI device */ 1603 return (FALSE); 1604 } 1605 1606 if (status & ATS_BSY) { 1607 ADBG_ERROR(("ata_id_common: BUSY status 0x%x error 0x%x\n", 1608 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS), 1609 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1610 return (FALSE); 1611 } 1612 1613 if (!(status & ATS_DRQ)) { 1614 if (status & (ATS_ERR | ATS_DF)) { 1615 return (FALSE); 1616 } 1617 /* 1618 * Give the drive another second to assert DRQ. Some older 1619 * drives de-assert BSY before asserting DRQ. 1620 */ 1621 if (!ata_wait(io_hdl2, ioaddr2, ATS_DRQ, ATS_BSY, 1000000)) { 1622 ADBG_WARN(("ata_id_common: !DRQ status 0x%x error 0x%x\n", 1623 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS), 1624 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1625 return (FALSE); 1626 } 1627 } 1628 1629 /* 1630 * transfer the data 1631 */ 1632 ddi_rep_get16(io_hdl1, (ushort_t *)aidp, (ushort_t *)ioaddr1 + AT_DATA, 1633 NBPSCTR >> 1, DDI_DEV_NO_AUTOINCR); 1634 1635 /* wait for the busy bit to settle */ 1636 ATA_DELAY_400NSEC(io_hdl2, ioaddr2); 1637 1638 1639 /* 1640 * Wait for the drive to recognize I've read all the data. 1641 * Some drives have been observed to take as much as 3msec to 1642 * deassert DRQ after reading the data; allow 10 msec just in case. 1643 * 1644 * Note: some non-compliant ATAPI drives (e.g., NEC Multispin 6V, 1645 * CDR-1350A) don't assert DRDY. If we've made it this far we can 1646 * safely ignore the DRDY bit since the ATAPI Packet command 1647 * actually doesn't require it to ever be asserted. 1648 * 1649 */ 1650 if (!ata_wait(io_hdl2, ioaddr2, (uchar_t)(expect_drdy ? ATS_DRDY : 0), 1651 (ATS_BSY | ATS_DRQ), 1000000)) { 1652 ADBG_WARN(("ata_id_common: bad status 0x%x error 0x%x\n", 1653 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS), 1654 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1655 return (FALSE); 1656 } 1657 1658 /* 1659 * Check to see if the command aborted. This happens if 1660 * an IDENTIFY DEVICE command is issued to an ATAPI PACKET device, 1661 * or if an IDENTIFY PACKET DEVICE command is issued to an ATA 1662 * (non-PACKET) device. 1663 */ 1664 if (status & (ATS_DF | ATS_ERR)) { 1665 ADBG_WARN(("ata_id_common: status 0x%x error 0x%x \n", 1666 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS), 1667 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1668 return (FALSE); 1669 } 1670 return (TRUE); 1671 } 1672 1673 1674 /* 1675 * Low level routine to issue a non-data command and busy wait for 1676 * the completion status. 1677 */ 1678 1679 int 1680 ata_command( 1681 ata_ctl_t *ata_ctlp, 1682 ata_drv_t *ata_drvp, 1683 int expect_drdy, 1684 int silent, 1685 uint_t busy_wait, 1686 uchar_t cmd, 1687 uchar_t feature, 1688 uchar_t count, 1689 uchar_t sector, 1690 uchar_t head, 1691 uchar_t cyl_low, 1692 uchar_t cyl_hi) 1693 { 1694 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 1695 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 1696 uchar_t status; 1697 1698 /* select the drive */ 1699 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ata_drvp->ad_drive_bits); 1700 ATA_DELAY_400NSEC(io_hdl2, ata_ctlp->ac_ioaddr2); 1701 1702 /* make certain the drive selected */ 1703 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 1704 (uchar_t)(expect_drdy ? ATS_DRDY : 0), 1705 ATS_BSY, busy_wait)) { 1706 ADBG_ERROR(("ata_command: select failed " 1707 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1708 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1709 expect_drdy, cmd, feature, count, 1710 sector, head, cyl_low, cyl_hi)); 1711 return (FALSE); 1712 } 1713 1714 /* 1715 * set all the regs 1716 */ 1717 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, (head | ata_drvp->ad_drive_bits)); 1718 ddi_put8(io_hdl1, ata_ctlp->ac_sect, sector); 1719 ddi_put8(io_hdl1, ata_ctlp->ac_count, count); 1720 ddi_put8(io_hdl1, ata_ctlp->ac_lcyl, cyl_low); 1721 ddi_put8(io_hdl1, ata_ctlp->ac_hcyl, cyl_hi); 1722 ddi_put8(io_hdl1, ata_ctlp->ac_feature, feature); 1723 1724 /* send the command */ 1725 ddi_put8(io_hdl1, ata_ctlp->ac_cmd, cmd); 1726 1727 /* wait for the busy bit to settle */ 1728 ATA_DELAY_400NSEC(io_hdl2, ata_ctlp->ac_ioaddr2); 1729 1730 /* wait for not busy */ 1731 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, busy_wait)) { 1732 ADBG_ERROR(("ata_command: BSY too long!" 1733 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1734 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1735 expect_drdy, cmd, feature, count, 1736 sector, head, cyl_low, cyl_hi)); 1737 return (FALSE); 1738 } 1739 1740 /* 1741 * wait for DRDY before continuing 1742 */ 1743 (void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2, 1744 ATS_DRDY, ATS_BSY, /* okay */ 1745 ATS_ERR, ATS_BSY, /* cmd failed */ 1746 ATS_DF, ATS_BSY, /* drive failed */ 1747 busy_wait); 1748 1749 /* read status to clear IRQ, and check for error */ 1750 status = ddi_get8(io_hdl1, ata_ctlp->ac_status); 1751 1752 if ((status & (ATS_BSY | ATS_DF | ATS_ERR)) == 0) 1753 return (TRUE); 1754 1755 if (!silent) { 1756 ADBG_ERROR(("ata_command status 0x%x error 0x%x " 1757 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1758 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1759 ddi_get8(io_hdl1, ata_ctlp->ac_status), 1760 ddi_get8(io_hdl1, ata_ctlp->ac_error), 1761 expect_drdy, cmd, feature, count, 1762 sector, head, cyl_low, cyl_hi)); 1763 } 1764 return (FALSE); 1765 } 1766 1767 1768 1769 /* 1770 * 1771 * Issue a SET FEATURES command 1772 * 1773 */ 1774 1775 int 1776 ata_set_feature( 1777 ata_ctl_t *ata_ctlp, 1778 ata_drv_t *ata_drvp, 1779 uchar_t feature, 1780 uchar_t value) 1781 { 1782 int rc; 1783 1784 rc = ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, ata_set_feature_wait, 1785 ATC_SET_FEAT, feature, value, 0, 0, 0, 0); 1786 /* feature, count, sector, head, cyl_low, cyl_hi */ 1787 1788 if (rc) { 1789 return (TRUE); 1790 } 1791 1792 ADBG_ERROR(("?ata_set_feature: (0x%x,0x%x) failed\n", feature, value)); 1793 return (FALSE); 1794 } 1795 1796 1797 1798 /* 1799 * 1800 * Issue a FLUSH CACHE command 1801 * 1802 */ 1803 1804 static int 1805 ata_flush_cache( 1806 ata_ctl_t *ata_ctlp, 1807 ata_drv_t *ata_drvp) 1808 { 1809 /* this command is optional so fail silently */ 1810 return (ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, 1811 ata_flush_cache_wait, 1812 ATC_FLUSH_CACHE, 0, 0, 0, 0, 0, 0)); 1813 } 1814 1815 /* 1816 * ata_setup_ioaddr() 1817 * 1818 * Map the device registers and return the handles. 1819 * 1820 * If this is a ISA-ATA controller then only two handles are 1821 * initialized and returned. 1822 * 1823 * If this is a PCI-IDE controller than a third handle (for the 1824 * PCI-IDE Bus Mastering registers) is initialized and returned. 1825 * 1826 */ 1827 1828 static int 1829 ata_setup_ioaddr( 1830 dev_info_t *dip, 1831 ddi_acc_handle_t *handle1p, 1832 caddr_t *addr1p, 1833 ddi_acc_handle_t *handle2p, 1834 caddr_t *addr2p, 1835 ddi_acc_handle_t *bm_hdlp, 1836 caddr_t *bm_addrp) 1837 { 1838 ddi_device_acc_attr_t dev_attr; 1839 char *bufp; 1840 int rnumber; 1841 int rc; 1842 off_t regsize; 1843 1844 /* 1845 * Make certain the controller is enabled and its regs are map-able 1846 * 1847 */ 1848 rc = ddi_dev_regsize(dip, 0, ®size); 1849 if (rc != DDI_SUCCESS || regsize <= AT_CMD) { 1850 ADBG_INIT(("ata_setup_ioaddr(1): rc %d regsize %lld\n", 1851 rc, (long long)regsize)); 1852 return (FALSE); 1853 } 1854 1855 rc = ddi_dev_regsize(dip, 1, ®size); 1856 if (rc != DDI_SUCCESS || regsize <= AT_ALTSTATUS) { 1857 ADBG_INIT(("ata_setup_ioaddr(2): rc %d regsize %lld\n", 1858 rc, (long long)regsize)); 1859 return (FALSE); 1860 } 1861 1862 /* 1863 * setup the device attribute structure for little-endian, 1864 * strict ordering access. 1865 */ 1866 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1867 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 1868 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1869 1870 *handle1p = NULL; 1871 *handle2p = NULL; 1872 *bm_hdlp = NULL; 1873 1874 /* 1875 * Determine whether this is a ISA, PNP-ISA, or PCI-IDE device 1876 */ 1877 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "pnp-csn")) { 1878 /* it's PNP-ISA, skip over the extra reg tuple */ 1879 rnumber = 1; 1880 goto not_pciide; 1881 } 1882 1883 /* else, it's ISA or PCI-IDE, check further */ 1884 rnumber = 0; 1885 1886 rc = ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_get_parent(dip), 1887 DDI_PROP_DONTPASS, "device_type", &bufp); 1888 if (rc != DDI_PROP_SUCCESS) { 1889 ADBG_ERROR(("ata_setup_ioaddr !device_type\n")); 1890 goto not_pciide; 1891 } 1892 1893 if (strcmp(bufp, "pci-ide") != 0) { 1894 /* 1895 * If it's not a PCI-IDE, there are only two reg tuples 1896 * and the first one contains the I/O base (170 or 1f0) 1897 * rather than the controller instance number. 1898 */ 1899 ADBG_TRACE(("ata_setup_ioaddr !pci-ide\n")); 1900 ddi_prop_free(bufp); 1901 goto not_pciide; 1902 } 1903 ddi_prop_free(bufp); 1904 1905 1906 /* 1907 * Map the correct half of the PCI-IDE Bus Master registers. 1908 * There's a single BAR that maps these registers for both 1909 * controller's in a dual-controller chip and it's upto my 1910 * parent nexus, pciide, to adjust which (based on my instance 1911 * number) half this call maps. 1912 */ 1913 rc = ddi_dev_regsize(dip, 2, ®size); 1914 if (rc != DDI_SUCCESS || regsize < 8) { 1915 ADBG_INIT(("ata_setup_ioaddr(3): rc %d regsize %lld\n", 1916 rc, (long long)regsize)); 1917 goto not_pciide; 1918 } 1919 1920 rc = ddi_regs_map_setup(dip, 2, bm_addrp, 0, 0, &dev_attr, bm_hdlp); 1921 1922 if (rc != DDI_SUCCESS) { 1923 /* map failed, try to use in non-pci-ide mode */ 1924 ADBG_WARN(("ata_setup_ioaddr bus master map failed, rc=0x%x\n", 1925 rc)); 1926 *bm_hdlp = NULL; 1927 } 1928 1929 not_pciide: 1930 /* 1931 * map the lower command block registers 1932 */ 1933 1934 rc = ddi_regs_map_setup(dip, rnumber, addr1p, 0, 0, &dev_attr, 1935 handle1p); 1936 1937 if (rc != DDI_SUCCESS) { 1938 cmn_err(CE_WARN, "ata: reg tuple 0 map failed, rc=0x%x\n", rc); 1939 goto out1; 1940 } 1941 1942 /* 1943 * If the controller is being used in compatibility mode 1944 * via /devices/isa/ata@1,{1f0,1f0}/..., the reg property 1945 * will specify zeros for the I/O ports for the PCI 1946 * instance. 1947 */ 1948 if (*addr1p == 0) { 1949 ADBG_TRACE(("ata_setup_ioaddr ioaddr1 0\n")); 1950 goto out2; 1951 } 1952 1953 /* 1954 * map the upper control block registers 1955 */ 1956 rc = ddi_regs_map_setup(dip, rnumber + 1, addr2p, 0, 0, &dev_attr, 1957 handle2p); 1958 if (rc == DDI_SUCCESS) 1959 return (TRUE); 1960 1961 cmn_err(CE_WARN, "ata: reg tuple 1 map failed, rc=0x%x", rc); 1962 1963 out2: 1964 if (*handle1p != NULL) { 1965 ddi_regs_map_free(handle1p); 1966 *handle1p = NULL; 1967 } 1968 1969 out1: 1970 if (*bm_hdlp != NULL) { 1971 ddi_regs_map_free(bm_hdlp); 1972 *bm_hdlp = NULL; 1973 } 1974 return (FALSE); 1975 1976 } 1977 1978 /* 1979 * 1980 * Currently, the only supported controllers are ones which 1981 * support the SFF-8038 Bus Mastering spec. 1982 * 1983 * Check the parent node's IEEE 1275 class-code property to 1984 * determine if it's an PCI-IDE instance which supports SFF-8038 1985 * Bus Mastering. It's perfectly valid to have a PCI-IDE controller 1986 * that doesn't do Bus Mastering. In that case, my interrupt handler 1987 * only uses the interrupt latch bit in PCI-IDE status register. 1988 * The assumption is that the programming interface byte of the 1989 * class-code property reflects the bus master DMA capability of 1990 * the controller. 1991 * 1992 * Whether the drive support supports the DMA option still needs 1993 * to be checked later. Each individual request also has to be 1994 * checked for alignment and size to decide whether to use the 1995 * DMA transfer mode. 1996 */ 1997 1998 static void 1999 ata_init_pciide( 2000 dev_info_t *dip, 2001 ata_ctl_t *ata_ctlp) 2002 { 2003 uint_t class_code; 2004 uchar_t status; 2005 2006 ata_cntrl_DMA_sel_msg = NULL; 2007 2008 if (ata_ctlp->ac_bmhandle == NULL) { 2009 ata_ctlp->ac_pciide = FALSE; 2010 ata_ctlp->ac_pciide_bm = FALSE; 2011 ata_cntrl_DMA_sel_msg = "cntrl not Bus Master DMA capable"; 2012 return; 2013 } 2014 2015 /* 2016 * check if it's a known bogus PCI-IDE chip 2017 */ 2018 if (ata_check_pciide_blacklist(dip, ATA_BL_BOGUS)) { 2019 ADBG_WARN(("ata_setup_ioaddr pci-ide blacklist\n")); 2020 ata_ctlp->ac_pciide = FALSE; 2021 ata_ctlp->ac_pciide_bm = FALSE; 2022 ata_cntrl_DMA_sel_msg = "cntrl blacklisted"; 2023 return; 2024 } 2025 ata_ctlp->ac_pciide = TRUE; 2026 2027 if (ata_check_pciide_blacklist(dip, ATA_BL_BMSTATREG_PIO_BROKEN)) { 2028 ata_ctlp->ac_flags |= AC_BMSTATREG_PIO_BROKEN; 2029 } 2030 2031 /* 2032 * check for a PCI-IDE chip with a broken DMA engine 2033 */ 2034 if (ata_check_pciide_blacklist(dip, ATA_BL_NODMA)) { 2035 ata_ctlp->ac_pciide_bm = FALSE; 2036 ata_cntrl_DMA_sel_msg = 2037 "cntrl blacklisted/DMA engine broken"; 2038 return; 2039 } 2040 2041 /* 2042 * Check the Programming Interface register to determine 2043 * if this device supports PCI-IDE Bus Mastering. Some PCI-IDE 2044 * devices don't support Bus Mastering or DMA. 2045 * Since we are dealing with pre-qualified pci-ide controller, 2046 * check programming interface byte only. 2047 */ 2048 2049 class_code = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 2050 DDI_PROP_DONTPASS, "class-code", 0); 2051 if ((class_code & PCIIDE_BM_CAP_MASK) != PCIIDE_BM_CAP_MASK) { 2052 ata_ctlp->ac_pciide_bm = FALSE; 2053 ata_cntrl_DMA_sel_msg = 2054 "cntrl not Bus Master DMA capable"; 2055 return; 2056 } 2057 2058 /* 2059 * Avoid doing DMA on "simplex" chips which share hardware 2060 * between channels 2061 */ 2062 status = ddi_get8(ata_ctlp->ac_bmhandle, 2063 (uchar_t *)ata_ctlp->ac_bmaddr + PCIIDE_BMISX_REG); 2064 /* 2065 * Some motherboards have CSB5's that are wired "to emulate CSB4 mode". 2066 * In such a mode, the simplex bit is asserted, but in fact testing 2067 * on such a motherboard has shown that the devices are not simplex 2068 * -- DMA can be used on both channels concurrently with no special 2069 * considerations. For chips like this, we have the ATA_BL_NO_SIMPLEX 2070 * flag set to indicate that the value of the simplex bit can be 2071 * ignored. 2072 */ 2073 2074 if (status & PCIIDE_BMISX_SIMPLEX) { 2075 if (ata_check_pciide_blacklist(dip, ATA_BL_NO_SIMPLEX)) { 2076 cmn_err(CE_WARN, "Ignoring false simplex bit \n"); 2077 2078 } else { 2079 2080 int simplex_dma_channel, *rp, proplen, channel; 2081 int dma_on = FALSE; 2082 2083 /* 2084 * By default,use DMA on channel 0 and PIO on channel 2085 * 1. This can be switched by setting 2086 * ata-simplex-dma-channel to: 2087 * 0 DMA on channel 0 (default without this 2088 * property) 2089 * 1 DMA on channel 1 2090 * any other value: DMA off on both channels. 2091 */ 2092 simplex_dma_channel = ata_prop_lookup_int(DDI_DEV_T_ANY, 2093 ata_ctlp->ac_dip, 0, "ata-simplex-dma-channel", 0); 2094 2095 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 2096 ata_ctlp->ac_dip, DDI_PROP_DONTPASS, "reg", &rp, 2097 (uint_t *)&proplen) == DDI_PROP_SUCCESS) { 2098 2099 channel = *rp; 2100 ddi_prop_free(rp); 2101 2102 if (simplex_dma_channel == channel) { 2103 cmn_err(CE_NOTE, "?ata: simplex " 2104 "controller. DMA on channel" 2105 " %d PIO on channel %d\n", 2106 channel, channel ? 0:1); 2107 dma_on = TRUE; 2108 } else { 2109 ata_cntrl_DMA_sel_msg = 2110 "simplex controller"; 2111 } 2112 } 2113 2114 if (dma_on == FALSE) { 2115 ata_ctlp->ac_pciide_bm = FALSE; 2116 2117 return; 2118 } 2119 } 2120 } 2121 2122 /* 2123 * It's a compatible PCI-IDE Bus Mastering controller, 2124 * allocate and map the DMA Scatter/Gather list (PRDE table). 2125 */ 2126 if (ata_pciide_alloc(dip, ata_ctlp)) 2127 ata_ctlp->ac_pciide_bm = TRUE; 2128 else { 2129 ata_ctlp->ac_pciide_bm = FALSE; 2130 ata_cntrl_DMA_sel_msg = "unable to init DMA S/G list"; 2131 } 2132 } 2133 2134 /* 2135 * 2136 * Determine whether to enable DMA support for this drive. 2137 * The controller and the drive both have to support DMA. 2138 * The controller's capabilities were already checked in 2139 * ata_init_pciide(), now just check the drive's capabilities. 2140 * 2141 */ 2142 2143 static int 2144 ata_init_drive_pcidma( 2145 ata_ctl_t *ata_ctlp, 2146 ata_drv_t *ata_drvp, 2147 dev_info_t *tdip) 2148 { 2149 boolean_t dma; 2150 boolean_t cd_dma; 2151 boolean_t disk_dma; 2152 boolean_t atapi_dma; 2153 int ata_options; 2154 2155 ata_dev_DMA_sel_msg = NULL; 2156 2157 if (ata_ctlp->ac_pciide_bm != TRUE) { 2158 ata_dev_DMA_sel_msg = 2159 "controller is not Bus Master capable"; 2160 2161 return (ATA_DMA_OFF); 2162 } 2163 2164 ata_options = ddi_prop_get_int(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 2165 0, "ata-options", 0); 2166 2167 if (!(ata_options & ATA_OPTIONS_DMA)) { 2168 /* 2169 * Either the ata-options property was not found or 2170 * DMA is not enabled by this property 2171 */ 2172 ata_dev_DMA_sel_msg = 2173 "disabled by \"ata-options\" property"; 2174 2175 return (ATA_DMA_OFF); 2176 } 2177 2178 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_NODMA)) { 2179 ata_dev_DMA_sel_msg = "device not DMA capable; blacklisted"; 2180 2181 return (ATA_DMA_OFF); 2182 } 2183 2184 /* 2185 * DMA mode is mandatory on ATA-3 (or newer) drives but is 2186 * optional on ATA-2 (or older) drives. 2187 * 2188 * On ATA-2 drives the ai_majorversion word will probably 2189 * be 0xffff or 0x0000, check the (now obsolete) DMA bit in 2190 * the capabilities word instead. The order of these tests 2191 * is important since an ATA-3 drive doesn't have to set 2192 * the DMA bit in the capabilities word. 2193 * 2194 */ 2195 2196 if (!((ata_drvp->ad_id.ai_majorversion & 0x8000) == 0 && 2197 ata_drvp->ad_id.ai_majorversion >= (1 << 2)) && 2198 !(ata_drvp->ad_id.ai_cap & ATAC_DMA_SUPPORT)) { 2199 ata_dev_DMA_sel_msg = "device not DMA capable"; 2200 2201 return (ATA_DMA_OFF); 2202 } 2203 2204 dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2205 0, "ata-dma-enabled", TRUE); 2206 disk_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2207 0, "ata-disk-dma-enabled", TRUE); 2208 cd_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2209 0, "atapi-cd-dma-enabled", FALSE); 2210 atapi_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2211 0, "atapi-other-dma-enabled", TRUE); 2212 2213 if (dma == FALSE) { 2214 cmn_err(CE_CONT, "?ata_init_drive_pcidma: " 2215 "DMA disabled by \"ata-dma-enabled\" property"); 2216 ata_dev_DMA_sel_msg = "disabled by prop ata-dma-enabled"; 2217 2218 return (ATA_DMA_OFF); 2219 } 2220 2221 if (IS_CDROM(ata_drvp) == TRUE) { 2222 if (cd_dma == FALSE) { 2223 ata_dev_DMA_sel_msg = 2224 "disabled. Control with \"atapi-cd-dma-enabled\"" 2225 " property"; 2226 2227 return (ATA_DMA_OFF); 2228 } 2229 2230 } else if (ATAPIDRV(ata_drvp) == FALSE) { 2231 if (disk_dma == FALSE) { 2232 ata_dev_DMA_sel_msg = 2233 "disabled by \"ata-disk-dma-enabled\" property"; 2234 2235 return (ATA_DMA_OFF); 2236 } 2237 2238 } else if (atapi_dma == FALSE) { 2239 ata_dev_DMA_sel_msg = 2240 "disabled by \"atapi-other-dma-enabled\" property"; 2241 2242 return (ATA_DMA_OFF); 2243 } 2244 2245 return (ATA_DMA_ON); 2246 } 2247 2248 2249 2250 /* 2251 * this compare routine squeezes out extra blanks and 2252 * returns TRUE if p1 matches the leftmost substring of p2 2253 */ 2254 2255 static int 2256 ata_strncmp( 2257 char *p1, 2258 char *p2, 2259 int cnt) 2260 { 2261 2262 for (;;) { 2263 /* 2264 * skip over any extra blanks in both strings 2265 */ 2266 while (*p1 != '\0' && *p1 == ' ') 2267 p1++; 2268 2269 while (cnt != 0 && *p2 == ' ') { 2270 p2++; 2271 cnt--; 2272 } 2273 2274 /* 2275 * compare the two strings 2276 */ 2277 2278 if (cnt == 0 || *p1 != *p2) 2279 break; 2280 2281 while (cnt > 0 && *p1 == *p2) { 2282 p1++; 2283 p2++; 2284 cnt--; 2285 } 2286 2287 } 2288 2289 /* return TRUE if both strings ended at same point */ 2290 return ((*p1 == '\0') ? TRUE : FALSE); 2291 } 2292 2293 /* 2294 * Per PSARC/1997/281 create variant="atapi" property (if necessary) 2295 * on the target's dev_info node. Currently, the sd target driver 2296 * is the only driver which refers to this property. 2297 * 2298 * If the flag ata_id_debug is set also create the 2299 * the "ata" or "atapi" property on the target's dev_info node 2300 * 2301 */ 2302 2303 int 2304 ata_prop_create( 2305 dev_info_t *tgt_dip, 2306 ata_drv_t *ata_drvp, 2307 char *name) 2308 { 2309 int rc; 2310 2311 ADBG_TRACE(("ata_prop_create 0x%p 0x%p %s\n", tgt_dip, ata_drvp, name)); 2312 2313 if (strcmp("atapi", name) == 0) { 2314 rc = ndi_prop_update_string(DDI_DEV_T_NONE, tgt_dip, 2315 "variant", name); 2316 if (rc != DDI_PROP_SUCCESS) 2317 return (FALSE); 2318 } 2319 2320 if (!ata_id_debug) 2321 return (TRUE); 2322 2323 rc = ndi_prop_update_byte_array(DDI_DEV_T_NONE, tgt_dip, name, 2324 (uchar_t *)&ata_drvp->ad_id, sizeof (ata_drvp->ad_id)); 2325 if (rc != DDI_PROP_SUCCESS) { 2326 ADBG_ERROR(("ata_prop_create failed, rc=%d\n", rc)); 2327 } 2328 return (TRUE); 2329 } 2330 2331 2332 /* *********************************************************************** */ 2333 /* *********************************************************************** */ 2334 /* *********************************************************************** */ 2335 2336 /* 2337 * This state machine doesn't implement the ATAPI Optional Overlap 2338 * feature. You need that feature to efficiently support ATAPI 2339 * tape drives. See the 1394-ATA Tailgate spec (D97107), Figure 24, 2340 * for an example of how to add the necessary additional NextActions 2341 * and NextStates to this FSM and the atapi_fsm, in order to support 2342 * the Overlap Feature. 2343 */ 2344 2345 2346 uchar_t ata_ctlr_fsm_NextAction[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = { 2347 /* --------------------- next action --------------------- | - current - */ 2348 /* start0 --- start1 ---- intr ------ fini --- reset --- */ 2349 { AC_START, AC_START, AC_NADA, AC_NADA, AC_RESET_I }, /* idle */ 2350 { AC_BUSY, AC_BUSY, AC_INTR, AC_FINI, AC_RESET_A }, /* active0 */ 2351 { AC_BUSY, AC_BUSY, AC_INTR, AC_FINI, AC_RESET_A }, /* active1 */ 2352 }; 2353 2354 uchar_t ata_ctlr_fsm_NextState[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = { 2355 2356 /* --------------------- next state --------------------- | - current - */ 2357 /* start0 --- start1 ---- intr ------ fini --- reset --- */ 2358 { AS_ACTIVE0, AS_ACTIVE1, AS_IDLE, AS_IDLE, AS_IDLE }, /* idle */ 2359 { AS_ACTIVE0, AS_ACTIVE0, AS_ACTIVE0, AS_IDLE, AS_ACTIVE0 }, /* active0 */ 2360 { AS_ACTIVE1, AS_ACTIVE1, AS_ACTIVE1, AS_IDLE, AS_ACTIVE1 }, /* active1 */ 2361 }; 2362 2363 2364 static int 2365 ata_ctlr_fsm( 2366 uchar_t fsm_func, 2367 ata_ctl_t *ata_ctlp, 2368 ata_drv_t *ata_drvp, 2369 ata_pkt_t *ata_pktp, 2370 int *DoneFlgp) 2371 { 2372 uchar_t action; 2373 uchar_t current_state; 2374 uchar_t next_state; 2375 int rc; 2376 2377 current_state = ata_ctlp->ac_state; 2378 action = ata_ctlr_fsm_NextAction[current_state][fsm_func]; 2379 next_state = ata_ctlr_fsm_NextState[current_state][fsm_func]; 2380 2381 /* 2382 * Set the controller's new state 2383 */ 2384 ata_ctlp->ac_state = next_state; 2385 switch (action) { 2386 2387 case AC_BUSY: 2388 return (ATA_FSM_RC_BUSY); 2389 2390 case AC_NADA: 2391 return (ATA_FSM_RC_OKAY); 2392 2393 case AC_START: 2394 ASSERT(ata_ctlp->ac_active_pktp == NULL); 2395 ASSERT(ata_ctlp->ac_active_drvp == NULL); 2396 2397 ata_ctlp->ac_active_pktp = ata_pktp; 2398 ata_ctlp->ac_active_drvp = ata_drvp; 2399 2400 rc = (*ata_pktp->ap_start)(ata_ctlp, ata_drvp, ata_pktp); 2401 2402 if (rc == ATA_FSM_RC_BUSY) { 2403 /* the request didn't start, GHD will requeue it */ 2404 ata_ctlp->ac_state = AS_IDLE; 2405 ata_ctlp->ac_active_pktp = NULL; 2406 ata_ctlp->ac_active_drvp = NULL; 2407 } 2408 return (rc); 2409 2410 case AC_INTR: 2411 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2412 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2413 2414 ata_drvp = ata_ctlp->ac_active_drvp; 2415 ata_pktp = ata_ctlp->ac_active_pktp; 2416 return ((*ata_pktp->ap_intr)(ata_ctlp, ata_drvp, ata_pktp)); 2417 2418 case AC_RESET_A: /* Reset, controller active */ 2419 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2420 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2421 2422 /* clean up the active request */ 2423 ata_pktp = ata_ctlp->ac_active_pktp; 2424 ata_pktp->ap_flags |= AP_DEV_RESET | AP_BUS_RESET; 2425 2426 /* halt the DMA engine */ 2427 if (ata_pktp->ap_pciide_dma) { 2428 ata_pciide_dma_stop(ata_ctlp); 2429 (void) ata_pciide_status_clear(ata_ctlp); 2430 } 2431 2432 /* Do a Software Reset to unwedge the bus */ 2433 if (!ata_software_reset(ata_ctlp)) { 2434 return (ATA_FSM_RC_BUSY); 2435 } 2436 2437 /* Then send a DEVICE RESET cmd to each ATAPI device */ 2438 atapi_fsm_reset(ata_ctlp); 2439 return (ATA_FSM_RC_FINI); 2440 2441 case AC_RESET_I: /* Reset, controller idle */ 2442 /* Do a Software Reset to unwedge the bus */ 2443 if (!ata_software_reset(ata_ctlp)) { 2444 return (ATA_FSM_RC_BUSY); 2445 } 2446 2447 /* Then send a DEVICE RESET cmd to each ATAPI device */ 2448 atapi_fsm_reset(ata_ctlp); 2449 return (ATA_FSM_RC_OKAY); 2450 2451 case AC_FINI: 2452 break; 2453 } 2454 2455 /* 2456 * AC_FINI, check ARQ needs to be started or finished 2457 */ 2458 2459 ASSERT(action == AC_FINI); 2460 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2461 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2462 2463 /* 2464 * The active request is done now. 2465 * Disconnect the request from the controller and 2466 * add it to the done queue. 2467 */ 2468 ata_drvp = ata_ctlp->ac_active_drvp; 2469 ata_pktp = ata_ctlp->ac_active_pktp; 2470 2471 /* 2472 * If ARQ pkt is done, get ptr to original pkt and wrap it up. 2473 */ 2474 if (ata_pktp == ata_ctlp->ac_arq_pktp) { 2475 ata_pkt_t *arq_pktp; 2476 2477 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ done\n", ata_ctlp)); 2478 2479 arq_pktp = ata_pktp; 2480 ata_pktp = ata_ctlp->ac_fault_pktp; 2481 ata_ctlp->ac_fault_pktp = NULL; 2482 if (arq_pktp->ap_flags & (AP_ERROR | AP_BUS_RESET)) 2483 ata_pktp->ap_flags |= AP_ARQ_ERROR; 2484 else 2485 ata_pktp->ap_flags |= AP_ARQ_OKAY; 2486 goto all_done; 2487 } 2488 2489 2490 #define AP_ARQ_NEEDED (AP_ARQ_ON_ERROR | AP_GOT_STATUS | AP_ERROR) 2491 2492 /* 2493 * Start ARQ pkt if necessary 2494 */ 2495 if ((ata_pktp->ap_flags & AP_ARQ_NEEDED) == AP_ARQ_NEEDED && 2496 (ata_pktp->ap_status & ATS_ERR)) { 2497 2498 /* set controller state back to active */ 2499 ata_ctlp->ac_state = current_state; 2500 2501 /* try to start the ARQ pkt */ 2502 rc = ata_start_arq(ata_ctlp, ata_drvp, ata_pktp); 2503 2504 if (rc == ATA_FSM_RC_BUSY) { 2505 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ BUSY\n", ata_ctlp)); 2506 /* let the target driver handle the problem */ 2507 ata_ctlp->ac_state = AS_IDLE; 2508 ata_ctlp->ac_active_pktp = NULL; 2509 ata_ctlp->ac_active_drvp = NULL; 2510 ata_ctlp->ac_fault_pktp = NULL; 2511 goto all_done; 2512 } 2513 2514 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ started\n", ata_ctlp)); 2515 return (rc); 2516 } 2517 2518 /* 2519 * Normal completion, no error status, and not an ARQ pkt, 2520 * just fall through. 2521 */ 2522 2523 all_done: 2524 2525 /* 2526 * wrap everything up and tie a ribbon around it 2527 */ 2528 ata_ctlp->ac_active_pktp = NULL; 2529 ata_ctlp->ac_active_drvp = NULL; 2530 if (APKT2GCMD(ata_pktp) != (gcmd_t *)0) { 2531 ghd_complete(&ata_ctlp->ac_ccc, APKT2GCMD(ata_pktp)); 2532 if (DoneFlgp) 2533 *DoneFlgp = TRUE; 2534 } 2535 2536 return (ATA_FSM_RC_OKAY); 2537 } 2538 2539 2540 static int 2541 ata_start_arq( 2542 ata_ctl_t *ata_ctlp, 2543 ata_drv_t *ata_drvp, 2544 ata_pkt_t *ata_pktp) 2545 { 2546 ata_pkt_t *arq_pktp; 2547 int bytes; 2548 uint_t senselen; 2549 2550 ADBG_ARQ(("ata_start_arq 0x%p ARQ needed\n", ata_ctlp)); 2551 2552 /* 2553 * Determine just the size of the Request Sense Data buffer within 2554 * the scsi_arq_status structure. 2555 */ 2556 #define SIZEOF_ARQ_HEADER (sizeof (struct scsi_arq_status) \ 2557 - sizeof (struct scsi_extended_sense)) 2558 senselen = ata_pktp->ap_statuslen - SIZEOF_ARQ_HEADER; 2559 ASSERT(senselen > 0); 2560 2561 2562 /* save ptr to original pkt */ 2563 ata_ctlp->ac_fault_pktp = ata_pktp; 2564 2565 /* switch the controller's active pkt to the ARQ pkt */ 2566 arq_pktp = ata_ctlp->ac_arq_pktp; 2567 ata_ctlp->ac_active_pktp = arq_pktp; 2568 2569 /* finish initializing the ARQ CDB */ 2570 ata_ctlp->ac_arq_cdb[1] = ata_drvp->ad_lun << 4; 2571 ata_ctlp->ac_arq_cdb[4] = senselen; 2572 2573 /* finish initializing the ARQ pkt */ 2574 arq_pktp->ap_v_addr = (caddr_t)&ata_pktp->ap_scbp->sts_sensedata; 2575 2576 arq_pktp->ap_resid = senselen; 2577 arq_pktp->ap_flags = AP_ATAPI | AP_READ; 2578 arq_pktp->ap_cdb_pad = 2579 ((unsigned)(ata_drvp->ad_cdb_len - arq_pktp->ap_cdb_len)) >> 1; 2580 2581 bytes = min(senselen, ATAPI_MAX_BYTES_PER_DRQ); 2582 arq_pktp->ap_hicyl = (uchar_t)(bytes >> 8); 2583 arq_pktp->ap_lwcyl = (uchar_t)bytes; 2584 2585 /* 2586 * This packet is shared by all drives on this controller 2587 * therefore we need to init the drive number on every ARQ. 2588 */ 2589 arq_pktp->ap_hd = ata_drvp->ad_drive_bits; 2590 2591 /* start it up */ 2592 return ((*arq_pktp->ap_start)(ata_ctlp, ata_drvp, arq_pktp)); 2593 } 2594 2595 /* 2596 * 2597 * reset the bus 2598 * 2599 */ 2600 2601 static int 2602 ata_reset_bus( 2603 ata_ctl_t *ata_ctlp) 2604 { 2605 int watchdog; 2606 uchar_t drive; 2607 int rc = FALSE; 2608 uchar_t fsm_func; 2609 int DoneFlg = FALSE; 2610 2611 /* 2612 * Do a Software Reset to unwedge the bus, and send 2613 * ATAPI DEVICE RESET to each ATAPI drive. 2614 */ 2615 fsm_func = ATA_FSM_RESET; 2616 for (watchdog = ata_reset_bus_watchdog; watchdog > 0; watchdog--) { 2617 switch (ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL, 2618 &DoneFlg)) { 2619 case ATA_FSM_RC_OKAY: 2620 rc = TRUE; 2621 goto fsm_done; 2622 2623 case ATA_FSM_RC_BUSY: 2624 return (FALSE); 2625 2626 case ATA_FSM_RC_INTR: 2627 fsm_func = ATA_FSM_INTR; 2628 rc = TRUE; 2629 continue; 2630 2631 case ATA_FSM_RC_FINI: 2632 fsm_func = ATA_FSM_FINI; 2633 rc = TRUE; 2634 continue; 2635 } 2636 } 2637 ADBG_WARN(("ata_reset_bus: watchdog\n")); 2638 2639 fsm_done: 2640 2641 /* 2642 * Reinitialize the ATA drives 2643 */ 2644 for (drive = 0; drive < ATA_MAXTARG; drive++) { 2645 ata_drv_t *ata_drvp; 2646 2647 if ((ata_drvp = CTL2DRV(ata_ctlp, drive, 0)) == NULL) 2648 continue; 2649 2650 if (ATAPIDRV(ata_drvp)) 2651 continue; 2652 2653 /* 2654 * Reprogram the Read/Write Multiple block factor 2655 * and current geometry into the drive. 2656 */ 2657 if (!ata_disk_setup_parms(ata_ctlp, ata_drvp)) 2658 rc = FALSE; 2659 } 2660 2661 /* If DoneFlg is TRUE, it means that ghd_complete() function */ 2662 /* has been already called. In this case ignore any errors and */ 2663 /* return TRUE to the caller, otherwise return the value of rc */ 2664 /* to the caller */ 2665 if (DoneFlg) 2666 return (TRUE); 2667 else 2668 return (rc); 2669 } 2670 2671 2672 /* 2673 * 2674 * Low level routine to toggle the Software Reset bit 2675 * 2676 */ 2677 2678 static int 2679 ata_software_reset( 2680 ata_ctl_t *ata_ctlp) 2681 { 2682 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 2683 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 2684 int time_left; 2685 2686 ADBG_TRACE(("ata_reset_bus entered\n")); 2687 2688 /* disable interrupts and turn the software reset bit on */ 2689 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, (ATDC_D3 | ATDC_SRST)); 2690 2691 /* why 30 milliseconds, the ATA/ATAPI-4 spec says 5 usec. */ 2692 drv_usecwait(30000); 2693 2694 /* turn the software reset bit back off */ 2695 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, ATDC_D3); 2696 2697 /* 2698 * Wait for the controller to assert BUSY status. 2699 * I don't think 300 msecs is correct. The ATA/ATAPI-4 2700 * spec says 400 nsecs, (and 2 msecs if device 2701 * was in sleep mode; but we don't put drives to sleep 2702 * so it probably doesn't matter). 2703 */ 2704 drv_usecwait(300000); 2705 2706 /* 2707 * If drive 0 exists the test for completion is simple 2708 */ 2709 time_left = 31 * 1000000; 2710 if (CTL2DRV(ata_ctlp, 0, 0)) { 2711 goto wait_for_not_busy; 2712 } 2713 2714 ASSERT(CTL2DRV(ata_ctlp, 1, 0) != NULL); 2715 2716 /* 2717 * This must be a single device configuration, with drive 1 2718 * only. This complicates the test for completion because 2719 * issuing the software reset just caused drive 1 to 2720 * deselect. With drive 1 deselected, if I just read the 2721 * status register to test the BSY bit I get garbage, but 2722 * I can't re-select drive 1 until I'm certain the BSY bit 2723 * is de-asserted. Catch-22. 2724 * 2725 * In ATA/ATAPI-4, rev 15, section 9.16.2, it says to handle 2726 * this situation like this: 2727 */ 2728 2729 /* give up if the drive doesn't settle within 31 seconds */ 2730 while (time_left > 0) { 2731 /* 2732 * delay 10msec each time around the loop 2733 */ 2734 drv_usecwait(10000); 2735 time_left -= 10000; 2736 2737 /* 2738 * try to select drive 1 2739 */ 2740 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ATDH_DRIVE1); 2741 2742 ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0x55); 2743 ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0xaa); 2744 if (ddi_get8(io_hdl1, ata_ctlp->ac_sect) != 0xaa) 2745 continue; 2746 2747 ddi_put8(io_hdl1, ata_ctlp->ac_count, 0x55); 2748 ddi_put8(io_hdl1, ata_ctlp->ac_count, 0xaa); 2749 if (ddi_get8(io_hdl1, ata_ctlp->ac_count) != 0xaa) 2750 continue; 2751 2752 goto wait_for_not_busy; 2753 } 2754 return (FALSE); 2755 2756 wait_for_not_busy: 2757 2758 /* 2759 * Now wait upto 31 seconds for BUSY to clear. 2760 */ 2761 (void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, 2762 ATS_ERR, ATS_BSY, ATS_DF, ATS_BSY, time_left); 2763 2764 return (TRUE); 2765 } 2766 2767 /* 2768 * 2769 * DDI interrupt handler 2770 * 2771 */ 2772 2773 static uint_t 2774 ata_intr( 2775 caddr_t arg) 2776 { 2777 ata_ctl_t *ata_ctlp; 2778 int one_shot = 1; 2779 2780 ata_ctlp = (ata_ctl_t *)arg; 2781 2782 return (ghd_intr(&ata_ctlp->ac_ccc, (void *)&one_shot)); 2783 } 2784 2785 2786 /* 2787 * 2788 * GHD ccc_get_status callback 2789 * 2790 */ 2791 2792 static int 2793 ata_get_status( 2794 void *hba_handle, 2795 void *intr_status) 2796 { 2797 ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle; 2798 uchar_t status; 2799 2800 ADBG_TRACE(("ata_get_status entered\n")); 2801 2802 /* 2803 * ignore interrupts before ata_attach completes 2804 */ 2805 if (!(ata_ctlp->ac_flags & AC_ATTACHED)) 2806 return (FALSE); 2807 2808 /* 2809 * can't be interrupt pending if nothing active 2810 */ 2811 switch (ata_ctlp->ac_state) { 2812 case AS_IDLE: 2813 return (FALSE); 2814 case AS_ACTIVE0: 2815 case AS_ACTIVE1: 2816 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2817 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2818 break; 2819 } 2820 2821 /* 2822 * If this is a PCI-IDE controller, check the PCI-IDE controller's 2823 * interrupt status latch. But don't clear it yet. 2824 * 2825 * AC_BMSTATREG_PIO_BROKEN flag is used currently for 2826 * CMD chips with device id 0x646. Since the interrupt bit on 2827 * Bus master IDE register is not usable when in PIO mode, 2828 * this chip is treated as a legacy device for interrupt 2829 * indication. The following code for CMD 2830 * chips may need to be revisited when we enable support for dma. 2831 * 2832 * CHANGE: DMA is not disabled for these devices. BM intr bit is 2833 * checked only if there was DMA used or BM intr is useable on PIO, 2834 * else treat it as before - as legacy device. 2835 */ 2836 2837 if ((ata_ctlp->ac_pciide) && 2838 ((ata_ctlp->ac_pciide_bm != FALSE) && 2839 ((ata_ctlp->ac_active_pktp->ap_pciide_dma == TRUE) || 2840 !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)))) { 2841 2842 if (!ata_pciide_status_pending(ata_ctlp)) 2843 return (FALSE); 2844 } else { 2845 /* 2846 * Interrupts from legacy ATA/IDE controllers are 2847 * edge-triggered but the dumb legacy ATA/IDE controllers 2848 * and drives don't have an interrupt status bit. 2849 * 2850 * Use a one_shot variable to make sure we only return 2851 * one status per interrupt. 2852 */ 2853 if (intr_status != NULL) { 2854 int *one_shot = (int *)intr_status; 2855 2856 if (*one_shot == 1) 2857 *one_shot = 0; 2858 else 2859 return (FALSE); 2860 } 2861 } 2862 2863 /* check if device is still busy */ 2864 2865 status = ddi_get8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_altstatus); 2866 if (status & ATS_BSY) 2867 return (FALSE); 2868 return (TRUE); 2869 } 2870 2871 2872 /* 2873 * 2874 * get the current status and clear the IRQ 2875 * 2876 */ 2877 2878 int 2879 ata_get_status_clear_intr( 2880 ata_ctl_t *ata_ctlp, 2881 ata_pkt_t *ata_pktp) 2882 { 2883 uchar_t status; 2884 2885 /* 2886 * Here's where we clear the PCI-IDE interrupt latch. If this 2887 * request used DMA mode then we also have to check and clear 2888 * the DMA error latch at the same time. 2889 */ 2890 2891 if (ata_pktp->ap_pciide_dma) { 2892 if (ata_pciide_status_dmacheck_clear(ata_ctlp)) 2893 ata_pktp->ap_flags |= AP_ERROR | AP_TRAN_ERROR; 2894 } else if ((ata_ctlp->ac_pciide) && 2895 !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)) { 2896 /* 2897 * Some requests don't use DMA mode and therefore won't 2898 * set the DMA error latch, but we still have to clear 2899 * the interrupt latch. 2900 * Controllers with broken BM intr in PIO mode do not go 2901 * through this path. 2902 */ 2903 (void) ata_pciide_status_clear(ata_ctlp); 2904 } 2905 2906 /* 2907 * this clears the drive's interrupt 2908 */ 2909 status = ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_status); 2910 ADBG_TRACE(("ata_get_status_clear_intr: 0x%x\n", status)); 2911 return (status); 2912 } 2913 2914 2915 2916 /* 2917 * 2918 * GHD interrupt handler 2919 * 2920 */ 2921 2922 /* ARGSUSED */ 2923 static void 2924 ata_process_intr( 2925 void *hba_handle, 2926 void *intr_status) 2927 { 2928 ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle; 2929 int watchdog; 2930 uchar_t fsm_func; 2931 int rc; 2932 2933 ADBG_TRACE(("ata_process_intr entered\n")); 2934 2935 /* 2936 * process the ATA or ATAPI interrupt 2937 */ 2938 2939 fsm_func = ATA_FSM_INTR; 2940 for (watchdog = ata_process_intr_watchdog; watchdog > 0; watchdog--) { 2941 rc = ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL, NULL); 2942 2943 switch (rc) { 2944 case ATA_FSM_RC_OKAY: 2945 return; 2946 2947 case ATA_FSM_RC_BUSY: /* wait for the next interrupt */ 2948 return; 2949 2950 case ATA_FSM_RC_INTR: /* re-invoke the FSM */ 2951 fsm_func = ATA_FSM_INTR; 2952 break; 2953 2954 case ATA_FSM_RC_FINI: /* move a request to done Q */ 2955 fsm_func = ATA_FSM_FINI; 2956 break; 2957 } 2958 } 2959 ADBG_WARN(("ata_process_intr: watchdog\n")); 2960 } 2961 2962 2963 2964 /* 2965 * 2966 * GHD ccc_hba_start callback 2967 * 2968 */ 2969 2970 static int 2971 ata_hba_start( 2972 void *hba_handle, 2973 gcmd_t *gcmdp) 2974 { 2975 ata_ctl_t *ata_ctlp; 2976 ata_drv_t *ata_drvp; 2977 ata_pkt_t *ata_pktp; 2978 uchar_t fsm_func; 2979 int request_started; 2980 int watchdog; 2981 2982 ADBG_TRACE(("ata_hba_start entered\n")); 2983 2984 ata_ctlp = (ata_ctl_t *)hba_handle; 2985 2986 if (ata_ctlp->ac_active_drvp != NULL) { 2987 ADBG_WARN(("ata_hba_start drvp not null\n")); 2988 return (FALSE); 2989 } 2990 if (ata_ctlp->ac_active_pktp != NULL) { 2991 ADBG_WARN(("ata_hba_start pktp not null\n")); 2992 return (FALSE); 2993 } 2994 2995 ata_pktp = GCMD2APKT(gcmdp); 2996 ata_drvp = GCMD2DRV(gcmdp); 2997 2998 /* 2999 * which drive? 3000 */ 3001 if (ata_drvp->ad_targ == 0) 3002 fsm_func = ATA_FSM_START0; 3003 else 3004 fsm_func = ATA_FSM_START1; 3005 3006 /* 3007 * start the request 3008 */ 3009 request_started = FALSE; 3010 for (watchdog = ata_hba_start_watchdog; watchdog > 0; watchdog--) { 3011 switch (ata_ctlr_fsm(fsm_func, ata_ctlp, ata_drvp, ata_pktp, 3012 NULL)) { 3013 case ATA_FSM_RC_OKAY: 3014 request_started = TRUE; 3015 goto fsm_done; 3016 3017 case ATA_FSM_RC_BUSY: 3018 /* if first time, tell GHD to requeue the request */ 3019 goto fsm_done; 3020 3021 case ATA_FSM_RC_INTR: 3022 /* 3023 * The start function polled for the next 3024 * bus phase, now fake an interrupt to process 3025 * the next action. 3026 */ 3027 request_started = TRUE; 3028 fsm_func = ATA_FSM_INTR; 3029 ata_drvp = NULL; 3030 ata_pktp = NULL; 3031 break; 3032 3033 case ATA_FSM_RC_FINI: /* move request to the done queue */ 3034 request_started = TRUE; 3035 fsm_func = ATA_FSM_FINI; 3036 ata_drvp = NULL; 3037 ata_pktp = NULL; 3038 break; 3039 } 3040 } 3041 ADBG_WARN(("ata_hba_start: watchdog\n")); 3042 3043 fsm_done: 3044 return (request_started); 3045 3046 } 3047 3048 static int 3049 ata_check_pciide_blacklist( 3050 dev_info_t *dip, 3051 uint_t flags) 3052 { 3053 ushort_t vendorid; 3054 ushort_t deviceid; 3055 pcibl_t *blp; 3056 int *propp; 3057 uint_t count; 3058 int rc; 3059 3060 3061 vendorid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3062 DDI_PROP_DONTPASS, "vendor-id", 0); 3063 deviceid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3064 DDI_PROP_DONTPASS, "device-id", 0); 3065 3066 /* 3067 * first check for a match in the "pci-ide-blacklist" property 3068 */ 3069 rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, 3070 "pci-ide-blacklist", &propp, &count); 3071 3072 if (rc == DDI_PROP_SUCCESS) { 3073 count = (count * sizeof (uint_t)) / sizeof (pcibl_t); 3074 blp = (pcibl_t *)propp; 3075 while (count--) { 3076 /* check for matching ID */ 3077 if ((vendorid & blp->b_vmask) 3078 != (blp->b_vendorid & blp->b_vmask)) { 3079 blp++; 3080 continue; 3081 } 3082 if ((deviceid & blp->b_dmask) 3083 != (blp->b_deviceid & blp->b_dmask)) { 3084 blp++; 3085 continue; 3086 } 3087 3088 /* got a match */ 3089 if (blp->b_flags & flags) { 3090 ddi_prop_free(propp); 3091 return (TRUE); 3092 } else { 3093 ddi_prop_free(propp); 3094 return (FALSE); 3095 } 3096 } 3097 ddi_prop_free(propp); 3098 } 3099 3100 /* 3101 * then check the built-in blacklist 3102 */ 3103 for (blp = ata_pciide_blacklist; blp->b_vendorid; blp++) { 3104 if ((vendorid & blp->b_vmask) != blp->b_vendorid) 3105 continue; 3106 if ((deviceid & blp->b_dmask) != blp->b_deviceid) 3107 continue; 3108 if (!(blp->b_flags & flags)) 3109 continue; 3110 return (TRUE); 3111 } 3112 return (FALSE); 3113 } 3114 3115 int 3116 ata_check_drive_blacklist( 3117 struct ata_id *aidp, 3118 uint_t flags) 3119 { 3120 atabl_t *blp; 3121 3122 for (blp = ata_drive_blacklist; blp->b_model; blp++) { 3123 if (!ata_strncmp(blp->b_model, aidp->ai_model, 3124 sizeof (aidp->ai_model))) 3125 continue; 3126 if (blp->b_flags & flags) 3127 return (TRUE); 3128 return (FALSE); 3129 } 3130 return (FALSE); 3131 } 3132 3133 /* 3134 * Queue a request to perform some sort of internally 3135 * generated command. When this request packet reaches 3136 * the front of the queue (*func)() is invoked. 3137 * 3138 */ 3139 3140 int 3141 ata_queue_cmd( 3142 int (*func)(ata_ctl_t *, ata_drv_t *, ata_pkt_t *), 3143 void *arg, 3144 ata_ctl_t *ata_ctlp, 3145 ata_drv_t *ata_drvp, 3146 gtgt_t *gtgtp) 3147 { 3148 ata_pkt_t *ata_pktp; 3149 gcmd_t *gcmdp; 3150 int rc; 3151 3152 if (!(gcmdp = ghd_gcmd_alloc(gtgtp, sizeof (*ata_pktp), TRUE))) { 3153 ADBG_ERROR(("atapi_id_update alloc failed\n")); 3154 return (FALSE); 3155 } 3156 3157 3158 /* set the back ptr from the ata_pkt to the gcmd_t */ 3159 ata_pktp = GCMD2APKT(gcmdp); 3160 ata_pktp->ap_gcmdp = gcmdp; 3161 ata_pktp->ap_hd = ata_drvp->ad_drive_bits; 3162 ata_pktp->ap_bytes_per_block = ata_drvp->ad_bytes_per_block; 3163 3164 /* 3165 * over-ride the default start function 3166 */ 3167 ata_pktp = GCMD2APKT(gcmdp); 3168 ata_pktp->ap_start = func; 3169 ata_pktp->ap_complete = NULL; 3170 ata_pktp->ap_v_addr = (caddr_t)arg; 3171 3172 /* 3173 * add it to the queue, when it gets to the front the 3174 * ap_start function is called. 3175 */ 3176 rc = ghd_transport(&ata_ctlp->ac_ccc, gcmdp, gcmdp->cmd_gtgtp, 3177 0, TRUE, NULL); 3178 3179 if (rc != TRAN_ACCEPT) { 3180 /* this should never, ever happen */ 3181 return (FALSE); 3182 } 3183 3184 if (ata_pktp->ap_flags & AP_ERROR) 3185 return (FALSE); 3186 return (TRUE); 3187 } 3188 3189 /* 3190 * Check if this drive has the "revert to defaults" bug 3191 * PSARC 2001/500 and 2001/xxx - check for the properties 3192 * ata-revert-to-defaults and atarvrt-<diskmodel> before 3193 * examining the blacklist. 3194 * <diskmodel> is made from the model number reported by Identify Drive 3195 * with uppercase letters converted to lowercase and all characters 3196 * except letters, digits, ".", "_", and "-" deleted. 3197 * Return value: 3198 * TRUE: enable revert to defaults 3199 * FALSE: disable revert to defaults 3200 * 3201 * NOTE: revert to power on defaults that includes reverting to MDMA 3202 * mode is allowed by ATA-6 & ATA-7 specs. 3203 * Therefore drives exhibiting this behaviour are not violating the spec. 3204 * Furthermore, the spec explicitly says that after the soft reset 3205 * host should check the current setting of the device features. 3206 * Correctly working BIOS would therefore reprogram either the drive 3207 * and/or the host controller to match transfer modes. 3208 * Devices with ATA_BL_NORVRT flag will be removed from 3209 * the ata_blacklist. 3210 * The default behaviour will be - no revert to power-on defaults 3211 * for all devices. The property is retained in case the user 3212 * explicitly requests revert-to-defaults before reboot. 3213 */ 3214 3215 #define ATA_REVERT_PROP_PREFIX "revert-" 3216 #define ATA_REVERT_PROP_GLOBAL "ata-revert-to-defaults" 3217 /* room for prefix + model number + terminating NUL character */ 3218 #define PROP_BUF_SIZE (sizeof (ATA_REVERT_PROP_PREFIX) + \ 3219 sizeof (aidp->ai_model) + 1) 3220 #define PROP_LEN_MAX (31) 3221 3222 static int 3223 ata_check_revert_to_defaults( 3224 ata_drv_t *ata_drvp) 3225 { 3226 struct ata_id *aidp = &ata_drvp->ad_id; 3227 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 3228 char prop_buf[PROP_BUF_SIZE]; 3229 int i, j; 3230 int propval; 3231 3232 /* put prefix into the buffer */ 3233 (void) strcpy(prop_buf, ATA_REVERT_PROP_PREFIX); 3234 j = strlen(prop_buf); 3235 3236 /* append the model number, leaving out invalid characters */ 3237 for (i = 0; i < sizeof (aidp->ai_model); ++i) { 3238 char c = aidp->ai_model[i]; 3239 if (c >= 'A' && c <= 'Z') /* uppercase -> lower */ 3240 c = c - 'A' + 'a'; 3241 if (c >= 'a' && c <= 'z' || c >= '0' && c <= '9' || 3242 c == '.' || c == '_' || c == '-') 3243 prop_buf[j++] = c; 3244 if (c == '\0') 3245 break; 3246 } 3247 3248 /* make sure there's a terminating NUL character */ 3249 if (j >= PROP_LEN_MAX) 3250 j = PROP_LEN_MAX; 3251 prop_buf[j] = '\0'; 3252 3253 /* look for a disk-specific "revert" property" */ 3254 propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 3255 DDI_PROP_DONTPASS, prop_buf, -1); 3256 if (propval == 0) 3257 return (FALSE); 3258 else if (propval != -1) 3259 return (TRUE); 3260 3261 /* look for a global "revert" property" */ 3262 propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 3263 0, ATA_REVERT_PROP_GLOBAL, -1); 3264 if (propval == 0) 3265 return (FALSE); 3266 else if (propval != -1) 3267 return (TRUE); 3268 3269 return (FALSE); 3270 } 3271 3272 void 3273 ata_show_transfer_mode(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp) 3274 { 3275 int i; 3276 3277 if (ata_ctlp->ac_pciide_bm == FALSE || 3278 ata_drvp->ad_pciide_dma != ATA_DMA_ON) { 3279 if (ata_cntrl_DMA_sel_msg) { 3280 ATAPRT(( 3281 "?\tATA DMA off: %s\n", ata_cntrl_DMA_sel_msg)); 3282 } else if (ata_dev_DMA_sel_msg) { 3283 ATAPRT(("?\tATA DMA off: %s\n", ata_dev_DMA_sel_msg)); 3284 } 3285 ATAPRT(("?\tPIO mode %d selected\n", 3286 (ata_drvp->ad_id.ai_advpiomode & ATAC_ADVPIO_4_SUP) == 3287 ATAC_ADVPIO_4_SUP ? 4 : 3)); 3288 } else { 3289 /* Using DMA */ 3290 if (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_SEL_MASK) { 3291 /* 3292 * Rely on the fact that either dwdma or udma is 3293 * selected, not both. 3294 */ 3295 ATAPRT(("?\tMultiwordDMA mode %d selected\n", 3296 (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_2_SEL) == 3297 ATAC_MDMA_2_SEL ? 2 : 3298 (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_1_SEL) == 3299 ATAC_MDMA_1_SEL ? 1 : 0)); 3300 } else { 3301 for (i = 0; i <= 6; i++) { 3302 if (ata_drvp->ad_id.ai_ultradma & 3303 (1 << (i + 8))) { 3304 ATAPRT(( 3305 "?\tUltraDMA mode %d selected\n", 3306 i)); 3307 break; 3308 } 3309 } 3310 } 3311 } 3312 } 3313 3314 /* 3315 * Controller-specific operation pointers. 3316 * Should be extended as needed - init only for now 3317 */ 3318 struct ata_ctl_spec_ops { 3319 uint_t (*cs_init)(dev_info_t *, ushort_t, ushort_t); /* ctlr init */ 3320 }; 3321 3322 3323 struct ata_ctl_spec { 3324 ushort_t cs_vendor_id; 3325 ushort_t cs_device_id; 3326 struct ata_ctl_spec_ops *cs_ops; 3327 }; 3328 3329 /* Sil3XXX-specific functions (init only for now) */ 3330 struct ata_ctl_spec_ops sil3xxx_ops = { 3331 &sil3xxx_init_controller /* Sil3XXX cntrl initialization */ 3332 }; 3333 3334 3335 struct ata_ctl_spec ata_cntrls_spec[] = { 3336 {0x1095, 0x3114, &sil3xxx_ops}, 3337 {0x1095, 0x3512, &sil3xxx_ops}, 3338 {0x1095, 0x3112, &sil3xxx_ops}, 3339 {0, 0, NULL} /* List must end with cs_ops set to NULL */ 3340 }; 3341 3342 /* 3343 * Do controller specific initialization if necessary. 3344 * Pick-up controller specific functions. 3345 */ 3346 3347 int 3348 ata_spec_init_controller(dev_info_t *dip) 3349 { 3350 ushort_t vendor_id; 3351 ushort_t device_id; 3352 struct ata_ctl_spec *ctlsp; 3353 3354 vendor_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3355 DDI_PROP_DONTPASS, "vendor-id", 0); 3356 device_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3357 DDI_PROP_DONTPASS, "device-id", 0); 3358 3359 /* Locate controller specific ops, if they exist */ 3360 ctlsp = ata_cntrls_spec; 3361 while (ctlsp->cs_ops != NULL) { 3362 if (ctlsp->cs_vendor_id == vendor_id && 3363 ctlsp->cs_device_id == device_id) 3364 break; 3365 ctlsp++; 3366 } 3367 3368 if (ctlsp->cs_ops != NULL) { 3369 if (ctlsp->cs_ops->cs_init != NULL) { 3370 /* Initialize controller */ 3371 if ((*(ctlsp->cs_ops->cs_init)) 3372 (dip, vendor_id, device_id) != TRUE) { 3373 cmn_err(CE_WARN, 3374 "pci%4x,%4x cntrl specific " 3375 "initialization failed", 3376 vendor_id, device_id); 3377 return (FALSE); 3378 } 3379 } 3380 } 3381 return (TRUE); 3382 } 3383 3384 /* 3385 * this routine works like ddi_prop_get_int, except that it works on 3386 * a string property that contains ascii representations 3387 * of an integer. 3388 * If the property is not found, the default value is returned. 3389 */ 3390 static int 3391 ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip, 3392 uint_t flags, char *name, int defvalue) 3393 { 3394 3395 char *bufp, *cp; 3396 int rc = defvalue; 3397 int proprc; 3398 3399 proprc = ddi_prop_lookup_string(match_dev, dip, 3400 flags, name, &bufp); 3401 3402 if (proprc == DDI_PROP_SUCCESS) { 3403 cp = bufp; 3404 rc = stoi(&cp); 3405 ddi_prop_free(bufp); 3406 } else { 3407 /* 3408 * see if property is encoded as an int instead of string. 3409 */ 3410 rc = ddi_prop_get_int(match_dev, dip, flags, name, defvalue); 3411 } 3412 3413 return (rc); 3414 } 3415