1 /* 2 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 #ifndef AMD8111S_MAIN_H 7 #define AMD8111S_MAIN_H 8 9 #pragma ident "%Z%%M% %I% %E% SMI" 10 11 /* 12 * Copyright (c) 2001-2006 Advanced Micro Devices, Inc. All rights reserved. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are met: 16 * 17 * + Redistributions of source code must retain the above copyright notice, 18 * + this list of conditions and the following disclaimer. 19 * 20 * + Redistributions in binary form must reproduce the above copyright 21 * + notice, this list of conditions and the following disclaimer in the 22 * + documentation and/or other materials provided with the distribution. 23 * 24 * + Neither the name of Advanced Micro Devices, Inc. nor the names of its 25 * + contributors may be used to endorse or promote products derived from 26 * + this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 29 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 30 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 31 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 32 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. OR 33 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 35 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 38 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 39 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 40 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 * Import/Export/Re-Export/Use/Release/Transfer Restrictions and 43 * Compliance with Applicable Laws. Notice is hereby given that 44 * the software may be subject to restrictions on use, release, 45 * transfer, importation, exportation and/or re-exportation under 46 * the laws and regulations of the United States or other 47 * countries ("Applicable Laws"), which include but are not 48 * limited to U.S. export control laws such as the Export 49 * Administration Regulations and national security controls as 50 * defined thereunder, as well as State Department controls under 51 * the U.S. Munitions List. Permission to use and/or 52 * redistribute the software is conditioned upon compliance with 53 * all Applicable Laws, including U.S. export control laws 54 * regarding specifically designated persons, countries and 55 * nationals of countries subject to national security controls. 56 */ 57 58 59 #pragma ident "@(#)$RCSfile: odl.h,v $ $Revision: 1.1 $ " \ 60 "$Date: 2004/04/22 15:22:52 $ AMD" 61 62 #include <sys/types.h> 63 #include <sys/errno.h> 64 #include <sys/kmem.h> 65 #include <sys/conf.h> 66 #include <sys/stat.h> 67 #include <sys/note.h> 68 #include <sys/modctl.h> 69 70 #include <sys/stream.h> 71 #include <sys/strsubr.h> 72 #include <sys/strsun.h> 73 74 #include <sys/dditypes.h> 75 #include <sys/ddi.h> 76 #include <sys/sunddi.h> 77 78 #include <sys/pci.h> 79 80 #include <sys/ethernet.h> 81 #include <sys/dlpi.h> 82 #include <sys/mac.h> 83 #include <sys/mac_ether.h> 84 #include <sys/netlb.h> 85 #include "amd8111s_hw.h" 86 87 #define MEM_REQ_MAX 100 88 #define MEMSET 4 89 90 #define IOC_LINESIZE 40 91 92 /* 93 * Loopback definitions 94 */ 95 #define AMD8111S_LB_NONE 0 96 #define AMD8111S_LB_EXTERNAL_1000 1 97 #define AMD8111S_LB_EXTERNAL_100 2 98 #define AMD8111S_LB_EXTERNAL_10 3 99 #define AMD8111S_LB_INTERNAL_PHY 4 100 #define AMD8111S_LB_INTERNAL_MAC 5 101 102 /* ((2 ^ (32 - 1)) * 8) / (10 ^ 8) >= 100 */ 103 #define AMD8111S_DUMP_MIB_SECONDS_THRESHOLD 100 104 #define AMD8111S_DUMP_MIB_BYTES_THRESHOLD 0x80000000 105 106 /* Bit flags for 'attach_progress' */ 107 #define AMD8111S_ATTACH_PCI 0x0001 /* pci_config_setup() */ 108 #define AMD8111S_ATTACH_RESOURCE 0x0002 /* odlInit() */ 109 #define AMD8111S_ATTACH_REGS 0x0004 /* ddi_regs_map_setup() */ 110 #define AMD8111S_ATTACH_INTRADDED 0x0010 /* intr_add() */ 111 #define AMD8111S_ATTACH_MACREGED 0x0020 /* mac_register() */ 112 #define AMD8111S_ATTACH_RESCHED 0x0040 /* soft_intr() */ 113 114 #define AMD8111S_TRY_SEND 0x0001 115 #define AMD8111S_SEND_READY 0x0002 116 117 #define NEXT(buf, ptr) \ 118 (buf.ptr + 1 >= buf.msg_buf + \ 119 buf.ring_size ? \ 120 buf.msg_buf : \ 121 buf.ptr + 1) 122 /* 123 * (Internal) return values from ioctl subroutines 124 */ 125 enum ioc_reply { 126 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 127 IOC_DONE, /* OK, reply sent */ 128 IOC_ACK, /* OK, just send ACK */ 129 IOC_REPLY, /* OK, just send reply */ 130 IOC_RESTART_ACK, /* OK, restart & ACK */ 131 IOC_RESTART_REPLY /* OK, restart & reply */ 132 }; 133 134 typedef int (*TIMERfUNC) (struct LayerPointers *); 135 136 struct TimerStructure { 137 int Type; 138 int Period; /* in milliseconds */ 139 timeout_id_t TimerHandle; 140 int (*TimerFunptr)(struct LayerPointers *); 141 struct LayerPointers *pLayerPointers; 142 }; 143 144 struct amd8111s_statistics 145 { 146 uint64_t intr_TINT0; /* # of TINT0 (Tx interrupts) */ 147 uint64_t intr_RINT0; /* # of RINT0 (Rx interrupts) */ 148 uint64_t intr_STINT; /* # of STINT (Software Timer Intr) */ 149 uint64_t intr_OTHER; /* Intr caused by other device */ 150 151 uint64_t tx_ok_packets; 152 uint64_t tx_no_descriptor; 153 uint64_t tx_no_buffer; 154 uint64_t tx_rescheduled; 155 uint64_t tx_unrescheduled; 156 157 /* # of call amd8111s_dump_mib function */ 158 uint64_t mib_dump_counter; 159 160 /* 161 * From MIB registers (TX) 162 */ 163 uint64_t tx_mib_packets; /* # of packets */ 164 uint64_t tx_mib_multicst_packets; /* # of multicast packets */ 165 uint64_t tx_mib_broadcst_packets; /* # of broadcast packets */ 166 uint64_t tx_mib_flowctrl_packets; /* # of flow ctrl packets */ 167 168 uint64_t tx_mib_bytes; /* # of all Tx bytes */ 169 170 /* Packet drop due to Tx FIFO underrun */ 171 uint64_t tx_mib_underrun_packets; 172 uint64_t tx_mib_collision_packets; 173 /* Packets successfully transmitted after experiencing one collision */ 174 uint64_t tx_mib_one_coll_packets; 175 uint64_t tx_mib_multi_coll_packets; 176 /* # of late collisions that occur */ 177 uint64_t tx_mib_late_coll_packets; 178 uint64_t tx_mib_ex_coll_packets; /* excessive collision */ 179 uint64_t tx_mib_oversize_packets; 180 uint64_t tx_mib_defer_trans_packets; /* defer transmit */ 181 182 183 /* 184 * Some error counter after "ifconfig amd8111sX unplumb" 185 */ 186 /* 187 * Count Tx mp number from GLD even after NIC has been unplumbed. 188 * This value should always be 0. 189 */ 190 uint64_t tx_afterunplumb; 191 /* 192 * We drain all pending tx packets during unplumb operation. This 193 * variable is to count the drain time. 194 * 30 means success; =30 means fail 195 */ 196 uint64_t tx_draintime; 197 198 uint64_t rx_ok_packets; /* # of all good packets */ 199 uint64_t rx_allocfail; /* alloc memory fail during Rx */ 200 uint64_t rx_error_zerosize; 201 202 uint64_t rx_0_packets; 203 uint64_t rx_1_15_packets; 204 uint64_t rx_16_31_packets; 205 uint64_t rx_32_47_packets; 206 uint64_t rx_48_63_packets; 207 uint64_t rx_double_overflow; 208 209 uint64_t rx_desc_err; 210 uint64_t rx_desc_err_FRAM; /* Framing error */ 211 uint64_t rx_desc_err_OFLO; /* Overflow error */ 212 uint64_t rx_desc_err_CRC; /* CRC error */ 213 uint64_t rx_desc_err_BUFF; /* BCRC error */ 214 215 /* 216 * From MIB registers (RX) 217 */ 218 uint64_t rx_mib_unicst_packets; /* # of unicast packets */ 219 uint64_t rx_mib_multicst_packets; /* # of multicast packets */ 220 uint64_t rx_mib_broadcst_packets; /* # of broadcast packets */ 221 uint64_t rx_mib_macctrl_packets; /* # of mac ctrl packets */ 222 uint64_t rx_mib_flowctrl_packets; /* # of flow ctrl packets */ 223 224 uint64_t rx_mib_bytes; /* # of all Rx bytes */ 225 uint64_t rx_mib_good_bytes; /* # of all Rx bytes */ 226 /* 227 * The total number of valid frames received that are less than 64 228 * bytes long (include the FCS). 229 */ 230 uint64_t rx_mib_undersize_packets; 231 /* 232 * The total number of valid frames received that are greater than the 233 * maximum valid frame size (include the FCS). 234 */ 235 uint64_t rx_mib_oversize_packets; 236 237 uint64_t rx_mib_align_err_packets; 238 uint64_t rx_mib_fcs_err_packets; /* has a bad FCS */ 239 /* Invalid data symbol (RX_ER) */ 240 uint64_t rx_mib_symbol_err_packets; 241 /* Packets that were dropped because no descriptor was available */ 242 uint64_t rx_mib_drop_packets; 243 /* 244 * Packets that were dropped due to lack of resources. This includes 245 * the number of times a packet was dropped due to receive FIFO 246 * overflow and lack of receive descriptor. 247 */ 248 uint64_t rx_mib_miss_packets; 249 }; 250 251 struct amd8111s_msgbuf { 252 uint64_t phy_addr; 253 caddr_t vir_addr; 254 uint32_t msg_size; 255 ddi_dma_handle_t p_hdl; 256 uint32_t offset; 257 }; 258 259 struct amd8111s_dma_ringbuf { 260 ddi_dma_handle_t *dma_hdl; 261 ddi_acc_handle_t *acc_hdl; 262 ddi_dma_cookie_t *dma_cookie; 263 caddr_t *trunk_addr; 264 uint32_t buf_sz; 265 uint32_t trunk_sz; 266 uint32_t trunk_num; 267 struct amd8111s_msgbuf *msg_buf; 268 uint32_t ring_size; 269 uint32_t dma_buf_sz; 270 struct amd8111s_msgbuf *free; 271 struct amd8111s_msgbuf *next; 272 struct amd8111s_msgbuf *curr; 273 274 kmutex_t ring_lock; 275 }; 276 277 struct odl { 278 dev_info_t *devinfo; 279 280 mac_handle_t mh; /* mac module handle */ 281 mac_resource_handle_t mrh; 282 283 struct amd8111s_statistics statistics; 284 285 /* Locks */ 286 kmutex_t mdlSendLock; 287 kmutex_t mdlRcvLock; 288 kmutex_t timer_lock; 289 kmutex_t send_cv_lock; 290 kcondvar_t send_cv; 291 292 ddi_softintr_t drain_id; 293 /* 294 * The chip_lock assures that the Rx/Tx process must be stopped while 295 * other functions change the hardware configuration, such as attach() 296 * detach() etc are executed. 297 */ 298 krwlock_t chip_lock; 299 300 /* 301 * HW operators and parameters on attach period 302 */ 303 ddi_iblock_cookie_t iblock; /* HW: interrupt block cookie */ 304 ddi_acc_handle_t MemBasehandle; 305 306 /* For pci configuration */ 307 ddi_acc_handle_t pci_handle; /* HW: access handle of PCI space */ 308 uint16_t vendor_id; 309 uint16_t device_id; 310 311 /* 312 * FreeQ: Transfer Rx Buffer parameters from top layer to low layers. 313 * Format of parameter: 314 * (struct RxBufInfo *, physical address) 315 */ 316 unsigned long FreeQ[2 * RX_RING_SIZE]; 317 unsigned long *FreeQStart; 318 unsigned long *FreeQEnd; 319 long *FreeQWrite; 320 long *FreeQRead; 321 322 /* For Rx descriptors */ 323 ddi_dma_handle_t rx_desc_dma_handle; 324 ddi_acc_handle_t rx_desc_acc_handle; 325 ddi_dma_cookie_t rx_desc_dma_cookie; 326 327 /* For Tx descriptors */ 328 ddi_dma_handle_t tx_desc_dma_handle; 329 ddi_acc_handle_t tx_desc_acc_handle; 330 ddi_dma_cookie_t tx_desc_dma_cookie; 331 332 /* For Tx buffers */ 333 struct amd8111s_dma_ringbuf tx_buf; 334 335 /* For Rx buffers */ 336 struct amd8111s_dma_ringbuf rx_buf; 337 338 ether_addr_t MacAddress; /* Mac address */ 339 340 /* Multicast addresses table */ 341 UCHAR MulticastAddresses 342 [MAX_MULTICAST_ADDRESSES][ETH_LENGTH_OF_ADDRESS]; 343 344 link_state_t LinkStatus; 345 346 /* Timer */ 347 timeout_id_t Timer_id; 348 int (*TimerFunc)(struct LayerPointers *); 349 int timer_run; 350 int timer_linkdown; 351 352 unsigned int dump_mib_seconds; 353 354 uint32_t loopback_mode; 355 unsigned int rx_fcs_stripped; 356 357 unsigned int rx_overflow_counter; 358 unsigned int pause_interval; 359 360 }; 361 362 #endif /* AMD8111S_MAIN_H */ 363