1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PSM_TYPES_H 28 #define _SYS_PSM_TYPES_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * Platform Specific Module Types 34 */ 35 36 #include <sys/types.h> 37 #include <sys/cpuvar.h> 38 #include <sys/time.h> 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* 45 * PSM_OPS definitions 46 */ 47 typedef enum psm_intr_op_e { 48 PSM_INTR_OP_ALLOC_VECTORS = 0, /* 0. Allocate vectors */ 49 PSM_INTR_OP_FREE_VECTORS, /* 1. Free vectors */ 50 PSM_INTR_OP_NAVAIL_VECTORS, /* 2. Get # of available vectors */ 51 PSM_INTR_OP_XLATE_VECTOR, /* 3. Translate vector */ 52 PSM_INTR_OP_GET_PENDING, /* 4. Get pending information */ 53 PSM_INTR_OP_CLEAR_MASK, /* 5. Clear interrupt mask */ 54 PSM_INTR_OP_SET_MASK, /* 6. Set interrupt mask */ 55 PSM_INTR_OP_GET_CAP, /* 7. Get devices's capabilities */ 56 PSM_INTR_OP_SET_CAP, /* 8. Set devices's capabilities */ 57 PSM_INTR_OP_SET_PRI, /* 9. Set the interrupt priority */ 58 PSM_INTR_OP_GET_SHARED, /* 10. Get the shared intr info */ 59 PSM_INTR_OP_CHECK_MSI, /* 11. Chk if device supports MSI */ 60 PSM_INTR_OP_SET_CPU, /* 12. Set vector's CPU */ 61 PSM_INTR_OP_GET_INTR, /* 13. Get vector's info */ 62 PSM_INTR_OP_GRP_SET_CPU, /* 14. Set all device's vectors' CPU */ 63 PSM_INTR_OP_APIC_TYPE /* 15. Returns APIC type */ 64 } psm_intr_op_t; 65 66 struct psm_ops { 67 int (*psm_probe)(void); 68 69 void (*psm_softinit)(void); 70 void (*psm_picinit)(void); 71 int (*psm_intr_enter)(int ipl, int *vectorp); 72 void (*psm_intr_exit)(int ipl, int irqno); 73 void (*psm_setspl)(int ipl); 74 int (*psm_addspl)(int irqno, int ipl, int min_ipl, int max_ipl); 75 int (*psm_delspl)(int irqno, int ipl, int min_ipl, int max_ipl); 76 int (*psm_disable_intr)(processorid_t cpun); 77 void (*psm_enable_intr)(processorid_t cpun); 78 int (*psm_softlvl_to_irq)(int ipl); 79 void (*psm_set_softintr)(int ipl); 80 void (*psm_set_idlecpu)(processorid_t cpun); 81 void (*psm_unset_idlecpu)(processorid_t cpun); 82 83 #if defined(PSMI_1_3) || defined(PSMI_1_4) || defined(PSMI_1_5) 84 int (*psm_clkinit)(int hertz); 85 #else 86 void (*psm_clkinit)(int hertz); 87 #endif 88 89 int (*psm_get_clockirq)(int ipl); 90 void (*psm_hrtimeinit)(void); 91 hrtime_t (*psm_gethrtime)(void); 92 93 processorid_t (*psm_get_next_processorid)(processorid_t cpu_id); 94 #if defined(PSMI_1_5) 95 int (*psm_cpu_start)(processorid_t cpun, caddr_t ctxt); 96 #else 97 void (*psm_cpu_start)(processorid_t cpun, caddr_t rm_code); 98 #endif 99 int (*psm_post_cpu_start)(void); 100 #if defined(PSMI_1_2) || defined(PSMI_1_3) || defined(PSMI_1_4) || \ 101 defined(PSMI_1_5) 102 void (*psm_shutdown)(int cmd, int fcn); 103 #else 104 void (*psm_shutdown)(void); 105 #endif 106 int (*psm_get_ipivect)(int ipl, int type); 107 void (*psm_send_ipi)(processorid_t cpun, int ipl); 108 109 int (*psm_translate_irq)(dev_info_t *dip, int irqno); 110 111 #if defined(PSMI_1_2) || defined(PSMI_1_3) || defined(PSMI_1_4) 112 int (*psm_tod_get)(todinfo_t *tod); 113 int (*psm_tod_set)(todinfo_t *tod); 114 #endif 115 void (*psm_notify_error)(int level, char *errmsg); 116 #if defined(PSMI_1_2) || defined(PSMI_1_3) || defined(PSMI_1_4) || \ 117 defined(PSMI_1_5) 118 void (*psm_notify_func)(int msg); 119 #endif 120 #if defined(PSMI_1_3) || defined(PSMI_1_4) || defined(PSMI_1_5) 121 void (*psm_timer_reprogram)(hrtime_t time); 122 void (*psm_timer_enable)(void); 123 void (*psm_timer_disable)(void); 124 void (*psm_post_cyclic_setup)(void *arg); 125 #endif 126 #if defined(PSMI_1_4) || defined(PSMI_1_5) 127 void (*psm_preshutdown)(int cmd, int fcn); 128 #endif 129 #if defined(PSMI_1_5) 130 int (*psm_intr_ops)(dev_info_t *dip, ddi_intr_handle_impl_t *handle, 131 psm_intr_op_t op, int *result); 132 #endif 133 }; 134 135 136 struct psm_info { 137 ushort_t p_version; 138 ushort_t p_owner; 139 struct psm_ops *p_ops; 140 char *p_mach_idstring; /* machine identification string */ 141 char *p_mach_desc; /* machine descriptions */ 142 }; 143 144 /* 145 * version 146 * 0x86vm where v = (version no. - 1) and m = (minor no. + 1) 147 * i.e. psmi 1.0 has v=0 and m=1, psmi 1.1 has v=0 and m=2 148 * also, 0x86 in the high byte is the signature of the psmi 149 */ 150 #define PSM_INFO_VER01 0x8601 151 #define PSM_INFO_VER01_1 0x8602 152 #define PSM_INFO_VER01_2 0x8603 153 #define PSM_INFO_VER01_3 0x8604 154 #define PSM_INFO_VER01_4 0x8605 155 #define PSM_INFO_VER01_5 0x8606 156 #define PSM_INFO_VER01_X (PSM_INFO_VER01_1 & 0xFFF0) /* ver 1.X */ 157 158 /* 159 * owner field definitions 160 */ 161 #define PSM_OWN_SYS_DEFAULT 0x0001 162 #define PSM_OWN_EXCLUSIVE 0x0002 163 #define PSM_OWN_OVERRIDE 0x0003 164 165 #define PSM_NULL_INFO -1 166 167 /* 168 * Arg to psm_notify_func 169 */ 170 #define PSM_DEBUG_ENTER 1 171 #define PSM_DEBUG_EXIT 2 172 #define PSM_PANIC_ENTER 3 173 174 /* 175 * Soft-level to interrupt vector 176 */ 177 #define PSM_SV_SOFTWARE -1 178 #define PSM_SV_MIXED -2 179 180 /* 181 * Inter-processor interrupt type 182 */ 183 #define PSM_INTR_IPI_HI 0x01 184 #define PSM_INTR_IPI_LO 0x02 185 #define PSM_INTR_POKE 0x03 186 187 /* 188 * Get INTR flags 189 */ 190 #define PSMGI_CPU_USER_BOUND 0x80000000 /* user requested bind if set */ 191 #define PSMGI_CPU_FLAGS 0x80000000 /* all possible flags */ 192 193 /* 194 * return code 195 */ 196 #define PSM_SUCCESS DDI_SUCCESS 197 #define PSM_FAILURE DDI_FAILURE 198 199 #define PSM_INVALID_IPL 0 200 #define PSM_INVALID_CPU -1 201 202 203 struct psm_ops_ver01 { 204 int (*psm_probe)(void); 205 206 void (*psm_softinit)(void); 207 void (*psm_picinit)(void); 208 int (*psm_intr_enter)(int ipl, int *vectorp); 209 void (*psm_intr_exit)(int ipl, int irqno); 210 void (*psm_setspl)(int ipl); 211 int (*psm_addspl)(int irqno, int ipl, int min_ipl, int max_ipl); 212 int (*psm_delspl)(int irqno, int ipl, int min_ipl, int max_ipl); 213 int (*psm_disable_intr)(processorid_t cpun); 214 void (*psm_enable_intr)(processorid_t cpun); 215 int (*psm_softlvl_to_irq)(int ipl); 216 void (*psm_set_softintr)(int ipl); 217 void (*psm_set_idlecpu)(processorid_t cpun); 218 void (*psm_unset_idlecpu)(processorid_t cpun); 219 220 void (*psm_clkinit)(int hertz); 221 int (*psm_get_clockirq)(int ipl); 222 void (*psm_hrtimeinit)(void); 223 hrtime_t (*psm_gethrtime)(void); 224 225 processorid_t (*psm_get_next_processorid)(processorid_t cpu_id); 226 void (*psm_cpu_start)(processorid_t cpun, caddr_t rm_code); 227 int (*psm_post_cpu_start)(void); 228 void (*psm_shutdown)(void); 229 int (*psm_get_ipivect)(int ipl, int type); 230 void (*psm_send_ipi)(processorid_t cpun, int ipl); 231 }; 232 233 #ifdef __cplusplus 234 } 235 #endif 236 237 #endif /* _SYS_PSM_TYPES_H */ 238