1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PCI_CFGACC_X86_H 27 #define _SYS_PCI_CFGACC_X86_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /* AMD's northbridges vendor-id and device-ids */ 34 #define AMD_NTBRDIGE_VID 0x1022 /* AMD vendor-id */ 35 #define AMD_HT_NTBRIDGE_DID 0x1100 /* HT Configuration */ 36 #define AMD_AM_NTBRIDGE_DID 0x1101 /* Address Map */ 37 #define AMD_DC_NTBRIDGE_DID 0x1102 /* DRAM Controller */ 38 #define AMD_MC_NTBRIDGE_DID 0x1103 /* Misc Controller */ 39 #define AMD_K10_NTBRIDGE_DID_0 0x1200 40 #define AMD_K10_NTBRIDGE_DID_1 0x1201 41 #define AMD_K10_NTBRIDGE_DID_2 0x1202 42 #define AMD_K10_NTBRIDGE_DID_3 0x1203 43 #define AMD_K10_NTBRIDGE_DID_4 0x1204 44 45 /* AMD's 8132 chipset vendor-id and device-ids */ 46 #define AMD_8132_BRIDGE_DID 0x7458 /* 8132 PCI-X bridge */ 47 #define AMD_8132_IOAPIC_DID 0x7459 /* 8132 IO APIC */ 48 49 /* 50 * Check if the given device is an AMD northbridge 51 */ 52 #define IS_BAD_AMD_NTBRIDGE(vid, did) \ 53 (((vid) == AMD_NTBRDIGE_VID) && \ 54 (((did) == AMD_HT_NTBRIDGE_DID) || \ 55 ((did) == AMD_AM_NTBRIDGE_DID) || \ 56 ((did) == AMD_DC_NTBRIDGE_DID) || \ 57 ((did) == AMD_MC_NTBRIDGE_DID))) 58 59 #define IS_K10_AMD_NTBRIDGE(vid, did) \ 60 (((vid) == AMD_NTBRDIGE_VID) && \ 61 (((did) == AMD_K10_NTBRIDGE_DID_0) || \ 62 ((did) == AMD_K10_NTBRIDGE_DID_1) || \ 63 ((did) == AMD_K10_NTBRIDGE_DID_2) || \ 64 ((did) == AMD_K10_NTBRIDGE_DID_3) || \ 65 ((did) == AMD_K10_NTBRIDGE_DID_4))) 66 67 #define IS_AMD_8132_CHIP(vid, did) \ 68 (((vid) == AMD_NTBRDIGE_VID) && \ 69 (((did) == AMD_8132_BRIDGE_DID)) || \ 70 (((did) == AMD_8132_IOAPIC_DID))) 71 72 #define MSR_AMD_NB_MMIO_CFG_BADDR 0xc0010058 73 #define AMD_MMIO_CFG_BADDR_ADDR_MASK 0xFFFFFFF00000ULL 74 #define AMD_MMIO_CFG_BADDR_ENA_MASK 0x000000000001ULL 75 #define AMD_MMIO_CFG_BADDR_ENA_ON 0x000000000001ULL 76 #define AMD_MMIO_CFG_BADDR_ENA_OFF 0x000000000000ULL 77 78 #ifdef __cplusplus 79 } 80 #endif 81 82 #endif /* _SYS_PCI_CFGACC_X86_H */ 83