1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 /* 26 * Copyright 2019 Joyent, Inc. 27 * Copyright 2026 Oxide Computer Company 28 */ 29 30 #ifndef _SYS_MACHCPUVAR_H 31 #define _SYS_MACHCPUVAR_H 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #include <sys/inttypes.h> 38 #include <sys/x_call.h> 39 #include <sys/tss.h> 40 #include <sys/segments.h> 41 #include <sys/rm_platter.h> 42 #include <sys/avintr.h> 43 #include <sys/pte.h> 44 #include <sys/stddef.h> 45 #include <sys/debug.h> 46 #include <sys/cpuvar.h> 47 #include <sys/smt_machcpu.h> 48 49 #ifndef _ASM 50 /* 51 * On a virtualized platform a virtual cpu may not be actually 52 * on a physical cpu, especially in situations where a configuration has 53 * more vcpus than pcpus. This function tells us (if it's able) if the 54 * specified vcpu is currently running on a pcpu. Note if it is not 55 * known or not able to determine, it will return the unknown state. 56 */ 57 #define VCPU_STATE_UNKNOWN 0 58 #define VCPU_ON_PCPU 1 59 #define VCPU_NOT_ON_PCPU 2 60 61 extern int vcpu_on_pcpu(processorid_t); 62 63 /* 64 * Machine specific fields of the cpu struct 65 * defined in common/sys/cpuvar.h. 66 * 67 * Note: This is kinda kludgy but seems to be the best 68 * of our alternatives. 69 */ 70 71 struct cpuid_info; 72 struct cpu_ucode_info; 73 struct cmi_hdl; 74 75 /* 76 * A note about the hypervisor affinity bits: a one bit in the affinity mask 77 * means the corresponding event channel is allowed to be serviced 78 * by this cpu. 79 */ 80 struct xen_evt_data { 81 ulong_t pending_sel[PIL_MAX + 1]; /* event array selectors */ 82 ulong_t pending_evts[PIL_MAX + 1][sizeof (ulong_t) * 8]; 83 ulong_t evt_affinity[sizeof (ulong_t) * 8]; /* service on cpu */ 84 }; 85 86 enum fast_syscall_state { 87 FSS_DISABLED = 0, 88 FSS_ASYSC_ENABLED = (1 << 0), 89 FSS_SEP_ENABLED = (1 << 1) 90 }; 91 92 struct kpti_frame { 93 uint64_t kf_lower_redzone; 94 95 /* Stashed value of %cr3 when we entered the trampoline. */ 96 greg_t kf_tr_cr3; 97 98 /* 99 * We use %r13-r14 as scratch registers in the trampoline code, 100 * so stash those here "below" the rest of the stack so they can be 101 * pushed/popped if needed. 102 */ 103 greg_t kf_r14; 104 greg_t kf_r13; 105 106 /* 107 * Part of this struct is used as the HW stack frame when taking an 108 * interrupt on the user page table. The CPU is going to push a bunch 109 * of regs onto the stack pointer set in the TSS/IDT (which we set to 110 * &kf_rsp here). 111 * 112 * This is only a temporary holding area for them (we'll move them over 113 * to the real interrupt stack once we've set %cr3). 114 * 115 * Note that these must be cleared during a process switch on this cpu. 116 */ 117 greg_t kf_err; /* Bottom of initial hw stack frame */ 118 greg_t kf_rip; 119 greg_t kf_cs; 120 greg_t kf_rflags; 121 greg_t kf_rsp; 122 greg_t kf_ss; 123 124 greg_t kf_tr_rsp; /* Top of HW stack frame */ 125 /* We also write this with the %rsp value on tramp entry */ 126 127 /* Written to 0x1 when this kpti_frame is in use. */ 128 uint64_t kf_tr_flag; 129 130 uint64_t kf_middle_redzone; 131 132 /* 133 * The things we need to write to %cr3 to change between page tables. 134 * These live "above" the HW stack. 135 */ 136 greg_t kf_kernel_cr3; 137 greg_t kf_user_cr3; 138 greg_t kf_tr_ret_rsp; 139 140 uint64_t kf_unused; /* For 16-byte align */ 141 142 uint64_t kf_upper_redzone; 143 }; 144 145 /* 146 * This first value, MACHCPU_SIZE is the size of all the members in the cpu_t 147 * AND struct machcpu, before we get to the mcpu_pad and the kpti area. 148 * The KPTI is used to contain per-CPU data that is visible in both sets of 149 * page-tables, and hence must be page-aligned and page-sized. See 150 * hat_pcp_setup(). 151 * 152 * There are CTASSERTs in os/intr.c that verify this all works out. 153 */ 154 #define MACHCPU_SIZE (1576 + 696) 155 #define MACHCPU_PAD (MMU_PAGESIZE - MACHCPU_SIZE) 156 #define MACHCPU_PAD2 (MMU_PAGESIZE - 16 - 3 * sizeof (struct kpti_frame)) 157 158 struct machcpu { 159 /* 160 * x_call fields - used for interprocessor cross calls 161 */ 162 struct xc_msg *xc_msgbox; 163 struct xc_msg *xc_curmsg; 164 struct xc_msg *xc_free; 165 xc_data_t xc_data; 166 uint32_t xc_wait_cnt; 167 volatile uint32_t xc_work_cnt; 168 169 int mcpu_nodeid; /* node-id */ 170 int mcpu_pri; /* CPU priority */ 171 172 struct hat *mcpu_current_hat; /* cpu's current hat */ 173 174 struct hat_cpu_info *mcpu_hat_info; 175 176 volatile ulong_t mcpu_tlb_info; 177 178 /* i86 hardware table addresses that cannot be shared */ 179 180 user_desc_t *mcpu_gdt; /* GDT */ 181 gate_desc_t *mcpu_idt; /* current IDT */ 182 183 tss_t *mcpu_tss; /* TSS */ 184 void *mcpu_ldt; 185 size_t mcpu_ldt_len; 186 187 kmutex_t mcpu_ppaddr_mutex; 188 caddr_t mcpu_caddr1; /* per cpu CADDR1 */ 189 caddr_t mcpu_caddr2; /* per cpu CADDR2 */ 190 uint64_t mcpu_caddr1pte; 191 uint64_t mcpu_caddr2pte; 192 193 struct softint mcpu_softinfo; 194 uint64_t pil_high_start[HIGH_LEVELS]; 195 uint64_t intrstat[PIL_MAX + 1][2]; 196 197 struct cpuid_info *mcpu_cpi; 198 199 #if defined(__amd64) 200 greg_t mcpu_rtmp_rsp; /* syscall: temporary %rsp stash */ 201 greg_t mcpu_rtmp_r15; /* syscall: temporary %r15 stash */ 202 #endif 203 204 struct vcpu_info *mcpu_vcpu_info; 205 uint64_t mcpu_gdtpa; /* hypervisor: GDT physical address */ 206 207 uint16_t mcpu_intr_pending; /* hypervisor: pending intrpt levels */ 208 uint16_t mcpu_ec_mbox; /* hypervisor: evtchn_dev mailbox */ 209 struct xen_evt_data *mcpu_evt_pend; /* hypervisor: pending events */ 210 211 volatile uint32_t *mcpu_mwait; /* MONITOR/MWAIT buffer */ 212 void (*mcpu_idle_cpu)(void); /* idle function */ 213 uint16_t mcpu_idle_type; /* CPU next idle type */ 214 uint16_t max_cstates; /* supported max cstates */ 215 216 enum fast_syscall_state mcpu_fast_syscall_state; 217 218 struct cpu_ucode_info *mcpu_ucode_info; 219 220 void *mcpu_pm_mach_state; 221 struct cmi_hdl *mcpu_cmi_hdl; 222 void *mcpu_mach_ctx_ptr; 223 224 /* 225 * A stamp that is unique per processor and changes 226 * whenever an interrupt happens. Userful for detecting 227 * if a section of code gets interrupted. 228 * The high order 16 bits will hold the cpu->cpu_id. 229 * The low order bits will be incremented on every interrupt. 230 */ 231 volatile uint32_t mcpu_istamp; 232 233 cpu_smt_t mcpu_smt; 234 235 char mcpu_pad[MACHCPU_PAD]; 236 237 /* This is the start of the page */ 238 char mcpu_pad2[MACHCPU_PAD2]; 239 struct kpti_frame mcpu_kpti; 240 struct kpti_frame mcpu_kpti_flt; 241 struct kpti_frame mcpu_kpti_dbg; 242 char mcpu_pad3[16]; 243 }; 244 245 #define NINTR_THREADS (LOCK_LEVEL-1) /* number of interrupt threads */ 246 #define MWAIT_HALTED (1) /* mcpu_mwait set when halting */ 247 #define MWAIT_RUNNING (0) /* mcpu_mwait set to wakeup */ 248 #define MWAIT_WAKEUP_IPI (2) /* need IPI to wakeup */ 249 #define MWAIT_WAKEUP(cpu) (*((cpu)->cpu_m.mcpu_mwait) = MWAIT_RUNNING) 250 251 #endif /* _ASM */ 252 253 /* Please DON'T add any more of this namespace-poisoning sewage here */ 254 255 #define cpu_nodeid cpu_m.mcpu_nodeid 256 #define cpu_pri cpu_m.mcpu_pri 257 #define cpu_current_hat cpu_m.mcpu_current_hat 258 #define cpu_hat_info cpu_m.mcpu_hat_info 259 #define cpu_ppaddr_mutex cpu_m.mcpu_ppaddr_mutex 260 #define cpu_gdt cpu_m.mcpu_gdt 261 #define cpu_idt cpu_m.mcpu_idt 262 #define cpu_tss cpu_m.mcpu_tss 263 #define cpu_caddr1 cpu_m.mcpu_caddr1 264 #define cpu_caddr2 cpu_m.mcpu_caddr2 265 #define cpu_softinfo cpu_m.mcpu_softinfo 266 #define cpu_caddr1pte cpu_m.mcpu_caddr1pte 267 #define cpu_caddr2pte cpu_m.mcpu_caddr2pte 268 269 #ifdef __cplusplus 270 } 271 #endif 272 273 #endif /* _SYS_MACHCPUVAR_H */ 274