1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_APIC_APIC_H 27 #define _SYS_APIC_APIC_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include <sys/psm_types.h> 32 #include <sys/avintr.h> 33 #include <sys/pci.h> 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 #include <sys/psm_common.h> 40 41 #define APIC_PCPLUSMP_NAME "pcplusmp" 42 43 #define APIC_IO_ADDR 0xfec00000 44 #define APIC_LOCAL_ADDR 0xfee00000 45 #define APIC_IO_MEMLEN 0xf 46 #define APIC_LOCAL_MEMLEN 0xfffff 47 48 /* Local Unit ID register */ 49 #define APIC_LID_REG 0x8 50 51 /* I/o Unit Version Register */ 52 #define APIC_VERS_REG 0xc 53 54 /* Task Priority register */ 55 #define APIC_TASK_REG 0x20 56 57 /* EOI register */ 58 #define APIC_EOI_REG 0x2c 59 60 /* Remote Read register */ 61 #define APIC_REMOTE_READ 0x30 62 63 /* Logical Destination register */ 64 #define APIC_DEST_REG 0x34 65 66 /* Destination Format rgister */ 67 #define APIC_FORMAT_REG 0x38 68 69 /* Spurious Interrupt Vector register */ 70 #define APIC_SPUR_INT_REG 0x3c 71 72 /* Error Status Register */ 73 #define APIC_ERROR_STATUS 0xa0 74 75 /* Interrupt Command registers */ 76 #define APIC_INT_CMD1 0xc0 77 #define APIC_INT_CMD2 0xc4 78 79 /* Timer Vector Table register */ 80 #define APIC_LOCAL_TIMER 0xc8 81 82 /* Local Interrupt Vector registers */ 83 #define APIC_THERM_VECT 0xcc 84 #define APIC_PCINT_VECT 0xd0 85 #define APIC_INT_VECT0 0xd4 86 #define APIC_INT_VECT1 0xd8 87 #define APIC_ERR_VECT 0xdc 88 89 /* IPL for performance counter interrupts */ 90 #define APIC_PCINT_IPL 0xe 91 #define APIC_LVT_MASK 0x10000 /* Mask bit (16) in LVT */ 92 93 /* Initial Count register */ 94 #define APIC_INIT_COUNT 0xe0 95 96 /* Current Count Register */ 97 #define APIC_CURR_COUNT 0xe4 98 #define APIC_CURR_ADD 0x39 /* used for remote read command */ 99 #define CURR_COUNT_OFFSET (sizeof (int32_t) * APIC_CURR_COUNT) 100 101 /* Divider Configuration Register */ 102 #define APIC_DIVIDE_REG 0xf8 103 104 /* IRR register */ 105 #define APIC_IRR_REG 0x80 106 107 /* ISR register */ 108 #define APIC_ISR_REG 0x40 109 110 #define APIC_IO_REG 0x0 111 #define APIC_IO_DATA 0x4 112 113 /* Bit offset of APIC ID in LID_REG, INT_CMD and in DEST_REG */ 114 #define APIC_ID_BIT_OFFSET 24 115 #define APIC_ICR_ID_BIT_OFFSET 24 116 #define APIC_LDR_ID_BIT_OFFSET 24 117 118 /* 119 * Choose between flat and clustered models by writing the following to the 120 * FORMAT_REG. 82489 DX documentation seemed to suggest that writing 0 will 121 * disable logical destination mode. 122 * Does not seem to be in the docs for local APICs on the processors. 123 */ 124 #define APIC_FLAT_MODEL 0xFFFFFFFFUL 125 #define APIC_CLUSTER_MODEL 0x0FFFFFFF 126 127 /* 128 * The commands which follow are window selectors written to APIC_IO_REG 129 * before data can be read/written from/to APIC_IO_DATA 130 */ 131 132 #define APIC_ID_CMD 0x0 133 #define APIC_VERS_CMD 0x1 134 #define APIC_RDT_CMD 0x10 135 #define APIC_RDT_CMD2 0x11 136 137 #define APIC_INTEGRATED_VERS 0x10 /* 0x10 & above indicates integrated */ 138 #define IOAPIC_VER_82489DX 0x01 /* Version ID: 82489DX External APIC */ 139 140 #define APIC_INT_SPURIOUS -1 141 142 #define APIC_IMCR_P1 0x22 /* int mode conf register port 1 */ 143 #define APIC_IMCR_P2 0x23 /* int mode conf register port 2 */ 144 #define APIC_IMCR_SELECT 0x70 /* select imcr by writing into P1 */ 145 #define APIC_IMCR_PIC 0x0 /* selects PIC mode (8259-> BSP) */ 146 #define APIC_IMCR_APIC 0x1 /* selects APIC mode (8259->APIC) */ 147 148 #define APIC_CT_VECT 0x4ac /* conf table vector */ 149 #define APIC_CT_SIZE 1024 /* conf table size */ 150 151 #define APIC_ID 'MPAT' /* conf table signature */ 152 153 #define VENID_AMD 0x1022 154 #define DEVID_8131_IOAPIC 0x7451 155 #define DEVID_8132_IOAPIC 0x7459 156 157 #define IOAPICS_NODE_NAME "ioapics" 158 #define IOAPICS_CHILD_NAME "ioapic" 159 #define IOAPICS_DEV_TYPE "ioapic" 160 #define IOAPICS_PROP_VENID "vendor-id" 161 #define IOAPICS_PROP_DEVID "device-id" 162 163 #define IS_CLASS_IOAPIC(b, s, p) \ 164 ((b) == PCI_CLASS_PERIPH && (s) == PCI_PERIPH_PIC && \ 165 ((p) == PCI_PERIPH_PIC_IF_IO_APIC || \ 166 (p) == PCI_PERIPH_PIC_IF_IOX_APIC)) 167 168 169 /* 170 * MP floating pointer structure defined in Intel MP Spec 1.1 171 */ 172 struct apic_mpfps_hdr { 173 uint32_t mpfps_sig; /* _MP_ (0x5F4D505F) */ 174 uint32_t mpfps_mpct_paddr; /* paddr of MP configuration tbl */ 175 uchar_t mpfps_length; /* in paragraph (16-bytes units) */ 176 uchar_t mpfps_spec_rev; /* version number of MP spec */ 177 uchar_t mpfps_checksum; /* checksum of complete structure */ 178 uchar_t mpfps_featinfo1; /* mp feature info bytes 1 */ 179 uchar_t mpfps_featinfo2; /* mp feature info bytes 2 */ 180 uchar_t mpfps_featinfo3; /* mp feature info bytes 3 */ 181 uchar_t mpfps_featinfo4; /* mp feature info bytes 4 */ 182 uchar_t mpfps_featinfo5; /* mp feature info bytes 5 */ 183 }; 184 185 #define MPFPS_FEATINFO2_IMCRP 0x80 /* IMCRP presence bit */ 186 187 #define APIC_MPS_OEM_ID_LEN 8 188 #define APIC_MPS_PROD_ID_LEN 12 189 190 struct apic_mp_cnf_hdr { 191 uint_t mpcnf_sig; 192 193 uint_t mpcnf_tbl_length: 16, 194 mpcnf_spec: 8, 195 mpcnf_cksum: 8; 196 197 char mpcnf_oem_str[APIC_MPS_OEM_ID_LEN]; 198 199 char mpcnf_prod_str[APIC_MPS_PROD_ID_LEN]; 200 201 uint_t mpcnf_oem_ptr; 202 203 uint_t mpcnf_oem_tbl_size: 16, 204 mpcnf_entry_cnt: 16; 205 206 uint_t mpcnf_local_apic; 207 208 uint_t mpcnf_resv; 209 }; 210 211 struct apic_procent { 212 uint_t proc_entry: 8, 213 proc_apicid: 8, 214 proc_version: 8, 215 proc_cpuflags: 8; 216 217 uint_t proc_stepping: 4, 218 proc_model: 4, 219 proc_family: 4, 220 proc_type: 2, /* undocumented feature */ 221 proc_resv1: 18; 222 223 uint_t proc_feature; 224 225 uint_t proc_resv2; 226 227 uint_t proc_resv3; 228 }; 229 230 /* 231 * proc_cpuflags definitions 232 */ 233 #define CPUFLAGS_EN 1 /* if not set, this processor is unusable */ 234 #define CPUFLAGS_BP 2 /* set if this is the bootstrap processor */ 235 236 237 struct apic_bus { 238 uchar_t bus_entry; 239 uchar_t bus_id; 240 ushort_t bus_str1; 241 uint_t bus_str2; 242 }; 243 244 struct apic_io_entry { 245 uint_t io_entry: 8, 246 io_apicid: 8, 247 io_version: 8, 248 io_flags: 8; 249 250 uint_t io_apic_addr; 251 }; 252 253 #define IOAPIC_FLAGS_EN 0x01 /* this I/O apic is enable or not */ 254 255 #define MAX_IO_APIC 32 /* maximum # of IOAPICs supported */ 256 257 struct apic_io_intr { 258 uint_t intr_entry: 8, 259 intr_type: 8, 260 intr_po: 2, 261 intr_el: 2, 262 intr_resv: 12; 263 264 uint_t intr_busid: 8, 265 intr_irq: 8, 266 intr_destid: 8, 267 intr_destintin: 8; 268 }; 269 270 /* 271 * intr_type definitions 272 */ 273 #define IO_INTR_INT 0x00 274 #define IO_INTR_NMI 0x01 275 #define IO_INTR_SMI 0x02 276 #define IO_INTR_EXTINT 0x03 277 278 /* 279 * destination APIC ID 280 */ 281 #define INTR_ALL_APIC 0xff 282 283 284 /* local vector table */ 285 #define AV_MASK 0x10000 286 287 /* interrupt command register 32-63 */ 288 #define AV_TOALL 0x7fffffff 289 #define AV_HIGH_ORDER 0x40000000 290 #define AV_IM_OFF 0x40000000 291 292 /* interrupt command register 0-31 */ 293 #define AV_DELIV_MODE 0x700 294 295 #define AV_FIXED 0x000 296 #define AV_LOPRI 0x100 297 #define AV_SMI 0x200 298 #define AV_REMOTE 0x300 299 #define AV_NMI 0x400 300 #define AV_RESET 0x500 301 #define AV_STARTUP 0x600 302 #define AV_EXTINT 0x700 303 304 #define AV_PDEST 0x000 305 #define AV_LDEST 0x800 306 307 /* IO & Local APIC Bit Definitions */ 308 #define RDT_VECTOR(x) ((uchar_t)((x) & 0xFF)) 309 #define AV_PENDING 0x1000 310 #define AV_ACTIVE_LOW 0x2000 /* only for integrated APIC */ 311 #define AV_REMOTE_IRR 0x4000 /* IOAPIC RDT-specific */ 312 #define AV_LEVEL 0x8000 313 #define AV_DEASSERT AV_LEVEL 314 #define AV_ASSERT 0xc000 315 316 #define AV_READ_PENDING 0x10000 317 #define AV_REMOTE_STATUS 0x20000 /* 1 = valid, 0 = invalid */ 318 319 #define AV_SH_SELF 0x40000 /* Short hand for self */ 320 #define AV_SH_ALL_INCSELF 0x80000 /* All processors */ 321 #define AV_SH_ALL_EXCSELF 0xc0000 /* All excluding self */ 322 /* spurious interrupt vector register */ 323 #define AV_UNIT_ENABLE 0x100 324 325 /* timer vector table */ 326 #define AV_TIME 0x20000 /* Set timer mode to periodic */ 327 328 #define APIC_MAXVAL 0xffffffffUL 329 #define APIC_TIME_MIN 0x5000 330 #define APIC_TIME_COUNT 0x4000 331 332 /* 333 * Range of the low byte value in apic_tick before starting calibration 334 */ 335 #define APIC_LB_MIN 0x60 336 #define APIC_LB_MAX 0xe0 337 338 #define APIC_MAX_VECTOR 255 339 #define APIC_RESV_VECT 0x00 340 #define APIC_RESV_IRQ 0xfe 341 #define APIC_BASE_VECT 0x20 /* This will come in as interrupt 0 */ 342 #define APIC_AVAIL_VECTOR (APIC_MAX_VECTOR+1-APIC_BASE_VECT) 343 #define APIC_VECTOR_PER_IPL 0x10 /* # of vectors before PRI changes */ 344 #define APIC_VECTOR(ipl) (apic_ipltopri[ipl] | APIC_RESV_VECT) 345 #define APIC_VECTOR_MASK 0x0f 346 #define APIC_HI_PRI_VECTS 2 /* vects reserved for hi pri reqs */ 347 #define APIC_IPL_MASK 0xf0 348 #define APIC_IPL_SHIFT 4 /* >> to get ipl part of vector */ 349 #define APIC_FIRST_FREE_IRQ 0x10 350 #define APIC_MAX_ISA_IRQ 15 351 #define APIC_IPL0 0x0f /* let IDLE_IPL be the lowest */ 352 #define APIC_IDLE_IPL 0x00 353 354 #define APIC_MASK_ALL 0xf0 /* Mask all interrupts */ 355 356 /* spurious interrupt vector */ 357 #define APIC_SPUR_INTR 0xFF 358 359 /* special or reserve vectors */ 360 #define APIC_CHECK_RESERVE_VECTORS(v) \ 361 (((v) == T_FASTTRAP) || ((v) == APIC_SPUR_INTR) || \ 362 ((v) == T_SYSCALLINT) || ((v) == T_DTRACE_RET) || ((v) == T_INT80)) 363 364 /* cmos shutdown code for BIOS */ 365 #define BIOS_SHUTDOWN 0x0a 366 367 /* define the entry types for BIOS information tables as defined in PC+MP */ 368 #define APIC_CPU_ENTRY 0 369 #define APIC_BUS_ENTRY 1 370 #define APIC_IO_ENTRY 2 371 #define APIC_IO_INTR_ENTRY 3 372 #define APIC_LOCAL_INTR_ENTRY 4 373 #define APIC_MPTBL_ADDR (639 * 1024) 374 /* 375 * The MP Floating Point structure could be in 1st 1KB of EBDA or last KB 376 * of system base memory or in ROM between 0xF0000 and 0xFFFFF 377 */ 378 #define MPFPS_RAM_WIN_LEN 1024 379 #define MPFPS_ROM_WIN_START (uint32_t)0xf0000 380 #define MPFPS_ROM_WIN_LEN 0x10000 381 382 #define EISA_LEVEL_CNTL 0x4D0 383 384 /* definitions for apic_irq_table */ 385 #define FREE_INDEX (short)-1 /* empty slot */ 386 #define RESERVE_INDEX (short)-2 /* ipi, softintr, clkintr */ 387 #define ACPI_INDEX (short)-3 /* ACPI */ 388 #define MSI_INDEX (short)-4 /* MSI */ 389 #define MSIX_INDEX (short)-5 /* MSI-X */ 390 #define DEFAULT_INDEX (short)0x7FFF 391 /* biggest positive no. to avoid conflict with actual index */ 392 393 #define APIC_IS_MSI_OR_MSIX_INDEX(index) \ 394 ((index) == MSI_INDEX || (index) == MSIX_INDEX) 395 396 /* 397 * definitions for MSI Address 398 */ 399 #define MSI_ADDR_HDR APIC_LOCAL_ADDR 400 #define MSI_ADDR_DEST_SHIFT 12 /* Destination CPU's apic id */ 401 #define MSI_ADDR_RH_FIXED 0x0 /* Redirection Hint Fixed */ 402 #define MSI_ADDR_RH_LOPRI 0x1 /* Redirection Hint Lowest priority */ 403 #define MSI_ADDR_RH_SHIFT 3 404 #define MSI_ADDR_DM_PHYSICAL 0x0 /* Physical Destination Mode */ 405 #define MSI_ADDR_DM_LOGICAL 0x1 /* Logical Destination Mode */ 406 #define MSI_ADDR_DM_SHIFT 2 407 408 /* 409 * definitions for MSI Data 410 */ 411 #define MSI_DATA_DELIVERY_FIXED 0x0 /* Fixed delivery */ 412 #define MSI_DATA_DELIVERY_LOPRI 0x1 /* Lowest priority delivery */ 413 #define MSI_DATA_DELIVERY_SMI 0x2 414 #define MSI_DATA_DELIVERY_NMI 0x4 415 #define MSI_DATA_DELIVERY_INIT 0x5 416 #define MSI_DATA_DELIVERY_EXTINT 0x7 417 #define MSI_DATA_DELIVERY_SHIFT 8 418 #define MSI_DATA_TM_EDGE 0x0 /* MSI is edge sensitive */ 419 #define MSI_DATA_TM_LEVEL 0x1 /* level sensitive */ 420 #define MSI_DATA_TM_SHIFT 15 421 #define MSI_DATA_LEVEL_DEASSERT 0x0 422 #define MSI_DATA_LEVEL_ASSERT 0x1 /* Edge always assert */ 423 #define MSI_DATA_LEVEL_SHIFT 14 424 425 /* 426 * use to define each irq setup by the apic 427 */ 428 typedef struct apic_irq { 429 short airq_mps_intr_index; /* index into mps interrupt entries */ 430 /* table */ 431 uchar_t airq_intin_no; 432 uchar_t airq_ioapicindex; 433 dev_info_t *airq_dip; /* device corresponding to this interrupt */ 434 /* 435 * IRQ could be shared (in H/W) in which case dip & major will be 436 * for the one that was last added at this level. We cannot keep a 437 * linked list as delspl does not tell us which device has just 438 * been unloaded. For most servers where we are worried about 439 * performance, interrupt should not be shared & should not be 440 * a problem. This does not cause any correctness issue - dip is 441 * used only as an optimisation to avoid going thru all the tables 442 * in translate IRQ (which is always called twice due to brokenness 443 * in the way IPLs are determined for devices). major is used only 444 * to bind interrupts corresponding to the same device on the same 445 * CPU. Not finding major will just cause it to be potentially bound 446 * to another CPU. 447 */ 448 major_t airq_major; /* major number corresponding to the device */ 449 ushort_t airq_rdt_entry; /* level, polarity & trig mode */ 450 ushort_t airq_cpu; /* Which CPU are we bound to ? */ 451 ushort_t airq_temp_cpu; /* Could be diff from cpu due to disable_intr */ 452 uchar_t airq_vector; /* Vector chosen for this irq */ 453 uchar_t airq_share; /* number of interrupts at this irq */ 454 uchar_t airq_share_id; /* id to identify source from irqno */ 455 uchar_t airq_ipl; /* The ipl at which this is handled */ 456 iflag_t airq_iflag; /* interrupt flag */ 457 uchar_t airq_origirq; /* original irq passed in */ 458 uint_t airq_busy; /* How frequently did clock find */ 459 /* us in this */ 460 struct apic_irq *airq_next; /* chain of shared intpts */ 461 } apic_irq_t; 462 463 #define IRQ_USER_BOUND 0x8000 /* user requested bind if set in airq_cpu */ 464 #define IRQ_UNBOUND (ushort_t)-1 /* set in airq_cpu and airq_temp_cpu */ 465 #define IRQ_UNINIT (ushort_t)-2 /* in airq_temp_cpu till addspl called */ 466 467 /* Macros to help deal with shared interrupts */ 468 #define VIRTIRQ(irqno, share_id) ((irqno) | ((share_id) << 8)) 469 #define IRQINDEX(irq) ((irq) & 0xFF) /* Mask to get irq from virtual irq */ 470 471 typedef struct apic_cpus_info { 472 uchar_t aci_local_id; 473 uchar_t aci_local_ver; 474 uchar_t aci_status; 475 uchar_t aci_redistribute; /* Selected for redistribution */ 476 uint_t aci_busy; /* Number of ticks we were in ISR */ 477 uint_t aci_spur_cnt; /* # of spurious intpts on this cpu */ 478 uint_t aci_ISR_in_progress; /* big enough to hold 1 << MAXIPL */ 479 uchar_t aci_curipl; /* IPL of current ISR */ 480 uchar_t aci_current[MAXIPL]; /* Current IRQ at each IPL */ 481 uint32_t aci_bound; /* # of user requested binds ? */ 482 uint32_t aci_temp_bound; /* # of non user IRQ binds */ 483 uchar_t aci_idle; /* The CPU is idle */ 484 /* 485 * fill to make sure each struct is in seperate cache line. 486 * Or atleast that ISR_in_progress/curipl is not shared with something 487 * that is read/written heavily by another CPU. 488 * Given kmem_alloc guarantees alignment to 8 bytes, having 8 489 * bytes on each side will isolate us in a 16 byte cache line. 490 */ 491 } apic_cpus_info_t; 492 493 #define APIC_CPU_ONLINE 1 494 #define APIC_CPU_INTR_ENABLE 2 495 496 /* 497 * Various poweroff methods and ports & bits for them 498 */ 499 #define APIC_POWEROFF_NONE 0 500 #define APIC_POWEROFF_VIA_RTC 1 501 #define APIC_POWEROFF_VIA_ASPEN_BMC 2 502 #define APIC_POWEROFF_VIA_SITKA_BMC 3 503 504 /* For RTC */ 505 #define RTC_REGA 0x0a 506 #define PFR_REG 0x4a /* extended control register */ 507 #define PAB_CBIT 0x08 508 #define WF_FLAG 0x02 509 #define KS_FLAG 0x01 510 #define EXT_BANK 0x10 511 512 /* For Aspen/Drake BMC */ 513 514 #define CC_SMS_GET_STATUS 0x40 515 #define CC_SMS_WR_START 0x41 516 #define CC_SMS_WR_NEXT 0x42 517 #define CC_SMS_WR_END 0x43 518 519 #define MISMIC_DATA_REGISTER 0x0ca9 520 #define MISMIC_CNTL_REGISTER 0x0caa 521 #define MISMIC_FLAG_REGISTER 0x0cab 522 523 #define MISMIC_BUSY_MASK 0x01 524 525 /* For Sitka/Cabrillo BMC */ 526 527 #define SMS_GET_STATUS 0x60 528 #define SMS_WRITE_START 0x61 529 #define SMS_WRITE_END 0x62 530 531 #define SMS_DATA_REGISTER 0x0ca2 532 #define SMS_STATUS_REGISTER 0x0ca3 533 #define SMS_COMMAND_REGISTER 0x0ca3 534 535 #define SMS_IBF_MASK 0x02 536 #define SMS_STATE_MASK 0xc0 537 538 #define SMS_IDLE_STATE 0x00 539 #define SMS_READ_STATE 0x40 540 #define SMS_WRITE_STATE 0x80 541 #define SMS_ERROR_STATE 0xc0 542 543 extern uint32_t ioapic_read(int ioapic_ix, uint32_t reg); 544 extern void ioapic_write(int ioapic_ix, uint32_t reg, uint32_t value); 545 546 /* Macros for reading/writing the IOAPIC RDT entries */ 547 #define READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin) \ 548 ioapic_read(ioapic_ix, APIC_RDT_CMD + (2 * (ipin))) 549 550 #define READ_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin) \ 551 ioapic_read(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin))) 552 553 #define WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin, value) \ 554 ioapic_write(ioapic_ix, APIC_RDT_CMD + (2 * (ipin)), value) 555 556 #define WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin, value) \ 557 ioapic_write(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin)), value) 558 559 /* Used by PSM_INTR_OP_GET_INTR to return device information. */ 560 typedef struct { 561 uint16_t avgi_req_flags; /* request flags - to kernel */ 562 uint8_t avgi_num_devs; /* # devs on this ino - from kernel */ 563 uint8_t avgi_vector; /* vector */ 564 uint32_t avgi_cpu_id; /* cpu of interrupt - from kernel */ 565 dev_info_t **avgi_dip_list; /* kmem_alloc'ed list of dev_infos. */ 566 /* Contains num_devs elements. */ 567 } apic_get_intr_t; 568 569 /* Masks for avgi_req_flags. */ 570 #define PSMGI_REQ_CPUID 0x1 /* Request CPU ID */ 571 #define PSMGI_REQ_NUM_DEVS 0x2 /* Request num of devices on vector */ 572 #define PSMGI_REQ_VECTOR 0x4 573 #define PSMGI_REQ_GET_DEVS 0x8 /* Request device list */ 574 #define PSMGI_REQ_ALL 0xf /* Request everything */ 575 576 /* Other flags */ 577 #define PSMGI_INTRBY_VEC 0 /* Vec passed. xlate to IRQ needed */ 578 #define PSMGI_INTRBY_IRQ 0x8000 /* IRQ passed. no xlate needed */ 579 #define PSMGI_INTRBY_FLAGS 0x8000 /* Mask for this flag */ 580 581 /* 582 * Use scaled-fixed-point arithmetic to calculate apic ticks. 583 * Round when dividing (by adding half of divisor to dividend) 584 * for one extra bit of precision. 585 */ 586 587 #define SF (1ULL<<20) /* Scaling Factor: scale by 2^20 */ 588 #define APIC_TICKS_TO_NSECS(ticks) ((((int64_t)(ticks) * SF) + \ 589 apic_ticks_per_SFnsecs / 2) / \ 590 apic_ticks_per_SFnsecs); 591 #define APIC_NSECS_TO_TICKS(nsecs) (((int64_t)(nsecs) * \ 592 apic_ticks_per_SFnsecs + (SF/2)) / SF) 593 594 extern int apic_verbose; 595 596 /* Flag definitions for apic_verbose */ 597 #define APIC_VERBOSE_IOAPIC_FLAG 0x00000001 598 #define APIC_VERBOSE_IRQ_FLAG 0x00000002 599 #define APIC_VERBOSE_POWEROFF_FLAG 0x00000004 600 #define APIC_VERBOSE_POWEROFF_PAUSE_FLAG 0x00000008 601 602 603 #define APIC_VERBOSE_IOAPIC(fmt) \ 604 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) \ 605 cmn_err fmt; 606 607 #define APIC_VERBOSE_IRQ(fmt) \ 608 if (apic_verbose & APIC_VERBOSE_IRQ_FLAG) \ 609 cmn_err fmt; 610 611 #define APIC_VERBOSE_POWEROFF(fmt) \ 612 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) \ 613 prom_printf fmt; 614 615 #ifdef DEBUG 616 #define DENT 0x0001 617 extern int apic_debug; 618 /* 619 * set apic_restrict_vector to the # of vectors we want to allow per range 620 * useful in testing shared interrupt logic by setting it to 2 or 3 621 */ 622 extern int apic_restrict_vector; 623 624 #define APIC_DEBUG_MSGBUFSIZE 2048 625 extern int apic_debug_msgbuf[]; 626 extern int apic_debug_msgbufindex; 627 628 /* 629 * Put "int" info into debug buffer. No MP consistency, but light weight. 630 * Good enough for most debugging. 631 */ 632 #define APIC_DEBUG_BUF_PUT(x) \ 633 apic_debug_msgbuf[apic_debug_msgbufindex++] = x; \ 634 if (apic_debug_msgbufindex >= (APIC_DEBUG_MSGBUFSIZE - NCPU)) \ 635 apic_debug_msgbufindex = 0; 636 637 #endif /* DEBUG */ 638 639 extern int apic_error; 640 /* values which apic_error can take. Not catastrophic, but may help debug */ 641 #define APIC_ERR_BOOT_EOI 0x1 642 #define APIC_ERR_GET_IPIVECT_FAIL 0x2 643 #define APIC_ERR_INVALID_INDEX 0x4 644 #define APIC_ERR_MARK_VECTOR_FAIL 0x8 645 #define APIC_ERR_APIC_ERROR 0x40000000 646 #define APIC_ERR_NMI 0x80000000 647 648 /* 649 * ACPI definitions 650 */ 651 /* _PIC method arguments */ 652 #define ACPI_PIC_MODE 0 653 #define ACPI_APIC_MODE 1 654 655 /* APIC error flags we care about */ 656 #define APIC_SEND_CS_ERROR 0x01 657 #define APIC_RECV_CS_ERROR 0x02 658 #define APIC_CS_ERRORS (APIC_SEND_CS_ERROR|APIC_RECV_CS_ERROR) 659 660 /* Maximum number of times to retry reprogramming at apic_intr_exit time */ 661 #define APIC_REPROGRAM_MAX_TRIES 10000 662 663 /* Parameter to ioapic_init_intr(): Should ioapic ints be masked? */ 664 #define IOAPIC_MASK 1 665 #define IOAPIC_NOMASK 0 666 667 #define INTR_ROUND_ROBIN_WITH_AFFINITY 0 668 #define INTR_ROUND_ROBIN 1 669 #define INTR_LOWEST_PRIORITY 2 670 671 672 673 struct ioapic_reprogram_data { 674 boolean_t done; 675 apic_irq_t *irqp; 676 /* The CPU to which the int will be bound */ 677 int bindcpu; 678 /* # times the reprogram timeout was called */ 679 unsigned tries; 680 }; 681 682 /* The irq # is implicit in the array index: */ 683 extern struct ioapic_reprogram_data apic_reprogram_info[]; 684 685 extern void apic_intr_exit(int ipl, int irq); 686 extern int apic_probe_common(); 687 extern void apic_init_common(); 688 extern void ioapic_init_intr(); 689 extern void ioapic_disable_redirection(); 690 extern int apic_addspl_common(int irqno, int ipl, int min_ipl, int max_ipl); 691 extern int apic_delspl_common(int irqno, int ipl, int min_ipl, int max_ipl); 692 extern void apic_cleanup_busy(); 693 extern void apic_intr_redistribute(); 694 extern uchar_t apic_xlate_vector(uchar_t vector); 695 extern uchar_t apic_allocate_vector(int ipl, int irq, int pri); 696 extern void apic_free_vector(uchar_t vector); 697 extern int apic_allocate_irq(int irq); 698 extern ushort_t apic_bind_intr(dev_info_t *dip, int irq, uchar_t ioapicid, 699 uchar_t intin); 700 extern int apic_rebind(apic_irq_t *irq_ptr, int bind_cpu, 701 struct ioapic_reprogram_data *drep); 702 extern int apic_rebind_all(apic_irq_t *irq_ptr, int bind_cpu); 703 extern int apic_introp_xlate(dev_info_t *dip, struct intrspec *ispec, int type); 704 extern int apic_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp, 705 psm_intr_op_t intr_op, int *result); 706 extern int apic_state(psm_state_request_t *); 707 extern boolean_t apic_cpu_in_range(int cpu); 708 extern int apic_check_msi_support(); 709 extern apic_irq_t *apic_find_irq(dev_info_t *dip, struct intrspec *ispec, 710 int type); 711 extern int apic_navail_vector(dev_info_t *dip, int pri); 712 extern int apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, 713 int pri, int behavior); 714 extern int apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, 715 int pri, int behavior); 716 extern void apic_free_vectors(dev_info_t *dip, int inum, int count, int pri, 717 int type); 718 extern int apic_get_vector_intr_info(int vecirq, 719 apic_get_intr_t *intr_params_p); 720 extern uchar_t apic_find_multi_vectors(int pri, int count); 721 extern int apic_setup_io_intr(void *p, int irq, boolean_t deferred); 722 extern uint32_t *mapin_apic(uint32_t addr, size_t len, int flags); 723 extern uint32_t *mapin_ioapic(uint32_t addr, size_t len, int flags); 724 extern void mapout_apic(caddr_t addr, size_t len); 725 extern void mapout_ioapic(caddr_t addr, size_t len); 726 extern uchar_t apic_modify_vector(uchar_t vector, int irq); 727 extern void apic_pci_msi_unconfigure(dev_info_t *rdip, int type, int inum); 728 extern void apic_pci_msi_disable_mode(dev_info_t *rdip, int type); 729 extern void apic_pci_msi_enable_mode(dev_info_t *rdip, int type, int inum); 730 extern void apic_pci_msi_enable_vector(dev_info_t *dip, int type, int inum, 731 int vector, int count, int target_apic_id); 732 extern char *apic_get_apic_type(); 733 extern uint16_t apic_get_apic_version(); 734 735 extern volatile uint32_t *apicadr; /* virtual addr of local APIC */ 736 extern int apic_forceload; 737 extern apic_cpus_info_t *apic_cpus; 738 #ifdef _MACHDEP 739 extern cpuset_t apic_cpumask; 740 #endif 741 extern uint_t apic_picinit_called; 742 extern uchar_t apic_ipltopri[MAXIPL+1]; 743 extern uchar_t apic_vector_to_irq[APIC_MAX_VECTOR+1]; 744 extern int apic_max_device_irq; 745 extern int apic_min_device_irq; 746 extern apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1]; 747 extern volatile uint32_t *apicioadr[MAX_IO_APIC]; 748 extern uchar_t apic_io_id[MAX_IO_APIC]; 749 extern lock_t apic_ioapic_lock; 750 extern uint32_t apic_physaddr[MAX_IO_APIC]; 751 extern kmutex_t airq_mutex; 752 extern int apic_first_avail_irq; 753 extern uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL]; 754 extern int apic_imcrp; 755 extern int apic_revector_pending; 756 extern char apic_level_intr[APIC_MAX_VECTOR+1]; 757 extern uchar_t apic_resv_vector[MAXIPL+1]; 758 extern int apic_sample_factor_redistribution; 759 extern int apic_int_busy_mark; 760 extern int apic_int_free_mark; 761 extern int apic_diff_for_redistribution; 762 extern int apic_poweroff_method; 763 extern int apic_enable_acpi; 764 extern int apic_nproc; 765 extern int apic_next_bind_cpu; 766 extern int apic_redistribute_sample_interval; 767 extern int apic_multi_msi_enable; 768 extern int apic_multi_msi_max; 769 extern int apic_msix_max; 770 extern int apic_sci_vect; 771 extern uchar_t apic_ipls[]; 772 773 774 #ifdef __cplusplus 775 } 776 #endif 777 778 #endif /* _SYS_APIC_APIC_H */ 779