1ae115bc7Smrj /* 2ae115bc7Smrj * CDDL HEADER START 3ae115bc7Smrj * 4ae115bc7Smrj * The contents of this file are subject to the terms of the 5ae115bc7Smrj * Common Development and Distribution License (the "License"). 6ae115bc7Smrj * You may not use this file except in compliance with the License. 7ae115bc7Smrj * 8ae115bc7Smrj * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9ae115bc7Smrj * or http://www.opensolaris.org/os/licensing. 10ae115bc7Smrj * See the License for the specific language governing permissions 11ae115bc7Smrj * and limitations under the License. 12ae115bc7Smrj * 13ae115bc7Smrj * When distributing Covered Code, include this CDDL HEADER in each 14ae115bc7Smrj * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15ae115bc7Smrj * If applicable, add the following below this CDDL HEADER, with the 16ae115bc7Smrj * fields enclosed by brackets "[]" replaced with your own identifying 17ae115bc7Smrj * information: Portions Copyright [yyyy] [name of copyright owner] 18ae115bc7Smrj * 19ae115bc7Smrj * CDDL HEADER END 20ae115bc7Smrj */ 21ae115bc7Smrj /* 22e7c3cdaeSjiang.liu@intel.com * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved. 23ae115bc7Smrj */ 24ae115bc7Smrj 25ae115bc7Smrj #ifndef _SYS_APIC_APIC_H 26ae115bc7Smrj #define _SYS_APIC_APIC_H 27ae115bc7Smrj 28ae115bc7Smrj #include <sys/psm_types.h> 29c8589f13Ssethg #include <sys/avintr.h> 30c8589f13Ssethg #include <sys/pci.h> 31ae115bc7Smrj 32ae115bc7Smrj #ifdef __cplusplus 33ae115bc7Smrj extern "C" { 34ae115bc7Smrj #endif 35ae115bc7Smrj 36ae115bc7Smrj #include <sys/psm_common.h> 37ae115bc7Smrj 382917a9c9Sschwartz #define APIC_PCPLUSMP_NAME "pcplusmp" 392917a9c9Sschwartz 40ae115bc7Smrj #define APIC_IO_ADDR 0xfec00000 41ae115bc7Smrj #define APIC_LOCAL_ADDR 0xfee00000 42ae115bc7Smrj #define APIC_IO_MEMLEN 0xf 43ae115bc7Smrj #define APIC_LOCAL_MEMLEN 0xfffff 44ae115bc7Smrj 45ae115bc7Smrj /* Local Unit ID register */ 46ae115bc7Smrj #define APIC_LID_REG 0x8 47ae115bc7Smrj 48ae115bc7Smrj /* I/o Unit Version Register */ 49ae115bc7Smrj #define APIC_VERS_REG 0xc 50ae115bc7Smrj 51ae115bc7Smrj /* Task Priority register */ 52ae115bc7Smrj #define APIC_TASK_REG 0x20 53ae115bc7Smrj 54ae115bc7Smrj /* EOI register */ 55ae115bc7Smrj #define APIC_EOI_REG 0x2c 56ae115bc7Smrj 57ae115bc7Smrj /* Remote Read register */ 58ae115bc7Smrj #define APIC_REMOTE_READ 0x30 59ae115bc7Smrj 60ae115bc7Smrj /* Logical Destination register */ 61ae115bc7Smrj #define APIC_DEST_REG 0x34 62ae115bc7Smrj 6387cc6269SSaurabh Misra /* Destination Format register */ 64ae115bc7Smrj #define APIC_FORMAT_REG 0x38 65ae115bc7Smrj 66ae115bc7Smrj /* Spurious Interrupt Vector register */ 67ae115bc7Smrj #define APIC_SPUR_INT_REG 0x3c 68ae115bc7Smrj 69ae115bc7Smrj /* Error Status Register */ 70ae115bc7Smrj #define APIC_ERROR_STATUS 0xa0 71ae115bc7Smrj 72ae115bc7Smrj /* Interrupt Command registers */ 73ae115bc7Smrj #define APIC_INT_CMD1 0xc0 74ae115bc7Smrj #define APIC_INT_CMD2 0xc4 75ae115bc7Smrj 76ae115bc7Smrj /* Timer Vector Table register */ 77ae115bc7Smrj #define APIC_LOCAL_TIMER 0xc8 78ae115bc7Smrj 79ae115bc7Smrj /* Local Interrupt Vector registers */ 80e3d60c9bSAdrian Frost #define APIC_CMCI_VECT 0xbc 81da2743adSdmick #define APIC_THERM_VECT 0xcc 82ae115bc7Smrj #define APIC_PCINT_VECT 0xd0 83ae115bc7Smrj #define APIC_INT_VECT0 0xd4 84ae115bc7Smrj #define APIC_INT_VECT1 0xd8 85ae115bc7Smrj #define APIC_ERR_VECT 0xdc 86ae115bc7Smrj 87ae115bc7Smrj /* IPL for performance counter interrupts */ 88ae115bc7Smrj #define APIC_PCINT_IPL 0xe 89ae115bc7Smrj #define APIC_LVT_MASK 0x10000 /* Mask bit (16) in LVT */ 90ae115bc7Smrj 91ae115bc7Smrj /* Initial Count register */ 92ae115bc7Smrj #define APIC_INIT_COUNT 0xe0 93ae115bc7Smrj 94ae115bc7Smrj /* Current Count Register */ 95ae115bc7Smrj #define APIC_CURR_COUNT 0xe4 96ae115bc7Smrj #define APIC_CURR_ADD 0x39 /* used for remote read command */ 97ae115bc7Smrj #define CURR_COUNT_OFFSET (sizeof (int32_t) * APIC_CURR_COUNT) 98ae115bc7Smrj 99ae115bc7Smrj /* Divider Configuration Register */ 100ae115bc7Smrj #define APIC_DIVIDE_REG 0xf8 101ae115bc7Smrj 102b6917abeSmishra /* Various mode for local APIC. Modes are mutually exclusive */ 103b6917abeSmishra #define APIC_IS_DISABLED 0x0 104b6917abeSmishra #define APIC_MODE_NOTSET 0x1 105b6917abeSmishra #define LOCAL_APIC 0x2 106b6917abeSmishra #define LOCAL_X2APIC 0x3 107b6917abeSmishra 1085d8efbbcSSaurabh Misra /* x2APIC SELF IPI Register */ 10987cc6269SSaurabh Misra #define X2APIC_SELF_IPI 0xFC 110b6917abeSmishra 111b6917abeSmishra /* General x2APIC constants used at various places */ 112e511d54dSSaurabh Misra #define APIC_SVR_SUPPRESS_BROADCAST_EOI 0x1000 113e511d54dSSaurabh Misra #define APIC_DIRECTED_EOI_BIT 0x1000000 114b6917abeSmishra 115ae115bc7Smrj /* IRR register */ 116ae115bc7Smrj #define APIC_IRR_REG 0x80 117ae115bc7Smrj 118ae115bc7Smrj /* ISR register */ 119ae115bc7Smrj #define APIC_ISR_REG 0x40 120ae115bc7Smrj 121ae115bc7Smrj #define APIC_IO_REG 0x0 122ae115bc7Smrj #define APIC_IO_DATA 0x4 123b6917abeSmishra #define APIC_IO_EOI 0x10 124ae115bc7Smrj 125ae115bc7Smrj /* Bit offset of APIC ID in LID_REG, INT_CMD and in DEST_REG */ 126ae115bc7Smrj #define APIC_ID_BIT_OFFSET 24 127ae115bc7Smrj #define APIC_ICR_ID_BIT_OFFSET 24 128ae115bc7Smrj #define APIC_LDR_ID_BIT_OFFSET 24 129ae115bc7Smrj 130ae115bc7Smrj /* 131ae115bc7Smrj * Choose between flat and clustered models by writing the following to the 132ae115bc7Smrj * FORMAT_REG. 82489 DX documentation seemed to suggest that writing 0 will 133ae115bc7Smrj * disable logical destination mode. 134ae115bc7Smrj * Does not seem to be in the docs for local APICs on the processors. 135ae115bc7Smrj */ 136ae115bc7Smrj #define APIC_FLAT_MODEL 0xFFFFFFFFUL 137ae115bc7Smrj #define APIC_CLUSTER_MODEL 0x0FFFFFFF 138ae115bc7Smrj 139ae115bc7Smrj /* 140ae115bc7Smrj * The commands which follow are window selectors written to APIC_IO_REG 141ae115bc7Smrj * before data can be read/written from/to APIC_IO_DATA 142ae115bc7Smrj */ 143ae115bc7Smrj 144ae115bc7Smrj #define APIC_ID_CMD 0x0 145ae115bc7Smrj #define APIC_VERS_CMD 0x1 146ae115bc7Smrj #define APIC_RDT_CMD 0x10 147ae115bc7Smrj #define APIC_RDT_CMD2 0x11 148ae115bc7Smrj 149ae115bc7Smrj #define APIC_INTEGRATED_VERS 0x10 /* 0x10 & above indicates integrated */ 150ae115bc7Smrj #define IOAPIC_VER_82489DX 0x01 /* Version ID: 82489DX External APIC */ 151ae115bc7Smrj 152ae115bc7Smrj #define APIC_INT_SPURIOUS -1 153ae115bc7Smrj 154ae115bc7Smrj #define APIC_IMCR_P1 0x22 /* int mode conf register port 1 */ 155ae115bc7Smrj #define APIC_IMCR_P2 0x23 /* int mode conf register port 2 */ 156ae115bc7Smrj #define APIC_IMCR_SELECT 0x70 /* select imcr by writing into P1 */ 157ae115bc7Smrj #define APIC_IMCR_PIC 0x0 /* selects PIC mode (8259-> BSP) */ 158ae115bc7Smrj #define APIC_IMCR_APIC 0x1 /* selects APIC mode (8259->APIC) */ 159ae115bc7Smrj 160ae115bc7Smrj #define APIC_CT_VECT 0x4ac /* conf table vector */ 161ae115bc7Smrj #define APIC_CT_SIZE 1024 /* conf table size */ 162ae115bc7Smrj 163ae115bc7Smrj #define APIC_ID 'MPAT' /* conf table signature */ 164ae115bc7Smrj 165c8589f13Ssethg #define VENID_AMD 0x1022 166c8589f13Ssethg #define DEVID_8131_IOAPIC 0x7451 167c8589f13Ssethg #define DEVID_8132_IOAPIC 0x7459 168c8589f13Ssethg 169c8589f13Ssethg #define IOAPICS_NODE_NAME "ioapics" 170c8589f13Ssethg #define IOAPICS_CHILD_NAME "ioapic" 171c8589f13Ssethg #define IOAPICS_DEV_TYPE "ioapic" 172c8589f13Ssethg #define IOAPICS_PROP_VENID "vendor-id" 173c8589f13Ssethg #define IOAPICS_PROP_DEVID "device-id" 174c8589f13Ssethg 175c8589f13Ssethg #define IS_CLASS_IOAPIC(b, s, p) \ 176c8589f13Ssethg ((b) == PCI_CLASS_PERIPH && (s) == PCI_PERIPH_PIC && \ 177c8589f13Ssethg ((p) == PCI_PERIPH_PIC_IF_IO_APIC || \ 178c8589f13Ssethg (p) == PCI_PERIPH_PIC_IF_IOX_APIC)) 179c8589f13Ssethg 180b6917abeSmishra /* 181b6917abeSmishra * These macros are used in frequently called routines like 182b6917abeSmishra * apic_intr_enter(). 183b6917abeSmishra */ 184b6917abeSmishra #define X2APIC_WRITE(reg, v) \ 185b6917abeSmishra wrmsr((REG_X2APIC_BASE_MSR + (reg >> 2)), v) 186b6917abeSmishra 187b6917abeSmishra #define LOCAL_APIC_WRITE_REG(reg, v) \ 188b6917abeSmishra apicadr[reg] = v 189ae115bc7Smrj 190ae115bc7Smrj /* 191ae115bc7Smrj * MP floating pointer structure defined in Intel MP Spec 1.1 192ae115bc7Smrj */ 193ae115bc7Smrj struct apic_mpfps_hdr { 194ae115bc7Smrj uint32_t mpfps_sig; /* _MP_ (0x5F4D505F) */ 195ae115bc7Smrj uint32_t mpfps_mpct_paddr; /* paddr of MP configuration tbl */ 196ae115bc7Smrj uchar_t mpfps_length; /* in paragraph (16-bytes units) */ 197ae115bc7Smrj uchar_t mpfps_spec_rev; /* version number of MP spec */ 198ae115bc7Smrj uchar_t mpfps_checksum; /* checksum of complete structure */ 199ae115bc7Smrj uchar_t mpfps_featinfo1; /* mp feature info bytes 1 */ 200ae115bc7Smrj uchar_t mpfps_featinfo2; /* mp feature info bytes 2 */ 201ae115bc7Smrj uchar_t mpfps_featinfo3; /* mp feature info bytes 3 */ 202ae115bc7Smrj uchar_t mpfps_featinfo4; /* mp feature info bytes 4 */ 203ae115bc7Smrj uchar_t mpfps_featinfo5; /* mp feature info bytes 5 */ 204ae115bc7Smrj }; 205ae115bc7Smrj 206ae115bc7Smrj #define MPFPS_FEATINFO2_IMCRP 0x80 /* IMCRP presence bit */ 207ae115bc7Smrj 208ae115bc7Smrj #define APIC_MPS_OEM_ID_LEN 8 209ae115bc7Smrj #define APIC_MPS_PROD_ID_LEN 12 210ae115bc7Smrj 211ae115bc7Smrj struct apic_mp_cnf_hdr { 212ae115bc7Smrj uint_t mpcnf_sig; 213ae115bc7Smrj 214ae115bc7Smrj uint_t mpcnf_tbl_length: 16, 215ae115bc7Smrj mpcnf_spec: 8, 216ae115bc7Smrj mpcnf_cksum: 8; 217ae115bc7Smrj 218ae115bc7Smrj char mpcnf_oem_str[APIC_MPS_OEM_ID_LEN]; 219ae115bc7Smrj 220ae115bc7Smrj char mpcnf_prod_str[APIC_MPS_PROD_ID_LEN]; 221ae115bc7Smrj 222ae115bc7Smrj uint_t mpcnf_oem_ptr; 223ae115bc7Smrj 224ae115bc7Smrj uint_t mpcnf_oem_tbl_size: 16, 225ae115bc7Smrj mpcnf_entry_cnt: 16; 226ae115bc7Smrj 227ae115bc7Smrj uint_t mpcnf_local_apic; 228ae115bc7Smrj 229ae115bc7Smrj uint_t mpcnf_resv; 230ae115bc7Smrj }; 231ae115bc7Smrj 232ae115bc7Smrj struct apic_procent { 233ae115bc7Smrj uint_t proc_entry: 8, 234ae115bc7Smrj proc_apicid: 8, 235ae115bc7Smrj proc_version: 8, 236ae115bc7Smrj proc_cpuflags: 8; 237ae115bc7Smrj 238ae115bc7Smrj uint_t proc_stepping: 4, 239ae115bc7Smrj proc_model: 4, 240ae115bc7Smrj proc_family: 4, 241ae115bc7Smrj proc_type: 2, /* undocumented feature */ 242ae115bc7Smrj proc_resv1: 18; 243ae115bc7Smrj 244ae115bc7Smrj uint_t proc_feature; 245ae115bc7Smrj 246ae115bc7Smrj uint_t proc_resv2; 247ae115bc7Smrj 248ae115bc7Smrj uint_t proc_resv3; 249ae115bc7Smrj }; 250ae115bc7Smrj 251ae115bc7Smrj /* 252ae115bc7Smrj * proc_cpuflags definitions 253ae115bc7Smrj */ 254ae115bc7Smrj #define CPUFLAGS_EN 1 /* if not set, this processor is unusable */ 255ae115bc7Smrj #define CPUFLAGS_BP 2 /* set if this is the bootstrap processor */ 256ae115bc7Smrj 257ae115bc7Smrj 258ae115bc7Smrj struct apic_bus { 259ae115bc7Smrj uchar_t bus_entry; 260ae115bc7Smrj uchar_t bus_id; 261ae115bc7Smrj ushort_t bus_str1; 262ae115bc7Smrj uint_t bus_str2; 263ae115bc7Smrj }; 264ae115bc7Smrj 265ae115bc7Smrj struct apic_io_entry { 266ae115bc7Smrj uint_t io_entry: 8, 267ae115bc7Smrj io_apicid: 8, 268ae115bc7Smrj io_version: 8, 269ae115bc7Smrj io_flags: 8; 270ae115bc7Smrj 271ae115bc7Smrj uint_t io_apic_addr; 272ae115bc7Smrj }; 273ae115bc7Smrj 274ae115bc7Smrj #define IOAPIC_FLAGS_EN 0x01 /* this I/O apic is enable or not */ 275ae115bc7Smrj 276ae115bc7Smrj #define MAX_IO_APIC 32 /* maximum # of IOAPICs supported */ 277ae115bc7Smrj 278ae115bc7Smrj struct apic_io_intr { 279ae115bc7Smrj uint_t intr_entry: 8, 280ae115bc7Smrj intr_type: 8, 281ae115bc7Smrj intr_po: 2, 282ae115bc7Smrj intr_el: 2, 283ae115bc7Smrj intr_resv: 12; 284ae115bc7Smrj 285ae115bc7Smrj uint_t intr_busid: 8, 286ae115bc7Smrj intr_irq: 8, 287ae115bc7Smrj intr_destid: 8, 288ae115bc7Smrj intr_destintin: 8; 289ae115bc7Smrj }; 290ae115bc7Smrj 291ae115bc7Smrj /* 292ae115bc7Smrj * intr_type definitions 293ae115bc7Smrj */ 294ae115bc7Smrj #define IO_INTR_INT 0x00 295ae115bc7Smrj #define IO_INTR_NMI 0x01 296ae115bc7Smrj #define IO_INTR_SMI 0x02 297ae115bc7Smrj #define IO_INTR_EXTINT 0x03 298ae115bc7Smrj 299ae115bc7Smrj /* 300ae115bc7Smrj * destination APIC ID 301ae115bc7Smrj */ 302ae115bc7Smrj #define INTR_ALL_APIC 0xff 303ae115bc7Smrj 304ae115bc7Smrj 305ae115bc7Smrj /* local vector table */ 306ae115bc7Smrj #define AV_MASK 0x10000 307ae115bc7Smrj 308ae115bc7Smrj /* interrupt command register 32-63 */ 309ae115bc7Smrj #define AV_TOALL 0x7fffffff 310ae115bc7Smrj #define AV_HIGH_ORDER 0x40000000 311ae115bc7Smrj #define AV_IM_OFF 0x40000000 312ae115bc7Smrj 313ae115bc7Smrj /* interrupt command register 0-31 */ 314da2743adSdmick #define AV_DELIV_MODE 0x700 315da2743adSdmick 316ae115bc7Smrj #define AV_FIXED 0x000 317ae115bc7Smrj #define AV_LOPRI 0x100 318da2743adSdmick #define AV_SMI 0x200 319ae115bc7Smrj #define AV_REMOTE 0x300 320ae115bc7Smrj #define AV_NMI 0x400 321ae115bc7Smrj #define AV_RESET 0x500 322ae115bc7Smrj #define AV_STARTUP 0x600 323ae115bc7Smrj #define AV_EXTINT 0x700 324ae115bc7Smrj 325ae115bc7Smrj #define AV_PDEST 0x000 326ae115bc7Smrj #define AV_LDEST 0x800 327ae115bc7Smrj 328ae115bc7Smrj /* IO & Local APIC Bit Definitions */ 329ae115bc7Smrj #define RDT_VECTOR(x) ((uchar_t)((x) & 0xFF)) 330ae115bc7Smrj #define AV_PENDING 0x1000 331ae115bc7Smrj #define AV_ACTIVE_LOW 0x2000 /* only for integrated APIC */ 332ae115bc7Smrj #define AV_REMOTE_IRR 0x4000 /* IOAPIC RDT-specific */ 333ae115bc7Smrj #define AV_LEVEL 0x8000 334ae115bc7Smrj #define AV_DEASSERT AV_LEVEL 335ae115bc7Smrj #define AV_ASSERT 0xc000 336ae115bc7Smrj 337ae115bc7Smrj #define AV_READ_PENDING 0x10000 338ae115bc7Smrj #define AV_REMOTE_STATUS 0x20000 /* 1 = valid, 0 = invalid */ 339ae115bc7Smrj 340ae115bc7Smrj #define AV_SH_SELF 0x40000 /* Short hand for self */ 341ae115bc7Smrj #define AV_SH_ALL_INCSELF 0x80000 /* All processors */ 342ae115bc7Smrj #define AV_SH_ALL_EXCSELF 0xc0000 /* All excluding self */ 343ae115bc7Smrj /* spurious interrupt vector register */ 344ae115bc7Smrj #define AV_UNIT_ENABLE 0x100 345ae115bc7Smrj 346ae115bc7Smrj /* timer vector table */ 347ae115bc7Smrj #define AV_TIME 0x20000 /* Set timer mode to periodic */ 348ae115bc7Smrj 349ae115bc7Smrj #define APIC_MAXVAL 0xffffffffUL 350ae115bc7Smrj #define APIC_TIME_MIN 0x5000 351ae115bc7Smrj #define APIC_TIME_COUNT 0x4000 352ae115bc7Smrj 353ae115bc7Smrj /* 354ae115bc7Smrj * Range of the low byte value in apic_tick before starting calibration 355ae115bc7Smrj */ 356ae115bc7Smrj #define APIC_LB_MIN 0x60 357ae115bc7Smrj #define APIC_LB_MAX 0xe0 358ae115bc7Smrj 359ae115bc7Smrj #define APIC_MAX_VECTOR 255 360ae115bc7Smrj #define APIC_RESV_VECT 0x00 361ae115bc7Smrj #define APIC_RESV_IRQ 0xfe 362ae115bc7Smrj #define APIC_BASE_VECT 0x20 /* This will come in as interrupt 0 */ 363ae115bc7Smrj #define APIC_AVAIL_VECTOR (APIC_MAX_VECTOR+1-APIC_BASE_VECT) 364ae115bc7Smrj #define APIC_VECTOR_PER_IPL 0x10 /* # of vectors before PRI changes */ 365ae115bc7Smrj #define APIC_VECTOR(ipl) (apic_ipltopri[ipl] | APIC_RESV_VECT) 366ae115bc7Smrj #define APIC_VECTOR_MASK 0x0f 367ae115bc7Smrj #define APIC_HI_PRI_VECTS 2 /* vects reserved for hi pri reqs */ 368ae115bc7Smrj #define APIC_IPL_MASK 0xf0 369ae115bc7Smrj #define APIC_IPL_SHIFT 4 /* >> to get ipl part of vector */ 370ae115bc7Smrj #define APIC_FIRST_FREE_IRQ 0x10 371ae115bc7Smrj #define APIC_MAX_ISA_IRQ 15 372ae115bc7Smrj #define APIC_IPL0 0x0f /* let IDLE_IPL be the lowest */ 373ae115bc7Smrj #define APIC_IDLE_IPL 0x00 374ae115bc7Smrj 375ae115bc7Smrj #define APIC_MASK_ALL 0xf0 /* Mask all interrupts */ 376ae115bc7Smrj 377ae115bc7Smrj /* spurious interrupt vector */ 378ae115bc7Smrj #define APIC_SPUR_INTR 0xFF 379ae115bc7Smrj 380ae115bc7Smrj /* special or reserve vectors */ 381ae115bc7Smrj #define APIC_CHECK_RESERVE_VECTORS(v) \ 382a7639048Sjohnny (((v) == T_FASTTRAP) || ((v) == APIC_SPUR_INTR) || \ 383*eb5a5c78SSurya Prakki ((v) == T_SYSCALLINT) || ((v) == T_DTRACE_RET)) 384ae115bc7Smrj 385ae115bc7Smrj /* cmos shutdown code for BIOS */ 386ae115bc7Smrj #define BIOS_SHUTDOWN 0x0a 387ae115bc7Smrj 388ae115bc7Smrj /* define the entry types for BIOS information tables as defined in PC+MP */ 389ae115bc7Smrj #define APIC_CPU_ENTRY 0 390ae115bc7Smrj #define APIC_BUS_ENTRY 1 391ae115bc7Smrj #define APIC_IO_ENTRY 2 392ae115bc7Smrj #define APIC_IO_INTR_ENTRY 3 393ae115bc7Smrj #define APIC_LOCAL_INTR_ENTRY 4 394ae115bc7Smrj #define APIC_MPTBL_ADDR (639 * 1024) 395ae115bc7Smrj /* 396ae115bc7Smrj * The MP Floating Point structure could be in 1st 1KB of EBDA or last KB 397ae115bc7Smrj * of system base memory or in ROM between 0xF0000 and 0xFFFFF 398ae115bc7Smrj */ 399ae115bc7Smrj #define MPFPS_RAM_WIN_LEN 1024 400ae115bc7Smrj #define MPFPS_ROM_WIN_START (uint32_t)0xf0000 401ae115bc7Smrj #define MPFPS_ROM_WIN_LEN 0x10000 402ae115bc7Smrj 403ae115bc7Smrj #define EISA_LEVEL_CNTL 0x4D0 404ae115bc7Smrj 405ae115bc7Smrj /* definitions for apic_irq_table */ 406ae115bc7Smrj #define FREE_INDEX (short)-1 /* empty slot */ 407ae115bc7Smrj #define RESERVE_INDEX (short)-2 /* ipi, softintr, clkintr */ 408ae115bc7Smrj #define ACPI_INDEX (short)-3 /* ACPI */ 409ae115bc7Smrj #define MSI_INDEX (short)-4 /* MSI */ 410ae115bc7Smrj #define MSIX_INDEX (short)-5 /* MSI-X */ 411ae115bc7Smrj #define DEFAULT_INDEX (short)0x7FFF 412ae115bc7Smrj /* biggest positive no. to avoid conflict with actual index */ 413ae115bc7Smrj 414ae115bc7Smrj #define APIC_IS_MSI_OR_MSIX_INDEX(index) \ 415ae115bc7Smrj ((index) == MSI_INDEX || (index) == MSIX_INDEX) 416ae115bc7Smrj 417ae115bc7Smrj /* 418ae115bc7Smrj * definitions for MSI Address 419ae115bc7Smrj */ 420ae115bc7Smrj #define MSI_ADDR_HDR APIC_LOCAL_ADDR 421ae115bc7Smrj #define MSI_ADDR_DEST_SHIFT 12 /* Destination CPU's apic id */ 422ae115bc7Smrj #define MSI_ADDR_RH_FIXED 0x0 /* Redirection Hint Fixed */ 423ae115bc7Smrj #define MSI_ADDR_RH_LOPRI 0x1 /* Redirection Hint Lowest priority */ 424ae115bc7Smrj #define MSI_ADDR_RH_SHIFT 3 425ae115bc7Smrj #define MSI_ADDR_DM_PHYSICAL 0x0 /* Physical Destination Mode */ 426ae115bc7Smrj #define MSI_ADDR_DM_LOGICAL 0x1 /* Logical Destination Mode */ 427ae115bc7Smrj #define MSI_ADDR_DM_SHIFT 2 428ae115bc7Smrj 429ae115bc7Smrj /* 430e511d54dSSaurabh Misra * TM is either edge or level. 431e511d54dSSaurabh Misra */ 432e511d54dSSaurabh Misra #define TRIGGER_MODE_EDGE 0x0 /* edge sensitive */ 433e511d54dSSaurabh Misra #define TRIGGER_MODE_LEVEL 0x1 /* level sensitive */ 434e511d54dSSaurabh Misra 435e511d54dSSaurabh Misra /* 436ae115bc7Smrj * definitions for MSI Data 437ae115bc7Smrj */ 438ae115bc7Smrj #define MSI_DATA_DELIVERY_FIXED 0x0 /* Fixed delivery */ 439ae115bc7Smrj #define MSI_DATA_DELIVERY_LOPRI 0x1 /* Lowest priority delivery */ 440ae115bc7Smrj #define MSI_DATA_DELIVERY_SMI 0x2 441ae115bc7Smrj #define MSI_DATA_DELIVERY_NMI 0x4 442ae115bc7Smrj #define MSI_DATA_DELIVERY_INIT 0x5 443ae115bc7Smrj #define MSI_DATA_DELIVERY_EXTINT 0x7 444ae115bc7Smrj #define MSI_DATA_DELIVERY_SHIFT 8 445e511d54dSSaurabh Misra #define MSI_DATA_TM_EDGE TRIGGER_MODE_EDGE 446e511d54dSSaurabh Misra #define MSI_DATA_TM_LEVEL TRIGGER_MODE_LEVEL 447ae115bc7Smrj #define MSI_DATA_TM_SHIFT 15 448ae115bc7Smrj #define MSI_DATA_LEVEL_DEASSERT 0x0 449ae115bc7Smrj #define MSI_DATA_LEVEL_ASSERT 0x1 /* Edge always assert */ 450ae115bc7Smrj #define MSI_DATA_LEVEL_SHIFT 14 451ae115bc7Smrj 452ae115bc7Smrj /* 453ae115bc7Smrj * use to define each irq setup by the apic 454ae115bc7Smrj */ 455ae115bc7Smrj typedef struct apic_irq { 456ae115bc7Smrj short airq_mps_intr_index; /* index into mps interrupt entries */ 457ae115bc7Smrj /* table */ 458ae115bc7Smrj uchar_t airq_intin_no; 459ae115bc7Smrj uchar_t airq_ioapicindex; 460ae115bc7Smrj dev_info_t *airq_dip; /* device corresponding to this interrupt */ 461ae115bc7Smrj /* 462ae115bc7Smrj * IRQ could be shared (in H/W) in which case dip & major will be 463ae115bc7Smrj * for the one that was last added at this level. We cannot keep a 464ae115bc7Smrj * linked list as delspl does not tell us which device has just 465ae115bc7Smrj * been unloaded. For most servers where we are worried about 466ae115bc7Smrj * performance, interrupt should not be shared & should not be 467ae115bc7Smrj * a problem. This does not cause any correctness issue - dip is 468ae115bc7Smrj * used only as an optimisation to avoid going thru all the tables 469ae115bc7Smrj * in translate IRQ (which is always called twice due to brokenness 470ae115bc7Smrj * in the way IPLs are determined for devices). major is used only 471ae115bc7Smrj * to bind interrupts corresponding to the same device on the same 472ae115bc7Smrj * CPU. Not finding major will just cause it to be potentially bound 473ae115bc7Smrj * to another CPU. 474ae115bc7Smrj */ 475ae115bc7Smrj major_t airq_major; /* major number corresponding to the device */ 476ae115bc7Smrj ushort_t airq_rdt_entry; /* level, polarity & trig mode */ 4774e30c628SEvan Yan uint32_t airq_cpu; /* target CPU, non-reserved IRQ only */ 4784e30c628SEvan Yan uint32_t airq_temp_cpu; /* non-reserved IRQ only, for disable_intr */ 479ae115bc7Smrj uchar_t airq_vector; /* Vector chosen for this irq */ 480ae115bc7Smrj uchar_t airq_share; /* number of interrupts at this irq */ 481ae115bc7Smrj uchar_t airq_share_id; /* id to identify source from irqno */ 482ae115bc7Smrj uchar_t airq_ipl; /* The ipl at which this is handled */ 483ae115bc7Smrj iflag_t airq_iflag; /* interrupt flag */ 484ae115bc7Smrj uchar_t airq_origirq; /* original irq passed in */ 485ae115bc7Smrj uint_t airq_busy; /* How frequently did clock find */ 486ae115bc7Smrj /* us in this */ 48786a9c507SGuoli Shu struct apic_irq *airq_next; /* chain of intpts sharing a vector */ 4883a634bfcSVikram Hegde void *airq_intrmap_private; /* intr remap private data */ 489ae115bc7Smrj } apic_irq_t; 490ae115bc7Smrj 491b6917abeSmishra #define IRQ_USER_BOUND 0x80000000 /* user requested bind if set in airq_cpu */ 492b6917abeSmishra #define IRQ_UNBOUND (uint32_t)-1 /* set in airq_cpu and airq_temp_cpu */ 493b6917abeSmishra #define IRQ_UNINIT (uint32_t)-2 /* in airq_temp_cpu till addspl called */ 494ae115bc7Smrj 495ae115bc7Smrj /* Macros to help deal with shared interrupts */ 496ae115bc7Smrj #define VIRTIRQ(irqno, share_id) ((irqno) | ((share_id) << 8)) 497ae115bc7Smrj #define IRQINDEX(irq) ((irq) & 0xFF) /* Mask to get irq from virtual irq */ 498ae115bc7Smrj 49978a542e2SSaurabh Misra /* 50078a542e2SSaurabh Misra * We align apic_cpus_info at 64-byte cache line boundary. Please make sure we 50178a542e2SSaurabh Misra * adjust APIC_PADSZ as we add/modify any member of apic_cpus_info. We also 50278a542e2SSaurabh Misra * don't want the compiler to optimize apic_cpus_info. 50378a542e2SSaurabh Misra */ 504a3114836SGerry Liu #define APIC_PADSZ 15 50578a542e2SSaurabh Misra 50678a542e2SSaurabh Misra #pragma pack(1) 507ae115bc7Smrj typedef struct apic_cpus_info { 508b6917abeSmishra uint32_t aci_local_id; 509ae115bc7Smrj uchar_t aci_local_ver; 510ae115bc7Smrj uchar_t aci_status; 511ae115bc7Smrj uchar_t aci_redistribute; /* Selected for redistribution */ 512ae115bc7Smrj uint_t aci_busy; /* Number of ticks we were in ISR */ 513ae115bc7Smrj uint_t aci_spur_cnt; /* # of spurious intpts on this cpu */ 514ae115bc7Smrj uint_t aci_ISR_in_progress; /* big enough to hold 1 << MAXIPL */ 515ae115bc7Smrj uchar_t aci_curipl; /* IPL of current ISR */ 516ae115bc7Smrj uchar_t aci_current[MAXIPL]; /* Current IRQ at each IPL */ 517ae115bc7Smrj uint32_t aci_bound; /* # of user requested binds ? */ 518ae115bc7Smrj uint32_t aci_temp_bound; /* # of non user IRQ binds */ 519a3114836SGerry Liu uint32_t aci_processor_id; /* Only used in ACPI mode. */ 520ae115bc7Smrj uchar_t aci_idle; /* The CPU is idle */ 521ae115bc7Smrj /* 52278a542e2SSaurabh Misra * Fill to make sure each struct is in separate 64-byte cache line. 523ae115bc7Smrj */ 52478a542e2SSaurabh Misra uchar_t aci_pad[APIC_PADSZ]; /* padding for 64-byte cache line */ 525ae115bc7Smrj } apic_cpus_info_t; 52678a542e2SSaurabh Misra #pragma pack() 527ae115bc7Smrj 528ae115bc7Smrj #define APIC_CPU_ONLINE 1 529ae115bc7Smrj #define APIC_CPU_INTR_ENABLE 2 530a3114836SGerry Liu #define APIC_CPU_FREE 4 /* APIC CPU slot is free */ 531a3114836SGerry Liu #define APIC_CPU_DIRTY 8 /* Slot was once used */ 532ae115bc7Smrj 533ae115bc7Smrj /* 534b6917abeSmishra * APIC ops to support various flavors of APIC like APIC and x2APIC. 535b6917abeSmishra */ 536b6917abeSmishra typedef struct apic_regs_ops { 537b6917abeSmishra uint64_t (*apic_read)(uint32_t); 538b6917abeSmishra void (*apic_write)(uint32_t, uint64_t); 539b6917abeSmishra int (*apic_get_pri)(void); 540b6917abeSmishra void (*apic_write_task_reg)(uint64_t); 541b6917abeSmishra void (*apic_write_int_cmd)(uint32_t, uint32_t); 542b6917abeSmishra void (*apic_send_eoi)(uint32_t); 543b6917abeSmishra } apic_reg_ops_t; 544b6917abeSmishra 545b6917abeSmishra /* 546bb8220baSVikram Hegde * interrupt structure for ioapic and msi 547bb8220baSVikram Hegde */ 548bb8220baSVikram Hegde typedef struct ioapic_rdt { 549bb8220baSVikram Hegde uint32_t ir_lo; 550bb8220baSVikram Hegde uint32_t ir_hi; 551bb8220baSVikram Hegde } ioapic_rdt_t; 552bb8220baSVikram Hegde 553bb8220baSVikram Hegde typedef struct msi_regs { 554bb8220baSVikram Hegde uint32_t mr_data; 555bb8220baSVikram Hegde uint64_t mr_addr; 556bb8220baSVikram Hegde }msi_regs_t; 557bb8220baSVikram Hegde 558bb8220baSVikram Hegde /* 559bb8220baSVikram Hegde * APIC ops to support intel interrupt remapping 560bb8220baSVikram Hegde */ 5613a634bfcSVikram Hegde typedef struct apic_intrmap_ops { 5623a634bfcSVikram Hegde int (*apic_intrmap_init)(int); 5633a634bfcSVikram Hegde void (*apic_intrmap_enable)(int); 5643a634bfcSVikram Hegde void (*apic_intrmap_alloc_entry)(apic_irq_t *); 5653a634bfcSVikram Hegde void (*apic_intrmap_map_entry)(apic_irq_t *, void *); 5663a634bfcSVikram Hegde void (*apic_intrmap_free_entry)(apic_irq_t *); 5673a634bfcSVikram Hegde void (*apic_intrmap_record_rdt)(apic_irq_t *, ioapic_rdt_t *); 5683a634bfcSVikram Hegde void (*apic_intrmap_record_msi)(apic_irq_t *, msi_regs_t *); 5693a634bfcSVikram Hegde } apic_intrmap_ops_t; 570bb8220baSVikram Hegde 571bb8220baSVikram Hegde /* 572ae115bc7Smrj * Various poweroff methods and ports & bits for them 573ae115bc7Smrj */ 574ae115bc7Smrj #define APIC_POWEROFF_NONE 0 575ae115bc7Smrj #define APIC_POWEROFF_VIA_RTC 1 576ae115bc7Smrj #define APIC_POWEROFF_VIA_ASPEN_BMC 2 577ae115bc7Smrj #define APIC_POWEROFF_VIA_SITKA_BMC 3 578ae115bc7Smrj 579ae115bc7Smrj /* For RTC */ 580ae115bc7Smrj #define RTC_REGA 0x0a 581ae115bc7Smrj #define PFR_REG 0x4a /* extended control register */ 582ae115bc7Smrj #define PAB_CBIT 0x08 583ae115bc7Smrj #define WF_FLAG 0x02 584ae115bc7Smrj #define KS_FLAG 0x01 585ae115bc7Smrj #define EXT_BANK 0x10 586ae115bc7Smrj 587ae115bc7Smrj /* For Aspen/Drake BMC */ 588ae115bc7Smrj 589ae115bc7Smrj #define CC_SMS_GET_STATUS 0x40 590ae115bc7Smrj #define CC_SMS_WR_START 0x41 591ae115bc7Smrj #define CC_SMS_WR_NEXT 0x42 592ae115bc7Smrj #define CC_SMS_WR_END 0x43 593ae115bc7Smrj 594ae115bc7Smrj #define MISMIC_DATA_REGISTER 0x0ca9 595ae115bc7Smrj #define MISMIC_CNTL_REGISTER 0x0caa 596ae115bc7Smrj #define MISMIC_FLAG_REGISTER 0x0cab 597ae115bc7Smrj 598ae115bc7Smrj #define MISMIC_BUSY_MASK 0x01 599ae115bc7Smrj 600ae115bc7Smrj /* For Sitka/Cabrillo BMC */ 601ae115bc7Smrj 602ae115bc7Smrj #define SMS_GET_STATUS 0x60 603ae115bc7Smrj #define SMS_WRITE_START 0x61 604ae115bc7Smrj #define SMS_WRITE_END 0x62 605ae115bc7Smrj 606ae115bc7Smrj #define SMS_DATA_REGISTER 0x0ca2 607ae115bc7Smrj #define SMS_STATUS_REGISTER 0x0ca3 608ae115bc7Smrj #define SMS_COMMAND_REGISTER 0x0ca3 609ae115bc7Smrj 610ae115bc7Smrj #define SMS_IBF_MASK 0x02 611ae115bc7Smrj #define SMS_STATE_MASK 0xc0 612ae115bc7Smrj 613ae115bc7Smrj #define SMS_IDLE_STATE 0x00 614ae115bc7Smrj #define SMS_READ_STATE 0x40 615ae115bc7Smrj #define SMS_WRITE_STATE 0x80 616ae115bc7Smrj #define SMS_ERROR_STATE 0xc0 617ae115bc7Smrj 618ae115bc7Smrj extern uint32_t ioapic_read(int ioapic_ix, uint32_t reg); 619ae115bc7Smrj extern void ioapic_write(int ioapic_ix, uint32_t reg, uint32_t value); 620b6917abeSmishra extern void ioapic_write_eoi(int ioapic_ix, uint32_t value); 621ae115bc7Smrj 622ae115bc7Smrj /* Macros for reading/writing the IOAPIC RDT entries */ 623ae115bc7Smrj #define READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin) \ 624ae115bc7Smrj ioapic_read(ioapic_ix, APIC_RDT_CMD + (2 * (ipin))) 625ae115bc7Smrj 626ae115bc7Smrj #define READ_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin) \ 627ae115bc7Smrj ioapic_read(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin))) 628ae115bc7Smrj 629ae115bc7Smrj #define WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin, value) \ 630ae115bc7Smrj ioapic_write(ioapic_ix, APIC_RDT_CMD + (2 * (ipin)), value) 631ae115bc7Smrj 632ae115bc7Smrj #define WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin, value) \ 633ae115bc7Smrj ioapic_write(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin)), value) 634ae115bc7Smrj 635ae115bc7Smrj /* Used by PSM_INTR_OP_GET_INTR to return device information. */ 636ae115bc7Smrj typedef struct { 637ae115bc7Smrj uint16_t avgi_req_flags; /* request flags - to kernel */ 638ae115bc7Smrj uint8_t avgi_num_devs; /* # devs on this ino - from kernel */ 639ae115bc7Smrj uint8_t avgi_vector; /* vector */ 640ae115bc7Smrj uint32_t avgi_cpu_id; /* cpu of interrupt - from kernel */ 641ae115bc7Smrj dev_info_t **avgi_dip_list; /* kmem_alloc'ed list of dev_infos. */ 642ae115bc7Smrj /* Contains num_devs elements. */ 643ae115bc7Smrj } apic_get_intr_t; 644ae115bc7Smrj 645ae115bc7Smrj /* Masks for avgi_req_flags. */ 646ae115bc7Smrj #define PSMGI_REQ_CPUID 0x1 /* Request CPU ID */ 647ae115bc7Smrj #define PSMGI_REQ_NUM_DEVS 0x2 /* Request num of devices on vector */ 648ae115bc7Smrj #define PSMGI_REQ_VECTOR 0x4 649ae115bc7Smrj #define PSMGI_REQ_GET_DEVS 0x8 /* Request device list */ 650ae115bc7Smrj #define PSMGI_REQ_ALL 0xf /* Request everything */ 651ae115bc7Smrj 652ae115bc7Smrj /* Other flags */ 653ae115bc7Smrj #define PSMGI_INTRBY_VEC 0 /* Vec passed. xlate to IRQ needed */ 654ae115bc7Smrj #define PSMGI_INTRBY_IRQ 0x8000 /* IRQ passed. no xlate needed */ 655ae115bc7Smrj #define PSMGI_INTRBY_FLAGS 0x8000 /* Mask for this flag */ 656ae115bc7Smrj 657ae115bc7Smrj /* 658ae115bc7Smrj * Use scaled-fixed-point arithmetic to calculate apic ticks. 659ae115bc7Smrj * Round when dividing (by adding half of divisor to dividend) 660ae115bc7Smrj * for one extra bit of precision. 661ae115bc7Smrj */ 662ae115bc7Smrj 663ae115bc7Smrj #define SF (1ULL<<20) /* Scaling Factor: scale by 2^20 */ 664ae115bc7Smrj #define APIC_TICKS_TO_NSECS(ticks) ((((int64_t)(ticks) * SF) + \ 665ae115bc7Smrj apic_ticks_per_SFnsecs / 2) / \ 666ae115bc7Smrj apic_ticks_per_SFnsecs); 667ae115bc7Smrj #define APIC_NSECS_TO_TICKS(nsecs) (((int64_t)(nsecs) * \ 668ae115bc7Smrj apic_ticks_per_SFnsecs + (SF/2)) / SF) 669ae115bc7Smrj 670ae115bc7Smrj extern int apic_verbose; 671ae115bc7Smrj 672ae115bc7Smrj /* Flag definitions for apic_verbose */ 673ae115bc7Smrj #define APIC_VERBOSE_IOAPIC_FLAG 0x00000001 674ae115bc7Smrj #define APIC_VERBOSE_IRQ_FLAG 0x00000002 675ae115bc7Smrj #define APIC_VERBOSE_POWEROFF_FLAG 0x00000004 676ae115bc7Smrj #define APIC_VERBOSE_POWEROFF_PAUSE_FLAG 0x00000008 677ae115bc7Smrj 678ae115bc7Smrj 679ae115bc7Smrj #define APIC_VERBOSE_IOAPIC(fmt) \ 680ae115bc7Smrj if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) \ 681ae115bc7Smrj cmn_err fmt; 682ae115bc7Smrj 6835d8efbbcSSaurabh Misra #define APIC_AV_PENDING_SET() \ 6845d8efbbcSSaurabh Misra while (apic_reg_ops->apic_read(APIC_INT_CMD1) & AV_PENDING) \ 6855d8efbbcSSaurabh Misra apic_ret(); 6865d8efbbcSSaurabh Misra 687ae115bc7Smrj #define APIC_VERBOSE_IRQ(fmt) \ 688ae115bc7Smrj if (apic_verbose & APIC_VERBOSE_IRQ_FLAG) \ 689ae115bc7Smrj cmn_err fmt; 690ae115bc7Smrj 691ae115bc7Smrj #define APIC_VERBOSE_POWEROFF(fmt) \ 692ae115bc7Smrj if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) \ 693ae115bc7Smrj prom_printf fmt; 694ae115bc7Smrj 695ae115bc7Smrj #ifdef DEBUG 696ae115bc7Smrj #define DENT 0x0001 697ae115bc7Smrj extern int apic_debug; 698ae115bc7Smrj /* 699ae115bc7Smrj * set apic_restrict_vector to the # of vectors we want to allow per range 700ae115bc7Smrj * useful in testing shared interrupt logic by setting it to 2 or 3 701ae115bc7Smrj */ 702ae115bc7Smrj extern int apic_restrict_vector; 703ae115bc7Smrj 704ae115bc7Smrj #define APIC_DEBUG_MSGBUFSIZE 2048 705ae115bc7Smrj extern int apic_debug_msgbuf[]; 706ae115bc7Smrj extern int apic_debug_msgbufindex; 707ae115bc7Smrj 708ae115bc7Smrj /* 709ae115bc7Smrj * Put "int" info into debug buffer. No MP consistency, but light weight. 710ae115bc7Smrj * Good enough for most debugging. 711ae115bc7Smrj */ 712ae115bc7Smrj #define APIC_DEBUG_BUF_PUT(x) \ 713ae115bc7Smrj apic_debug_msgbuf[apic_debug_msgbufindex++] = x; \ 714ae115bc7Smrj if (apic_debug_msgbufindex >= (APIC_DEBUG_MSGBUFSIZE - NCPU)) \ 715ae115bc7Smrj apic_debug_msgbufindex = 0; 716ae115bc7Smrj 717ae115bc7Smrj #endif /* DEBUG */ 718ae115bc7Smrj 719ae115bc7Smrj extern int apic_error; 720ae115bc7Smrj /* values which apic_error can take. Not catastrophic, but may help debug */ 721ae115bc7Smrj #define APIC_ERR_BOOT_EOI 0x1 722ae115bc7Smrj #define APIC_ERR_GET_IPIVECT_FAIL 0x2 723ae115bc7Smrj #define APIC_ERR_INVALID_INDEX 0x4 724ae115bc7Smrj #define APIC_ERR_MARK_VECTOR_FAIL 0x8 725ae115bc7Smrj #define APIC_ERR_APIC_ERROR 0x40000000 726ae115bc7Smrj #define APIC_ERR_NMI 0x80000000 727ae115bc7Smrj 728ae115bc7Smrj /* 729ae115bc7Smrj * ACPI definitions 730ae115bc7Smrj */ 731ae115bc7Smrj /* _PIC method arguments */ 732ae115bc7Smrj #define ACPI_PIC_MODE 0 733ae115bc7Smrj #define ACPI_APIC_MODE 1 734ae115bc7Smrj 735ae115bc7Smrj /* APIC error flags we care about */ 736ae115bc7Smrj #define APIC_SEND_CS_ERROR 0x01 737ae115bc7Smrj #define APIC_RECV_CS_ERROR 0x02 738ae115bc7Smrj #define APIC_CS_ERRORS (APIC_SEND_CS_ERROR|APIC_RECV_CS_ERROR) 739ae115bc7Smrj 740ae115bc7Smrj /* Maximum number of times to retry reprogramming at apic_intr_exit time */ 741ae115bc7Smrj #define APIC_REPROGRAM_MAX_TRIES 10000 742ae115bc7Smrj 743ae115bc7Smrj /* Parameter to ioapic_init_intr(): Should ioapic ints be masked? */ 744ae115bc7Smrj #define IOAPIC_MASK 1 745ae115bc7Smrj #define IOAPIC_NOMASK 0 746ae115bc7Smrj 747ae115bc7Smrj #define INTR_ROUND_ROBIN_WITH_AFFINITY 0 748ae115bc7Smrj #define INTR_ROUND_ROBIN 1 749ae115bc7Smrj #define INTR_LOWEST_PRIORITY 2 750ae115bc7Smrj 751ae115bc7Smrj 752ae115bc7Smrj 753ae115bc7Smrj struct ioapic_reprogram_data { 754ae115bc7Smrj boolean_t done; 755ae115bc7Smrj apic_irq_t *irqp; 756ae115bc7Smrj /* The CPU to which the int will be bound */ 757ae115bc7Smrj int bindcpu; 758ae115bc7Smrj /* # times the reprogram timeout was called */ 759ae115bc7Smrj unsigned tries; 760ae115bc7Smrj }; 761ae115bc7Smrj 762ae115bc7Smrj /* The irq # is implicit in the array index: */ 763ae115bc7Smrj extern struct ioapic_reprogram_data apic_reprogram_info[]; 764ae115bc7Smrj 765ae115bc7Smrj extern void apic_intr_exit(int ipl, int irq); 766b6917abeSmishra extern void x2apic_intr_exit(int ipl, int irq); 767ae115bc7Smrj extern int apic_probe_common(); 768ae115bc7Smrj extern void apic_init_common(); 769ae115bc7Smrj extern void ioapic_init_intr(); 770ae115bc7Smrj extern void ioapic_disable_redirection(); 771ae115bc7Smrj extern int apic_addspl_common(int irqno, int ipl, int min_ipl, int max_ipl); 772ae115bc7Smrj extern int apic_delspl_common(int irqno, int ipl, int min_ipl, int max_ipl); 773ae115bc7Smrj extern void apic_cleanup_busy(); 774ae115bc7Smrj extern void apic_intr_redistribute(); 775ae115bc7Smrj extern uchar_t apic_xlate_vector(uchar_t vector); 776ae115bc7Smrj extern uchar_t apic_allocate_vector(int ipl, int irq, int pri); 777ae115bc7Smrj extern void apic_free_vector(uchar_t vector); 778ae115bc7Smrj extern int apic_allocate_irq(int irq); 779b6917abeSmishra extern uint32_t apic_bind_intr(dev_info_t *dip, int irq, uchar_t ioapicid, 780ae115bc7Smrj uchar_t intin); 781ae115bc7Smrj extern int apic_rebind(apic_irq_t *irq_ptr, int bind_cpu, 782ae115bc7Smrj struct ioapic_reprogram_data *drep); 783ae115bc7Smrj extern int apic_rebind_all(apic_irq_t *irq_ptr, int bind_cpu); 784ae115bc7Smrj extern int apic_introp_xlate(dev_info_t *dip, struct intrspec *ispec, int type); 785ae115bc7Smrj extern int apic_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp, 786ae115bc7Smrj psm_intr_op_t intr_op, int *result); 7872df1fe9cSrandyf extern int apic_state(psm_state_request_t *); 788ae115bc7Smrj extern boolean_t apic_cpu_in_range(int cpu); 789ae115bc7Smrj extern int apic_check_msi_support(); 790ae115bc7Smrj extern apic_irq_t *apic_find_irq(dev_info_t *dip, struct intrspec *ispec, 791ae115bc7Smrj int type); 792ae115bc7Smrj extern int apic_navail_vector(dev_info_t *dip, int pri); 793a7639048Sjohnny extern int apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, 794a7639048Sjohnny int pri, int behavior); 795a7639048Sjohnny extern int apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, 796a7639048Sjohnny int pri, int behavior); 797ae115bc7Smrj extern void apic_free_vectors(dev_info_t *dip, int inum, int count, int pri, 798ae115bc7Smrj int type); 799843e1988Sjohnlev extern int apic_get_vector_intr_info(int vecirq, 800843e1988Sjohnlev apic_get_intr_t *intr_params_p); 801ae115bc7Smrj extern uchar_t apic_find_multi_vectors(int pri, int count); 802ae115bc7Smrj extern int apic_setup_io_intr(void *p, int irq, boolean_t deferred); 803ae115bc7Smrj extern uint32_t *mapin_apic(uint32_t addr, size_t len, int flags); 804ae115bc7Smrj extern uint32_t *mapin_ioapic(uint32_t addr, size_t len, int flags); 805ae115bc7Smrj extern void mapout_apic(caddr_t addr, size_t len); 806ae115bc7Smrj extern void mapout_ioapic(caddr_t addr, size_t len); 807ae115bc7Smrj extern uchar_t apic_modify_vector(uchar_t vector, int irq); 808a7639048Sjohnny extern void apic_pci_msi_unconfigure(dev_info_t *rdip, int type, int inum); 809a7639048Sjohnny extern void apic_pci_msi_disable_mode(dev_info_t *rdip, int type); 810a7639048Sjohnny extern void apic_pci_msi_enable_mode(dev_info_t *rdip, int type, int inum); 811bb8220baSVikram Hegde extern void apic_pci_msi_enable_vector(apic_irq_t *, int type, int inum, 812a7639048Sjohnny int vector, int count, int target_apic_id); 8132917a9c9Sschwartz extern char *apic_get_apic_type(); 8142917a9c9Sschwartz extern uint16_t apic_get_apic_version(); 815b6917abeSmishra extern void x2apic_send_ipi(); 816b6917abeSmishra extern void apic_ret(); 817b6917abeSmishra extern int apic_detect_x2apic(); 818b6917abeSmishra extern void apic_enable_x2apic(); 819325e77f4SSaurabh Misra extern int apic_local_mode(); 820b6917abeSmishra extern void apic_change_eoi(); 821b6917abeSmishra extern void apic_send_EOI(uint32_t); 822b6917abeSmishra extern void apic_send_directed_EOI(uint32_t); 823ae115bc7Smrj 824ae115bc7Smrj extern volatile uint32_t *apicadr; /* virtual addr of local APIC */ 825ae115bc7Smrj extern int apic_forceload; 826ae115bc7Smrj extern apic_cpus_info_t *apic_cpus; 827c8589f13Ssethg #ifdef _MACHDEP 828ae115bc7Smrj extern cpuset_t apic_cpumask; 829c8589f13Ssethg #endif 830843e1988Sjohnlev extern uint_t apic_picinit_called; 831ae115bc7Smrj extern uchar_t apic_ipltopri[MAXIPL+1]; 832ae115bc7Smrj extern uchar_t apic_vector_to_irq[APIC_MAX_VECTOR+1]; 833ae115bc7Smrj extern int apic_max_device_irq; 834ae115bc7Smrj extern int apic_min_device_irq; 835ae115bc7Smrj extern apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1]; 836ae115bc7Smrj extern volatile uint32_t *apicioadr[MAX_IO_APIC]; 837ae115bc7Smrj extern uchar_t apic_io_id[MAX_IO_APIC]; 838ae115bc7Smrj extern lock_t apic_ioapic_lock; 839ae115bc7Smrj extern uint32_t apic_physaddr[MAX_IO_APIC]; 840ae115bc7Smrj extern kmutex_t airq_mutex; 841ae115bc7Smrj extern int apic_first_avail_irq; 842ae115bc7Smrj extern uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL]; 843ae115bc7Smrj extern int apic_imcrp; 844ae115bc7Smrj extern int apic_revector_pending; 845ae115bc7Smrj extern char apic_level_intr[APIC_MAX_VECTOR+1]; 846ae115bc7Smrj extern uchar_t apic_resv_vector[MAXIPL+1]; 847ae115bc7Smrj extern int apic_sample_factor_redistribution; 848ae115bc7Smrj extern int apic_int_busy_mark; 849ae115bc7Smrj extern int apic_int_free_mark; 850ae115bc7Smrj extern int apic_diff_for_redistribution; 851ae115bc7Smrj extern int apic_poweroff_method; 852ae115bc7Smrj extern int apic_enable_acpi; 853ae115bc7Smrj extern int apic_nproc; 854a3114836SGerry Liu extern int apic_max_nproc; 855ae115bc7Smrj extern int apic_next_bind_cpu; 856ae115bc7Smrj extern int apic_redistribute_sample_interval; 857ae115bc7Smrj extern int apic_multi_msi_enable; 858ae115bc7Smrj extern int apic_sci_vect; 859c8589f13Ssethg extern uchar_t apic_ipls[]; 860b6917abeSmishra extern apic_reg_ops_t *apic_reg_ops; 861b6917abeSmishra extern int apic_mode; 862b6917abeSmishra extern void x2apic_update_psm(); 863325e77f4SSaurabh Misra extern void apic_change_ops(); 864325e77f4SSaurabh Misra extern void apic_common_send_ipi(int, int); 865e511d54dSSaurabh Misra extern void apic_set_directed_EOI_handler(); 866e511d54dSSaurabh Misra extern int apic_directed_EOI_supported(); 867ae115bc7Smrj 8683a634bfcSVikram Hegde extern apic_intrmap_ops_t *apic_vt_ops; 869ae115bc7Smrj 870ae115bc7Smrj #ifdef __cplusplus 871ae115bc7Smrj } 872ae115bc7Smrj #endif 873ae115bc7Smrj 874ae115bc7Smrj #endif /* _SYS_APIC_APIC_H */ 875