1ae115bc7Smrj /* 2ae115bc7Smrj * CDDL HEADER START 3ae115bc7Smrj * 4ae115bc7Smrj * The contents of this file are subject to the terms of the 5ae115bc7Smrj * Common Development and Distribution License (the "License"). 6ae115bc7Smrj * You may not use this file except in compliance with the License. 7ae115bc7Smrj * 8ae115bc7Smrj * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9ae115bc7Smrj * or http://www.opensolaris.org/os/licensing. 10ae115bc7Smrj * See the License for the specific language governing permissions 11ae115bc7Smrj * and limitations under the License. 12ae115bc7Smrj * 13ae115bc7Smrj * When distributing Covered Code, include this CDDL HEADER in each 14ae115bc7Smrj * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15ae115bc7Smrj * If applicable, add the following below this CDDL HEADER, with the 16ae115bc7Smrj * fields enclosed by brackets "[]" replaced with your own identifying 17ae115bc7Smrj * information: Portions Copyright [yyyy] [name of copyright owner] 18ae115bc7Smrj * 19ae115bc7Smrj * CDDL HEADER END 20ae115bc7Smrj */ 21ae115bc7Smrj /* 22a563a037Sbholler * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23ae115bc7Smrj * Use is subject to license terms. 24ae115bc7Smrj */ 25ae115bc7Smrj 26ae115bc7Smrj #ifndef _SYS_APIC_APIC_H 27ae115bc7Smrj #define _SYS_APIC_APIC_H 28ae115bc7Smrj 29ae115bc7Smrj #pragma ident "%Z%%M% %I% %E% SMI" 30ae115bc7Smrj 31ae115bc7Smrj #include <sys/psm_types.h> 32c8589f13Ssethg #include <sys/avintr.h> 33c8589f13Ssethg #include <sys/pci.h> 34ae115bc7Smrj 35ae115bc7Smrj #ifdef __cplusplus 36ae115bc7Smrj extern "C" { 37ae115bc7Smrj #endif 38ae115bc7Smrj 39ae115bc7Smrj #include <sys/psm_common.h> 40ae115bc7Smrj 412917a9c9Sschwartz #define APIC_PCPLUSMP_NAME "pcplusmp" 422917a9c9Sschwartz 43ae115bc7Smrj #define APIC_IO_ADDR 0xfec00000 44ae115bc7Smrj #define APIC_LOCAL_ADDR 0xfee00000 45ae115bc7Smrj #define APIC_IO_MEMLEN 0xf 46ae115bc7Smrj #define APIC_LOCAL_MEMLEN 0xfffff 47ae115bc7Smrj 48ae115bc7Smrj /* Local Unit ID register */ 49ae115bc7Smrj #define APIC_LID_REG 0x8 50ae115bc7Smrj 51ae115bc7Smrj /* I/o Unit Version Register */ 52ae115bc7Smrj #define APIC_VERS_REG 0xc 53ae115bc7Smrj 54ae115bc7Smrj /* Task Priority register */ 55ae115bc7Smrj #define APIC_TASK_REG 0x20 56ae115bc7Smrj 57ae115bc7Smrj /* EOI register */ 58ae115bc7Smrj #define APIC_EOI_REG 0x2c 59ae115bc7Smrj 60ae115bc7Smrj /* Remote Read register */ 61ae115bc7Smrj #define APIC_REMOTE_READ 0x30 62ae115bc7Smrj 63ae115bc7Smrj /* Logical Destination register */ 64ae115bc7Smrj #define APIC_DEST_REG 0x34 65ae115bc7Smrj 66ae115bc7Smrj /* Destination Format rgister */ 67ae115bc7Smrj #define APIC_FORMAT_REG 0x38 68ae115bc7Smrj 69ae115bc7Smrj /* Spurious Interrupt Vector register */ 70ae115bc7Smrj #define APIC_SPUR_INT_REG 0x3c 71ae115bc7Smrj 72ae115bc7Smrj /* Error Status Register */ 73ae115bc7Smrj #define APIC_ERROR_STATUS 0xa0 74ae115bc7Smrj 75ae115bc7Smrj /* Interrupt Command registers */ 76ae115bc7Smrj #define APIC_INT_CMD1 0xc0 77ae115bc7Smrj #define APIC_INT_CMD2 0xc4 78ae115bc7Smrj 79ae115bc7Smrj /* Timer Vector Table register */ 80ae115bc7Smrj #define APIC_LOCAL_TIMER 0xc8 81ae115bc7Smrj 82ae115bc7Smrj /* Local Interrupt Vector registers */ 83*da2743adSdmick #define APIC_THERM_VECT 0xcc 84ae115bc7Smrj #define APIC_PCINT_VECT 0xd0 85ae115bc7Smrj #define APIC_INT_VECT0 0xd4 86ae115bc7Smrj #define APIC_INT_VECT1 0xd8 87ae115bc7Smrj #define APIC_ERR_VECT 0xdc 88ae115bc7Smrj 89ae115bc7Smrj /* IPL for performance counter interrupts */ 90ae115bc7Smrj #define APIC_PCINT_IPL 0xe 91ae115bc7Smrj #define APIC_LVT_MASK 0x10000 /* Mask bit (16) in LVT */ 92ae115bc7Smrj 93ae115bc7Smrj /* Initial Count register */ 94ae115bc7Smrj #define APIC_INIT_COUNT 0xe0 95ae115bc7Smrj 96ae115bc7Smrj /* Current Count Register */ 97ae115bc7Smrj #define APIC_CURR_COUNT 0xe4 98ae115bc7Smrj #define APIC_CURR_ADD 0x39 /* used for remote read command */ 99ae115bc7Smrj #define CURR_COUNT_OFFSET (sizeof (int32_t) * APIC_CURR_COUNT) 100ae115bc7Smrj 101ae115bc7Smrj /* Divider Configuration Register */ 102ae115bc7Smrj #define APIC_DIVIDE_REG 0xf8 103ae115bc7Smrj 104ae115bc7Smrj /* IRR register */ 105ae115bc7Smrj #define APIC_IRR_REG 0x80 106ae115bc7Smrj 107ae115bc7Smrj /* ISR register */ 108ae115bc7Smrj #define APIC_ISR_REG 0x40 109ae115bc7Smrj 110ae115bc7Smrj #define APIC_IO_REG 0x0 111ae115bc7Smrj #define APIC_IO_DATA 0x4 112ae115bc7Smrj 113ae115bc7Smrj /* Bit offset of APIC ID in LID_REG, INT_CMD and in DEST_REG */ 114ae115bc7Smrj #define APIC_ID_BIT_OFFSET 24 115ae115bc7Smrj #define APIC_ICR_ID_BIT_OFFSET 24 116ae115bc7Smrj #define APIC_LDR_ID_BIT_OFFSET 24 117ae115bc7Smrj 118ae115bc7Smrj /* 119ae115bc7Smrj * Choose between flat and clustered models by writing the following to the 120ae115bc7Smrj * FORMAT_REG. 82489 DX documentation seemed to suggest that writing 0 will 121ae115bc7Smrj * disable logical destination mode. 122ae115bc7Smrj * Does not seem to be in the docs for local APICs on the processors. 123ae115bc7Smrj */ 124ae115bc7Smrj #define APIC_FLAT_MODEL 0xFFFFFFFFUL 125ae115bc7Smrj #define APIC_CLUSTER_MODEL 0x0FFFFFFF 126ae115bc7Smrj 127ae115bc7Smrj /* 128ae115bc7Smrj * The commands which follow are window selectors written to APIC_IO_REG 129ae115bc7Smrj * before data can be read/written from/to APIC_IO_DATA 130ae115bc7Smrj */ 131ae115bc7Smrj 132ae115bc7Smrj #define APIC_ID_CMD 0x0 133ae115bc7Smrj #define APIC_VERS_CMD 0x1 134ae115bc7Smrj #define APIC_RDT_CMD 0x10 135ae115bc7Smrj #define APIC_RDT_CMD2 0x11 136ae115bc7Smrj 137ae115bc7Smrj #define APIC_INTEGRATED_VERS 0x10 /* 0x10 & above indicates integrated */ 138ae115bc7Smrj #define IOAPIC_VER_82489DX 0x01 /* Version ID: 82489DX External APIC */ 139ae115bc7Smrj 140ae115bc7Smrj #define APIC_INT_SPURIOUS -1 141ae115bc7Smrj 142ae115bc7Smrj #define APIC_IMCR_P1 0x22 /* int mode conf register port 1 */ 143ae115bc7Smrj #define APIC_IMCR_P2 0x23 /* int mode conf register port 2 */ 144ae115bc7Smrj #define APIC_IMCR_SELECT 0x70 /* select imcr by writing into P1 */ 145ae115bc7Smrj #define APIC_IMCR_PIC 0x0 /* selects PIC mode (8259-> BSP) */ 146ae115bc7Smrj #define APIC_IMCR_APIC 0x1 /* selects APIC mode (8259->APIC) */ 147ae115bc7Smrj 148ae115bc7Smrj #define APIC_CT_VECT 0x4ac /* conf table vector */ 149ae115bc7Smrj #define APIC_CT_SIZE 1024 /* conf table size */ 150ae115bc7Smrj 151ae115bc7Smrj #define APIC_ID 'MPAT' /* conf table signature */ 152ae115bc7Smrj 153c8589f13Ssethg #define VENID_AMD 0x1022 154c8589f13Ssethg #define DEVID_8131_IOAPIC 0x7451 155c8589f13Ssethg #define DEVID_8132_IOAPIC 0x7459 156c8589f13Ssethg 157c8589f13Ssethg #define IOAPICS_NODE_NAME "ioapics" 158c8589f13Ssethg #define IOAPICS_CHILD_NAME "ioapic" 159c8589f13Ssethg #define IOAPICS_DEV_TYPE "ioapic" 160c8589f13Ssethg #define IOAPICS_PROP_VENID "vendor-id" 161c8589f13Ssethg #define IOAPICS_PROP_DEVID "device-id" 162c8589f13Ssethg 163c8589f13Ssethg #define IS_CLASS_IOAPIC(b, s, p) \ 164c8589f13Ssethg ((b) == PCI_CLASS_PERIPH && (s) == PCI_PERIPH_PIC && \ 165c8589f13Ssethg ((p) == PCI_PERIPH_PIC_IF_IO_APIC || \ 166c8589f13Ssethg (p) == PCI_PERIPH_PIC_IF_IOX_APIC)) 167c8589f13Ssethg 168ae115bc7Smrj 169ae115bc7Smrj /* 170ae115bc7Smrj * MP floating pointer structure defined in Intel MP Spec 1.1 171ae115bc7Smrj */ 172ae115bc7Smrj struct apic_mpfps_hdr { 173ae115bc7Smrj uint32_t mpfps_sig; /* _MP_ (0x5F4D505F) */ 174ae115bc7Smrj uint32_t mpfps_mpct_paddr; /* paddr of MP configuration tbl */ 175ae115bc7Smrj uchar_t mpfps_length; /* in paragraph (16-bytes units) */ 176ae115bc7Smrj uchar_t mpfps_spec_rev; /* version number of MP spec */ 177ae115bc7Smrj uchar_t mpfps_checksum; /* checksum of complete structure */ 178ae115bc7Smrj uchar_t mpfps_featinfo1; /* mp feature info bytes 1 */ 179ae115bc7Smrj uchar_t mpfps_featinfo2; /* mp feature info bytes 2 */ 180ae115bc7Smrj uchar_t mpfps_featinfo3; /* mp feature info bytes 3 */ 181ae115bc7Smrj uchar_t mpfps_featinfo4; /* mp feature info bytes 4 */ 182ae115bc7Smrj uchar_t mpfps_featinfo5; /* mp feature info bytes 5 */ 183ae115bc7Smrj }; 184ae115bc7Smrj 185ae115bc7Smrj #define MPFPS_FEATINFO2_IMCRP 0x80 /* IMCRP presence bit */ 186ae115bc7Smrj 187ae115bc7Smrj #define APIC_MPS_OEM_ID_LEN 8 188ae115bc7Smrj #define APIC_MPS_PROD_ID_LEN 12 189ae115bc7Smrj 190ae115bc7Smrj struct apic_mp_cnf_hdr { 191ae115bc7Smrj uint_t mpcnf_sig; 192ae115bc7Smrj 193ae115bc7Smrj uint_t mpcnf_tbl_length: 16, 194ae115bc7Smrj mpcnf_spec: 8, 195ae115bc7Smrj mpcnf_cksum: 8; 196ae115bc7Smrj 197ae115bc7Smrj char mpcnf_oem_str[APIC_MPS_OEM_ID_LEN]; 198ae115bc7Smrj 199ae115bc7Smrj char mpcnf_prod_str[APIC_MPS_PROD_ID_LEN]; 200ae115bc7Smrj 201ae115bc7Smrj uint_t mpcnf_oem_ptr; 202ae115bc7Smrj 203ae115bc7Smrj uint_t mpcnf_oem_tbl_size: 16, 204ae115bc7Smrj mpcnf_entry_cnt: 16; 205ae115bc7Smrj 206ae115bc7Smrj uint_t mpcnf_local_apic; 207ae115bc7Smrj 208ae115bc7Smrj uint_t mpcnf_resv; 209ae115bc7Smrj }; 210ae115bc7Smrj 211ae115bc7Smrj struct apic_procent { 212ae115bc7Smrj uint_t proc_entry: 8, 213ae115bc7Smrj proc_apicid: 8, 214ae115bc7Smrj proc_version: 8, 215ae115bc7Smrj proc_cpuflags: 8; 216ae115bc7Smrj 217ae115bc7Smrj uint_t proc_stepping: 4, 218ae115bc7Smrj proc_model: 4, 219ae115bc7Smrj proc_family: 4, 220ae115bc7Smrj proc_type: 2, /* undocumented feature */ 221ae115bc7Smrj proc_resv1: 18; 222ae115bc7Smrj 223ae115bc7Smrj uint_t proc_feature; 224ae115bc7Smrj 225ae115bc7Smrj uint_t proc_resv2; 226ae115bc7Smrj 227ae115bc7Smrj uint_t proc_resv3; 228ae115bc7Smrj }; 229ae115bc7Smrj 230ae115bc7Smrj /* 231ae115bc7Smrj * proc_cpuflags definitions 232ae115bc7Smrj */ 233ae115bc7Smrj #define CPUFLAGS_EN 1 /* if not set, this processor is unusable */ 234ae115bc7Smrj #define CPUFLAGS_BP 2 /* set if this is the bootstrap processor */ 235ae115bc7Smrj 236ae115bc7Smrj 237ae115bc7Smrj struct apic_bus { 238ae115bc7Smrj uchar_t bus_entry; 239ae115bc7Smrj uchar_t bus_id; 240ae115bc7Smrj ushort_t bus_str1; 241ae115bc7Smrj uint_t bus_str2; 242ae115bc7Smrj }; 243ae115bc7Smrj 244ae115bc7Smrj struct apic_io_entry { 245ae115bc7Smrj uint_t io_entry: 8, 246ae115bc7Smrj io_apicid: 8, 247ae115bc7Smrj io_version: 8, 248ae115bc7Smrj io_flags: 8; 249ae115bc7Smrj 250ae115bc7Smrj uint_t io_apic_addr; 251ae115bc7Smrj }; 252ae115bc7Smrj 253ae115bc7Smrj #define IOAPIC_FLAGS_EN 0x01 /* this I/O apic is enable or not */ 254ae115bc7Smrj 255ae115bc7Smrj #define MAX_IO_APIC 32 /* maximum # of IOAPICs supported */ 256ae115bc7Smrj 257ae115bc7Smrj struct apic_io_intr { 258ae115bc7Smrj uint_t intr_entry: 8, 259ae115bc7Smrj intr_type: 8, 260ae115bc7Smrj intr_po: 2, 261ae115bc7Smrj intr_el: 2, 262ae115bc7Smrj intr_resv: 12; 263ae115bc7Smrj 264ae115bc7Smrj uint_t intr_busid: 8, 265ae115bc7Smrj intr_irq: 8, 266ae115bc7Smrj intr_destid: 8, 267ae115bc7Smrj intr_destintin: 8; 268ae115bc7Smrj }; 269ae115bc7Smrj 270ae115bc7Smrj /* 271ae115bc7Smrj * intr_type definitions 272ae115bc7Smrj */ 273ae115bc7Smrj #define IO_INTR_INT 0x00 274ae115bc7Smrj #define IO_INTR_NMI 0x01 275ae115bc7Smrj #define IO_INTR_SMI 0x02 276ae115bc7Smrj #define IO_INTR_EXTINT 0x03 277ae115bc7Smrj 278ae115bc7Smrj /* 279ae115bc7Smrj * destination APIC ID 280ae115bc7Smrj */ 281ae115bc7Smrj #define INTR_ALL_APIC 0xff 282ae115bc7Smrj 283ae115bc7Smrj 284ae115bc7Smrj /* local vector table */ 285ae115bc7Smrj #define AV_MASK 0x10000 286ae115bc7Smrj 287ae115bc7Smrj /* interrupt command register 32-63 */ 288ae115bc7Smrj #define AV_TOALL 0x7fffffff 289ae115bc7Smrj #define AV_HIGH_ORDER 0x40000000 290ae115bc7Smrj #define AV_IM_OFF 0x40000000 291ae115bc7Smrj 292ae115bc7Smrj /* interrupt command register 0-31 */ 293*da2743adSdmick #define AV_DELIV_MODE 0x700 294*da2743adSdmick 295ae115bc7Smrj #define AV_FIXED 0x000 296ae115bc7Smrj #define AV_LOPRI 0x100 297*da2743adSdmick #define AV_SMI 0x200 298ae115bc7Smrj #define AV_REMOTE 0x300 299ae115bc7Smrj #define AV_NMI 0x400 300ae115bc7Smrj #define AV_RESET 0x500 301ae115bc7Smrj #define AV_STARTUP 0x600 302ae115bc7Smrj #define AV_EXTINT 0x700 303ae115bc7Smrj 304ae115bc7Smrj #define AV_PDEST 0x000 305ae115bc7Smrj #define AV_LDEST 0x800 306ae115bc7Smrj 307ae115bc7Smrj /* IO & Local APIC Bit Definitions */ 308ae115bc7Smrj #define RDT_VECTOR(x) ((uchar_t)((x) & 0xFF)) 309ae115bc7Smrj #define AV_PENDING 0x1000 310ae115bc7Smrj #define AV_ACTIVE_LOW 0x2000 /* only for integrated APIC */ 311ae115bc7Smrj #define AV_REMOTE_IRR 0x4000 /* IOAPIC RDT-specific */ 312ae115bc7Smrj #define AV_LEVEL 0x8000 313ae115bc7Smrj #define AV_DEASSERT AV_LEVEL 314ae115bc7Smrj #define AV_ASSERT 0xc000 315ae115bc7Smrj 316ae115bc7Smrj #define AV_READ_PENDING 0x10000 317ae115bc7Smrj #define AV_REMOTE_STATUS 0x20000 /* 1 = valid, 0 = invalid */ 318ae115bc7Smrj 319ae115bc7Smrj #define AV_SH_SELF 0x40000 /* Short hand for self */ 320ae115bc7Smrj #define AV_SH_ALL_INCSELF 0x80000 /* All processors */ 321ae115bc7Smrj #define AV_SH_ALL_EXCSELF 0xc0000 /* All excluding self */ 322ae115bc7Smrj /* spurious interrupt vector register */ 323ae115bc7Smrj #define AV_UNIT_ENABLE 0x100 324ae115bc7Smrj 325ae115bc7Smrj /* timer vector table */ 326ae115bc7Smrj #define AV_TIME 0x20000 /* Set timer mode to periodic */ 327ae115bc7Smrj 328ae115bc7Smrj #define APIC_MAXVAL 0xffffffffUL 329ae115bc7Smrj #define APIC_TIME_MIN 0x5000 330ae115bc7Smrj #define APIC_TIME_COUNT 0x4000 331ae115bc7Smrj 332ae115bc7Smrj /* 333ae115bc7Smrj * Range of the low byte value in apic_tick before starting calibration 334ae115bc7Smrj */ 335ae115bc7Smrj #define APIC_LB_MIN 0x60 336ae115bc7Smrj #define APIC_LB_MAX 0xe0 337ae115bc7Smrj 338ae115bc7Smrj #define APIC_MAX_VECTOR 255 339ae115bc7Smrj #define APIC_RESV_VECT 0x00 340ae115bc7Smrj #define APIC_RESV_IRQ 0xfe 341ae115bc7Smrj #define APIC_BASE_VECT 0x20 /* This will come in as interrupt 0 */ 342ae115bc7Smrj #define APIC_AVAIL_VECTOR (APIC_MAX_VECTOR+1-APIC_BASE_VECT) 343ae115bc7Smrj #define APIC_VECTOR_PER_IPL 0x10 /* # of vectors before PRI changes */ 344ae115bc7Smrj #define APIC_VECTOR(ipl) (apic_ipltopri[ipl] | APIC_RESV_VECT) 345ae115bc7Smrj #define APIC_VECTOR_MASK 0x0f 346ae115bc7Smrj #define APIC_HI_PRI_VECTS 2 /* vects reserved for hi pri reqs */ 347ae115bc7Smrj #define APIC_IPL_MASK 0xf0 348ae115bc7Smrj #define APIC_IPL_SHIFT 4 /* >> to get ipl part of vector */ 349ae115bc7Smrj #define APIC_FIRST_FREE_IRQ 0x10 350ae115bc7Smrj #define APIC_MAX_ISA_IRQ 15 351ae115bc7Smrj #define APIC_IPL0 0x0f /* let IDLE_IPL be the lowest */ 352ae115bc7Smrj #define APIC_IDLE_IPL 0x00 353ae115bc7Smrj 354ae115bc7Smrj #define APIC_MASK_ALL 0xf0 /* Mask all interrupts */ 355ae115bc7Smrj 356ae115bc7Smrj /* spurious interrupt vector */ 357ae115bc7Smrj #define APIC_SPUR_INTR 0xFF 358ae115bc7Smrj 359ae115bc7Smrj /* special or reserve vectors */ 360ae115bc7Smrj #define APIC_CHECK_RESERVE_VECTORS(v) \ 361a7639048Sjohnny (((v) == T_FASTTRAP) || ((v) == APIC_SPUR_INTR) || \ 362a7639048Sjohnny ((v) == T_SYSCALLINT) || ((v) == T_DTRACE_RET) || ((v) == T_INT80)) 363ae115bc7Smrj 364ae115bc7Smrj /* cmos shutdown code for BIOS */ 365ae115bc7Smrj #define BIOS_SHUTDOWN 0x0a 366ae115bc7Smrj 367ae115bc7Smrj /* define the entry types for BIOS information tables as defined in PC+MP */ 368ae115bc7Smrj #define APIC_CPU_ENTRY 0 369ae115bc7Smrj #define APIC_BUS_ENTRY 1 370ae115bc7Smrj #define APIC_IO_ENTRY 2 371ae115bc7Smrj #define APIC_IO_INTR_ENTRY 3 372ae115bc7Smrj #define APIC_LOCAL_INTR_ENTRY 4 373ae115bc7Smrj #define APIC_MPTBL_ADDR (639 * 1024) 374ae115bc7Smrj /* 375ae115bc7Smrj * The MP Floating Point structure could be in 1st 1KB of EBDA or last KB 376ae115bc7Smrj * of system base memory or in ROM between 0xF0000 and 0xFFFFF 377ae115bc7Smrj */ 378ae115bc7Smrj #define MPFPS_RAM_WIN_LEN 1024 379ae115bc7Smrj #define MPFPS_ROM_WIN_START (uint32_t)0xf0000 380ae115bc7Smrj #define MPFPS_ROM_WIN_LEN 0x10000 381ae115bc7Smrj 382ae115bc7Smrj #define EISA_LEVEL_CNTL 0x4D0 383ae115bc7Smrj 384ae115bc7Smrj /* definitions for apic_irq_table */ 385ae115bc7Smrj #define FREE_INDEX (short)-1 /* empty slot */ 386ae115bc7Smrj #define RESERVE_INDEX (short)-2 /* ipi, softintr, clkintr */ 387ae115bc7Smrj #define ACPI_INDEX (short)-3 /* ACPI */ 388ae115bc7Smrj #define MSI_INDEX (short)-4 /* MSI */ 389ae115bc7Smrj #define MSIX_INDEX (short)-5 /* MSI-X */ 390ae115bc7Smrj #define DEFAULT_INDEX (short)0x7FFF 391ae115bc7Smrj /* biggest positive no. to avoid conflict with actual index */ 392ae115bc7Smrj 393ae115bc7Smrj #define APIC_IS_MSI_OR_MSIX_INDEX(index) \ 394ae115bc7Smrj ((index) == MSI_INDEX || (index) == MSIX_INDEX) 395ae115bc7Smrj 396ae115bc7Smrj /* 397ae115bc7Smrj * definitions for MSI Address 398ae115bc7Smrj */ 399ae115bc7Smrj #define MSI_ADDR_HDR APIC_LOCAL_ADDR 400ae115bc7Smrj #define MSI_ADDR_DEST_SHIFT 12 /* Destination CPU's apic id */ 401ae115bc7Smrj #define MSI_ADDR_RH_FIXED 0x0 /* Redirection Hint Fixed */ 402ae115bc7Smrj #define MSI_ADDR_RH_LOPRI 0x1 /* Redirection Hint Lowest priority */ 403ae115bc7Smrj #define MSI_ADDR_RH_SHIFT 3 404ae115bc7Smrj #define MSI_ADDR_DM_PHYSICAL 0x0 /* Physical Destination Mode */ 405ae115bc7Smrj #define MSI_ADDR_DM_LOGICAL 0x1 /* Logical Destination Mode */ 406ae115bc7Smrj #define MSI_ADDR_DM_SHIFT 2 407ae115bc7Smrj 408ae115bc7Smrj /* 409ae115bc7Smrj * definitions for MSI Data 410ae115bc7Smrj */ 411ae115bc7Smrj #define MSI_DATA_DELIVERY_FIXED 0x0 /* Fixed delivery */ 412ae115bc7Smrj #define MSI_DATA_DELIVERY_LOPRI 0x1 /* Lowest priority delivery */ 413ae115bc7Smrj #define MSI_DATA_DELIVERY_SMI 0x2 414ae115bc7Smrj #define MSI_DATA_DELIVERY_NMI 0x4 415ae115bc7Smrj #define MSI_DATA_DELIVERY_INIT 0x5 416ae115bc7Smrj #define MSI_DATA_DELIVERY_EXTINT 0x7 417ae115bc7Smrj #define MSI_DATA_DELIVERY_SHIFT 8 418ae115bc7Smrj #define MSI_DATA_TM_EDGE 0x0 /* MSI is edge sensitive */ 419ae115bc7Smrj #define MSI_DATA_TM_LEVEL 0x1 /* level sensitive */ 420ae115bc7Smrj #define MSI_DATA_TM_SHIFT 15 421ae115bc7Smrj #define MSI_DATA_LEVEL_DEASSERT 0x0 422ae115bc7Smrj #define MSI_DATA_LEVEL_ASSERT 0x1 /* Edge always assert */ 423ae115bc7Smrj #define MSI_DATA_LEVEL_SHIFT 14 424ae115bc7Smrj 425ae115bc7Smrj /* 426ae115bc7Smrj * use to define each irq setup by the apic 427ae115bc7Smrj */ 428ae115bc7Smrj typedef struct apic_irq { 429ae115bc7Smrj short airq_mps_intr_index; /* index into mps interrupt entries */ 430ae115bc7Smrj /* table */ 431ae115bc7Smrj uchar_t airq_intin_no; 432ae115bc7Smrj uchar_t airq_ioapicindex; 433ae115bc7Smrj dev_info_t *airq_dip; /* device corresponding to this interrupt */ 434ae115bc7Smrj /* 435ae115bc7Smrj * IRQ could be shared (in H/W) in which case dip & major will be 436ae115bc7Smrj * for the one that was last added at this level. We cannot keep a 437ae115bc7Smrj * linked list as delspl does not tell us which device has just 438ae115bc7Smrj * been unloaded. For most servers where we are worried about 439ae115bc7Smrj * performance, interrupt should not be shared & should not be 440ae115bc7Smrj * a problem. This does not cause any correctness issue - dip is 441ae115bc7Smrj * used only as an optimisation to avoid going thru all the tables 442ae115bc7Smrj * in translate IRQ (which is always called twice due to brokenness 443ae115bc7Smrj * in the way IPLs are determined for devices). major is used only 444ae115bc7Smrj * to bind interrupts corresponding to the same device on the same 445ae115bc7Smrj * CPU. Not finding major will just cause it to be potentially bound 446ae115bc7Smrj * to another CPU. 447ae115bc7Smrj */ 448ae115bc7Smrj major_t airq_major; /* major number corresponding to the device */ 449ae115bc7Smrj ushort_t airq_rdt_entry; /* level, polarity & trig mode */ 450a563a037Sbholler ushort_t airq_cpu; /* Which CPU are we bound to ? */ 451a563a037Sbholler ushort_t airq_temp_cpu; /* Could be diff from cpu due to disable_intr */ 452ae115bc7Smrj uchar_t airq_vector; /* Vector chosen for this irq */ 453ae115bc7Smrj uchar_t airq_share; /* number of interrupts at this irq */ 454ae115bc7Smrj uchar_t airq_share_id; /* id to identify source from irqno */ 455ae115bc7Smrj uchar_t airq_ipl; /* The ipl at which this is handled */ 456ae115bc7Smrj iflag_t airq_iflag; /* interrupt flag */ 457ae115bc7Smrj uchar_t airq_origirq; /* original irq passed in */ 458ae115bc7Smrj uint_t airq_busy; /* How frequently did clock find */ 459ae115bc7Smrj /* us in this */ 460ae115bc7Smrj struct apic_irq *airq_next; /* chain of shared intpts */ 461ae115bc7Smrj } apic_irq_t; 462ae115bc7Smrj 463a563a037Sbholler #define IRQ_USER_BOUND 0x8000 /* user requested bind if set in airq_cpu */ 464a563a037Sbholler #define IRQ_UNBOUND (ushort_t)-1 /* set in airq_cpu and airq_temp_cpu */ 465a563a037Sbholler #define IRQ_UNINIT (ushort_t)-2 /* in airq_temp_cpu till addspl called */ 466ae115bc7Smrj 467ae115bc7Smrj /* Macros to help deal with shared interrupts */ 468ae115bc7Smrj #define VIRTIRQ(irqno, share_id) ((irqno) | ((share_id) << 8)) 469ae115bc7Smrj #define IRQINDEX(irq) ((irq) & 0xFF) /* Mask to get irq from virtual irq */ 470ae115bc7Smrj 471ae115bc7Smrj typedef struct apic_cpus_info { 472ae115bc7Smrj uchar_t aci_local_id; 473ae115bc7Smrj uchar_t aci_local_ver; 474ae115bc7Smrj uchar_t aci_status; 475ae115bc7Smrj uchar_t aci_redistribute; /* Selected for redistribution */ 476ae115bc7Smrj uint_t aci_busy; /* Number of ticks we were in ISR */ 477ae115bc7Smrj uint_t aci_spur_cnt; /* # of spurious intpts on this cpu */ 478ae115bc7Smrj uint_t aci_ISR_in_progress; /* big enough to hold 1 << MAXIPL */ 479ae115bc7Smrj uchar_t aci_curipl; /* IPL of current ISR */ 480ae115bc7Smrj uchar_t aci_current[MAXIPL]; /* Current IRQ at each IPL */ 481ae115bc7Smrj uint32_t aci_bound; /* # of user requested binds ? */ 482ae115bc7Smrj uint32_t aci_temp_bound; /* # of non user IRQ binds */ 483ae115bc7Smrj uchar_t aci_idle; /* The CPU is idle */ 484ae115bc7Smrj /* 485ae115bc7Smrj * fill to make sure each struct is in seperate cache line. 486ae115bc7Smrj * Or atleast that ISR_in_progress/curipl is not shared with something 487ae115bc7Smrj * that is read/written heavily by another CPU. 488ae115bc7Smrj * Given kmem_alloc guarantees alignment to 8 bytes, having 8 489ae115bc7Smrj * bytes on each side will isolate us in a 16 byte cache line. 490ae115bc7Smrj */ 491ae115bc7Smrj } apic_cpus_info_t; 492ae115bc7Smrj 493ae115bc7Smrj #define APIC_CPU_ONLINE 1 494ae115bc7Smrj #define APIC_CPU_INTR_ENABLE 2 495ae115bc7Smrj 496ae115bc7Smrj /* 497ae115bc7Smrj * Various poweroff methods and ports & bits for them 498ae115bc7Smrj */ 499ae115bc7Smrj #define APIC_POWEROFF_NONE 0 500ae115bc7Smrj #define APIC_POWEROFF_VIA_RTC 1 501ae115bc7Smrj #define APIC_POWEROFF_VIA_ASPEN_BMC 2 502ae115bc7Smrj #define APIC_POWEROFF_VIA_SITKA_BMC 3 503ae115bc7Smrj 504ae115bc7Smrj /* For RTC */ 505ae115bc7Smrj #define RTC_REGA 0x0a 506ae115bc7Smrj #define PFR_REG 0x4a /* extended control register */ 507ae115bc7Smrj #define PAB_CBIT 0x08 508ae115bc7Smrj #define WF_FLAG 0x02 509ae115bc7Smrj #define KS_FLAG 0x01 510ae115bc7Smrj #define EXT_BANK 0x10 511ae115bc7Smrj 512ae115bc7Smrj /* For Aspen/Drake BMC */ 513ae115bc7Smrj 514ae115bc7Smrj #define CC_SMS_GET_STATUS 0x40 515ae115bc7Smrj #define CC_SMS_WR_START 0x41 516ae115bc7Smrj #define CC_SMS_WR_NEXT 0x42 517ae115bc7Smrj #define CC_SMS_WR_END 0x43 518ae115bc7Smrj 519ae115bc7Smrj #define MISMIC_DATA_REGISTER 0x0ca9 520ae115bc7Smrj #define MISMIC_CNTL_REGISTER 0x0caa 521ae115bc7Smrj #define MISMIC_FLAG_REGISTER 0x0cab 522ae115bc7Smrj 523ae115bc7Smrj #define MISMIC_BUSY_MASK 0x01 524ae115bc7Smrj 525ae115bc7Smrj /* For Sitka/Cabrillo BMC */ 526ae115bc7Smrj 527ae115bc7Smrj #define SMS_GET_STATUS 0x60 528ae115bc7Smrj #define SMS_WRITE_START 0x61 529ae115bc7Smrj #define SMS_WRITE_END 0x62 530ae115bc7Smrj 531ae115bc7Smrj #define SMS_DATA_REGISTER 0x0ca2 532ae115bc7Smrj #define SMS_STATUS_REGISTER 0x0ca3 533ae115bc7Smrj #define SMS_COMMAND_REGISTER 0x0ca3 534ae115bc7Smrj 535ae115bc7Smrj #define SMS_IBF_MASK 0x02 536ae115bc7Smrj #define SMS_STATE_MASK 0xc0 537ae115bc7Smrj 538ae115bc7Smrj #define SMS_IDLE_STATE 0x00 539ae115bc7Smrj #define SMS_READ_STATE 0x40 540ae115bc7Smrj #define SMS_WRITE_STATE 0x80 541ae115bc7Smrj #define SMS_ERROR_STATE 0xc0 542ae115bc7Smrj 543ae115bc7Smrj extern uint32_t ioapic_read(int ioapic_ix, uint32_t reg); 544ae115bc7Smrj extern void ioapic_write(int ioapic_ix, uint32_t reg, uint32_t value); 545ae115bc7Smrj 546ae115bc7Smrj /* Macros for reading/writing the IOAPIC RDT entries */ 547ae115bc7Smrj #define READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin) \ 548ae115bc7Smrj ioapic_read(ioapic_ix, APIC_RDT_CMD + (2 * (ipin))) 549ae115bc7Smrj 550ae115bc7Smrj #define READ_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin) \ 551ae115bc7Smrj ioapic_read(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin))) 552ae115bc7Smrj 553ae115bc7Smrj #define WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin, value) \ 554ae115bc7Smrj ioapic_write(ioapic_ix, APIC_RDT_CMD + (2 * (ipin)), value) 555ae115bc7Smrj 556ae115bc7Smrj #define WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin, value) \ 557ae115bc7Smrj ioapic_write(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin)), value) 558ae115bc7Smrj 559ae115bc7Smrj /* Used by PSM_INTR_OP_GET_INTR to return device information. */ 560ae115bc7Smrj typedef struct { 561ae115bc7Smrj uint16_t avgi_req_flags; /* request flags - to kernel */ 562ae115bc7Smrj uint8_t avgi_num_devs; /* # devs on this ino - from kernel */ 563ae115bc7Smrj uint8_t avgi_vector; /* vector */ 564ae115bc7Smrj uint32_t avgi_cpu_id; /* cpu of interrupt - from kernel */ 565ae115bc7Smrj dev_info_t **avgi_dip_list; /* kmem_alloc'ed list of dev_infos. */ 566ae115bc7Smrj /* Contains num_devs elements. */ 567ae115bc7Smrj } apic_get_intr_t; 568ae115bc7Smrj 569ae115bc7Smrj /* Masks for avgi_req_flags. */ 570ae115bc7Smrj #define PSMGI_REQ_CPUID 0x1 /* Request CPU ID */ 571ae115bc7Smrj #define PSMGI_REQ_NUM_DEVS 0x2 /* Request num of devices on vector */ 572ae115bc7Smrj #define PSMGI_REQ_VECTOR 0x4 573ae115bc7Smrj #define PSMGI_REQ_GET_DEVS 0x8 /* Request device list */ 574ae115bc7Smrj #define PSMGI_REQ_ALL 0xf /* Request everything */ 575ae115bc7Smrj 576ae115bc7Smrj /* Other flags */ 577ae115bc7Smrj #define PSMGI_INTRBY_VEC 0 /* Vec passed. xlate to IRQ needed */ 578ae115bc7Smrj #define PSMGI_INTRBY_IRQ 0x8000 /* IRQ passed. no xlate needed */ 579ae115bc7Smrj #define PSMGI_INTRBY_FLAGS 0x8000 /* Mask for this flag */ 580ae115bc7Smrj 581ae115bc7Smrj /* 582ae115bc7Smrj * Use scaled-fixed-point arithmetic to calculate apic ticks. 583ae115bc7Smrj * Round when dividing (by adding half of divisor to dividend) 584ae115bc7Smrj * for one extra bit of precision. 585ae115bc7Smrj */ 586ae115bc7Smrj 587ae115bc7Smrj #define SF (1ULL<<20) /* Scaling Factor: scale by 2^20 */ 588ae115bc7Smrj #define APIC_TICKS_TO_NSECS(ticks) ((((int64_t)(ticks) * SF) + \ 589ae115bc7Smrj apic_ticks_per_SFnsecs / 2) / \ 590ae115bc7Smrj apic_ticks_per_SFnsecs); 591ae115bc7Smrj #define APIC_NSECS_TO_TICKS(nsecs) (((int64_t)(nsecs) * \ 592ae115bc7Smrj apic_ticks_per_SFnsecs + (SF/2)) / SF) 593ae115bc7Smrj 594ae115bc7Smrj extern int apic_verbose; 595ae115bc7Smrj 596ae115bc7Smrj /* Flag definitions for apic_verbose */ 597ae115bc7Smrj #define APIC_VERBOSE_IOAPIC_FLAG 0x00000001 598ae115bc7Smrj #define APIC_VERBOSE_IRQ_FLAG 0x00000002 599ae115bc7Smrj #define APIC_VERBOSE_POWEROFF_FLAG 0x00000004 600ae115bc7Smrj #define APIC_VERBOSE_POWEROFF_PAUSE_FLAG 0x00000008 601ae115bc7Smrj 602ae115bc7Smrj 603ae115bc7Smrj #define APIC_VERBOSE_IOAPIC(fmt) \ 604ae115bc7Smrj if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) \ 605ae115bc7Smrj cmn_err fmt; 606ae115bc7Smrj 607ae115bc7Smrj #define APIC_VERBOSE_IRQ(fmt) \ 608ae115bc7Smrj if (apic_verbose & APIC_VERBOSE_IRQ_FLAG) \ 609ae115bc7Smrj cmn_err fmt; 610ae115bc7Smrj 611ae115bc7Smrj #define APIC_VERBOSE_POWEROFF(fmt) \ 612ae115bc7Smrj if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) \ 613ae115bc7Smrj prom_printf fmt; 614ae115bc7Smrj 615ae115bc7Smrj #ifdef DEBUG 616ae115bc7Smrj #define DENT 0x0001 617ae115bc7Smrj extern int apic_debug; 618ae115bc7Smrj /* 619ae115bc7Smrj * set apic_restrict_vector to the # of vectors we want to allow per range 620ae115bc7Smrj * useful in testing shared interrupt logic by setting it to 2 or 3 621ae115bc7Smrj */ 622ae115bc7Smrj extern int apic_restrict_vector; 623ae115bc7Smrj 624ae115bc7Smrj #define APIC_DEBUG_MSGBUFSIZE 2048 625ae115bc7Smrj extern int apic_debug_msgbuf[]; 626ae115bc7Smrj extern int apic_debug_msgbufindex; 627ae115bc7Smrj 628ae115bc7Smrj /* 629ae115bc7Smrj * Put "int" info into debug buffer. No MP consistency, but light weight. 630ae115bc7Smrj * Good enough for most debugging. 631ae115bc7Smrj */ 632ae115bc7Smrj #define APIC_DEBUG_BUF_PUT(x) \ 633ae115bc7Smrj apic_debug_msgbuf[apic_debug_msgbufindex++] = x; \ 634ae115bc7Smrj if (apic_debug_msgbufindex >= (APIC_DEBUG_MSGBUFSIZE - NCPU)) \ 635ae115bc7Smrj apic_debug_msgbufindex = 0; 636ae115bc7Smrj 637ae115bc7Smrj #endif /* DEBUG */ 638ae115bc7Smrj 639ae115bc7Smrj extern int apic_error; 640ae115bc7Smrj /* values which apic_error can take. Not catastrophic, but may help debug */ 641ae115bc7Smrj #define APIC_ERR_BOOT_EOI 0x1 642ae115bc7Smrj #define APIC_ERR_GET_IPIVECT_FAIL 0x2 643ae115bc7Smrj #define APIC_ERR_INVALID_INDEX 0x4 644ae115bc7Smrj #define APIC_ERR_MARK_VECTOR_FAIL 0x8 645ae115bc7Smrj #define APIC_ERR_APIC_ERROR 0x40000000 646ae115bc7Smrj #define APIC_ERR_NMI 0x80000000 647ae115bc7Smrj 648ae115bc7Smrj /* 649ae115bc7Smrj * ACPI definitions 650ae115bc7Smrj */ 651ae115bc7Smrj /* _PIC method arguments */ 652ae115bc7Smrj #define ACPI_PIC_MODE 0 653ae115bc7Smrj #define ACPI_APIC_MODE 1 654ae115bc7Smrj 655ae115bc7Smrj /* APIC error flags we care about */ 656ae115bc7Smrj #define APIC_SEND_CS_ERROR 0x01 657ae115bc7Smrj #define APIC_RECV_CS_ERROR 0x02 658ae115bc7Smrj #define APIC_CS_ERRORS (APIC_SEND_CS_ERROR|APIC_RECV_CS_ERROR) 659ae115bc7Smrj 660ae115bc7Smrj /* Maximum number of times to retry reprogramming at apic_intr_exit time */ 661ae115bc7Smrj #define APIC_REPROGRAM_MAX_TRIES 10000 662ae115bc7Smrj 663ae115bc7Smrj /* Parameter to ioapic_init_intr(): Should ioapic ints be masked? */ 664ae115bc7Smrj #define IOAPIC_MASK 1 665ae115bc7Smrj #define IOAPIC_NOMASK 0 666ae115bc7Smrj 667ae115bc7Smrj #define INTR_ROUND_ROBIN_WITH_AFFINITY 0 668ae115bc7Smrj #define INTR_ROUND_ROBIN 1 669ae115bc7Smrj #define INTR_LOWEST_PRIORITY 2 670ae115bc7Smrj 671ae115bc7Smrj 672ae115bc7Smrj 673ae115bc7Smrj struct ioapic_reprogram_data { 674ae115bc7Smrj boolean_t done; 675ae115bc7Smrj apic_irq_t *irqp; 676ae115bc7Smrj /* The CPU to which the int will be bound */ 677ae115bc7Smrj int bindcpu; 678ae115bc7Smrj /* # times the reprogram timeout was called */ 679ae115bc7Smrj unsigned tries; 680ae115bc7Smrj }; 681ae115bc7Smrj 682ae115bc7Smrj /* The irq # is implicit in the array index: */ 683ae115bc7Smrj extern struct ioapic_reprogram_data apic_reprogram_info[]; 684ae115bc7Smrj 685ae115bc7Smrj extern void apic_intr_exit(int ipl, int irq); 686ae115bc7Smrj extern int apic_probe_common(); 687ae115bc7Smrj extern void apic_init_common(); 688ae115bc7Smrj extern void ioapic_init_intr(); 689ae115bc7Smrj extern void ioapic_disable_redirection(); 690ae115bc7Smrj extern int apic_addspl_common(int irqno, int ipl, int min_ipl, int max_ipl); 691ae115bc7Smrj extern int apic_delspl_common(int irqno, int ipl, int min_ipl, int max_ipl); 692ae115bc7Smrj extern void apic_cleanup_busy(); 693ae115bc7Smrj extern void apic_intr_redistribute(); 694ae115bc7Smrj extern uchar_t apic_xlate_vector(uchar_t vector); 695ae115bc7Smrj extern uchar_t apic_allocate_vector(int ipl, int irq, int pri); 696ae115bc7Smrj extern void apic_free_vector(uchar_t vector); 697ae115bc7Smrj extern int apic_allocate_irq(int irq); 698a563a037Sbholler extern ushort_t apic_bind_intr(dev_info_t *dip, int irq, uchar_t ioapicid, 699ae115bc7Smrj uchar_t intin); 700ae115bc7Smrj extern int apic_rebind(apic_irq_t *irq_ptr, int bind_cpu, 701ae115bc7Smrj struct ioapic_reprogram_data *drep); 702ae115bc7Smrj extern int apic_rebind_all(apic_irq_t *irq_ptr, int bind_cpu); 703ae115bc7Smrj extern int apic_introp_xlate(dev_info_t *dip, struct intrspec *ispec, int type); 704ae115bc7Smrj extern int apic_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp, 705ae115bc7Smrj psm_intr_op_t intr_op, int *result); 7062df1fe9cSrandyf extern int apic_state(psm_state_request_t *); 707ae115bc7Smrj extern boolean_t apic_cpu_in_range(int cpu); 708ae115bc7Smrj extern int apic_check_msi_support(); 709ae115bc7Smrj extern apic_irq_t *apic_find_irq(dev_info_t *dip, struct intrspec *ispec, 710ae115bc7Smrj int type); 711ae115bc7Smrj extern int apic_navail_vector(dev_info_t *dip, int pri); 712a7639048Sjohnny extern int apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, 713a7639048Sjohnny int pri, int behavior); 714a7639048Sjohnny extern int apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, 715a7639048Sjohnny int pri, int behavior); 716ae115bc7Smrj extern void apic_free_vectors(dev_info_t *dip, int inum, int count, int pri, 717ae115bc7Smrj int type); 718843e1988Sjohnlev extern int apic_get_vector_intr_info(int vecirq, 719843e1988Sjohnlev apic_get_intr_t *intr_params_p); 720ae115bc7Smrj extern uchar_t apic_find_multi_vectors(int pri, int count); 721ae115bc7Smrj extern int apic_setup_io_intr(void *p, int irq, boolean_t deferred); 722ae115bc7Smrj extern uint32_t *mapin_apic(uint32_t addr, size_t len, int flags); 723ae115bc7Smrj extern uint32_t *mapin_ioapic(uint32_t addr, size_t len, int flags); 724ae115bc7Smrj extern void mapout_apic(caddr_t addr, size_t len); 725ae115bc7Smrj extern void mapout_ioapic(caddr_t addr, size_t len); 726ae115bc7Smrj extern uchar_t apic_modify_vector(uchar_t vector, int irq); 727a7639048Sjohnny extern void apic_pci_msi_unconfigure(dev_info_t *rdip, int type, int inum); 728a7639048Sjohnny extern void apic_pci_msi_disable_mode(dev_info_t *rdip, int type); 729a7639048Sjohnny extern void apic_pci_msi_enable_mode(dev_info_t *rdip, int type, int inum); 730a7639048Sjohnny extern void apic_pci_msi_enable_vector(dev_info_t *dip, int type, int inum, 731a7639048Sjohnny int vector, int count, int target_apic_id); 7322917a9c9Sschwartz extern char *apic_get_apic_type(); 7332917a9c9Sschwartz extern uint16_t apic_get_apic_version(); 734ae115bc7Smrj 735ae115bc7Smrj extern volatile uint32_t *apicadr; /* virtual addr of local APIC */ 736ae115bc7Smrj extern int apic_forceload; 737ae115bc7Smrj extern apic_cpus_info_t *apic_cpus; 738c8589f13Ssethg #ifdef _MACHDEP 739ae115bc7Smrj extern cpuset_t apic_cpumask; 740c8589f13Ssethg #endif 741843e1988Sjohnlev extern uint_t apic_picinit_called; 742ae115bc7Smrj extern uchar_t apic_ipltopri[MAXIPL+1]; 743ae115bc7Smrj extern uchar_t apic_vector_to_irq[APIC_MAX_VECTOR+1]; 744ae115bc7Smrj extern int apic_max_device_irq; 745ae115bc7Smrj extern int apic_min_device_irq; 746ae115bc7Smrj extern apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1]; 747ae115bc7Smrj extern volatile uint32_t *apicioadr[MAX_IO_APIC]; 748ae115bc7Smrj extern uchar_t apic_io_id[MAX_IO_APIC]; 749ae115bc7Smrj extern lock_t apic_ioapic_lock; 750ae115bc7Smrj extern uint32_t apic_physaddr[MAX_IO_APIC]; 751ae115bc7Smrj extern kmutex_t airq_mutex; 752ae115bc7Smrj extern int apic_first_avail_irq; 753ae115bc7Smrj extern uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL]; 754ae115bc7Smrj extern int apic_imcrp; 755ae115bc7Smrj extern int apic_revector_pending; 756ae115bc7Smrj extern char apic_level_intr[APIC_MAX_VECTOR+1]; 757ae115bc7Smrj extern uchar_t apic_resv_vector[MAXIPL+1]; 758ae115bc7Smrj extern int apic_sample_factor_redistribution; 759ae115bc7Smrj extern int apic_int_busy_mark; 760ae115bc7Smrj extern int apic_int_free_mark; 761ae115bc7Smrj extern int apic_diff_for_redistribution; 762ae115bc7Smrj extern int apic_poweroff_method; 763ae115bc7Smrj extern int apic_enable_acpi; 764ae115bc7Smrj extern int apic_nproc; 765ae115bc7Smrj extern int apic_next_bind_cpu; 766ae115bc7Smrj extern int apic_redistribute_sample_interval; 767ae115bc7Smrj extern int apic_multi_msi_enable; 768ae115bc7Smrj extern int apic_multi_msi_max; 769a7639048Sjohnny extern int apic_msix_max; 770ae115bc7Smrj extern int apic_sci_vect; 771c8589f13Ssethg extern uchar_t apic_ipls[]; 772ae115bc7Smrj 773ae115bc7Smrj 774ae115bc7Smrj #ifdef __cplusplus 775ae115bc7Smrj } 776ae115bc7Smrj #endif 777ae115bc7Smrj 778ae115bc7Smrj #endif /* _SYS_APIC_APIC_H */ 779