1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 26 /* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */ 27 /* Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T */ 28 /* All Rights Reserved */ 29 /* */ 30 /* Copyright (c) 1987, 1988 Microsoft Corporation */ 31 /* All Rights Reserved */ 32 /* */ 33 34 /* 35 * Copyright 2018 Joyent, Inc. 36 */ 37 38 #include <sys/types.h> 39 #include <sys/sysmacros.h> 40 #include <sys/param.h> 41 #include <sys/signal.h> 42 #include <sys/systm.h> 43 #include <sys/user.h> 44 #include <sys/proc.h> 45 #include <sys/disp.h> 46 #include <sys/class.h> 47 #include <sys/core.h> 48 #include <sys/syscall.h> 49 #include <sys/cpuvar.h> 50 #include <sys/vm.h> 51 #include <sys/sysinfo.h> 52 #include <sys/fault.h> 53 #include <sys/stack.h> 54 #include <sys/psw.h> 55 #include <sys/regset.h> 56 #include <sys/fp.h> 57 #include <sys/trap.h> 58 #include <sys/kmem.h> 59 #include <sys/vtrace.h> 60 #include <sys/cmn_err.h> 61 #include <sys/prsystm.h> 62 #include <sys/mutex_impl.h> 63 #include <sys/machsystm.h> 64 #include <sys/archsystm.h> 65 #include <sys/sdt.h> 66 #include <sys/avintr.h> 67 #include <sys/kobj.h> 68 69 #include <vm/hat.h> 70 71 #include <vm/seg_kmem.h> 72 #include <vm/as.h> 73 #include <vm/seg.h> 74 #include <vm/hat_pte.h> 75 #include <vm/hat_i86.h> 76 77 #include <sys/procfs.h> 78 79 #include <sys/reboot.h> 80 #include <sys/debug.h> 81 #include <sys/debugreg.h> 82 #include <sys/modctl.h> 83 #include <sys/aio_impl.h> 84 #include <sys/tnf.h> 85 #include <sys/tnf_probe.h> 86 #include <sys/cred.h> 87 #include <sys/mman.h> 88 #include <sys/x86_archext.h> 89 #include <sys/copyops.h> 90 #include <c2/audit.h> 91 #include <sys/ftrace.h> 92 #include <sys/panic.h> 93 #include <sys/traptrace.h> 94 #include <sys/ontrap.h> 95 #include <sys/cpc_impl.h> 96 #include <sys/bootconf.h> 97 #include <sys/bootinfo.h> 98 #include <sys/promif.h> 99 #include <sys/mach_mmu.h> 100 #if defined(__xpv) 101 #include <sys/hypervisor.h> 102 #endif 103 #include <sys/contract/process_impl.h> 104 105 #define USER 0x10000 /* user-mode flag added to trap type */ 106 107 static const char *trap_type_mnemonic[] = { 108 "de", "db", "2", "bp", 109 "of", "br", "ud", "nm", 110 "df", "9", "ts", "np", 111 "ss", "gp", "pf", "15", 112 "mf", "ac", "mc", "xf" 113 }; 114 115 static const char *trap_type[] = { 116 "Divide error", /* trap id 0 */ 117 "Debug", /* trap id 1 */ 118 "NMI interrupt", /* trap id 2 */ 119 "Breakpoint", /* trap id 3 */ 120 "Overflow", /* trap id 4 */ 121 "BOUND range exceeded", /* trap id 5 */ 122 "Invalid opcode", /* trap id 6 */ 123 "Device not available", /* trap id 7 */ 124 "Double fault", /* trap id 8 */ 125 "Coprocessor segment overrun", /* trap id 9 */ 126 "Invalid TSS", /* trap id 10 */ 127 "Segment not present", /* trap id 11 */ 128 "Stack segment fault", /* trap id 12 */ 129 "General protection", /* trap id 13 */ 130 "Page fault", /* trap id 14 */ 131 "Reserved", /* trap id 15 */ 132 "x87 floating point error", /* trap id 16 */ 133 "Alignment check", /* trap id 17 */ 134 "Machine check", /* trap id 18 */ 135 "SIMD floating point exception", /* trap id 19 */ 136 }; 137 138 #define TRAP_TYPES (sizeof (trap_type) / sizeof (trap_type[0])) 139 140 #define SLOW_SCALL_SIZE 2 141 #define FAST_SCALL_SIZE 2 142 143 int tudebug = 0; 144 int tudebugbpt = 0; 145 int tudebugfpe = 0; 146 int tudebugsse = 0; 147 148 #if defined(TRAPDEBUG) || defined(lint) 149 int tdebug = 0; 150 int lodebug = 0; 151 int faultdebug = 0; 152 #else 153 #define tdebug 0 154 #define lodebug 0 155 #define faultdebug 0 156 #endif /* defined(TRAPDEBUG) || defined(lint) */ 157 158 #if defined(TRAPTRACE) 159 /* 160 * trap trace record for cpu0 is allocated here. 161 * trap trace records for non-boot cpus are allocated in mp_startup_init(). 162 */ 163 static trap_trace_rec_t trap_tr0[TRAPTR_NENT]; 164 trap_trace_ctl_t trap_trace_ctl[NCPU] = { 165 { 166 (uintptr_t)trap_tr0, /* next record */ 167 (uintptr_t)trap_tr0, /* first record */ 168 (uintptr_t)(trap_tr0 + TRAPTR_NENT), /* limit */ 169 (uintptr_t)0 /* current */ 170 }, 171 }; 172 173 /* 174 * default trap buffer size 175 */ 176 size_t trap_trace_bufsize = TRAPTR_NENT * sizeof (trap_trace_rec_t); 177 int trap_trace_freeze = 0; 178 int trap_trace_off = 0; 179 180 /* 181 * A dummy TRAPTRACE entry to use after death. 182 */ 183 trap_trace_rec_t trap_trace_postmort; 184 185 static void dump_ttrace(void); 186 #endif /* TRAPTRACE */ 187 static void dumpregs(struct regs *); 188 static void showregs(uint_t, struct regs *, caddr_t); 189 static int kern_gpfault(struct regs *); 190 191 /*ARGSUSED*/ 192 static int 193 die(uint_t type, struct regs *rp, caddr_t addr, processorid_t cpuid) 194 { 195 struct panic_trap_info ti; 196 const char *trap_name, *trap_mnemonic; 197 198 if (type < TRAP_TYPES) { 199 trap_name = trap_type[type]; 200 trap_mnemonic = trap_type_mnemonic[type]; 201 } else { 202 trap_name = "trap"; 203 trap_mnemonic = "-"; 204 } 205 206 #ifdef TRAPTRACE 207 TRAPTRACE_FREEZE; 208 #endif 209 210 ti.trap_regs = rp; 211 ti.trap_type = type & ~USER; 212 ti.trap_addr = addr; 213 214 curthread->t_panic_trap = &ti; 215 216 if (type == T_PGFLT && addr < (caddr_t)kernelbase) { 217 panic("BAD TRAP: type=%x (#%s %s) rp=%p addr=%p " 218 "occurred in module \"%s\" due to %s", 219 type, trap_mnemonic, trap_name, (void *)rp, (void *)addr, 220 mod_containing_pc((caddr_t)rp->r_pc), 221 addr < (caddr_t)PAGESIZE ? 222 "a NULL pointer dereference" : 223 "an illegal access to a user address"); 224 } else 225 panic("BAD TRAP: type=%x (#%s %s) rp=%p addr=%p", 226 type, trap_mnemonic, trap_name, (void *)rp, (void *)addr); 227 return (0); 228 } 229 230 /* 231 * Rewrite the instruction at pc to be an int $T_SYSCALLINT instruction. 232 * 233 * int <vector> is two bytes: 0xCD <vector> 234 */ 235 236 static int 237 rewrite_syscall(caddr_t pc) 238 { 239 uchar_t instr[SLOW_SCALL_SIZE] = { 0xCD, T_SYSCALLINT }; 240 241 if (uwrite(curthread->t_procp, instr, SLOW_SCALL_SIZE, 242 (uintptr_t)pc) != 0) 243 return (1); 244 245 return (0); 246 } 247 248 /* 249 * Test to see if the instruction at pc is sysenter or syscall. The second 250 * argument should be the x86 feature flag corresponding to the expected 251 * instruction. 252 * 253 * sysenter is two bytes: 0x0F 0x34 254 * syscall is two bytes: 0x0F 0x05 255 * int $T_SYSCALLINT is two bytes: 0xCD 0x91 256 */ 257 258 static int 259 instr_is_other_syscall(caddr_t pc, int which) 260 { 261 uchar_t instr[FAST_SCALL_SIZE]; 262 263 ASSERT(which == X86FSET_SEP || which == X86FSET_ASYSC || which == 0xCD); 264 265 if (copyin_nowatch(pc, (caddr_t)instr, FAST_SCALL_SIZE) != 0) 266 return (0); 267 268 switch (which) { 269 case X86FSET_SEP: 270 if (instr[0] == 0x0F && instr[1] == 0x34) 271 return (1); 272 break; 273 case X86FSET_ASYSC: 274 if (instr[0] == 0x0F && instr[1] == 0x05) 275 return (1); 276 break; 277 case 0xCD: 278 if (instr[0] == 0xCD && instr[1] == T_SYSCALLINT) 279 return (1); 280 break; 281 } 282 283 return (0); 284 } 285 286 static const char * 287 syscall_insn_string(int syscall_insn) 288 { 289 switch (syscall_insn) { 290 case X86FSET_SEP: 291 return ("sysenter"); 292 case X86FSET_ASYSC: 293 return ("syscall"); 294 case 0xCD: 295 return ("int"); 296 default: 297 return ("Unknown"); 298 } 299 } 300 301 static int 302 ldt_rewrite_syscall(struct regs *rp, proc_t *p, int syscall_insn) 303 { 304 caddr_t linearpc; 305 int return_code = 0; 306 307 mutex_enter(&p->p_ldtlock); /* Must be held across linear_pc() */ 308 309 if (linear_pc(rp, p, &linearpc) == 0) { 310 311 /* 312 * If another thread beat us here, it already changed 313 * this site to the slower (int) syscall instruction. 314 */ 315 if (instr_is_other_syscall(linearpc, 0xCD)) { 316 return_code = 1; 317 } else if (instr_is_other_syscall(linearpc, syscall_insn)) { 318 319 if (rewrite_syscall(linearpc) == 0) { 320 return_code = 1; 321 } 322 #ifdef DEBUG 323 else 324 cmn_err(CE_WARN, "failed to rewrite %s " 325 "instruction in process %d", 326 syscall_insn_string(syscall_insn), 327 p->p_pid); 328 #endif /* DEBUG */ 329 } 330 } 331 332 mutex_exit(&p->p_ldtlock); /* Must be held across linear_pc() */ 333 334 return (return_code); 335 } 336 337 /* 338 * Test to see if the instruction at pc is a system call instruction. 339 * 340 * The bytes of an lcall instruction used for the syscall trap. 341 * static uchar_t lcall[7] = { 0x9a, 0, 0, 0, 0, 0x7, 0 }; 342 * static uchar_t lcallalt[7] = { 0x9a, 0, 0, 0, 0, 0x27, 0 }; 343 */ 344 345 #define LCALLSIZE 7 346 347 static int 348 instr_is_lcall_syscall(caddr_t pc) 349 { 350 uchar_t instr[LCALLSIZE]; 351 352 if (copyin_nowatch(pc, (caddr_t)instr, LCALLSIZE) == 0 && 353 instr[0] == 0x9a && 354 instr[1] == 0 && 355 instr[2] == 0 && 356 instr[3] == 0 && 357 instr[4] == 0 && 358 (instr[5] == 0x7 || instr[5] == 0x27) && 359 instr[6] == 0) 360 return (1); 361 362 return (0); 363 } 364 365 #ifdef __amd64 366 367 /* 368 * In the first revisions of amd64 CPUs produced by AMD, the LAHF and 369 * SAHF instructions were not implemented in 64-bit mode. Later revisions 370 * did implement these instructions. An extension to the cpuid instruction 371 * was added to check for the capability of executing these instructions 372 * in 64-bit mode. 373 * 374 * Intel originally did not implement these instructions in EM64T either, 375 * but added them in later revisions. 376 * 377 * So, there are different chip revisions by both vendors out there that 378 * may or may not implement these instructions. The easy solution is to 379 * just always emulate these instructions on demand. 380 * 381 * SAHF == store %ah in the lower 8 bits of %rflags (opcode 0x9e) 382 * LAHF == load the lower 8 bits of %rflags into %ah (opcode 0x9f) 383 */ 384 385 #define LSAHFSIZE 1 386 387 static int 388 instr_is_lsahf(caddr_t pc, uchar_t *instr) 389 { 390 if (copyin_nowatch(pc, (caddr_t)instr, LSAHFSIZE) == 0 && 391 (*instr == 0x9e || *instr == 0x9f)) 392 return (1); 393 return (0); 394 } 395 396 /* 397 * Emulate the LAHF and SAHF instructions. The reference manuals define 398 * these instructions to always load/store bit 1 as a 1, and bits 3 and 5 399 * as a 0. The other, defined, bits are copied (the PS_ICC bits and PS_P). 400 * 401 * Note that %ah is bits 8-15 of %rax. 402 */ 403 static void 404 emulate_lsahf(struct regs *rp, uchar_t instr) 405 { 406 if (instr == 0x9e) { 407 /* sahf. Copy bits from %ah to flags. */ 408 rp->r_ps = (rp->r_ps & ~0xff) | 409 ((rp->r_rax >> 8) & PSL_LSAHFMASK) | PS_MB1; 410 } else { 411 /* lahf. Copy bits from flags to %ah. */ 412 rp->r_rax = (rp->r_rax & ~0xff00) | 413 (((rp->r_ps & PSL_LSAHFMASK) | PS_MB1) << 8); 414 } 415 rp->r_pc += LSAHFSIZE; 416 } 417 #endif /* __amd64 */ 418 419 #ifdef OPTERON_ERRATUM_91 420 421 /* 422 * Test to see if the instruction at pc is a prefetch instruction. 423 * 424 * The first byte of prefetch instructions is always 0x0F. 425 * The second byte is 0x18 for regular prefetch or 0x0D for AMD 3dnow prefetch. 426 * The third byte (ModRM) contains the register field bits (bits 3-5). 427 * These bits must be between 0 and 3 inclusive for regular prefetch and 428 * 0 and 1 inclusive for AMD 3dnow prefetch. 429 * 430 * In 64-bit mode, there may be a one-byte REX prefex (0x40-0x4F). 431 */ 432 433 static int 434 cmp_to_prefetch(uchar_t *p) 435 { 436 #ifdef _LP64 437 if ((p[0] & 0xF0) == 0x40) /* 64-bit REX prefix */ 438 p++; 439 #endif 440 return ((p[0] == 0x0F && p[1] == 0x18 && ((p[2] >> 3) & 7) <= 3) || 441 (p[0] == 0x0F && p[1] == 0x0D && ((p[2] >> 3) & 7) <= 1)); 442 } 443 444 static int 445 instr_is_prefetch(caddr_t pc) 446 { 447 uchar_t instr[4]; /* optional REX prefix plus 3-byte opcode */ 448 449 return (copyin_nowatch(pc, instr, sizeof (instr)) == 0 && 450 cmp_to_prefetch(instr)); 451 } 452 453 #endif /* OPTERON_ERRATUM_91 */ 454 455 /* 456 * Called from the trap handler when a processor trap occurs. 457 * 458 * Note: All user-level traps that might call stop() must exit 459 * trap() by 'goto out' or by falling through. 460 * Note Also: trap() is usually called with interrupts enabled, (PS_IE == 1) 461 * however, there are paths that arrive here with PS_IE == 0 so special care 462 * must be taken in those cases. 463 */ 464 void 465 trap(struct regs *rp, caddr_t addr, processorid_t cpuid) 466 { 467 kthread_t *ct = curthread; 468 enum seg_rw rw; 469 unsigned type; 470 proc_t *p = ttoproc(ct); 471 klwp_t *lwp = ttolwp(ct); 472 uintptr_t lofault; 473 label_t *onfault; 474 faultcode_t pagefault(), res, errcode; 475 enum fault_type fault_type; 476 k_siginfo_t siginfo; 477 uint_t fault = 0; 478 int mstate; 479 int sicode = 0; 480 int watchcode; 481 int watchpage; 482 caddr_t vaddr; 483 size_t sz; 484 int ta; 485 #ifdef __amd64 486 uchar_t instr; 487 #endif 488 489 ASSERT_STACK_ALIGNED(); 490 491 type = rp->r_trapno; 492 CPU_STATS_ADDQ(CPU, sys, trap, 1); 493 ASSERT(ct->t_schedflag & TS_DONT_SWAP); 494 495 if (type == T_PGFLT) { 496 497 errcode = rp->r_err; 498 if (errcode & PF_ERR_WRITE) 499 rw = S_WRITE; 500 else if ((caddr_t)rp->r_pc == addr || 501 (mmu.pt_nx != 0 && (errcode & PF_ERR_EXEC))) 502 rw = S_EXEC; 503 else 504 rw = S_READ; 505 506 #if defined(__i386) 507 /* 508 * Pentium Pro work-around 509 */ 510 if ((errcode & PF_ERR_PROT) && pentiumpro_bug4046376) { 511 uint_t attr; 512 uint_t priv_violation; 513 uint_t access_violation; 514 515 if (hat_getattr(addr < (caddr_t)kernelbase ? 516 curproc->p_as->a_hat : kas.a_hat, addr, &attr) 517 == -1) { 518 errcode &= ~PF_ERR_PROT; 519 } else { 520 priv_violation = (errcode & PF_ERR_USER) && 521 !(attr & PROT_USER); 522 access_violation = (errcode & PF_ERR_WRITE) && 523 !(attr & PROT_WRITE); 524 if (!priv_violation && !access_violation) 525 goto cleanup; 526 } 527 } 528 #endif /* __i386 */ 529 530 } else if (type == T_SGLSTP && lwp != NULL) 531 lwp->lwp_pcb.pcb_drstat = (uintptr_t)addr; 532 533 if (tdebug) 534 showregs(type, rp, addr); 535 536 if (USERMODE(rp->r_cs)) { 537 /* 538 * Set up the current cred to use during this trap. u_cred 539 * no longer exists. t_cred is used instead. 540 * The current process credential applies to the thread for 541 * the entire trap. If trapping from the kernel, this 542 * should already be set up. 543 */ 544 if (ct->t_cred != p->p_cred) { 545 cred_t *oldcred = ct->t_cred; 546 /* 547 * DTrace accesses t_cred in probe context. t_cred 548 * must always be either NULL, or point to a valid, 549 * allocated cred structure. 550 */ 551 ct->t_cred = crgetcred(); 552 crfree(oldcred); 553 } 554 ASSERT(lwp != NULL); 555 type |= USER; 556 ASSERT(lwptoregs(lwp) == rp); 557 lwp->lwp_state = LWP_SYS; 558 559 switch (type) { 560 case T_PGFLT + USER: 561 if ((caddr_t)rp->r_pc == addr) 562 mstate = LMS_TFAULT; 563 else 564 mstate = LMS_DFAULT; 565 break; 566 default: 567 mstate = LMS_TRAP; 568 break; 569 } 570 /* Kernel probe */ 571 TNF_PROBE_1(thread_state, "thread", /* CSTYLED */, 572 tnf_microstate, state, mstate); 573 mstate = new_mstate(ct, mstate); 574 575 bzero(&siginfo, sizeof (siginfo)); 576 } 577 578 switch (type) { 579 case T_PGFLT + USER: 580 case T_SGLSTP: 581 case T_SGLSTP + USER: 582 case T_BPTFLT + USER: 583 break; 584 585 default: 586 FTRACE_2("trap(): type=0x%lx, regs=0x%lx", 587 (ulong_t)type, (ulong_t)rp); 588 break; 589 } 590 591 switch (type) { 592 case T_SIMDFPE: 593 /* Make sure we enable interrupts before die()ing */ 594 sti(); /* The SIMD exception comes in via cmninttrap */ 595 /*FALLTHROUGH*/ 596 default: 597 if (type & USER) { 598 if (tudebug) 599 showregs(type, rp, (caddr_t)0); 600 printf("trap: Unknown trap type %d in user mode\n", 601 type & ~USER); 602 siginfo.si_signo = SIGILL; 603 siginfo.si_code = ILL_ILLTRP; 604 siginfo.si_addr = (caddr_t)rp->r_pc; 605 siginfo.si_trapno = type & ~USER; 606 fault = FLTILL; 607 } else { 608 (void) die(type, rp, addr, cpuid); 609 /*NOTREACHED*/ 610 } 611 break; 612 613 case T_PGFLT: /* system page fault */ 614 /* 615 * If we're under on_trap() protection (see <sys/ontrap.h>), 616 * set ot_trap and bounce back to the on_trap() call site 617 * via the installed trampoline. 618 */ 619 if ((ct->t_ontrap != NULL) && 620 (ct->t_ontrap->ot_prot & OT_DATA_ACCESS)) { 621 ct->t_ontrap->ot_trap |= OT_DATA_ACCESS; 622 rp->r_pc = ct->t_ontrap->ot_trampoline; 623 goto cleanup; 624 } 625 626 /* 627 * If we have an Instruction fault in kernel mode, then that 628 * means we've tried to execute a user page (SMEP) or both of 629 * PAE and NXE are enabled. In either case, given that it's a 630 * kernel fault, we should panic immediately and not try to make 631 * any more forward progress. This indicates a bug in the 632 * kernel, which if execution continued, could be exploited to 633 * wreak havoc on the system. 634 */ 635 if (errcode & PF_ERR_EXEC) { 636 (void) die(type, rp, addr, cpuid); 637 } 638 639 /* 640 * We need to check if SMAP is in play. If SMAP is in play, then 641 * any access to a user page will show up as a protection 642 * violation. To see if SMAP is enabled we first check if it's a 643 * user address and whether we have the feature flag set. If we 644 * do and the interrupted registers do not allow for user 645 * accesses (PS_ACHK is not enabled), then we need to die 646 * immediately. 647 */ 648 if (addr < (caddr_t)kernelbase && 649 is_x86_feature(x86_featureset, X86FSET_SMAP) == B_TRUE && 650 (rp->r_ps & PS_ACHK) == 0) { 651 (void) die(type, rp, addr, cpuid); 652 } 653 654 /* 655 * See if we can handle as pagefault. Save lofault and onfault 656 * across this. Here we assume that an address less than 657 * KERNELBASE is a user fault. We can do this as copy.s 658 * routines verify that the starting address is less than 659 * KERNELBASE before starting and because we know that we 660 * always have KERNELBASE mapped as invalid to serve as a 661 * "barrier". 662 */ 663 lofault = ct->t_lofault; 664 onfault = ct->t_onfault; 665 ct->t_lofault = 0; 666 667 mstate = new_mstate(ct, LMS_KFAULT); 668 669 if (addr < (caddr_t)kernelbase) { 670 res = pagefault(addr, 671 (errcode & PF_ERR_PROT)? F_PROT: F_INVAL, rw, 0); 672 if (res == FC_NOMAP && 673 addr < p->p_usrstack && 674 grow(addr)) 675 res = 0; 676 } else { 677 res = pagefault(addr, 678 (errcode & PF_ERR_PROT)? F_PROT: F_INVAL, rw, 1); 679 } 680 (void) new_mstate(ct, mstate); 681 682 /* 683 * Restore lofault and onfault. If we resolved the fault, exit. 684 * If we didn't and lofault wasn't set, die. 685 */ 686 ct->t_lofault = lofault; 687 ct->t_onfault = onfault; 688 if (res == 0) 689 goto cleanup; 690 691 #if defined(OPTERON_ERRATUM_93) && defined(_LP64) 692 if (lofault == 0 && opteron_erratum_93) { 693 /* 694 * Workaround for Opteron Erratum 93. On return from 695 * a System Managment Interrupt at a HLT instruction 696 * the %rip might be truncated to a 32 bit value. 697 * BIOS is supposed to fix this, but some don't. 698 * If this occurs we simply restore the high order bits. 699 * The HLT instruction is 1 byte of 0xf4. 700 */ 701 uintptr_t rip = rp->r_pc; 702 703 if ((rip & 0xfffffffful) == rip) { 704 rip |= 0xfffffffful << 32; 705 if (hat_getpfnum(kas.a_hat, (caddr_t)rip) != 706 PFN_INVALID && 707 (*(uchar_t *)rip == 0xf4 || 708 *(uchar_t *)(rip - 1) == 0xf4)) { 709 rp->r_pc = rip; 710 goto cleanup; 711 } 712 } 713 } 714 #endif /* OPTERON_ERRATUM_93 && _LP64 */ 715 716 #ifdef OPTERON_ERRATUM_91 717 if (lofault == 0 && opteron_erratum_91) { 718 /* 719 * Workaround for Opteron Erratum 91. Prefetches may 720 * generate a page fault (they're not supposed to do 721 * that!). If this occurs we simply return back to the 722 * instruction. 723 */ 724 caddr_t pc = (caddr_t)rp->r_pc; 725 726 /* 727 * If the faulting PC is not mapped, this is a 728 * legitimate kernel page fault that must result in a 729 * panic. If the faulting PC is mapped, it could contain 730 * a prefetch instruction. Check for that here. 731 */ 732 if (hat_getpfnum(kas.a_hat, pc) != PFN_INVALID) { 733 if (cmp_to_prefetch((uchar_t *)pc)) { 734 #ifdef DEBUG 735 cmn_err(CE_WARN, "Opteron erratum 91 " 736 "occurred: kernel prefetch" 737 " at %p generated a page fault!", 738 (void *)rp->r_pc); 739 #endif /* DEBUG */ 740 goto cleanup; 741 } 742 } 743 (void) die(type, rp, addr, cpuid); 744 } 745 #endif /* OPTERON_ERRATUM_91 */ 746 747 if (lofault == 0) 748 (void) die(type, rp, addr, cpuid); 749 750 /* 751 * Cannot resolve fault. Return to lofault. 752 */ 753 if (lodebug) { 754 showregs(type, rp, addr); 755 traceregs(rp); 756 } 757 if (FC_CODE(res) == FC_OBJERR) 758 res = FC_ERRNO(res); 759 else 760 res = EFAULT; 761 rp->r_r0 = res; 762 rp->r_pc = ct->t_lofault; 763 goto cleanup; 764 765 case T_PGFLT + USER: /* user page fault */ 766 if (faultdebug) { 767 char *fault_str; 768 769 switch (rw) { 770 case S_READ: 771 fault_str = "read"; 772 break; 773 case S_WRITE: 774 fault_str = "write"; 775 break; 776 case S_EXEC: 777 fault_str = "exec"; 778 break; 779 default: 780 fault_str = ""; 781 break; 782 } 783 printf("user %s fault: addr=0x%lx errcode=0x%x\n", 784 fault_str, (uintptr_t)addr, errcode); 785 } 786 787 #if defined(OPTERON_ERRATUM_100) && defined(_LP64) 788 /* 789 * Workaround for AMD erratum 100 790 * 791 * A 32-bit process may receive a page fault on a non 792 * 32-bit address by mistake. The range of the faulting 793 * address will be 794 * 795 * 0xffffffff80000000 .. 0xffffffffffffffff or 796 * 0x0000000100000000 .. 0x000000017fffffff 797 * 798 * The fault is always due to an instruction fetch, however 799 * the value of r_pc should be correct (in 32 bit range), 800 * so we ignore the page fault on the bogus address. 801 */ 802 if (p->p_model == DATAMODEL_ILP32 && 803 (0xffffffff80000000 <= (uintptr_t)addr || 804 (0x100000000 <= (uintptr_t)addr && 805 (uintptr_t)addr <= 0x17fffffff))) { 806 if (!opteron_erratum_100) 807 panic("unexpected erratum #100"); 808 if (rp->r_pc <= 0xffffffff) 809 goto out; 810 } 811 #endif /* OPTERON_ERRATUM_100 && _LP64 */ 812 813 ASSERT(!(curthread->t_flag & T_WATCHPT)); 814 watchpage = (pr_watch_active(p) && pr_is_watchpage(addr, rw)); 815 #ifdef __i386 816 /* 817 * In 32-bit mode, the lcall (system call) instruction fetches 818 * one word from the stack, at the stack pointer, because of the 819 * way the call gate is constructed. This is a bogus 820 * read and should not be counted as a read watchpoint. 821 * We work around the problem here by testing to see if 822 * this situation applies and, if so, simply jumping to 823 * the code in locore.s that fields the system call trap. 824 * The registers on the stack are already set up properly 825 * due to the match between the call gate sequence and the 826 * trap gate sequence. We just have to adjust the pc. 827 */ 828 if (watchpage && addr == (caddr_t)rp->r_sp && 829 rw == S_READ && instr_is_lcall_syscall((caddr_t)rp->r_pc)) { 830 extern void watch_syscall(void); 831 832 rp->r_pc += LCALLSIZE; 833 watch_syscall(); /* never returns */ 834 /* NOTREACHED */ 835 } 836 #endif /* __i386 */ 837 vaddr = addr; 838 if (!watchpage || (sz = instr_size(rp, &vaddr, rw)) <= 0) 839 fault_type = (errcode & PF_ERR_PROT)? F_PROT: F_INVAL; 840 else if ((watchcode = pr_is_watchpoint(&vaddr, &ta, 841 sz, NULL, rw)) != 0) { 842 if (ta) { 843 do_watch_step(vaddr, sz, rw, 844 watchcode, rp->r_pc); 845 fault_type = F_INVAL; 846 } else { 847 bzero(&siginfo, sizeof (siginfo)); 848 siginfo.si_signo = SIGTRAP; 849 siginfo.si_code = watchcode; 850 siginfo.si_addr = vaddr; 851 siginfo.si_trapafter = 0; 852 siginfo.si_pc = (caddr_t)rp->r_pc; 853 fault = FLTWATCH; 854 break; 855 } 856 } else { 857 /* XXX pr_watch_emul() never succeeds (for now) */ 858 if (rw != S_EXEC && pr_watch_emul(rp, vaddr, rw)) 859 goto out; 860 do_watch_step(vaddr, sz, rw, 0, 0); 861 fault_type = F_INVAL; 862 } 863 864 res = pagefault(addr, fault_type, rw, 0); 865 866 /* 867 * If pagefault() succeeded, ok. 868 * Otherwise attempt to grow the stack. 869 */ 870 if (res == 0 || 871 (res == FC_NOMAP && 872 addr < p->p_usrstack && 873 grow(addr))) { 874 lwp->lwp_lastfault = FLTPAGE; 875 lwp->lwp_lastfaddr = addr; 876 if (prismember(&p->p_fltmask, FLTPAGE)) { 877 bzero(&siginfo, sizeof (siginfo)); 878 siginfo.si_addr = addr; 879 (void) stop_on_fault(FLTPAGE, &siginfo); 880 } 881 goto out; 882 } else if (res == FC_PROT && addr < p->p_usrstack && 883 (mmu.pt_nx != 0 && (errcode & PF_ERR_EXEC))) { 884 report_stack_exec(p, addr); 885 } 886 887 #ifdef OPTERON_ERRATUM_91 888 /* 889 * Workaround for Opteron Erratum 91. Prefetches may generate a 890 * page fault (they're not supposed to do that!). If this 891 * occurs we simply return back to the instruction. 892 * 893 * We rely on copyin to properly fault in the page with r_pc. 894 */ 895 if (opteron_erratum_91 && 896 addr != (caddr_t)rp->r_pc && 897 instr_is_prefetch((caddr_t)rp->r_pc)) { 898 #ifdef DEBUG 899 cmn_err(CE_WARN, "Opteron erratum 91 occurred: " 900 "prefetch at %p in pid %d generated a trap!", 901 (void *)rp->r_pc, p->p_pid); 902 #endif /* DEBUG */ 903 goto out; 904 } 905 #endif /* OPTERON_ERRATUM_91 */ 906 907 if (tudebug) 908 showregs(type, rp, addr); 909 /* 910 * In the case where both pagefault and grow fail, 911 * set the code to the value provided by pagefault. 912 * We map all errors returned from pagefault() to SIGSEGV. 913 */ 914 bzero(&siginfo, sizeof (siginfo)); 915 siginfo.si_addr = addr; 916 switch (FC_CODE(res)) { 917 case FC_HWERR: 918 case FC_NOSUPPORT: 919 siginfo.si_signo = SIGBUS; 920 siginfo.si_code = BUS_ADRERR; 921 fault = FLTACCESS; 922 break; 923 case FC_ALIGN: 924 siginfo.si_signo = SIGBUS; 925 siginfo.si_code = BUS_ADRALN; 926 fault = FLTACCESS; 927 break; 928 case FC_OBJERR: 929 if ((siginfo.si_errno = FC_ERRNO(res)) != EINTR) { 930 siginfo.si_signo = SIGBUS; 931 siginfo.si_code = BUS_OBJERR; 932 fault = FLTACCESS; 933 } 934 break; 935 default: /* FC_NOMAP or FC_PROT */ 936 siginfo.si_signo = SIGSEGV; 937 siginfo.si_code = 938 (res == FC_NOMAP)? SEGV_MAPERR : SEGV_ACCERR; 939 fault = FLTBOUNDS; 940 break; 941 } 942 break; 943 944 case T_ILLINST + USER: /* invalid opcode fault */ 945 /* 946 * If the syscall instruction is disabled due to LDT usage, a 947 * user program that attempts to execute it will trigger a #ud 948 * trap. Check for that case here. If this occurs on a CPU which 949 * doesn't even support syscall, the result of all of this will 950 * be to emulate that particular instruction. 951 */ 952 if (p->p_ldt != NULL && 953 ldt_rewrite_syscall(rp, p, X86FSET_ASYSC)) 954 goto out; 955 956 #ifdef __amd64 957 /* 958 * Emulate the LAHF and SAHF instructions if needed. 959 * See the instr_is_lsahf function for details. 960 */ 961 if (p->p_model == DATAMODEL_LP64 && 962 instr_is_lsahf((caddr_t)rp->r_pc, &instr)) { 963 emulate_lsahf(rp, instr); 964 goto out; 965 } 966 #endif 967 968 /*FALLTHROUGH*/ 969 970 if (tudebug) 971 showregs(type, rp, (caddr_t)0); 972 siginfo.si_signo = SIGILL; 973 siginfo.si_code = ILL_ILLOPC; 974 siginfo.si_addr = (caddr_t)rp->r_pc; 975 fault = FLTILL; 976 break; 977 978 case T_ZERODIV + USER: /* integer divide by zero */ 979 if (tudebug && tudebugfpe) 980 showregs(type, rp, (caddr_t)0); 981 siginfo.si_signo = SIGFPE; 982 siginfo.si_code = FPE_INTDIV; 983 siginfo.si_addr = (caddr_t)rp->r_pc; 984 fault = FLTIZDIV; 985 break; 986 987 case T_OVFLW + USER: /* integer overflow */ 988 if (tudebug && tudebugfpe) 989 showregs(type, rp, (caddr_t)0); 990 siginfo.si_signo = SIGFPE; 991 siginfo.si_code = FPE_INTOVF; 992 siginfo.si_addr = (caddr_t)rp->r_pc; 993 fault = FLTIOVF; 994 break; 995 996 /* 997 * When using an eager FPU on x86, the #NM trap is no longer meaningful. 998 * Userland should not be able to trigger it. Anything that does 999 * represents a fatal error in the kernel and likely in the register 1000 * state of the system. User FPU state should always be valid. 1001 */ 1002 case T_NOEXTFLT + USER: /* math coprocessor not available */ 1003 case T_NOEXTFLT: 1004 (void) die(type, rp, addr, cpuid); 1005 break; 1006 1007 /* 1008 * Kernel threads leveraging floating point need to mask the exceptions 1009 * or ensure that they cannot happen. There is no recovery from this. 1010 */ 1011 case T_EXTERRFLT: /* x87 floating point exception pending */ 1012 sti(); /* T_EXTERRFLT comes in via cmninttrap */ 1013 (void) die(type, rp, addr, cpuid); 1014 break; 1015 1016 case T_EXTERRFLT + USER: /* x87 floating point exception pending */ 1017 if (tudebug && tudebugfpe) 1018 showregs(type, rp, addr); 1019 if (sicode = fpexterrflt(rp)) { 1020 siginfo.si_signo = SIGFPE; 1021 siginfo.si_code = sicode; 1022 siginfo.si_addr = (caddr_t)rp->r_pc; 1023 fault = FLTFPE; 1024 } 1025 break; 1026 1027 case T_SIMDFPE + USER: /* SSE and SSE2 exceptions */ 1028 if (tudebug && tudebugsse) 1029 showregs(type, rp, addr); 1030 if (!is_x86_feature(x86_featureset, X86FSET_SSE) && 1031 !is_x86_feature(x86_featureset, X86FSET_SSE2)) { 1032 /* 1033 * There are rumours that some user instructions 1034 * on older CPUs can cause this trap to occur; in 1035 * which case send a SIGILL instead of a SIGFPE. 1036 */ 1037 siginfo.si_signo = SIGILL; 1038 siginfo.si_code = ILL_ILLTRP; 1039 siginfo.si_addr = (caddr_t)rp->r_pc; 1040 siginfo.si_trapno = type & ~USER; 1041 fault = FLTILL; 1042 } else if ((sicode = fpsimderrflt(rp)) != 0) { 1043 siginfo.si_signo = SIGFPE; 1044 siginfo.si_code = sicode; 1045 siginfo.si_addr = (caddr_t)rp->r_pc; 1046 fault = FLTFPE; 1047 } 1048 1049 sti(); /* The SIMD exception comes in via cmninttrap */ 1050 break; 1051 1052 case T_BPTFLT: /* breakpoint trap */ 1053 /* 1054 * Kernel breakpoint traps should only happen when kmdb is 1055 * active, and even then, it'll have interposed on the IDT, so 1056 * control won't get here. If it does, we've hit a breakpoint 1057 * without the debugger, which is very strange, and very 1058 * fatal. 1059 */ 1060 if (tudebug && tudebugbpt) 1061 showregs(type, rp, (caddr_t)0); 1062 1063 (void) die(type, rp, addr, cpuid); 1064 break; 1065 1066 case T_SGLSTP: /* single step/hw breakpoint exception */ 1067 1068 #if !defined(__xpv) 1069 /* 1070 * We'd never normally get here, as kmdb handles its own single 1071 * step traps. There is one nasty exception though, as 1072 * described in more detail in sys_sysenter(). Note that 1073 * checking for all four locations covers both the KPTI and the 1074 * non-KPTI cases correctly: the former will never be found at 1075 * (brand_)sys_sysenter, and vice versa. 1076 */ 1077 if (lwp != NULL && (lwp->lwp_pcb.pcb_drstat & DR_SINGLESTEP)) { 1078 if (rp->r_pc == (greg_t)brand_sys_sysenter || 1079 rp->r_pc == (greg_t)sys_sysenter || 1080 rp->r_pc == (greg_t)tr_brand_sys_sysenter || 1081 rp->r_pc == (greg_t)tr_sys_sysenter) { 1082 1083 rp->r_pc += 0x3; /* sizeof (swapgs) */ 1084 1085 rp->r_ps &= ~PS_T; /* turn off trace */ 1086 lwp->lwp_pcb.pcb_flags |= DEBUG_PENDING; 1087 ct->t_post_sys = 1; 1088 aston(curthread); 1089 goto cleanup; 1090 } else { 1091 if (tudebug && tudebugbpt) 1092 showregs(type, rp, (caddr_t)0); 1093 } 1094 } 1095 #endif /* !__xpv */ 1096 1097 if (boothowto & RB_DEBUG) 1098 debug_enter((char *)NULL); 1099 else 1100 (void) die(type, rp, addr, cpuid); 1101 break; 1102 1103 case T_NMIFLT: /* NMI interrupt */ 1104 printf("Unexpected NMI in system mode\n"); 1105 goto cleanup; 1106 1107 case T_NMIFLT + USER: /* NMI interrupt */ 1108 printf("Unexpected NMI in user mode\n"); 1109 break; 1110 1111 case T_GPFLT: /* general protection violation */ 1112 /* 1113 * Any #GP that occurs during an on_trap .. no_trap bracket 1114 * with OT_DATA_ACCESS or OT_SEGMENT_ACCESS protection, 1115 * or in a on_fault .. no_fault bracket, is forgiven 1116 * and we trampoline. This protection is given regardless 1117 * of whether we are 32/64 bit etc - if a distinction is 1118 * required then define new on_trap protection types. 1119 * 1120 * On amd64, we can get a #gp from referencing addresses 1121 * in the virtual address hole e.g. from a copyin or in 1122 * update_sregs while updating user segment registers. 1123 * 1124 * On the 32-bit hypervisor we could also generate one in 1125 * mfn_to_pfn by reaching around or into where the hypervisor 1126 * lives which is protected by segmentation. 1127 */ 1128 1129 /* 1130 * If we're under on_trap() protection (see <sys/ontrap.h>), 1131 * set ot_trap and trampoline back to the on_trap() call site 1132 * for OT_DATA_ACCESS or OT_SEGMENT_ACCESS. 1133 */ 1134 if (ct->t_ontrap != NULL) { 1135 int ttype = ct->t_ontrap->ot_prot & 1136 (OT_DATA_ACCESS | OT_SEGMENT_ACCESS); 1137 1138 if (ttype != 0) { 1139 ct->t_ontrap->ot_trap |= ttype; 1140 if (tudebug) 1141 showregs(type, rp, (caddr_t)0); 1142 rp->r_pc = ct->t_ontrap->ot_trampoline; 1143 goto cleanup; 1144 } 1145 } 1146 1147 /* 1148 * If we're under lofault protection (copyin etc.), 1149 * longjmp back to lofault with an EFAULT. 1150 */ 1151 if (ct->t_lofault) { 1152 /* 1153 * Fault is not resolvable, so just return to lofault 1154 */ 1155 if (lodebug) { 1156 showregs(type, rp, addr); 1157 traceregs(rp); 1158 } 1159 rp->r_r0 = EFAULT; 1160 rp->r_pc = ct->t_lofault; 1161 goto cleanup; 1162 } 1163 1164 /* 1165 * We fall through to the next case, which repeats 1166 * the OT_SEGMENT_ACCESS check which we've already 1167 * done, so we'll always fall through to the 1168 * T_STKFLT case. 1169 */ 1170 /*FALLTHROUGH*/ 1171 case T_SEGFLT: /* segment not present fault */ 1172 /* 1173 * One example of this is #NP in update_sregs while 1174 * attempting to update a user segment register 1175 * that points to a descriptor that is marked not 1176 * present. 1177 */ 1178 if (ct->t_ontrap != NULL && 1179 ct->t_ontrap->ot_prot & OT_SEGMENT_ACCESS) { 1180 ct->t_ontrap->ot_trap |= OT_SEGMENT_ACCESS; 1181 if (tudebug) 1182 showregs(type, rp, (caddr_t)0); 1183 rp->r_pc = ct->t_ontrap->ot_trampoline; 1184 goto cleanup; 1185 } 1186 /*FALLTHROUGH*/ 1187 case T_STKFLT: /* stack fault */ 1188 case T_TSSFLT: /* invalid TSS fault */ 1189 if (tudebug) 1190 showregs(type, rp, (caddr_t)0); 1191 if (kern_gpfault(rp)) 1192 (void) die(type, rp, addr, cpuid); 1193 goto cleanup; 1194 1195 /* 1196 * ONLY 32-bit PROCESSES can USE a PRIVATE LDT! 64-bit apps 1197 * should have no need for them, so we put a stop to it here. 1198 * 1199 * So: not-present fault is ONLY valid for 32-bit processes with 1200 * a private LDT trying to do a system call. Emulate it. 1201 * 1202 * #gp fault is ONLY valid for 32-bit processes also, which DO NOT 1203 * have a private LDT, and are trying to do a system call. Emulate it. 1204 */ 1205 1206 case T_SEGFLT + USER: /* segment not present fault */ 1207 case T_GPFLT + USER: /* general protection violation */ 1208 #ifdef _SYSCALL32_IMPL 1209 if (p->p_model != DATAMODEL_NATIVE) { 1210 #endif /* _SYSCALL32_IMPL */ 1211 if (instr_is_lcall_syscall((caddr_t)rp->r_pc)) { 1212 if (type == T_SEGFLT + USER) 1213 ASSERT(p->p_ldt != NULL); 1214 1215 if ((p->p_ldt == NULL && type == T_GPFLT + USER) || 1216 type == T_SEGFLT + USER) { 1217 1218 /* 1219 * The user attempted a system call via the obsolete 1220 * call gate mechanism. Because the process doesn't have 1221 * an LDT (i.e. the ldtr contains 0), a #gp results. 1222 * Emulate the syscall here, just as we do above for a 1223 * #np trap. 1224 */ 1225 1226 /* 1227 * Since this is a not-present trap, rp->r_pc points to 1228 * the trapping lcall instruction. We need to bump it 1229 * to the next insn so the app can continue on. 1230 */ 1231 rp->r_pc += LCALLSIZE; 1232 lwp->lwp_regs = rp; 1233 1234 /* 1235 * Normally the microstate of the LWP is forced back to 1236 * LMS_USER by the syscall handlers. Emulate that 1237 * behavior here. 1238 */ 1239 mstate = LMS_USER; 1240 1241 dosyscall(); 1242 goto out; 1243 } 1244 } 1245 #ifdef _SYSCALL32_IMPL 1246 } 1247 #endif /* _SYSCALL32_IMPL */ 1248 /* 1249 * If the current process is using a private LDT and the 1250 * trapping instruction is sysenter, the sysenter instruction 1251 * has been disabled on the CPU because it destroys segment 1252 * registers. If this is the case, rewrite the instruction to 1253 * be a safe system call and retry it. If this occurs on a CPU 1254 * which doesn't even support sysenter, the result of all of 1255 * this will be to emulate that particular instruction. 1256 */ 1257 if (p->p_ldt != NULL && 1258 ldt_rewrite_syscall(rp, p, X86FSET_SEP)) 1259 goto out; 1260 1261 /*FALLTHROUGH*/ 1262 1263 case T_BOUNDFLT + USER: /* bound fault */ 1264 case T_STKFLT + USER: /* stack fault */ 1265 case T_TSSFLT + USER: /* invalid TSS fault */ 1266 if (tudebug) 1267 showregs(type, rp, (caddr_t)0); 1268 siginfo.si_signo = SIGSEGV; 1269 siginfo.si_code = SEGV_MAPERR; 1270 siginfo.si_addr = (caddr_t)rp->r_pc; 1271 fault = FLTBOUNDS; 1272 break; 1273 1274 case T_ALIGNMENT + USER: /* user alignment error (486) */ 1275 if (tudebug) 1276 showregs(type, rp, (caddr_t)0); 1277 bzero(&siginfo, sizeof (siginfo)); 1278 siginfo.si_signo = SIGBUS; 1279 siginfo.si_code = BUS_ADRALN; 1280 siginfo.si_addr = (caddr_t)rp->r_pc; 1281 fault = FLTACCESS; 1282 break; 1283 1284 case T_SGLSTP + USER: /* single step/hw breakpoint exception */ 1285 if (tudebug && tudebugbpt) 1286 showregs(type, rp, (caddr_t)0); 1287 1288 /* Was it single-stepping? */ 1289 if (lwp->lwp_pcb.pcb_drstat & DR_SINGLESTEP) { 1290 pcb_t *pcb = &lwp->lwp_pcb; 1291 1292 rp->r_ps &= ~PS_T; 1293 /* 1294 * If both NORMAL_STEP and WATCH_STEP are in effect, 1295 * give precedence to WATCH_STEP. If neither is set, 1296 * user must have set the PS_T bit in %efl; treat this 1297 * as NORMAL_STEP. 1298 */ 1299 if ((fault = undo_watch_step(&siginfo)) == 0 && 1300 ((pcb->pcb_flags & NORMAL_STEP) || 1301 !(pcb->pcb_flags & WATCH_STEP))) { 1302 siginfo.si_signo = SIGTRAP; 1303 siginfo.si_code = TRAP_TRACE; 1304 siginfo.si_addr = (caddr_t)rp->r_pc; 1305 fault = FLTTRACE; 1306 } 1307 pcb->pcb_flags &= ~(NORMAL_STEP|WATCH_STEP); 1308 } 1309 break; 1310 1311 case T_BPTFLT + USER: /* breakpoint trap */ 1312 if (tudebug && tudebugbpt) 1313 showregs(type, rp, (caddr_t)0); 1314 /* 1315 * int 3 (the breakpoint instruction) leaves the pc referring 1316 * to the address one byte after the breakpointed address. 1317 * If the P_PR_BPTADJ flag has been set via /proc, We adjust 1318 * it back so it refers to the breakpointed address. 1319 */ 1320 if (p->p_proc_flag & P_PR_BPTADJ) 1321 rp->r_pc--; 1322 siginfo.si_signo = SIGTRAP; 1323 siginfo.si_code = TRAP_BRKPT; 1324 siginfo.si_addr = (caddr_t)rp->r_pc; 1325 fault = FLTBPT; 1326 break; 1327 1328 case T_AST: 1329 /* 1330 * This occurs only after the cs register has been made to 1331 * look like a kernel selector, either through debugging or 1332 * possibly by functions like setcontext(). The thread is 1333 * about to cause a general protection fault at common_iret() 1334 * in locore. We let that happen immediately instead of 1335 * doing the T_AST processing. 1336 */ 1337 goto cleanup; 1338 1339 case T_AST + USER: /* profiling, resched, h/w error pseudo trap */ 1340 if (lwp->lwp_pcb.pcb_flags & ASYNC_HWERR) { 1341 proc_t *p = ttoproc(curthread); 1342 extern void print_msg_hwerr(ctid_t ct_id, proc_t *p); 1343 1344 lwp->lwp_pcb.pcb_flags &= ~ASYNC_HWERR; 1345 print_msg_hwerr(p->p_ct_process->conp_contract.ct_id, 1346 p); 1347 contract_process_hwerr(p->p_ct_process, p); 1348 siginfo.si_signo = SIGKILL; 1349 siginfo.si_code = SI_NOINFO; 1350 } else if (lwp->lwp_pcb.pcb_flags & CPC_OVERFLOW) { 1351 lwp->lwp_pcb.pcb_flags &= ~CPC_OVERFLOW; 1352 if (kcpc_overflow_ast()) { 1353 /* 1354 * Signal performance counter overflow 1355 */ 1356 if (tudebug) 1357 showregs(type, rp, (caddr_t)0); 1358 bzero(&siginfo, sizeof (siginfo)); 1359 siginfo.si_signo = SIGEMT; 1360 siginfo.si_code = EMT_CPCOVF; 1361 siginfo.si_addr = (caddr_t)rp->r_pc; 1362 fault = FLTCPCOVF; 1363 } 1364 } 1365 1366 break; 1367 } 1368 1369 /* 1370 * We can't get here from a system trap 1371 */ 1372 ASSERT(type & USER); 1373 1374 if (fault) { 1375 /* We took a fault so abort single step. */ 1376 lwp->lwp_pcb.pcb_flags &= ~(NORMAL_STEP|WATCH_STEP); 1377 /* 1378 * Remember the fault and fault adddress 1379 * for real-time (SIGPROF) profiling. 1380 */ 1381 lwp->lwp_lastfault = fault; 1382 lwp->lwp_lastfaddr = siginfo.si_addr; 1383 1384 DTRACE_PROC2(fault, int, fault, ksiginfo_t *, &siginfo); 1385 1386 /* 1387 * If a debugger has declared this fault to be an 1388 * event of interest, stop the lwp. Otherwise just 1389 * deliver the associated signal. 1390 */ 1391 if (siginfo.si_signo != SIGKILL && 1392 prismember(&p->p_fltmask, fault) && 1393 stop_on_fault(fault, &siginfo) == 0) 1394 siginfo.si_signo = 0; 1395 } 1396 1397 if (siginfo.si_signo) 1398 trapsig(&siginfo, (fault != FLTFPE && fault != FLTCPCOVF)); 1399 1400 if (lwp->lwp_oweupc) 1401 profil_tick(rp->r_pc); 1402 1403 if (ct->t_astflag | ct->t_sig_check) { 1404 /* 1405 * Turn off the AST flag before checking all the conditions that 1406 * may have caused an AST. This flag is on whenever a signal or 1407 * unusual condition should be handled after the next trap or 1408 * syscall. 1409 */ 1410 astoff(ct); 1411 /* 1412 * If a single-step trap occurred on a syscall (see above) 1413 * recognize it now. Do this before checking for signals 1414 * because deferred_singlestep_trap() may generate a SIGTRAP to 1415 * the LWP or may otherwise mark the LWP to call issig(FORREAL). 1416 */ 1417 if (lwp->lwp_pcb.pcb_flags & DEBUG_PENDING) 1418 deferred_singlestep_trap((caddr_t)rp->r_pc); 1419 1420 ct->t_sig_check = 0; 1421 1422 /* 1423 * As in other code paths that check against TP_CHANGEBIND, 1424 * we perform the check first without p_lock held -- only 1425 * acquiring p_lock in the unlikely event that it is indeed 1426 * set. This is safe because we are doing this after the 1427 * astoff(); if we are racing another thread setting 1428 * TP_CHANGEBIND on us, we will pick it up on a subsequent 1429 * lap through. 1430 */ 1431 if (curthread->t_proc_flag & TP_CHANGEBIND) { 1432 mutex_enter(&p->p_lock); 1433 if (curthread->t_proc_flag & TP_CHANGEBIND) { 1434 timer_lwpbind(); 1435 curthread->t_proc_flag &= ~TP_CHANGEBIND; 1436 } 1437 mutex_exit(&p->p_lock); 1438 } 1439 1440 /* 1441 * for kaio requests that are on the per-process poll queue, 1442 * aiop->aio_pollq, they're AIO_POLL bit is set, the kernel 1443 * should copyout their result_t to user memory. by copying 1444 * out the result_t, the user can poll on memory waiting 1445 * for the kaio request to complete. 1446 */ 1447 if (p->p_aio) 1448 aio_cleanup(0); 1449 /* 1450 * If this LWP was asked to hold, call holdlwp(), which will 1451 * stop. holdlwps() sets this up and calls pokelwps() which 1452 * sets the AST flag. 1453 * 1454 * Also check TP_EXITLWP, since this is used by fresh new LWPs 1455 * through lwp_rtt(). That flag is set if the lwp_create(2) 1456 * syscall failed after creating the LWP. 1457 */ 1458 if (ISHOLD(p)) 1459 holdlwp(); 1460 1461 /* 1462 * All code that sets signals and makes ISSIG evaluate true must 1463 * set t_astflag afterwards. 1464 */ 1465 if (ISSIG_PENDING(ct, lwp, p)) { 1466 if (issig(FORREAL)) 1467 psig(); 1468 ct->t_sig_check = 1; 1469 } 1470 1471 if (ct->t_rprof != NULL) { 1472 realsigprof(0, 0, 0); 1473 ct->t_sig_check = 1; 1474 } 1475 1476 /* 1477 * /proc can't enable/disable the trace bit itself 1478 * because that could race with the call gate used by 1479 * system calls via "lcall". If that happened, an 1480 * invalid EFLAGS would result. prstep()/prnostep() 1481 * therefore schedule an AST for the purpose. 1482 */ 1483 if (lwp->lwp_pcb.pcb_flags & REQUEST_STEP) { 1484 lwp->lwp_pcb.pcb_flags &= ~REQUEST_STEP; 1485 rp->r_ps |= PS_T; 1486 } 1487 if (lwp->lwp_pcb.pcb_flags & REQUEST_NOSTEP) { 1488 lwp->lwp_pcb.pcb_flags &= ~REQUEST_NOSTEP; 1489 rp->r_ps &= ~PS_T; 1490 } 1491 } 1492 1493 out: /* We can't get here from a system trap */ 1494 ASSERT(type & USER); 1495 1496 if (ISHOLD(p)) 1497 holdlwp(); 1498 1499 /* 1500 * Set state to LWP_USER here so preempt won't give us a kernel 1501 * priority if it occurs after this point. Call CL_TRAPRET() to 1502 * restore the user-level priority. 1503 * 1504 * It is important that no locks (other than spinlocks) be entered 1505 * after this point before returning to user mode (unless lwp_state 1506 * is set back to LWP_SYS). 1507 */ 1508 lwp->lwp_state = LWP_USER; 1509 1510 if (ct->t_trapret) { 1511 ct->t_trapret = 0; 1512 thread_lock(ct); 1513 CL_TRAPRET(ct); 1514 thread_unlock(ct); 1515 } 1516 if (CPU->cpu_runrun || curthread->t_schedflag & TS_ANYWAITQ) 1517 preempt(); 1518 prunstop(); 1519 (void) new_mstate(ct, mstate); 1520 1521 /* Kernel probe */ 1522 TNF_PROBE_1(thread_state, "thread", /* CSTYLED */, 1523 tnf_microstate, state, LMS_USER); 1524 1525 return; 1526 1527 cleanup: /* system traps end up here */ 1528 ASSERT(!(type & USER)); 1529 } 1530 1531 /* 1532 * Patch non-zero to disable preemption of threads in the kernel. 1533 */ 1534 int IGNORE_KERNEL_PREEMPTION = 0; /* XXX - delete this someday */ 1535 1536 struct kpreempt_cnts { /* kernel preemption statistics */ 1537 int kpc_idle; /* executing idle thread */ 1538 int kpc_intr; /* executing interrupt thread */ 1539 int kpc_clock; /* executing clock thread */ 1540 int kpc_blocked; /* thread has blocked preemption (t_preempt) */ 1541 int kpc_notonproc; /* thread is surrendering processor */ 1542 int kpc_inswtch; /* thread has ratified scheduling decision */ 1543 int kpc_prilevel; /* processor interrupt level is too high */ 1544 int kpc_apreempt; /* asynchronous preemption */ 1545 int kpc_spreempt; /* synchronous preemption */ 1546 } kpreempt_cnts; 1547 1548 /* 1549 * kernel preemption: forced rescheduling, preempt the running kernel thread. 1550 * the argument is old PIL for an interrupt, 1551 * or the distingished value KPREEMPT_SYNC. 1552 */ 1553 void 1554 kpreempt(int asyncspl) 1555 { 1556 kthread_t *ct = curthread; 1557 1558 if (IGNORE_KERNEL_PREEMPTION) { 1559 aston(CPU->cpu_dispthread); 1560 return; 1561 } 1562 1563 /* 1564 * Check that conditions are right for kernel preemption 1565 */ 1566 do { 1567 if (ct->t_preempt) { 1568 /* 1569 * either a privileged thread (idle, panic, interrupt) 1570 * or will check when t_preempt is lowered 1571 * We need to specifically handle the case where 1572 * the thread is in the middle of swtch (resume has 1573 * been called) and has its t_preempt set 1574 * [idle thread and a thread which is in kpreempt 1575 * already] and then a high priority thread is 1576 * available in the local dispatch queue. 1577 * In this case the resumed thread needs to take a 1578 * trap so that it can call kpreempt. We achieve 1579 * this by using siron(). 1580 * How do we detect this condition: 1581 * idle thread is running and is in the midst of 1582 * resume: curthread->t_pri == -1 && CPU->dispthread 1583 * != CPU->thread 1584 * Need to ensure that this happens only at high pil 1585 * resume is called at high pil 1586 * Only in resume_from_idle is the pil changed. 1587 */ 1588 if (ct->t_pri < 0) { 1589 kpreempt_cnts.kpc_idle++; 1590 if (CPU->cpu_dispthread != CPU->cpu_thread) 1591 siron(); 1592 } else if (ct->t_flag & T_INTR_THREAD) { 1593 kpreempt_cnts.kpc_intr++; 1594 if (ct->t_pil == CLOCK_LEVEL) 1595 kpreempt_cnts.kpc_clock++; 1596 } else { 1597 kpreempt_cnts.kpc_blocked++; 1598 if (CPU->cpu_dispthread != CPU->cpu_thread) 1599 siron(); 1600 } 1601 aston(CPU->cpu_dispthread); 1602 return; 1603 } 1604 if (ct->t_state != TS_ONPROC || 1605 ct->t_disp_queue != CPU->cpu_disp) { 1606 /* this thread will be calling swtch() shortly */ 1607 kpreempt_cnts.kpc_notonproc++; 1608 if (CPU->cpu_thread != CPU->cpu_dispthread) { 1609 /* already in swtch(), force another */ 1610 kpreempt_cnts.kpc_inswtch++; 1611 siron(); 1612 } 1613 return; 1614 } 1615 if (getpil() >= DISP_LEVEL) { 1616 /* 1617 * We can't preempt this thread if it is at 1618 * a PIL >= DISP_LEVEL since it may be holding 1619 * a spin lock (like sched_lock). 1620 */ 1621 siron(); /* check back later */ 1622 kpreempt_cnts.kpc_prilevel++; 1623 return; 1624 } 1625 if (!interrupts_enabled()) { 1626 /* 1627 * Can't preempt while running with ints disabled 1628 */ 1629 kpreempt_cnts.kpc_prilevel++; 1630 return; 1631 } 1632 if (asyncspl != KPREEMPT_SYNC) 1633 kpreempt_cnts.kpc_apreempt++; 1634 else 1635 kpreempt_cnts.kpc_spreempt++; 1636 1637 ct->t_preempt++; 1638 preempt(); 1639 ct->t_preempt--; 1640 } while (CPU->cpu_kprunrun); 1641 } 1642 1643 /* 1644 * Print out debugging info. 1645 */ 1646 static void 1647 showregs(uint_t type, struct regs *rp, caddr_t addr) 1648 { 1649 int s; 1650 1651 s = spl7(); 1652 type &= ~USER; 1653 if (PTOU(curproc)->u_comm[0]) 1654 printf("%s: ", PTOU(curproc)->u_comm); 1655 if (type < TRAP_TYPES) 1656 printf("#%s %s\n", trap_type_mnemonic[type], trap_type[type]); 1657 else 1658 switch (type) { 1659 case T_SYSCALL: 1660 printf("Syscall Trap:\n"); 1661 break; 1662 case T_AST: 1663 printf("AST\n"); 1664 break; 1665 default: 1666 printf("Bad Trap = %d\n", type); 1667 break; 1668 } 1669 if (type == T_PGFLT) { 1670 printf("Bad %s fault at addr=0x%lx\n", 1671 USERMODE(rp->r_cs) ? "user": "kernel", (uintptr_t)addr); 1672 } else if (addr) { 1673 printf("addr=0x%lx\n", (uintptr_t)addr); 1674 } 1675 1676 printf("pid=%d, pc=0x%lx, sp=0x%lx, eflags=0x%lx\n", 1677 (ttoproc(curthread) && ttoproc(curthread)->p_pidp) ? 1678 ttoproc(curthread)->p_pid : 0, rp->r_pc, rp->r_sp, rp->r_ps); 1679 1680 #if defined(__lint) 1681 /* 1682 * this clause can be deleted when lint bug 4870403 is fixed 1683 * (lint thinks that bit 32 is illegal in a %b format string) 1684 */ 1685 printf("cr0: %x cr4: %b\n", 1686 (uint_t)getcr0(), (uint_t)getcr4(), FMT_CR4); 1687 #else 1688 printf("cr0: %b cr4: %b\n", 1689 (uint_t)getcr0(), FMT_CR0, (uint_t)getcr4(), FMT_CR4); 1690 #endif /* __lint */ 1691 1692 printf("cr2: %lx ", getcr2()); 1693 #if !defined(__xpv) 1694 printf("cr3: %lx ", getcr3()); 1695 #if defined(__amd64) 1696 printf("cr8: %lx\n", getcr8()); 1697 #endif 1698 #endif 1699 printf("\n"); 1700 1701 dumpregs(rp); 1702 splx(s); 1703 } 1704 1705 static void 1706 dumpregs(struct regs *rp) 1707 { 1708 #if defined(__amd64) 1709 const char fmt[] = "\t%3s: %16lx %3s: %16lx %3s: %16lx\n"; 1710 1711 printf(fmt, "rdi", rp->r_rdi, "rsi", rp->r_rsi, "rdx", rp->r_rdx); 1712 printf(fmt, "rcx", rp->r_rcx, " r8", rp->r_r8, " r9", rp->r_r9); 1713 printf(fmt, "rax", rp->r_rax, "rbx", rp->r_rbx, "rbp", rp->r_rbp); 1714 printf(fmt, "r10", rp->r_r10, "r11", rp->r_r11, "r12", rp->r_r12); 1715 printf(fmt, "r13", rp->r_r13, "r14", rp->r_r14, "r15", rp->r_r15); 1716 1717 printf(fmt, "fsb", rdmsr(MSR_AMD_FSBASE), "gsb", rdmsr(MSR_AMD_GSBASE), 1718 " ds", rp->r_ds); 1719 printf(fmt, " es", rp->r_es, " fs", rp->r_fs, " gs", rp->r_gs); 1720 1721 printf(fmt, "trp", rp->r_trapno, "err", rp->r_err, "rip", rp->r_rip); 1722 printf(fmt, " cs", rp->r_cs, "rfl", rp->r_rfl, "rsp", rp->r_rsp); 1723 1724 printf("\t%3s: %16lx\n", " ss", rp->r_ss); 1725 1726 #elif defined(__i386) 1727 const char fmt[] = "\t%3s: %8lx %3s: %8lx %3s: %8lx %3s: %8lx\n"; 1728 1729 printf(fmt, " gs", rp->r_gs, " fs", rp->r_fs, 1730 " es", rp->r_es, " ds", rp->r_ds); 1731 printf(fmt, "edi", rp->r_edi, "esi", rp->r_esi, 1732 "ebp", rp->r_ebp, "esp", rp->r_esp); 1733 printf(fmt, "ebx", rp->r_ebx, "edx", rp->r_edx, 1734 "ecx", rp->r_ecx, "eax", rp->r_eax); 1735 printf(fmt, "trp", rp->r_trapno, "err", rp->r_err, 1736 "eip", rp->r_eip, " cs", rp->r_cs); 1737 printf("\t%3s: %8lx %3s: %8lx %3s: %8lx\n", 1738 "efl", rp->r_efl, "usp", rp->r_uesp, " ss", rp->r_ss); 1739 1740 #endif /* __i386 */ 1741 } 1742 1743 /* 1744 * Test to see if the instruction is iret on i386 or iretq on amd64. 1745 * 1746 * On the hypervisor we can only test for nopop_sys_rtt_syscall. If true 1747 * then we are in the context of hypervisor's failsafe handler because it 1748 * tried to iret and failed due to a bad selector. See xen_failsafe_callback. 1749 */ 1750 static int 1751 instr_is_iret(caddr_t pc) 1752 { 1753 1754 #if defined(__xpv) 1755 extern void nopop_sys_rtt_syscall(void); 1756 return ((pc == (caddr_t)nopop_sys_rtt_syscall) ? 1 : 0); 1757 1758 #else 1759 1760 #if defined(__amd64) 1761 static const uint8_t iret_insn[2] = { 0x48, 0xcf }; /* iretq */ 1762 1763 #elif defined(__i386) 1764 static const uint8_t iret_insn[1] = { 0xcf }; /* iret */ 1765 #endif /* __i386 */ 1766 return (bcmp(pc, iret_insn, sizeof (iret_insn)) == 0); 1767 1768 #endif /* __xpv */ 1769 } 1770 1771 #if defined(__i386) 1772 1773 /* 1774 * Test to see if the instruction is part of __SEGREGS_POP 1775 * 1776 * Note carefully the appallingly awful dependency between 1777 * the instruction sequence used in __SEGREGS_POP and these 1778 * instructions encoded here. 1779 */ 1780 static int 1781 instr_is_segregs_pop(caddr_t pc) 1782 { 1783 static const uint8_t movw_0_esp_gs[4] = { 0x8e, 0x6c, 0x24, 0x0 }; 1784 static const uint8_t movw_4_esp_fs[4] = { 0x8e, 0x64, 0x24, 0x4 }; 1785 static const uint8_t movw_8_esp_es[4] = { 0x8e, 0x44, 0x24, 0x8 }; 1786 static const uint8_t movw_c_esp_ds[4] = { 0x8e, 0x5c, 0x24, 0xc }; 1787 1788 if (bcmp(pc, movw_0_esp_gs, sizeof (movw_0_esp_gs)) == 0 || 1789 bcmp(pc, movw_4_esp_fs, sizeof (movw_4_esp_fs)) == 0 || 1790 bcmp(pc, movw_8_esp_es, sizeof (movw_8_esp_es)) == 0 || 1791 bcmp(pc, movw_c_esp_ds, sizeof (movw_c_esp_ds)) == 0) 1792 return (1); 1793 1794 return (0); 1795 } 1796 1797 #endif /* __i386 */ 1798 1799 /* 1800 * Test to see if the instruction is part of _sys_rtt (or the KPTI trampolines 1801 * which are used by _sys_rtt). 1802 * 1803 * Again on the hypervisor if we try to IRET to user land with a bad code 1804 * or stack selector we will get vectored through xen_failsafe_callback. 1805 * In which case we assume we got here via _sys_rtt since we only allow 1806 * IRET to user land to take place in _sys_rtt. 1807 */ 1808 static int 1809 instr_is_sys_rtt(caddr_t pc) 1810 { 1811 extern void _sys_rtt(), _sys_rtt_end(); 1812 1813 #if !defined(__xpv) 1814 extern void tr_sysc_ret_start(), tr_sysc_ret_end(); 1815 extern void tr_intr_ret_start(), tr_intr_ret_end(); 1816 1817 if ((uintptr_t)pc >= (uintptr_t)tr_sysc_ret_start && 1818 (uintptr_t)pc <= (uintptr_t)tr_sysc_ret_end) 1819 return (1); 1820 1821 if ((uintptr_t)pc >= (uintptr_t)tr_intr_ret_start && 1822 (uintptr_t)pc <= (uintptr_t)tr_intr_ret_end) 1823 return (1); 1824 #endif 1825 1826 if ((uintptr_t)pc < (uintptr_t)_sys_rtt || 1827 (uintptr_t)pc > (uintptr_t)_sys_rtt_end) 1828 return (0); 1829 1830 return (1); 1831 } 1832 1833 /* 1834 * Handle #gp faults in kernel mode. 1835 * 1836 * One legitimate way this can happen is if we attempt to update segment 1837 * registers to naughty values on the way out of the kernel. 1838 * 1839 * This can happen in a couple of ways: someone - either accidentally or 1840 * on purpose - creates (setcontext(2), lwp_create(2)) or modifies 1841 * (signal(2)) a ucontext that contains silly segment register values. 1842 * Or someone - either accidentally or on purpose - modifies the prgregset_t 1843 * of a subject process via /proc to contain silly segment register values. 1844 * 1845 * (The unfortunate part is that we can end up discovering the bad segment 1846 * register value in the middle of an 'iret' after we've popped most of the 1847 * stack. So it becomes quite difficult to associate an accurate ucontext 1848 * with the lwp, because the act of taking the #gp trap overwrites most of 1849 * what we were going to send the lwp.) 1850 * 1851 * OTOH if it turns out that's -not- the problem, and we're -not- an lwp 1852 * trying to return to user mode and we get a #gp fault, then we need 1853 * to die() -- which will happen if we return non-zero from this routine. 1854 */ 1855 static int 1856 kern_gpfault(struct regs *rp) 1857 { 1858 kthread_t *t = curthread; 1859 proc_t *p = ttoproc(t); 1860 klwp_t *lwp = ttolwp(t); 1861 struct regs tmpregs, *trp = NULL; 1862 caddr_t pc = (caddr_t)rp->r_pc; 1863 int v; 1864 uint32_t auditing = AU_AUDITING(); 1865 1866 /* 1867 * if we're not an lwp, or in the case of running native the 1868 * pc range is outside _sys_rtt, then we should immediately 1869 * be die()ing horribly. 1870 */ 1871 if (lwp == NULL || !instr_is_sys_rtt(pc)) 1872 return (1); 1873 1874 /* 1875 * So at least we're in the right part of the kernel. 1876 * 1877 * Disassemble the instruction at the faulting pc. 1878 * Once we know what it is, we carefully reconstruct the stack 1879 * based on the order in which the stack is deconstructed in 1880 * _sys_rtt. Ew. 1881 */ 1882 if (instr_is_iret(pc)) { 1883 /* 1884 * We took the #gp while trying to perform the IRET. 1885 * This means that either %cs or %ss are bad. 1886 * All we know for sure is that most of the general 1887 * registers have been restored, including the 1888 * segment registers, and all we have left on the 1889 * topmost part of the lwp's stack are the 1890 * registers that the iretq was unable to consume. 1891 * 1892 * All the rest of the state was crushed by the #gp 1893 * which pushed -its- registers atop our old save area 1894 * (because we had to decrement the stack pointer, sigh) so 1895 * all that we can try and do is to reconstruct the 1896 * crushed frame from the #gp trap frame itself. 1897 */ 1898 trp = &tmpregs; 1899 trp->r_ss = lwptoregs(lwp)->r_ss; 1900 trp->r_sp = lwptoregs(lwp)->r_sp; 1901 trp->r_ps = lwptoregs(lwp)->r_ps; 1902 trp->r_cs = lwptoregs(lwp)->r_cs; 1903 trp->r_pc = lwptoregs(lwp)->r_pc; 1904 bcopy(rp, trp, offsetof(struct regs, r_pc)); 1905 1906 /* 1907 * Validate simple math 1908 */ 1909 ASSERT(trp->r_pc == lwptoregs(lwp)->r_pc); 1910 ASSERT(trp->r_err == rp->r_err); 1911 1912 1913 1914 } 1915 1916 #if defined(__amd64) 1917 if (trp == NULL && PCB_NEED_UPDATE_SEGS(&lwp->lwp_pcb)) { 1918 1919 /* 1920 * This is the common case -- we're trying to load 1921 * a bad segment register value in the only section 1922 * of kernel code that ever loads segment registers. 1923 * 1924 * We don't need to do anything at this point because 1925 * the pcb contains all the pending segment register 1926 * state, and the regs are still intact because we 1927 * didn't adjust the stack pointer yet. Given the fidelity 1928 * of all this, we could conceivably send a signal 1929 * to the lwp, rather than core-ing. 1930 */ 1931 trp = lwptoregs(lwp); 1932 ASSERT((caddr_t)trp == (caddr_t)rp->r_sp); 1933 } 1934 1935 #elif defined(__i386) 1936 1937 if (trp == NULL && instr_is_segregs_pop(pc)) 1938 trp = lwptoregs(lwp); 1939 1940 #endif /* __i386 */ 1941 1942 if (trp == NULL) 1943 return (1); 1944 1945 /* 1946 * If we get to here, we're reasonably confident that we've 1947 * correctly decoded what happened on the way out of the kernel. 1948 * Rewrite the lwp's registers so that we can create a core dump 1949 * the (at least vaguely) represents the mcontext we were 1950 * being asked to restore when things went so terribly wrong. 1951 */ 1952 1953 /* 1954 * Make sure that we have a meaningful %trapno and %err. 1955 */ 1956 trp->r_trapno = rp->r_trapno; 1957 trp->r_err = rp->r_err; 1958 1959 if ((caddr_t)trp != (caddr_t)lwptoregs(lwp)) 1960 bcopy(trp, lwptoregs(lwp), sizeof (*trp)); 1961 1962 1963 mutex_enter(&p->p_lock); 1964 lwp->lwp_cursig = SIGSEGV; 1965 mutex_exit(&p->p_lock); 1966 1967 /* 1968 * Terminate all LWPs but don't discard them. If another lwp beat 1969 * us to the punch by calling exit(), evaporate now. 1970 */ 1971 proc_is_exiting(p); 1972 if (exitlwps(1) != 0) { 1973 mutex_enter(&p->p_lock); 1974 lwp_exit(); 1975 } 1976 1977 if (auditing) /* audit core dump */ 1978 audit_core_start(SIGSEGV); 1979 v = core(SIGSEGV, B_FALSE); 1980 if (auditing) /* audit core dump */ 1981 audit_core_finish(v ? CLD_KILLED : CLD_DUMPED); 1982 exit(v ? CLD_KILLED : CLD_DUMPED, SIGSEGV); 1983 return (0); 1984 } 1985 1986 /* 1987 * dump_tss() - Display the TSS structure 1988 */ 1989 1990 #if !defined(__xpv) 1991 #if defined(__amd64) 1992 1993 static void 1994 dump_tss(void) 1995 { 1996 const char tss_fmt[] = "tss.%s:\t0x%p\n"; /* Format string */ 1997 tss_t *tss = CPU->cpu_tss; 1998 1999 printf(tss_fmt, "tss_rsp0", (void *)tss->tss_rsp0); 2000 printf(tss_fmt, "tss_rsp1", (void *)tss->tss_rsp1); 2001 printf(tss_fmt, "tss_rsp2", (void *)tss->tss_rsp2); 2002 2003 printf(tss_fmt, "tss_ist1", (void *)tss->tss_ist1); 2004 printf(tss_fmt, "tss_ist2", (void *)tss->tss_ist2); 2005 printf(tss_fmt, "tss_ist3", (void *)tss->tss_ist3); 2006 printf(tss_fmt, "tss_ist4", (void *)tss->tss_ist4); 2007 printf(tss_fmt, "tss_ist5", (void *)tss->tss_ist5); 2008 printf(tss_fmt, "tss_ist6", (void *)tss->tss_ist6); 2009 printf(tss_fmt, "tss_ist7", (void *)tss->tss_ist7); 2010 } 2011 2012 #elif defined(__i386) 2013 2014 static void 2015 dump_tss(void) 2016 { 2017 const char tss_fmt[] = "tss.%s:\t0x%p\n"; /* Format string */ 2018 tss_t *tss = CPU->cpu_tss; 2019 2020 printf(tss_fmt, "tss_link", (void *)(uintptr_t)tss->tss_link); 2021 printf(tss_fmt, "tss_esp0", (void *)(uintptr_t)tss->tss_esp0); 2022 printf(tss_fmt, "tss_ss0", (void *)(uintptr_t)tss->tss_ss0); 2023 printf(tss_fmt, "tss_esp1", (void *)(uintptr_t)tss->tss_esp1); 2024 printf(tss_fmt, "tss_ss1", (void *)(uintptr_t)tss->tss_ss1); 2025 printf(tss_fmt, "tss_esp2", (void *)(uintptr_t)tss->tss_esp2); 2026 printf(tss_fmt, "tss_ss2", (void *)(uintptr_t)tss->tss_ss2); 2027 printf(tss_fmt, "tss_cr3", (void *)(uintptr_t)tss->tss_cr3); 2028 printf(tss_fmt, "tss_eip", (void *)(uintptr_t)tss->tss_eip); 2029 printf(tss_fmt, "tss_eflags", (void *)(uintptr_t)tss->tss_eflags); 2030 printf(tss_fmt, "tss_eax", (void *)(uintptr_t)tss->tss_eax); 2031 printf(tss_fmt, "tss_ebx", (void *)(uintptr_t)tss->tss_ebx); 2032 printf(tss_fmt, "tss_ecx", (void *)(uintptr_t)tss->tss_ecx); 2033 printf(tss_fmt, "tss_edx", (void *)(uintptr_t)tss->tss_edx); 2034 printf(tss_fmt, "tss_esp", (void *)(uintptr_t)tss->tss_esp); 2035 } 2036 2037 #endif /* __amd64 */ 2038 #endif /* !__xpv */ 2039 2040 #if defined(TRAPTRACE) 2041 2042 int ttrace_nrec = 10; /* number of records to dump out */ 2043 int ttrace_dump_nregs = 0; /* dump out this many records with regs too */ 2044 2045 /* 2046 * Dump out the last ttrace_nrec traptrace records on each CPU 2047 */ 2048 static void 2049 dump_ttrace(void) 2050 { 2051 trap_trace_ctl_t *ttc; 2052 trap_trace_rec_t *rec; 2053 uintptr_t current; 2054 int i, j, k; 2055 int n = NCPU; 2056 #if defined(__amd64) 2057 const char banner[] = 2058 "CPU ADDRESS TIMESTAMP TYPE VC HANDLER PC\n"; 2059 /* Define format for the CPU, ADDRESS, and TIMESTAMP fields */ 2060 const char fmt1[] = "%3d %016lx %12llx"; 2061 char data1[34]; /* length of string formatted by fmt1 + 1 */ 2062 #elif defined(__i386) 2063 const char banner[] = 2064 "CPU ADDRESS TIMESTAMP TYPE VC HANDLER PC\n"; 2065 /* Define format for the CPU, ADDRESS, and TIMESTAMP fields */ 2066 const char fmt1[] = "%3d %08lx %12llx"; 2067 char data1[26]; /* length of string formatted by fmt1 + 1 */ 2068 #endif 2069 /* Define format for the TYPE and VC fields */ 2070 const char fmt2[] = "%4s %3x"; 2071 const char fmt2s[] = "%4s %3s"; 2072 char data2[9]; /* length of string formatted by fmt2 + 1 */ 2073 /* 2074 * Define format for the HANDLER field. Width is arbitrary, but should 2075 * be enough for common handler's names, and leave enough space for 2076 * the PC field, especially when we are in kmdb. 2077 */ 2078 const char fmt3h[] = "#%-15s"; 2079 const char fmt3p[] = "%-16p"; 2080 const char fmt3s[] = "%-16s"; 2081 char data3[17]; /* length of string formatted by fmt3* + 1 */ 2082 2083 if (ttrace_nrec == 0) 2084 return; 2085 2086 printf("\n"); 2087 printf(banner); 2088 2089 for (i = 0; i < n; i++) { 2090 ttc = &trap_trace_ctl[i]; 2091 if (ttc->ttc_first == (uintptr_t)NULL) 2092 continue; 2093 2094 current = ttc->ttc_next - sizeof (trap_trace_rec_t); 2095 for (j = 0; j < ttrace_nrec; j++) { 2096 struct sysent *sys; 2097 struct autovec *vec; 2098 extern struct av_head autovect[]; 2099 int type; 2100 ulong_t off; 2101 char *sym, *stype; 2102 2103 if (current < ttc->ttc_first) 2104 current = 2105 ttc->ttc_limit - sizeof (trap_trace_rec_t); 2106 2107 if (current == (uintptr_t)NULL) 2108 continue; 2109 2110 rec = (trap_trace_rec_t *)current; 2111 2112 if (rec->ttr_stamp == 0) 2113 break; 2114 2115 (void) snprintf(data1, sizeof (data1), fmt1, i, 2116 (uintptr_t)rec, rec->ttr_stamp); 2117 2118 switch (rec->ttr_marker) { 2119 case TT_SYSCALL: 2120 case TT_SYSENTER: 2121 case TT_SYSC: 2122 case TT_SYSC64: 2123 sys = &sysent32[rec->ttr_sysnum]; 2124 switch (rec->ttr_marker) { 2125 case TT_SYSC64: 2126 sys = &sysent[rec->ttr_sysnum]; 2127 /* FALLTHROUGH */ 2128 case TT_SYSC: 2129 stype = "sysc"; /* syscall */ 2130 break; 2131 case TT_SYSCALL: 2132 stype = "lcal"; /* lcall */ 2133 break; 2134 case TT_SYSENTER: 2135 stype = "syse"; /* sysenter */ 2136 break; 2137 default: 2138 break; 2139 } 2140 (void) snprintf(data2, sizeof (data2), fmt2, 2141 stype, rec->ttr_sysnum); 2142 if (sys != NULL) { 2143 sym = kobj_getsymname( 2144 (uintptr_t)sys->sy_callc, 2145 &off); 2146 if (sym != NULL) { 2147 (void) snprintf(data3, 2148 sizeof (data3), fmt3s, sym); 2149 } else { 2150 (void) snprintf(data3, 2151 sizeof (data3), fmt3p, 2152 sys->sy_callc); 2153 } 2154 } else { 2155 (void) snprintf(data3, sizeof (data3), 2156 fmt3s, "unknown"); 2157 } 2158 break; 2159 2160 case TT_INTERRUPT: 2161 if (rec->ttr_regs.r_trapno == T_SOFTINT) { 2162 (void) snprintf(data2, sizeof (data2), 2163 fmt2s, "intr", "-"); 2164 (void) snprintf(data3, sizeof (data3), 2165 fmt3s, "(fakesoftint)"); 2166 break; 2167 } 2168 2169 (void) snprintf(data2, sizeof (data2), fmt2, 2170 "intr", rec->ttr_vector); 2171 if (get_intr_handler != NULL) 2172 vec = (struct autovec *) 2173 (*get_intr_handler) 2174 (rec->ttr_cpuid, rec->ttr_vector); 2175 else 2176 vec = 2177 autovect[rec->ttr_vector].avh_link; 2178 2179 if (vec != NULL) { 2180 sym = kobj_getsymname( 2181 (uintptr_t)vec->av_vector, &off); 2182 if (sym != NULL) { 2183 (void) snprintf(data3, 2184 sizeof (data3), fmt3s, sym); 2185 } else { 2186 (void) snprintf(data3, 2187 sizeof (data3), fmt3p, 2188 vec->av_vector); 2189 } 2190 } else { 2191 (void) snprintf(data3, sizeof (data3), 2192 fmt3s, "unknown"); 2193 } 2194 break; 2195 2196 case TT_TRAP: 2197 case TT_EVENT: 2198 type = rec->ttr_regs.r_trapno; 2199 (void) snprintf(data2, sizeof (data2), fmt2, 2200 "trap", type); 2201 if (type < TRAP_TYPES) { 2202 (void) snprintf(data3, sizeof (data3), 2203 fmt3h, trap_type_mnemonic[type]); 2204 } else { 2205 switch (type) { 2206 case T_AST: 2207 (void) snprintf(data3, 2208 sizeof (data3), fmt3s, 2209 "ast"); 2210 break; 2211 default: 2212 (void) snprintf(data3, 2213 sizeof (data3), fmt3s, ""); 2214 break; 2215 } 2216 } 2217 break; 2218 2219 default: 2220 break; 2221 } 2222 2223 sym = kobj_getsymname(rec->ttr_regs.r_pc, &off); 2224 if (sym != NULL) { 2225 printf("%s %s %s %s+%lx\n", data1, data2, data3, 2226 sym, off); 2227 } else { 2228 printf("%s %s %s %lx\n", data1, data2, data3, 2229 rec->ttr_regs.r_pc); 2230 } 2231 2232 if (ttrace_dump_nregs-- > 0) { 2233 int s; 2234 2235 if (rec->ttr_marker == TT_INTERRUPT) 2236 printf( 2237 "\t\tipl %x spl %x pri %x\n", 2238 rec->ttr_ipl, 2239 rec->ttr_spl, 2240 rec->ttr_pri); 2241 2242 dumpregs(&rec->ttr_regs); 2243 2244 printf("\t%3s: %p\n\n", " ct", 2245 (void *)rec->ttr_curthread); 2246 2247 /* 2248 * print out the pc stack that we recorded 2249 * at trap time (if any) 2250 */ 2251 for (s = 0; s < rec->ttr_sdepth; s++) { 2252 uintptr_t fullpc; 2253 2254 if (s >= TTR_STACK_DEPTH) { 2255 printf("ttr_sdepth corrupt\n"); 2256 break; 2257 } 2258 2259 fullpc = (uintptr_t)rec->ttr_stack[s]; 2260 2261 sym = kobj_getsymname(fullpc, &off); 2262 if (sym != NULL) 2263 printf("-> %s+0x%lx()\n", 2264 sym, off); 2265 else 2266 printf("-> 0x%lx()\n", fullpc); 2267 } 2268 printf("\n"); 2269 } 2270 current -= sizeof (trap_trace_rec_t); 2271 } 2272 } 2273 } 2274 2275 #endif /* TRAPTRACE */ 2276 2277 void 2278 panic_showtrap(struct panic_trap_info *tip) 2279 { 2280 showregs(tip->trap_type, tip->trap_regs, tip->trap_addr); 2281 2282 #if defined(TRAPTRACE) 2283 dump_ttrace(); 2284 #endif 2285 2286 #if !defined(__xpv) 2287 if (tip->trap_type == T_DBLFLT) 2288 dump_tss(); 2289 #endif 2290 } 2291 2292 void 2293 panic_savetrap(panic_data_t *pdp, struct panic_trap_info *tip) 2294 { 2295 panic_saveregs(pdp, tip->trap_regs); 2296 } 2297