1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 * 26 * Derived from pseudocode supplied by Intel. 27 */ 28 29 /* 30 * Workaround for Intel Orion chipset bug 31 * 32 * It is intended that this code implements exactly the workaround 33 * described in the errata. There is one exception, described below. 34 */ 35 36 #include <sys/types.h> 37 #include <sys/pci.h> 38 #include <sys/mutex.h> 39 #include <sys/pci_cfgspace_impl.h> 40 41 #define PCI_82454_RW_CONTROL 0x54 42 43 static int ncDevNo; 44 45 boolean_t 46 pci_is_broken_orion() 47 { 48 int Num82454 = 0; 49 boolean_t A2B0Found = B_FALSE; 50 boolean_t c82454PostingEnabled = B_FALSE; 51 uint8_t PciReg; 52 uint16_t VendorID; 53 uint16_t DeviceID; 54 boolean_t A2B0WorkAroundReqd; 55 56 int BusNo = 0; 57 int FunctionNo = 0; 58 int DeviceNo; 59 uint8_t RevisionID; 60 61 for (DeviceNo = 0; DeviceNo < PCI_MAX_DEVS; DeviceNo++) { 62 VendorID = pci_mech1_getw(BusNo, DeviceNo, FunctionNo, 63 PCI_CONF_VENID); 64 DeviceID = pci_mech1_getw(BusNo, DeviceNo, FunctionNo, 65 PCI_CONF_DEVID); 66 RevisionID = pci_mech1_getb(BusNo, DeviceNo, FunctionNo, 67 PCI_CONF_REVID); 68 if (VendorID == 0x8086 && DeviceID == 0x84c4) { 69 /* Found 82454 PCI Bridge */ 70 Num82454++; 71 if (RevisionID <= 4) { 72 A2B0Found = B_TRUE; 73 } 74 if (DeviceNo == (0xc8 >> 3)) { 75 /* 76 * c82454 Found - determine the status of 77 * inbound posting. 78 */ 79 PciReg = pci_mech1_getb(BusNo, DeviceNo, 80 FunctionNo, PCI_82454_RW_CONTROL); 81 if (PciReg & 0x01) { 82 c82454PostingEnabled = B_TRUE; 83 } 84 } else { 85 /* nc82454 Found - store device no. */ 86 ncDevNo = DeviceNo; 87 } 88 } 89 } /* DeviceNo */ 90 /* 91 * Determine if nc82454 posting is to be enabled 92 * and need of workaround. 93 * 94 * [[ This is a deviation from the pseudocode in the errata. 95 * The errata has mismatched braces, leading to uncertainty 96 * as to whether this code is inside the test for 8086/84c4. 97 * The errata has this code clearly inside the DeviceNo loop. 98 * This code is obviously pointless until you've at least found 99 * the second 82454, and there's no need to execute it more 100 * than once, so I'm moving it outside that loop to execute 101 * once on completion of the scan. ]] 102 */ 103 if (Num82454 >= 2 && A2B0Found && 104 c82454PostingEnabled) { 105 A2B0WorkAroundReqd = B_TRUE; 106 /* Enable inbound posting on nc82454 */ 107 PciReg = pci_mech1_getb(0, ncDevNo, 0, 108 PCI_82454_RW_CONTROL); 109 PciReg |= 0x01; 110 pci_mech1_putb(0, ncDevNo, 0, 111 PCI_82454_RW_CONTROL, PciReg); 112 } else { 113 A2B0WorkAroundReqd = B_FALSE; 114 } 115 116 return (A2B0WorkAroundReqd); 117 } 118 119 /* 120 * When I first read this code in the errata document, I asked "why doesn't 121 * the initial read of CFC (possibly) lead to the 'two responses' problem?" 122 * 123 * After thinking about it for a while, the answer is that we're trying to 124 * talk to the nc82454 itself. The c82454 doesn't have the problem, so it 125 * will recognize that this request is *not* for it, and won't respond. 126 * The nc82454 will either respond or not, depending on whether it "saw" 127 * the CF8 write, and if it responds it might or might not return the 128 * right data. That's all pretty much OK, if we're willing to assume 129 * that the only way that 84C48086 will come back is from the vendor ID/ 130 * device ID registers on the nc82454. This is probabilistic, of course, 131 * because the nc82454 *could* be pointing at a register on some device 132 * that just *happened* to have that value, but that seems unlikely. 133 */ 134 static void 135 FuncDisableInboundPostingnc82454() 136 { 137 uint32_t test; 138 uint8_t PciReg; 139 140 mutex_enter(&pcicfg_chipset_mutex); 141 do { 142 test = pci_mech1_getl(0, ncDevNo, 0, PCI_CONF_VENID); 143 } while (test != 0x84c48086UL); 144 145 /* 146 * At this point we are guaranteed to be pointing to the nc82454 PCI 147 * bridge Vendor ID register. 148 */ 149 do { 150 /* 151 * Impact of the erratum is that the configuration read will 152 * return the value which was last read. 153 * Hence read register 0x54 until the previous read value 154 * (VendorId/DeviceId) is not read anymore. 155 */ 156 test = pci_mech1_getl(0, ncDevNo, 0, PCI_82454_RW_CONTROL); 157 } while (test == 0x84c48086UL); 158 /* 159 * At this point we are guaranteed to be pointing to the PCI 160 * Read/Write Control Register in the nc82454 PCI Bridge. 161 */ 162 PciReg = pci_mech1_getb(0, ncDevNo, 0, PCI_82454_RW_CONTROL); 163 PciReg &= ~0x01; 164 pci_mech1_putb(0, ncDevNo, 0, PCI_82454_RW_CONTROL, PciReg); 165 } 166 167 static void 168 FuncEnableInboundPostingnc82454() 169 { 170 uint8_t PciReg; 171 172 PciReg = pci_mech1_getb(0, ncDevNo, 0, PCI_82454_RW_CONTROL); 173 PciReg |= 0x01; 174 pci_mech1_putb(0, ncDevNo, 0, PCI_82454_RW_CONTROL, PciReg); 175 mutex_exit(&pcicfg_chipset_mutex); 176 } 177 178 uint8_t 179 pci_orion_getb(int bus, int device, int function, int reg) 180 { 181 uint8_t val; 182 183 FuncDisableInboundPostingnc82454(); 184 185 val = pci_mech1_getb(bus, device, function, reg); 186 187 FuncEnableInboundPostingnc82454(); 188 return (val); 189 } 190 191 uint16_t 192 pci_orion_getw(int bus, int device, int function, int reg) 193 { 194 uint16_t val; 195 196 FuncDisableInboundPostingnc82454(); 197 198 val = pci_mech1_getw(bus, device, function, reg); 199 200 FuncEnableInboundPostingnc82454(); 201 return (val); 202 } 203 204 uint32_t 205 pci_orion_getl(int bus, int device, int function, int reg) 206 { 207 uint32_t val; 208 209 FuncDisableInboundPostingnc82454(); 210 211 val = pci_mech1_getl(bus, device, function, reg); 212 213 FuncEnableInboundPostingnc82454(); 214 return (val); 215 } 216 217 void 218 pci_orion_putb(int bus, int device, int function, int reg, uint8_t val) 219 { 220 FuncDisableInboundPostingnc82454(); 221 222 pci_mech1_putb(bus, device, function, reg, val); 223 224 FuncEnableInboundPostingnc82454(); 225 } 226 227 void 228 pci_orion_putw(int bus, int device, int function, int reg, uint16_t val) 229 { 230 FuncDisableInboundPostingnc82454(); 231 232 pci_mech1_putw(bus, device, function, reg, val); 233 234 FuncEnableInboundPostingnc82454(); 235 } 236 237 void 238 pci_orion_putl(int bus, int device, int function, int reg, uint32_t val) 239 { 240 FuncDisableInboundPostingnc82454(); 241 242 pci_mech1_putl(bus, device, function, reg, val); 243 244 FuncEnableInboundPostingnc82454(); 245 } 246