1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 26 /* 27 * PCI configuration space access routines 28 */ 29 30 #include <sys/systm.h> 31 #include <sys/psw.h> 32 #include <sys/bootconf.h> 33 #include <sys/reboot.h> 34 #include <sys/pci_impl.h> 35 #include <sys/pci_cfgspace.h> 36 #include <sys/pci_cfgspace_impl.h> 37 #include <sys/pci_cfgacc.h> 38 #if defined(__xpv) 39 #include <sys/hypervisor.h> 40 #endif 41 42 #if defined(__xpv) 43 int pci_max_nbus = 0xFE; 44 #else 45 int pci_max_nbus = 0xFF; 46 #endif 47 int pci_bios_cfg_type = PCI_MECHANISM_UNKNOWN; 48 int pci_bios_maxbus; 49 int pci_bios_mech; 50 int pci_bios_vers; 51 52 /* 53 * These two variables can be used to force a configuration mechanism or 54 * to force which function is used to probe for the presence of the PCI bus. 55 */ 56 int PCI_CFG_TYPE = 0; 57 int PCI_PROBE_TYPE = 0; 58 59 /* 60 * No valid mcfg_mem_base by default, and accessing pci config space 61 * in mem-mapped way is disabled. 62 */ 63 uint64_t mcfg_mem_base = 0; 64 uint8_t mcfg_bus_start = 0; 65 uint8_t mcfg_bus_end = 0xff; 66 67 /* 68 * Maximum offset in config space when not using MMIO 69 */ 70 uint_t pci_iocfg_max_offset = 0xff; 71 72 /* 73 * These function pointers lead to the actual implementation routines 74 * for configuration space access. Normally they lead to either the 75 * pci_mech1_* or pci_mech2_* routines, but they can also lead to 76 * routines that work around chipset bugs. 77 * These functions are accessing pci config space via I/O way. 78 * Pci_cfgacc_get/put functions shoul be used as more common interfaces, 79 * which also provide accessing pci config space via mem-mapped way. 80 */ 81 uint8_t (*pci_getb_func)(int bus, int dev, int func, int reg); 82 uint16_t (*pci_getw_func)(int bus, int dev, int func, int reg); 83 uint32_t (*pci_getl_func)(int bus, int dev, int func, int reg); 84 void (*pci_putb_func)(int bus, int dev, int func, int reg, uint8_t val); 85 void (*pci_putw_func)(int bus, int dev, int func, int reg, uint16_t val); 86 void (*pci_putl_func)(int bus, int dev, int func, int reg, uint32_t val); 87 88 extern void (*pci_cfgacc_acc_p)(pci_cfgacc_req_t *req); 89 90 /* 91 * Internal routines 92 */ 93 static int pci_check(void); 94 95 #if !defined(__xpv) 96 static int pci_check_bios(void); 97 static int pci_get_cfg_type(void); 98 #endif 99 100 /* for legacy io-based config space access */ 101 kmutex_t pcicfg_mutex; 102 103 /* for mmio-based config space access */ 104 kmutex_t pcicfg_mmio_mutex; 105 106 /* ..except Orion and Neptune, which have to have their own */ 107 kmutex_t pcicfg_chipset_mutex; 108 109 void 110 pci_cfgspace_init(void) 111 { 112 mutex_init(&pcicfg_mutex, NULL, MUTEX_SPIN, 113 (ddi_iblock_cookie_t)ipltospl(15)); 114 mutex_init(&pcicfg_mmio_mutex, NULL, MUTEX_SPIN, 115 (ddi_iblock_cookie_t)ipltospl(DISP_LEVEL)); 116 mutex_init(&pcicfg_chipset_mutex, NULL, MUTEX_SPIN, 117 (ddi_iblock_cookie_t)ipltospl(15)); 118 if (!pci_check()) { 119 mutex_destroy(&pcicfg_mutex); 120 mutex_destroy(&pcicfg_mmio_mutex); 121 mutex_destroy(&pcicfg_chipset_mutex); 122 } 123 } 124 125 /* 126 * This code determines if this system supports PCI/PCIE and which 127 * type of configuration access method is used 128 */ 129 static int 130 pci_check(void) 131 { 132 uint64_t ecfginfo[4]; 133 134 /* 135 * Only do this once. NB: If this is not a PCI system, and we 136 * get called twice, we can't detect it and will probably die 137 * horribly when we try to ask the BIOS whether PCI is present. 138 * This code is safe *ONLY* during system startup when the 139 * BIOS is still available. 140 */ 141 if (pci_bios_cfg_type != PCI_MECHANISM_UNKNOWN) 142 return (TRUE); 143 144 #if defined(__xpv) 145 /* 146 * only support PCI config mechanism 1 in i86xpv. This should be fine 147 * since the other ones are workarounds for old broken H/W which won't 148 * be supported in i86xpv anyway. 149 */ 150 if (DOMAIN_IS_INITDOMAIN(xen_info)) { 151 pci_bios_cfg_type = PCI_MECHANISM_1; 152 pci_getb_func = pci_mech1_getb; 153 pci_getw_func = pci_mech1_getw; 154 pci_getl_func = pci_mech1_getl; 155 pci_putb_func = pci_mech1_putb; 156 pci_putw_func = pci_mech1_putw; 157 pci_putl_func = pci_mech1_putl; 158 159 /* 160 * Since we can't get the BIOS info in i86xpv, we will do an 161 * exhaustive search of all PCI buses. We have to do this until 162 * we start using the PCI information in ACPI. 163 */ 164 pci_bios_maxbus = pci_max_nbus; 165 } 166 #else /* !__xpv */ 167 168 pci_bios_cfg_type = pci_check_bios(); 169 170 if (pci_bios_cfg_type == PCI_MECHANISM_NONE) 171 pci_bios_cfg_type = PCI_MECHANISM_1; /* default to mech 1 */ 172 173 switch (pci_get_cfg_type()) { 174 case PCI_MECHANISM_1: 175 if (pci_is_broken_orion()) { 176 pci_getb_func = pci_orion_getb; 177 pci_getw_func = pci_orion_getw; 178 pci_getl_func = pci_orion_getl; 179 pci_putb_func = pci_orion_putb; 180 pci_putw_func = pci_orion_putw; 181 pci_putl_func = pci_orion_putl; 182 } else if (pci_check_amd_ioecs()) { 183 pci_getb_func = pci_mech1_amd_getb; 184 pci_getw_func = pci_mech1_amd_getw; 185 pci_getl_func = pci_mech1_amd_getl; 186 pci_putb_func = pci_mech1_amd_putb; 187 pci_putw_func = pci_mech1_amd_putw; 188 pci_putl_func = pci_mech1_amd_putl; 189 pci_iocfg_max_offset = 0xfff; 190 } else { 191 pci_getb_func = pci_mech1_getb; 192 pci_getw_func = pci_mech1_getw; 193 pci_getl_func = pci_mech1_getl; 194 pci_putb_func = pci_mech1_putb; 195 pci_putw_func = pci_mech1_putw; 196 pci_putl_func = pci_mech1_putl; 197 } 198 break; 199 200 case PCI_MECHANISM_2: 201 if (pci_check_neptune()) { 202 /* 203 * The BIOS for some systems with the Intel 204 * Neptune chipset seem to default to #2 even 205 * though the chipset can do #1. Override 206 * the BIOS so that MP systems will work 207 * correctly. 208 */ 209 210 pci_getb_func = pci_neptune_getb; 211 pci_getw_func = pci_neptune_getw; 212 pci_getl_func = pci_neptune_getl; 213 pci_putb_func = pci_neptune_putb; 214 pci_putw_func = pci_neptune_putw; 215 pci_putl_func = pci_neptune_putl; 216 } else { 217 pci_getb_func = pci_mech2_getb; 218 pci_getw_func = pci_mech2_getw; 219 pci_getl_func = pci_mech2_getl; 220 pci_putb_func = pci_mech2_putb; 221 pci_putw_func = pci_mech2_putw; 222 pci_putl_func = pci_mech2_putl; 223 } 224 break; 225 226 default: 227 return (FALSE); 228 } 229 #endif /* __xpv */ 230 231 /* 232 * Try to get a valid mcfg_mem_base in early boot 233 * If failed, leave mem-mapped pci config space accessing disabled 234 * until pci boot code (pci_autoconfig) makes sure this is a PCIE 235 * platform. 236 */ 237 if (do_bsys_getprop(NULL, MCFG_PROPNAME, ecfginfo) != -1) { 238 mcfg_mem_base = ecfginfo[0]; 239 mcfg_bus_start = ecfginfo[2]; 240 mcfg_bus_end = ecfginfo[3]; 241 } 242 243 /* See pci_cfgacc.c */ 244 pci_cfgacc_acc_p = pci_cfgacc_acc; 245 246 return (TRUE); 247 } 248 249 #if !defined(__xpv) 250 251 static int 252 pci_check_bios(void) 253 { 254 struct bop_regs regs; 255 uint32_t carryflag; 256 uint16_t ax, dx; 257 258 /* 259 * This mechanism uses a legacy BIOS call to detect PCI configuration, 260 * but such calls are not available on systems with UEFI firmware. 261 * For UEFI systems we must assume some reasonable defaults and scan 262 * all possible buses. 263 */ 264 if (BOP_GETPROPLEN(bootops, "efi-systab") > 0) { 265 pci_bios_mech = 1; 266 pci_bios_vers = 0; 267 pci_bios_maxbus = pci_max_nbus; 268 return (PCI_MECHANISM_1); 269 } 270 271 bzero(®s, sizeof (regs)); 272 regs.eax.word.ax = (PCI_FUNCTION_ID << 8) | PCI_BIOS_PRESENT; 273 274 BOP_DOINT(bootops, 0x1a, ®s); 275 carryflag = regs.eflags & PS_C; 276 ax = regs.eax.word.ax; 277 dx = regs.edx.word.dx; 278 279 /* the carry flag must not be set */ 280 if (carryflag != 0) 281 return (PCI_MECHANISM_NONE); 282 283 if (dx != ('P' | 'C'<<8)) 284 return (PCI_MECHANISM_NONE); 285 286 /* ah (the high byte of ax) must be zero */ 287 if ((ax & 0xff00) != 0) 288 return (PCI_MECHANISM_NONE); 289 290 pci_bios_mech = (ax & 0x3); 291 pci_bios_vers = regs.ebx.word.bx; 292 pci_bios_maxbus = (regs.ecx.word.cx & 0xff); 293 294 switch (pci_bios_mech) { 295 default: /* ?!? */ 296 case 0: /* supports neither? */ 297 return (PCI_MECHANISM_NONE); 298 299 case 1: 300 case 3: /* supports both */ 301 return (PCI_MECHANISM_1); 302 303 case 2: 304 return (PCI_MECHANISM_2); 305 } 306 } 307 308 static int 309 pci_get_cfg_type(void) 310 { 311 /* Check to see if the config mechanism has been set in /etc/system */ 312 switch (PCI_CFG_TYPE) { 313 default: 314 case 0: 315 break; 316 case 1: 317 return (PCI_MECHANISM_1); 318 case 2: 319 return (PCI_MECHANISM_2); 320 case -1: 321 return (PCI_MECHANISM_NONE); 322 } 323 324 /* call one of the PCI detection algorithms */ 325 switch (PCI_PROBE_TYPE) { 326 default: 327 case 0: 328 /* From pci_check() and pci_check_bios() */ 329 return (pci_bios_cfg_type); 330 case -1: 331 return (PCI_MECHANISM_NONE); 332 } 333 } 334 335 #endif /* __xpv */ 336