1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include <sys/types.h> 28 #include <sys/thread.h> 29 #include <sys/cpuvar.h> 30 #include <sys/t_lock.h> 31 #include <sys/param.h> 32 #include <sys/proc.h> 33 #include <sys/disp.h> 34 #include <sys/class.h> 35 #include <sys/cmn_err.h> 36 #include <sys/debug.h> 37 #include <sys/asm_linkage.h> 38 #include <sys/x_call.h> 39 #include <sys/systm.h> 40 #include <sys/var.h> 41 #include <sys/vtrace.h> 42 #include <vm/hat.h> 43 #include <vm/as.h> 44 #include <vm/seg_kmem.h> 45 #include <vm/seg_kp.h> 46 #include <sys/segments.h> 47 #include <sys/kmem.h> 48 #include <sys/stack.h> 49 #include <sys/smp_impldefs.h> 50 #include <sys/x86_archext.h> 51 #include <sys/machsystm.h> 52 #include <sys/traptrace.h> 53 #include <sys/clock.h> 54 #include <sys/cpc_impl.h> 55 #include <sys/pg.h> 56 #include <sys/cmt.h> 57 #include <sys/dtrace.h> 58 #include <sys/archsystm.h> 59 #include <sys/fp.h> 60 #include <sys/reboot.h> 61 #include <sys/kdi_machimpl.h> 62 #include <vm/hat_i86.h> 63 #include <sys/memnode.h> 64 #include <sys/pci_cfgspace.h> 65 #include <sys/mach_mmu.h> 66 #include <sys/sysmacros.h> 67 #if defined(__xpv) 68 #include <sys/hypervisor.h> 69 #endif 70 #include <sys/cpu_module.h> 71 72 struct cpu cpus[1]; /* CPU data */ 73 struct cpu *cpu[NCPU] = {&cpus[0]}; /* pointers to all CPUs */ 74 cpu_core_t cpu_core[NCPU]; /* cpu_core structures */ 75 76 /* 77 * Useful for disabling MP bring-up on a MP capable system. 78 */ 79 int use_mp = 1; 80 81 /* 82 * to be set by a PSM to indicate what cpus 83 * are sitting around on the system. 84 */ 85 cpuset_t mp_cpus; 86 87 /* 88 * This variable is used by the hat layer to decide whether or not 89 * critical sections are needed to prevent race conditions. For sun4m, 90 * this variable is set once enough MP initialization has been done in 91 * order to allow cross calls. 92 */ 93 int flushes_require_xcalls; 94 95 cpuset_t cpu_ready_set; /* initialized in startup() */ 96 97 static void mp_startup(void); 98 99 static void cpu_sep_enable(void); 100 static void cpu_sep_disable(void); 101 static void cpu_asysc_enable(void); 102 static void cpu_asysc_disable(void); 103 104 /* 105 * Init CPU info - get CPU type info for processor_info system call. 106 */ 107 void 108 init_cpu_info(struct cpu *cp) 109 { 110 processor_info_t *pi = &cp->cpu_type_info; 111 char buf[CPU_IDSTRLEN]; 112 113 /* 114 * Get clock-frequency property for the CPU. 115 */ 116 pi->pi_clock = cpu_freq; 117 118 /* 119 * Current frequency in Hz. 120 */ 121 cp->cpu_curr_clock = cpu_freq_hz; 122 123 /* 124 * Supported frequencies. 125 */ 126 cpu_set_supp_freqs(cp, NULL); 127 128 (void) strcpy(pi->pi_processor_type, "i386"); 129 if (fpu_exists) 130 (void) strcpy(pi->pi_fputypes, "i387 compatible"); 131 132 (void) cpuid_getidstr(cp, buf, sizeof (buf)); 133 134 cp->cpu_idstr = kmem_alloc(strlen(buf) + 1, KM_SLEEP); 135 (void) strcpy(cp->cpu_idstr, buf); 136 137 (void) cpuid_getbrandstr(cp, buf, sizeof (buf)); 138 cp->cpu_brandstr = kmem_alloc(strlen(buf) + 1, KM_SLEEP); 139 (void) strcpy(cp->cpu_brandstr, buf); 140 } 141 142 /* 143 * Configure syscall support on this CPU. 144 */ 145 /*ARGSUSED*/ 146 void 147 init_cpu_syscall(struct cpu *cp) 148 { 149 kpreempt_disable(); 150 151 #if defined(__amd64) 152 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) { 153 154 #if !defined(__lint) 155 /* 156 * The syscall instruction imposes a certain ordering on 157 * segment selectors, so we double-check that ordering 158 * here. 159 */ 160 ASSERT(KDS_SEL == KCS_SEL + 8); 161 ASSERT(UDS_SEL == U32CS_SEL + 8); 162 ASSERT(UCS_SEL == U32CS_SEL + 16); 163 #endif 164 /* 165 * Turn syscall/sysret extensions on. 166 */ 167 cpu_asysc_enable(); 168 169 /* 170 * Program the magic registers .. 171 */ 172 wrmsr(MSR_AMD_STAR, 173 ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32); 174 wrmsr(MSR_AMD_LSTAR, (uint64_t)(uintptr_t)sys_syscall); 175 wrmsr(MSR_AMD_CSTAR, (uint64_t)(uintptr_t)sys_syscall32); 176 177 /* 178 * This list of flags is masked off the incoming 179 * %rfl when we enter the kernel. 180 */ 181 wrmsr(MSR_AMD_SFMASK, (uint64_t)(uintptr_t)(PS_IE | PS_T)); 182 } 183 #endif 184 185 /* 186 * On 32-bit kernels, we use sysenter/sysexit because it's too 187 * hard to use syscall/sysret, and it is more portable anyway. 188 * 189 * On 64-bit kernels on Nocona machines, the 32-bit syscall 190 * variant isn't available to 32-bit applications, but sysenter is. 191 */ 192 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) { 193 194 #if !defined(__lint) 195 /* 196 * The sysenter instruction imposes a certain ordering on 197 * segment selectors, so we double-check that ordering 198 * here. See "sysenter" in Intel document 245471-012, "IA-32 199 * Intel Architecture Software Developer's Manual Volume 2: 200 * Instruction Set Reference" 201 */ 202 ASSERT(KDS_SEL == KCS_SEL + 8); 203 204 ASSERT32(UCS_SEL == ((KCS_SEL + 16) | 3)); 205 ASSERT32(UDS_SEL == UCS_SEL + 8); 206 207 ASSERT64(U32CS_SEL == ((KCS_SEL + 16) | 3)); 208 ASSERT64(UDS_SEL == U32CS_SEL + 8); 209 #endif 210 211 cpu_sep_enable(); 212 213 /* 214 * resume() sets this value to the base of the threads stack 215 * via a context handler. 216 */ 217 wrmsr(MSR_INTC_SEP_ESP, 0); 218 wrmsr(MSR_INTC_SEP_EIP, (uint64_t)(uintptr_t)sys_sysenter); 219 } 220 221 kpreempt_enable(); 222 } 223 224 /* 225 * Multiprocessor initialization. 226 * 227 * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the 228 * startup and idle threads for the specified CPU. 229 */ 230 struct cpu * 231 mp_startup_init(int cpun) 232 { 233 struct cpu *cp; 234 kthread_id_t tp; 235 caddr_t sp; 236 proc_t *procp; 237 #if !defined(__xpv) 238 extern int idle_cpu_prefer_mwait; 239 #endif 240 extern void idle(); 241 242 #ifdef TRAPTRACE 243 trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun]; 244 #endif 245 246 ASSERT(cpun < NCPU && cpu[cpun] == NULL); 247 248 cp = kmem_zalloc(sizeof (*cp), KM_SLEEP); 249 #if !defined(__xpv) 250 if ((x86_feature & X86_MWAIT) && idle_cpu_prefer_mwait) 251 cp->cpu_m.mcpu_mwait = cpuid_mwait_alloc(CPU); 252 #endif 253 254 procp = curthread->t_procp; 255 256 mutex_enter(&cpu_lock); 257 /* 258 * Initialize the dispatcher first. 259 */ 260 disp_cpu_init(cp); 261 mutex_exit(&cpu_lock); 262 263 cpu_vm_data_init(cp); 264 265 /* 266 * Allocate and initialize the startup thread for this CPU. 267 * Interrupt and process switch stacks get allocated later 268 * when the CPU starts running. 269 */ 270 tp = thread_create(NULL, 0, NULL, NULL, 0, procp, 271 TS_STOPPED, maxclsyspri); 272 273 /* 274 * Set state to TS_ONPROC since this thread will start running 275 * as soon as the CPU comes online. 276 * 277 * All the other fields of the thread structure are setup by 278 * thread_create(). 279 */ 280 THREAD_ONPROC(tp, cp); 281 tp->t_preempt = 1; 282 tp->t_bound_cpu = cp; 283 tp->t_affinitycnt = 1; 284 tp->t_cpu = cp; 285 tp->t_disp_queue = cp->cpu_disp; 286 287 /* 288 * Setup thread to start in mp_startup. 289 */ 290 sp = tp->t_stk; 291 tp->t_pc = (uintptr_t)mp_startup; 292 tp->t_sp = (uintptr_t)(sp - MINFRAME); 293 #if defined(__amd64) 294 tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */ 295 #endif 296 297 cp->cpu_id = cpun; 298 cp->cpu_self = cp; 299 cp->cpu_thread = tp; 300 cp->cpu_lwp = NULL; 301 cp->cpu_dispthread = tp; 302 cp->cpu_dispatch_pri = DISP_PRIO(tp); 303 304 /* 305 * cpu_base_spl must be set explicitly here to prevent any blocking 306 * operations in mp_startup from causing the spl of the cpu to drop 307 * to 0 (allowing device interrupts before we're ready) in resume(). 308 * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY. 309 * As an extra bit of security on DEBUG kernels, this is enforced with 310 * an assertion in mp_startup() -- before cpu_base_spl is set to its 311 * proper value. 312 */ 313 cp->cpu_base_spl = ipltospl(LOCK_LEVEL); 314 315 /* 316 * Now, initialize per-CPU idle thread for this CPU. 317 */ 318 tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1); 319 320 cp->cpu_idle_thread = tp; 321 322 tp->t_preempt = 1; 323 tp->t_bound_cpu = cp; 324 tp->t_affinitycnt = 1; 325 tp->t_cpu = cp; 326 tp->t_disp_queue = cp->cpu_disp; 327 328 /* 329 * Bootstrap the CPU's PG data 330 */ 331 pg_cpu_bootstrap(cp); 332 333 /* 334 * Perform CPC initialization on the new CPU. 335 */ 336 kcpc_hw_init(cp); 337 338 /* 339 * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2 340 * for each CPU. 341 */ 342 setup_vaddr_for_ppcopy(cp); 343 344 /* 345 * Allocate page for new GDT and initialize from current GDT. 346 */ 347 #if !defined(__lint) 348 ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE); 349 #endif 350 cp->cpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP); 351 bcopy(CPU->cpu_gdt, cp->cpu_gdt, (sizeof (*cp->cpu_gdt) * NGDT)); 352 353 #if defined(__i386) 354 /* 355 * setup kernel %gs. 356 */ 357 set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA, 358 SEL_KPL, 0, 1); 359 #endif 360 361 /* 362 * If we have more than one node, each cpu gets a copy of IDT 363 * local to its node. If this is a Pentium box, we use cpu 0's 364 * IDT. cpu 0's IDT has been made read-only to workaround the 365 * cmpxchgl register bug 366 */ 367 if (system_hardware.hd_nodes && x86_type != X86_TYPE_P5) { 368 #if !defined(__lint) 369 ASSERT((sizeof (*CPU->cpu_idt) * NIDT) <= PAGESIZE); 370 #endif 371 cp->cpu_idt = kmem_zalloc(PAGESIZE, KM_SLEEP); 372 bcopy(CPU->cpu_idt, cp->cpu_idt, PAGESIZE); 373 } else { 374 cp->cpu_idt = CPU->cpu_idt; 375 } 376 377 /* 378 * Get interrupt priority data from cpu 0. 379 */ 380 cp->cpu_pri_data = CPU->cpu_pri_data; 381 382 /* 383 * alloc space for cpuid info 384 */ 385 cpuid_alloc_space(cp); 386 387 /* 388 * alloc space for ucode_info 389 */ 390 ucode_alloc_space(cp); 391 392 hat_cpu_online(cp); 393 394 #ifdef TRAPTRACE 395 /* 396 * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers 397 */ 398 ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP); 399 ttc->ttc_next = ttc->ttc_first; 400 ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize; 401 #endif 402 /* 403 * Record that we have another CPU. 404 */ 405 mutex_enter(&cpu_lock); 406 /* 407 * Initialize the interrupt threads for this CPU 408 */ 409 cpu_intr_alloc(cp, NINTR_THREADS); 410 /* 411 * Add CPU to list of available CPUs. It'll be on the active list 412 * after mp_startup(). 413 */ 414 cpu_add_unit(cp); 415 mutex_exit(&cpu_lock); 416 417 return (cp); 418 } 419 420 /* 421 * Undo what was done in mp_startup_init 422 */ 423 static void 424 mp_startup_fini(struct cpu *cp, int error) 425 { 426 mutex_enter(&cpu_lock); 427 428 /* 429 * Remove the CPU from the list of available CPUs. 430 */ 431 cpu_del_unit(cp->cpu_id); 432 433 if (error == ETIMEDOUT) { 434 /* 435 * The cpu was started, but never *seemed* to run any 436 * code in the kernel; it's probably off spinning in its 437 * own private world, though with potential references to 438 * our kmem-allocated IDTs and GDTs (for example). 439 * 440 * Worse still, it may actually wake up some time later, 441 * so rather than guess what it might or might not do, we 442 * leave the fundamental data structures intact. 443 */ 444 cp->cpu_flags = 0; 445 mutex_exit(&cpu_lock); 446 return; 447 } 448 449 /* 450 * At this point, the only threads bound to this CPU should 451 * special per-cpu threads: it's idle thread, it's pause threads, 452 * and it's interrupt threads. Clean these up. 453 */ 454 cpu_destroy_bound_threads(cp); 455 cp->cpu_idle_thread = NULL; 456 457 /* 458 * Free the interrupt stack. 459 */ 460 segkp_release(segkp, 461 cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME))); 462 463 mutex_exit(&cpu_lock); 464 465 #ifdef TRAPTRACE 466 /* 467 * Discard the trap trace buffer 468 */ 469 { 470 trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id]; 471 472 kmem_free((void *)ttc->ttc_first, trap_trace_bufsize); 473 ttc->ttc_first = NULL; 474 } 475 #endif 476 477 hat_cpu_offline(cp); 478 479 cpuid_free_space(cp); 480 481 ucode_free_space(cp); 482 483 if (cp->cpu_idt != CPU->cpu_idt) 484 kmem_free(cp->cpu_idt, PAGESIZE); 485 cp->cpu_idt = NULL; 486 487 kmem_free(cp->cpu_gdt, PAGESIZE); 488 cp->cpu_gdt = NULL; 489 490 teardown_vaddr_for_ppcopy(cp); 491 492 kcpc_hw_fini(cp); 493 494 cp->cpu_dispthread = NULL; 495 cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */ 496 497 cpu_vm_data_destroy(cp); 498 499 mutex_enter(&cpu_lock); 500 disp_cpu_fini(cp); 501 mutex_exit(&cpu_lock); 502 503 #if !defined(__xpv) 504 if (cp->cpu_m.mcpu_mwait != NULL) 505 cpuid_mwait_free(cp); 506 #endif 507 kmem_free(cp, sizeof (*cp)); 508 } 509 510 /* 511 * Apply workarounds for known errata, and warn about those that are absent. 512 * 513 * System vendors occasionally create configurations which contain different 514 * revisions of the CPUs that are almost but not exactly the same. At the 515 * time of writing, this meant that their clock rates were the same, their 516 * feature sets were the same, but the required workaround were -not- 517 * necessarily the same. So, this routine is invoked on -every- CPU soon 518 * after starting to make sure that the resulting system contains the most 519 * pessimal set of workarounds needed to cope with *any* of the CPUs in the 520 * system. 521 * 522 * workaround_errata is invoked early in mlsetup() for CPU 0, and in 523 * mp_startup() for all slave CPUs. Slaves process workaround_errata prior 524 * to acknowledging their readiness to the master, so this routine will 525 * never be executed by multiple CPUs in parallel, thus making updates to 526 * global data safe. 527 * 528 * These workarounds are based on Rev 3.57 of the Revision Guide for 529 * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005. 530 */ 531 532 #if defined(OPTERON_ERRATUM_88) 533 int opteron_erratum_88; /* if non-zero -> at least one cpu has it */ 534 #endif 535 536 #if defined(OPTERON_ERRATUM_91) 537 int opteron_erratum_91; /* if non-zero -> at least one cpu has it */ 538 #endif 539 540 #if defined(OPTERON_ERRATUM_93) 541 int opteron_erratum_93; /* if non-zero -> at least one cpu has it */ 542 #endif 543 544 #if defined(OPTERON_ERRATUM_95) 545 int opteron_erratum_95; /* if non-zero -> at least one cpu has it */ 546 #endif 547 548 #if defined(OPTERON_ERRATUM_100) 549 int opteron_erratum_100; /* if non-zero -> at least one cpu has it */ 550 #endif 551 552 #if defined(OPTERON_ERRATUM_108) 553 int opteron_erratum_108; /* if non-zero -> at least one cpu has it */ 554 #endif 555 556 #if defined(OPTERON_ERRATUM_109) 557 int opteron_erratum_109; /* if non-zero -> at least one cpu has it */ 558 #endif 559 560 #if defined(OPTERON_ERRATUM_121) 561 int opteron_erratum_121; /* if non-zero -> at least one cpu has it */ 562 #endif 563 564 #if defined(OPTERON_ERRATUM_122) 565 int opteron_erratum_122; /* if non-zero -> at least one cpu has it */ 566 #endif 567 568 #if defined(OPTERON_ERRATUM_123) 569 int opteron_erratum_123; /* if non-zero -> at least one cpu has it */ 570 #endif 571 572 #if defined(OPTERON_ERRATUM_131) 573 int opteron_erratum_131; /* if non-zero -> at least one cpu has it */ 574 #endif 575 576 #if defined(OPTERON_WORKAROUND_6336786) 577 int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */ 578 int opteron_workaround_6336786_UP = 0; /* Not needed for UP */ 579 #endif 580 581 #if defined(OPTERON_WORKAROUND_6323525) 582 int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */ 583 #endif 584 585 #if defined(OPTERON_ERRATUM_298) 586 int opteron_erratum_298; 587 #endif 588 589 static void 590 workaround_warning(cpu_t *cp, uint_t erratum) 591 { 592 cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u", 593 cp->cpu_id, erratum); 594 } 595 596 static void 597 workaround_applied(uint_t erratum) 598 { 599 if (erratum > 1000000) 600 cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n", 601 erratum); 602 else 603 cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n", 604 erratum); 605 } 606 607 static void 608 msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error) 609 { 610 cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d", 611 cp->cpu_id, rw, msr, error); 612 } 613 614 /* 615 * Determine the number of nodes in an Opteron / Greyhound family system. 616 */ 617 static uint_t 618 opteron_get_nnodes(void) 619 { 620 static uint_t nnodes = 0; 621 622 #ifdef DEBUG 623 uint_t family; 624 625 family = cpuid_getfamily(CPU); 626 ASSERT(family == 0xf || family == 0x10); 627 #endif /* DEBUG */ 628 629 if (nnodes == 0) { 630 /* 631 * Obtain the number of nodes in the system from 632 * bits [6:4] of the Node ID register on node 0. 633 * 634 * The actual node count is NodeID[6:4] + 1 635 * 636 * The Node ID register is accessed via function 0, 637 * offset 0x60. Node 0 is device 24. 638 */ 639 nnodes = ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1; 640 } 641 return (nnodes); 642 } 643 644 #if defined(__xpv) 645 646 /* 647 * On dom0, we can determine the number of physical cpus on the machine. 648 * This number is important when figuring out what workarounds are 649 * appropriate, so compute it now. 650 */ 651 uint_t 652 xen_get_nphyscpus(void) 653 { 654 static uint_t nphyscpus = 0; 655 656 ASSERT(DOMAIN_IS_INITDOMAIN(xen_info)); 657 658 if (nphyscpus == 0) { 659 xen_sysctl_t op; 660 xen_sysctl_physinfo_t *pi = &op.u.physinfo; 661 662 op.cmd = XEN_SYSCTL_physinfo; 663 op.interface_version = XEN_SYSCTL_INTERFACE_VERSION; 664 if (HYPERVISOR_sysctl(&op) == 0) 665 nphyscpus = pi->threads_per_core * 666 pi->cores_per_socket * pi->sockets_per_node * 667 pi->nr_nodes; 668 } 669 return (nphyscpus); 670 } 671 #endif 672 673 uint_t 674 do_erratum_298(struct cpu *cpu) 675 { 676 static int osvwrc = -3; 677 extern int osvw_opteron_erratum(cpu_t *, uint_t); 678 679 /* 680 * L2 Eviction May Occur During Processor Operation To Set 681 * Accessed or Dirty Bit. 682 */ 683 if (osvwrc == -3) { 684 osvwrc = osvw_opteron_erratum(cpu, 298); 685 } else { 686 /* osvw return codes should be consistent for all cpus */ 687 ASSERT(osvwrc == osvw_opteron_erratum(cpu, 298)); 688 } 689 690 switch (osvwrc) { 691 case 0: /* erratum is not present: do nothing */ 692 break; 693 case 1: /* erratum is present: BIOS workaround applied */ 694 /* 695 * check if workaround is actually in place and issue warning 696 * if not. 697 */ 698 if (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || 699 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0)) { 700 #if defined(OPTERON_ERRATUM_298) 701 opteron_erratum_298++; 702 #else 703 workaround_warning(cpu, 298); 704 return (1); 705 #endif 706 } 707 break; 708 case -1: /* cannot determine via osvw: check cpuid */ 709 if ((cpuid_opteron_erratum(cpu, 298) > 0) && 710 (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || 711 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0))) { 712 #if defined(OPTERON_ERRATUM_298) 713 opteron_erratum_298++; 714 #else 715 workaround_warning(cpu, 298); 716 return (1); 717 #endif 718 } 719 break; 720 } 721 return (0); 722 } 723 724 uint_t 725 workaround_errata(struct cpu *cpu) 726 { 727 uint_t missing = 0; 728 729 ASSERT(cpu == CPU); 730 731 /*LINTED*/ 732 if (cpuid_opteron_erratum(cpu, 88) > 0) { 733 /* 734 * SWAPGS May Fail To Read Correct GS Base 735 */ 736 #if defined(OPTERON_ERRATUM_88) 737 /* 738 * The workaround is an mfence in the relevant assembler code 739 */ 740 opteron_erratum_88++; 741 #else 742 workaround_warning(cpu, 88); 743 missing++; 744 #endif 745 } 746 747 if (cpuid_opteron_erratum(cpu, 91) > 0) { 748 /* 749 * Software Prefetches May Report A Page Fault 750 */ 751 #if defined(OPTERON_ERRATUM_91) 752 /* 753 * fix is in trap.c 754 */ 755 opteron_erratum_91++; 756 #else 757 workaround_warning(cpu, 91); 758 missing++; 759 #endif 760 } 761 762 if (cpuid_opteron_erratum(cpu, 93) > 0) { 763 /* 764 * RSM Auto-Halt Restart Returns to Incorrect RIP 765 */ 766 #if defined(OPTERON_ERRATUM_93) 767 /* 768 * fix is in trap.c 769 */ 770 opteron_erratum_93++; 771 #else 772 workaround_warning(cpu, 93); 773 missing++; 774 #endif 775 } 776 777 /*LINTED*/ 778 if (cpuid_opteron_erratum(cpu, 95) > 0) { 779 /* 780 * RET Instruction May Return to Incorrect EIP 781 */ 782 #if defined(OPTERON_ERRATUM_95) 783 #if defined(_LP64) 784 /* 785 * Workaround this by ensuring that 32-bit user code and 786 * 64-bit kernel code never occupy the same address 787 * range mod 4G. 788 */ 789 if (_userlimit32 > 0xc0000000ul) 790 *(uintptr_t *)&_userlimit32 = 0xc0000000ul; 791 792 /*LINTED*/ 793 ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u); 794 opteron_erratum_95++; 795 #endif /* _LP64 */ 796 #else 797 workaround_warning(cpu, 95); 798 missing++; 799 #endif 800 } 801 802 if (cpuid_opteron_erratum(cpu, 100) > 0) { 803 /* 804 * Compatibility Mode Branches Transfer to Illegal Address 805 */ 806 #if defined(OPTERON_ERRATUM_100) 807 /* 808 * fix is in trap.c 809 */ 810 opteron_erratum_100++; 811 #else 812 workaround_warning(cpu, 100); 813 missing++; 814 #endif 815 } 816 817 /*LINTED*/ 818 if (cpuid_opteron_erratum(cpu, 108) > 0) { 819 /* 820 * CPUID Instruction May Return Incorrect Model Number In 821 * Some Processors 822 */ 823 #if defined(OPTERON_ERRATUM_108) 824 /* 825 * (Our cpuid-handling code corrects the model number on 826 * those processors) 827 */ 828 #else 829 workaround_warning(cpu, 108); 830 missing++; 831 #endif 832 } 833 834 /*LINTED*/ 835 if (cpuid_opteron_erratum(cpu, 109) > 0) do { 836 /* 837 * Certain Reverse REP MOVS May Produce Unpredictable Behaviour 838 */ 839 #if defined(OPTERON_ERRATUM_109) 840 /* 841 * The "workaround" is to print a warning to upgrade the BIOS 842 */ 843 uint64_t value; 844 const uint_t msr = MSR_AMD_PATCHLEVEL; 845 int err; 846 847 if ((err = checked_rdmsr(msr, &value)) != 0) { 848 msr_warning(cpu, "rd", msr, err); 849 workaround_warning(cpu, 109); 850 missing++; 851 } 852 if (value == 0) 853 opteron_erratum_109++; 854 #else 855 workaround_warning(cpu, 109); 856 missing++; 857 #endif 858 /*CONSTANTCONDITION*/ 859 } while (0); 860 861 /*LINTED*/ 862 if (cpuid_opteron_erratum(cpu, 121) > 0) { 863 /* 864 * Sequential Execution Across Non_Canonical Boundary Caused 865 * Processor Hang 866 */ 867 #if defined(OPTERON_ERRATUM_121) 868 #if defined(_LP64) 869 /* 870 * Erratum 121 is only present in long (64 bit) mode. 871 * Workaround is to include the page immediately before the 872 * va hole to eliminate the possibility of system hangs due to 873 * sequential execution across the va hole boundary. 874 */ 875 if (opteron_erratum_121) 876 opteron_erratum_121++; 877 else { 878 if (hole_start) { 879 hole_start -= PAGESIZE; 880 } else { 881 /* 882 * hole_start not yet initialized by 883 * mmu_init. Initialize hole_start 884 * with value to be subtracted. 885 */ 886 hole_start = PAGESIZE; 887 } 888 opteron_erratum_121++; 889 } 890 #endif /* _LP64 */ 891 #else 892 workaround_warning(cpu, 121); 893 missing++; 894 #endif 895 } 896 897 /*LINTED*/ 898 if (cpuid_opteron_erratum(cpu, 122) > 0) do { 899 /* 900 * TLB Flush Filter May Cause Coherency Problem in 901 * Multiprocessor Systems 902 */ 903 #if defined(OPTERON_ERRATUM_122) 904 uint64_t value; 905 const uint_t msr = MSR_AMD_HWCR; 906 int error; 907 908 /* 909 * Erratum 122 is only present in MP configurations (multi-core 910 * or multi-processor). 911 */ 912 #if defined(__xpv) 913 if (!DOMAIN_IS_INITDOMAIN(xen_info)) 914 break; 915 if (!opteron_erratum_122 && xen_get_nphyscpus() == 1) 916 break; 917 #else 918 if (!opteron_erratum_122 && opteron_get_nnodes() == 1 && 919 cpuid_get_ncpu_per_chip(cpu) == 1) 920 break; 921 #endif 922 /* disable TLB Flush Filter */ 923 924 if ((error = checked_rdmsr(msr, &value)) != 0) { 925 msr_warning(cpu, "rd", msr, error); 926 workaround_warning(cpu, 122); 927 missing++; 928 } else { 929 value |= (uint64_t)AMD_HWCR_FFDIS; 930 if ((error = checked_wrmsr(msr, value)) != 0) { 931 msr_warning(cpu, "wr", msr, error); 932 workaround_warning(cpu, 122); 933 missing++; 934 } 935 } 936 opteron_erratum_122++; 937 #else 938 workaround_warning(cpu, 122); 939 missing++; 940 #endif 941 /*CONSTANTCONDITION*/ 942 } while (0); 943 944 /*LINTED*/ 945 if (cpuid_opteron_erratum(cpu, 123) > 0) do { 946 /* 947 * Bypassed Reads May Cause Data Corruption of System Hang in 948 * Dual Core Processors 949 */ 950 #if defined(OPTERON_ERRATUM_123) 951 uint64_t value; 952 const uint_t msr = MSR_AMD_PATCHLEVEL; 953 int err; 954 955 /* 956 * Erratum 123 applies only to multi-core cpus. 957 */ 958 if (cpuid_get_ncpu_per_chip(cpu) < 2) 959 break; 960 #if defined(__xpv) 961 if (!DOMAIN_IS_INITDOMAIN(xen_info)) 962 break; 963 #endif 964 /* 965 * The "workaround" is to print a warning to upgrade the BIOS 966 */ 967 if ((err = checked_rdmsr(msr, &value)) != 0) { 968 msr_warning(cpu, "rd", msr, err); 969 workaround_warning(cpu, 123); 970 missing++; 971 } 972 if (value == 0) 973 opteron_erratum_123++; 974 #else 975 workaround_warning(cpu, 123); 976 missing++; 977 978 #endif 979 /*CONSTANTCONDITION*/ 980 } while (0); 981 982 /*LINTED*/ 983 if (cpuid_opteron_erratum(cpu, 131) > 0) do { 984 /* 985 * Multiprocessor Systems with Four or More Cores May Deadlock 986 * Waiting for a Probe Response 987 */ 988 #if defined(OPTERON_ERRATUM_131) 989 uint64_t nbcfg; 990 const uint_t msr = MSR_AMD_NB_CFG; 991 const uint64_t wabits = 992 AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR; 993 int error; 994 995 /* 996 * Erratum 131 applies to any system with four or more cores. 997 */ 998 if (opteron_erratum_131) 999 break; 1000 #if defined(__xpv) 1001 if (!DOMAIN_IS_INITDOMAIN(xen_info)) 1002 break; 1003 if (xen_get_nphyscpus() < 4) 1004 break; 1005 #else 1006 if (opteron_get_nnodes() * cpuid_get_ncpu_per_chip(cpu) < 4) 1007 break; 1008 #endif 1009 /* 1010 * Print a warning if neither of the workarounds for 1011 * erratum 131 is present. 1012 */ 1013 if ((error = checked_rdmsr(msr, &nbcfg)) != 0) { 1014 msr_warning(cpu, "rd", msr, error); 1015 workaround_warning(cpu, 131); 1016 missing++; 1017 } else if ((nbcfg & wabits) == 0) { 1018 opteron_erratum_131++; 1019 } else { 1020 /* cannot have both workarounds set */ 1021 ASSERT((nbcfg & wabits) != wabits); 1022 } 1023 #else 1024 workaround_warning(cpu, 131); 1025 missing++; 1026 #endif 1027 /*CONSTANTCONDITION*/ 1028 } while (0); 1029 1030 /* 1031 * This isn't really an erratum, but for convenience the 1032 * detection/workaround code lives here and in cpuid_opteron_erratum. 1033 */ 1034 if (cpuid_opteron_erratum(cpu, 6336786) > 0) { 1035 #if defined(OPTERON_WORKAROUND_6336786) 1036 /* 1037 * Disable C1-Clock ramping on multi-core/multi-processor 1038 * K8 platforms to guard against TSC drift. 1039 */ 1040 if (opteron_workaround_6336786) { 1041 opteron_workaround_6336786++; 1042 #if defined(__xpv) 1043 } else if ((DOMAIN_IS_INITDOMAIN(xen_info) && 1044 xen_get_nphyscpus() > 1) || 1045 opteron_workaround_6336786_UP) { 1046 /* 1047 * XXPV Hmm. We can't walk the Northbridges on 1048 * the hypervisor; so just complain and drive 1049 * on. This probably needs to be fixed in 1050 * the hypervisor itself. 1051 */ 1052 opteron_workaround_6336786++; 1053 workaround_warning(cpu, 6336786); 1054 #else /* __xpv */ 1055 } else if ((opteron_get_nnodes() * 1056 cpuid_get_ncpu_per_chip(cpu) > 1) || 1057 opteron_workaround_6336786_UP) { 1058 1059 uint_t node, nnodes; 1060 uint8_t data; 1061 1062 nnodes = opteron_get_nnodes(); 1063 for (node = 0; node < nnodes; node++) { 1064 /* 1065 * Clear PMM7[1:0] (function 3, offset 0x87) 1066 * Northbridge device is the node id + 24. 1067 */ 1068 data = pci_getb_func(0, node + 24, 3, 0x87); 1069 data &= 0xFC; 1070 pci_putb_func(0, node + 24, 3, 0x87, data); 1071 } 1072 opteron_workaround_6336786++; 1073 #endif /* __xpv */ 1074 } 1075 #else 1076 workaround_warning(cpu, 6336786); 1077 missing++; 1078 #endif 1079 } 1080 1081 /*LINTED*/ 1082 /* 1083 * Mutex primitives don't work as expected. 1084 */ 1085 if (cpuid_opteron_erratum(cpu, 6323525) > 0) { 1086 #if defined(OPTERON_WORKAROUND_6323525) 1087 /* 1088 * This problem only occurs with 2 or more cores. If bit in 1089 * MSR_AMD_BU_CFG set, then not applicable. The workaround 1090 * is to patch the semaphone routines with the lfence 1091 * instruction to provide necessary load memory barrier with 1092 * possible subsequent read-modify-write ops. 1093 * 1094 * It is too early in boot to call the patch routine so 1095 * set erratum variable to be done in startup_end(). 1096 */ 1097 if (opteron_workaround_6323525) { 1098 opteron_workaround_6323525++; 1099 #if defined(__xpv) 1100 } else if (x86_feature & X86_SSE2) { 1101 if (DOMAIN_IS_INITDOMAIN(xen_info)) { 1102 /* 1103 * XXPV Use dom0_msr here when extended 1104 * operations are supported? 1105 */ 1106 if (xen_get_nphyscpus() > 1) 1107 opteron_workaround_6323525++; 1108 } else { 1109 /* 1110 * We have no way to tell how many physical 1111 * cpus there are, or even if this processor 1112 * has the problem, so enable the workaround 1113 * unconditionally (at some performance cost). 1114 */ 1115 opteron_workaround_6323525++; 1116 } 1117 #else /* __xpv */ 1118 } else if ((x86_feature & X86_SSE2) && ((opteron_get_nnodes() * 1119 cpuid_get_ncpu_per_chip(cpu)) > 1)) { 1120 if ((xrdmsr(MSR_AMD_BU_CFG) & 0x02) == 0) 1121 opteron_workaround_6323525++; 1122 #endif /* __xpv */ 1123 } 1124 #else 1125 workaround_warning(cpu, 6323525); 1126 missing++; 1127 #endif 1128 } 1129 1130 missing += do_erratum_298(cpu); 1131 1132 #ifdef __xpv 1133 return (0); 1134 #else 1135 return (missing); 1136 #endif 1137 } 1138 1139 void 1140 workaround_errata_end() 1141 { 1142 #if defined(OPTERON_ERRATUM_88) 1143 if (opteron_erratum_88) 1144 workaround_applied(88); 1145 #endif 1146 #if defined(OPTERON_ERRATUM_91) 1147 if (opteron_erratum_91) 1148 workaround_applied(91); 1149 #endif 1150 #if defined(OPTERON_ERRATUM_93) 1151 if (opteron_erratum_93) 1152 workaround_applied(93); 1153 #endif 1154 #if defined(OPTERON_ERRATUM_95) 1155 if (opteron_erratum_95) 1156 workaround_applied(95); 1157 #endif 1158 #if defined(OPTERON_ERRATUM_100) 1159 if (opteron_erratum_100) 1160 workaround_applied(100); 1161 #endif 1162 #if defined(OPTERON_ERRATUM_108) 1163 if (opteron_erratum_108) 1164 workaround_applied(108); 1165 #endif 1166 #if defined(OPTERON_ERRATUM_109) 1167 if (opteron_erratum_109) { 1168 cmn_err(CE_WARN, 1169 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1170 " processor\nerratum 109 was not detected; updating your" 1171 " system's BIOS to a version\ncontaining this" 1172 " microcode patch is HIGHLY recommended or erroneous" 1173 " system\noperation may occur.\n"); 1174 } 1175 #endif 1176 #if defined(OPTERON_ERRATUM_121) 1177 if (opteron_erratum_121) 1178 workaround_applied(121); 1179 #endif 1180 #if defined(OPTERON_ERRATUM_122) 1181 if (opteron_erratum_122) 1182 workaround_applied(122); 1183 #endif 1184 #if defined(OPTERON_ERRATUM_123) 1185 if (opteron_erratum_123) { 1186 cmn_err(CE_WARN, 1187 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1188 " processor\nerratum 123 was not detected; updating your" 1189 " system's BIOS to a version\ncontaining this" 1190 " microcode patch is HIGHLY recommended or erroneous" 1191 " system\noperation may occur.\n"); 1192 } 1193 #endif 1194 #if defined(OPTERON_ERRATUM_131) 1195 if (opteron_erratum_131) { 1196 cmn_err(CE_WARN, 1197 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1198 " processor\nerratum 131 was not detected; updating your" 1199 " system's BIOS to a version\ncontaining this" 1200 " microcode patch is HIGHLY recommended or erroneous" 1201 " system\noperation may occur.\n"); 1202 } 1203 #endif 1204 #if defined(OPTERON_WORKAROUND_6336786) 1205 if (opteron_workaround_6336786) 1206 workaround_applied(6336786); 1207 #endif 1208 #if defined(OPTERON_WORKAROUND_6323525) 1209 if (opteron_workaround_6323525) 1210 workaround_applied(6323525); 1211 #endif 1212 #if defined(OPTERON_ERRATUM_298) 1213 if (opteron_erratum_298) { 1214 cmn_err(CE_WARN, 1215 "BIOS microcode patch for AMD 64/Opteron(tm)" 1216 " processor\nerratum 298 was not detected; updating your" 1217 " system's BIOS to a version\ncontaining this" 1218 " microcode patch is HIGHLY recommended or erroneous" 1219 " system\noperation may occur.\n"); 1220 } 1221 #endif 1222 } 1223 1224 static cpuset_t procset; 1225 1226 /* 1227 * Start a single cpu, assuming that the kernel context is available 1228 * to successfully start another cpu. 1229 * 1230 * (For example, real mode code is mapped into the right place 1231 * in memory and is ready to be run.) 1232 */ 1233 int 1234 start_cpu(processorid_t who) 1235 { 1236 void *ctx; 1237 cpu_t *cp; 1238 int delays; 1239 int error = 0; 1240 1241 ASSERT(who != 0); 1242 1243 /* 1244 * Check if there's at least a Mbyte of kmem available 1245 * before attempting to start the cpu. 1246 */ 1247 if (kmem_avail() < 1024 * 1024) { 1248 /* 1249 * Kick off a reap in case that helps us with 1250 * later attempts .. 1251 */ 1252 kmem_reap(); 1253 return (ENOMEM); 1254 } 1255 1256 cp = mp_startup_init(who); 1257 if ((ctx = mach_cpucontext_alloc(cp)) == NULL || 1258 (error = mach_cpu_start(cp, ctx)) != 0) { 1259 1260 /* 1261 * Something went wrong before we even started it 1262 */ 1263 if (ctx) 1264 cmn_err(CE_WARN, 1265 "cpu%d: failed to start error %d", 1266 cp->cpu_id, error); 1267 else 1268 cmn_err(CE_WARN, 1269 "cpu%d: failed to allocate context", cp->cpu_id); 1270 1271 if (ctx) 1272 mach_cpucontext_free(cp, ctx, error); 1273 else 1274 error = EAGAIN; /* hmm. */ 1275 mp_startup_fini(cp, error); 1276 return (error); 1277 } 1278 1279 for (delays = 0; !CPU_IN_SET(procset, who); delays++) { 1280 if (delays == 500) { 1281 /* 1282 * After five seconds, things are probably looking 1283 * a bit bleak - explain the hang. 1284 */ 1285 cmn_err(CE_NOTE, "cpu%d: started, " 1286 "but not running in the kernel yet", who); 1287 } else if (delays > 2000) { 1288 /* 1289 * We waited at least 20 seconds, bail .. 1290 */ 1291 error = ETIMEDOUT; 1292 cmn_err(CE_WARN, "cpu%d: timed out", who); 1293 mach_cpucontext_free(cp, ctx, error); 1294 mp_startup_fini(cp, error); 1295 return (error); 1296 } 1297 1298 /* 1299 * wait at least 10ms, then check again.. 1300 */ 1301 delay(USEC_TO_TICK_ROUNDUP(10000)); 1302 } 1303 1304 mach_cpucontext_free(cp, ctx, 0); 1305 1306 #ifndef __xpv 1307 if (tsc_gethrtime_enable) 1308 tsc_sync_master(who); 1309 #endif 1310 1311 if (dtrace_cpu_init != NULL) { 1312 /* 1313 * DTrace CPU initialization expects cpu_lock to be held. 1314 */ 1315 mutex_enter(&cpu_lock); 1316 (*dtrace_cpu_init)(who); 1317 mutex_exit(&cpu_lock); 1318 } 1319 1320 while (!CPU_IN_SET(cpu_ready_set, who)) 1321 delay(1); 1322 1323 return (0); 1324 } 1325 1326 1327 /*ARGSUSED*/ 1328 void 1329 start_other_cpus(int cprboot) 1330 { 1331 uint_t who; 1332 uint_t skipped = 0; 1333 uint_t bootcpuid = 0; 1334 1335 /* 1336 * Initialize our own cpu_info. 1337 */ 1338 init_cpu_info(CPU); 1339 1340 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_idstr); 1341 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_brandstr); 1342 1343 /* 1344 * Initialize our syscall handlers 1345 */ 1346 init_cpu_syscall(CPU); 1347 1348 /* 1349 * Take the boot cpu out of the mp_cpus set because we know 1350 * it's already running. Add it to the cpu_ready_set for 1351 * precisely the same reason. 1352 */ 1353 CPUSET_DEL(mp_cpus, bootcpuid); 1354 CPUSET_ADD(cpu_ready_set, bootcpuid); 1355 1356 /* 1357 * if only 1 cpu or not using MP, skip the rest of this 1358 */ 1359 if (CPUSET_ISNULL(mp_cpus) || use_mp == 0) { 1360 if (use_mp == 0) 1361 cmn_err(CE_CONT, "?***** Not in MP mode\n"); 1362 goto done; 1363 } 1364 1365 /* 1366 * perform such initialization as is needed 1367 * to be able to take CPUs on- and off-line. 1368 */ 1369 cpu_pause_init(); 1370 1371 xc_init(); /* initialize processor crosscalls */ 1372 1373 if (mach_cpucontext_init() != 0) 1374 goto done; 1375 1376 flushes_require_xcalls = 1; 1377 1378 /* 1379 * We lock our affinity to the master CPU to ensure that all slave CPUs 1380 * do their TSC syncs with the same CPU. 1381 */ 1382 affinity_set(CPU_CURRENT); 1383 1384 for (who = 0; who < NCPU; who++) { 1385 1386 if (!CPU_IN_SET(mp_cpus, who)) 1387 continue; 1388 ASSERT(who != bootcpuid); 1389 if (ncpus >= max_ncpus) { 1390 skipped = who; 1391 continue; 1392 } 1393 if (start_cpu(who) != 0) 1394 CPUSET_DEL(mp_cpus, who); 1395 } 1396 1397 /* Free the space allocated to hold the microcode file */ 1398 ucode_cleanup(); 1399 1400 affinity_clear(); 1401 1402 if (skipped) { 1403 cmn_err(CE_NOTE, 1404 "System detected %d cpus, but " 1405 "only %d cpu(s) were enabled during boot.", 1406 skipped + 1, ncpus); 1407 cmn_err(CE_NOTE, 1408 "Use \"boot-ncpus\" parameter to enable more CPU(s). " 1409 "See eeprom(1M)."); 1410 } 1411 1412 done: 1413 workaround_errata_end(); 1414 mach_cpucontext_fini(); 1415 1416 cmi_post_mpstartup(); 1417 } 1418 1419 /* 1420 * Dummy functions - no i86pc platforms support dynamic cpu allocation. 1421 */ 1422 /*ARGSUSED*/ 1423 int 1424 mp_cpu_configure(int cpuid) 1425 { 1426 return (ENOTSUP); /* not supported */ 1427 } 1428 1429 /*ARGSUSED*/ 1430 int 1431 mp_cpu_unconfigure(int cpuid) 1432 { 1433 return (ENOTSUP); /* not supported */ 1434 } 1435 1436 /* 1437 * Startup function for 'other' CPUs (besides boot cpu). 1438 * Called from real_mode_start. 1439 * 1440 * WARNING: until CPU_READY is set, mp_startup and routines called by 1441 * mp_startup should not call routines (e.g. kmem_free) that could call 1442 * hat_unload which requires CPU_READY to be set. 1443 */ 1444 void 1445 mp_startup(void) 1446 { 1447 struct cpu *cp = CPU; 1448 uint_t new_x86_feature; 1449 1450 /* 1451 * We need to get TSC on this proc synced (i.e., any delta 1452 * from cpu0 accounted for) as soon as we can, because many 1453 * many things use gethrtime/pc_gethrestime, including 1454 * interrupts, cmn_err, etc. 1455 */ 1456 1457 /* Let cpu0 continue into tsc_sync_master() */ 1458 CPUSET_ATOMIC_ADD(procset, cp->cpu_id); 1459 1460 #ifndef __xpv 1461 if (tsc_gethrtime_enable) 1462 tsc_sync_slave(); 1463 #endif 1464 1465 /* 1466 * Once this was done from assembly, but it's safer here; if 1467 * it blocks, we need to be able to swtch() to and from, and 1468 * since we get here by calling t_pc, we need to do that call 1469 * before swtch() overwrites it. 1470 */ 1471 (void) (*ap_mlsetup)(); 1472 1473 new_x86_feature = cpuid_pass1(cp); 1474 1475 #ifndef __xpv 1476 /* 1477 * Program this cpu's PAT 1478 */ 1479 if (x86_feature & X86_PAT) 1480 pat_sync(); 1481 #endif 1482 1483 /* 1484 * Set up TSC_AUX to contain the cpuid for this processor 1485 * for the rdtscp instruction. 1486 */ 1487 if (x86_feature & X86_TSCP) 1488 (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id); 1489 1490 /* 1491 * Initialize this CPU's syscall handlers 1492 */ 1493 init_cpu_syscall(cp); 1494 1495 /* 1496 * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the 1497 * highest level at which a routine is permitted to block on 1498 * an adaptive mutex (allows for cpu poke interrupt in case 1499 * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks 1500 * device interrupts that may end up in the hat layer issuing cross 1501 * calls before CPU_READY is set. 1502 */ 1503 splx(ipltospl(LOCK_LEVEL)); 1504 sti(); 1505 1506 /* 1507 * Do a sanity check to make sure this new CPU is a sane thing 1508 * to add to the collection of processors running this system. 1509 * 1510 * XXX Clearly this needs to get more sophisticated, if x86 1511 * systems start to get built out of heterogenous CPUs; as is 1512 * likely to happen once the number of processors in a configuration 1513 * gets large enough. 1514 */ 1515 if ((x86_feature & new_x86_feature) != x86_feature) { 1516 cmn_err(CE_CONT, "?cpu%d: %b\n", 1517 cp->cpu_id, new_x86_feature, FMT_X86_FEATURE); 1518 cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id); 1519 } 1520 1521 /* 1522 * We do not support cpus with mixed monitor/mwait support if the 1523 * boot cpu supports monitor/mwait. 1524 */ 1525 if ((x86_feature & ~new_x86_feature) & X86_MWAIT) 1526 panic("unsupported mixed cpu monitor/mwait support detected"); 1527 1528 /* 1529 * We could be more sophisticated here, and just mark the CPU 1530 * as "faulted" but at this point we'll opt for the easier 1531 * answer of dieing horribly. Provided the boot cpu is ok, 1532 * the system can be recovered by booting with use_mp set to zero. 1533 */ 1534 if (workaround_errata(cp) != 0) 1535 panic("critical workaround(s) missing for cpu%d", cp->cpu_id); 1536 1537 cpuid_pass2(cp); 1538 cpuid_pass3(cp); 1539 (void) cpuid_pass4(cp); 1540 1541 init_cpu_info(cp); 1542 1543 mutex_enter(&cpu_lock); 1544 /* 1545 * Processor group initialization for this CPU is dependent on the 1546 * cpuid probing, which must be done in the context of the current 1547 * CPU. 1548 */ 1549 pghw_physid_create(cp); 1550 pg_cpu_init(cp); 1551 pg_cmt_cpu_startup(cp); 1552 1553 cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_EXISTS; 1554 1555 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr); 1556 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr); 1557 1558 if (dtrace_cpu_init != NULL) { 1559 (*dtrace_cpu_init)(cp->cpu_id); 1560 } 1561 1562 /* 1563 * Fill out cpu_ucode_info. Update microcode if necessary. 1564 */ 1565 ucode_check(cp); 1566 1567 mutex_exit(&cpu_lock); 1568 1569 /* 1570 * Enable preemption here so that contention for any locks acquired 1571 * later in mp_startup may be preempted if the thread owning those 1572 * locks is continously executing on other CPUs (for example, this 1573 * CPU must be preemptible to allow other CPUs to pause it during their 1574 * startup phases). It's safe to enable preemption here because the 1575 * CPU state is pretty-much fully constructed. 1576 */ 1577 curthread->t_preempt = 0; 1578 1579 /* The base spl should still be at LOCK LEVEL here */ 1580 ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL)); 1581 set_base_spl(); /* Restore the spl to its proper value */ 1582 1583 /* Enable interrupts */ 1584 (void) spl0(); 1585 mutex_enter(&cpu_lock); 1586 cpu_enable_intr(cp); 1587 cpu_add_active(cp); 1588 mutex_exit(&cpu_lock); 1589 1590 add_cpunode2devtree(cp->cpu_id, cp->cpu_m.mcpu_cpi); 1591 1592 #ifndef __xpv 1593 { 1594 /* 1595 * Set up the CPU module for this CPU. This can't be done 1596 * before this CPU is made CPU_READY, because we may (in 1597 * heterogeneous systems) need to go load another CPU module. 1598 * The act of attempting to load a module may trigger a 1599 * cross-call, which will ASSERT unless this cpu is CPU_READY. 1600 */ 1601 cmi_hdl_t hdl; 1602 1603 if ((hdl = cmi_init(CMI_HDL_NATIVE, cmi_ntv_hwchipid(CPU), 1604 cmi_ntv_hwcoreid(CPU), cmi_ntv_hwstrandid(CPU))) != NULL) { 1605 if (x86_feature & X86_MCA) 1606 cmi_mca_init(hdl); 1607 } 1608 } 1609 #endif /* __xpv */ 1610 1611 if (boothowto & RB_DEBUG) 1612 kdi_cpu_init(); 1613 1614 /* 1615 * Setting the bit in cpu_ready_set must be the last operation in 1616 * processor initialization; the boot CPU will continue to boot once 1617 * it sees this bit set for all active CPUs. 1618 */ 1619 CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id); 1620 1621 /* 1622 * Because mp_startup() gets fired off after init() starts, we 1623 * can't use the '?' trick to do 'boot -v' printing - so we 1624 * always direct the 'cpu .. online' messages to the log. 1625 */ 1626 cmn_err(CE_CONT, "!cpu%d initialization complete - online\n", 1627 cp->cpu_id); 1628 1629 /* 1630 * Now we are done with the startup thread, so free it up. 1631 */ 1632 thread_exit(); 1633 panic("mp_startup: cannot return"); 1634 /*NOTREACHED*/ 1635 } 1636 1637 1638 /* 1639 * Start CPU on user request. 1640 */ 1641 /* ARGSUSED */ 1642 int 1643 mp_cpu_start(struct cpu *cp) 1644 { 1645 ASSERT(MUTEX_HELD(&cpu_lock)); 1646 return (0); 1647 } 1648 1649 /* 1650 * Stop CPU on user request. 1651 */ 1652 /* ARGSUSED */ 1653 int 1654 mp_cpu_stop(struct cpu *cp) 1655 { 1656 extern int cbe_psm_timer_mode; 1657 ASSERT(MUTEX_HELD(&cpu_lock)); 1658 1659 #ifdef __xpv 1660 /* 1661 * We can't offline vcpu0. 1662 */ 1663 if (cp->cpu_id == 0) 1664 return (EBUSY); 1665 #endif 1666 1667 /* 1668 * If TIMER_PERIODIC mode is used, CPU0 is the one running it; 1669 * can't stop it. (This is true only for machines with no TSC.) 1670 */ 1671 1672 if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0)) 1673 return (EBUSY); 1674 1675 return (0); 1676 } 1677 1678 /* 1679 * Take the specified CPU out of participation in interrupts. 1680 */ 1681 int 1682 cpu_disable_intr(struct cpu *cp) 1683 { 1684 if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS) 1685 return (EBUSY); 1686 1687 cp->cpu_flags &= ~CPU_ENABLE; 1688 return (0); 1689 } 1690 1691 /* 1692 * Allow the specified CPU to participate in interrupts. 1693 */ 1694 void 1695 cpu_enable_intr(struct cpu *cp) 1696 { 1697 ASSERT(MUTEX_HELD(&cpu_lock)); 1698 cp->cpu_flags |= CPU_ENABLE; 1699 psm_enable_intr(cp->cpu_id); 1700 } 1701 1702 1703 /*ARGSUSED*/ 1704 void 1705 mp_cpu_faulted_enter(struct cpu *cp) 1706 { 1707 #ifndef __xpv 1708 cmi_hdl_t hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), 1709 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); 1710 1711 if (hdl != NULL) { 1712 cmi_faulted_enter(hdl); 1713 cmi_hdl_rele(hdl); 1714 } 1715 #endif 1716 } 1717 1718 /*ARGSUSED*/ 1719 void 1720 mp_cpu_faulted_exit(struct cpu *cp) 1721 { 1722 #ifndef __xpv 1723 cmi_hdl_t hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), 1724 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); 1725 1726 if (hdl != NULL) { 1727 cmi_faulted_exit(hdl); 1728 cmi_hdl_rele(hdl); 1729 } 1730 #endif 1731 } 1732 1733 /* 1734 * The following two routines are used as context operators on threads belonging 1735 * to processes with a private LDT (see sysi86). Due to the rarity of such 1736 * processes, these routines are currently written for best code readability and 1737 * organization rather than speed. We could avoid checking x86_feature at every 1738 * context switch by installing different context ops, depending on the 1739 * x86_feature flags, at LDT creation time -- one for each combination of fast 1740 * syscall feature flags. 1741 */ 1742 1743 /*ARGSUSED*/ 1744 void 1745 cpu_fast_syscall_disable(void *arg) 1746 { 1747 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) 1748 cpu_sep_disable(); 1749 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) 1750 cpu_asysc_disable(); 1751 } 1752 1753 /*ARGSUSED*/ 1754 void 1755 cpu_fast_syscall_enable(void *arg) 1756 { 1757 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) 1758 cpu_sep_enable(); 1759 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) 1760 cpu_asysc_enable(); 1761 } 1762 1763 static void 1764 cpu_sep_enable(void) 1765 { 1766 ASSERT(x86_feature & X86_SEP); 1767 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1768 1769 wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL); 1770 } 1771 1772 static void 1773 cpu_sep_disable(void) 1774 { 1775 ASSERT(x86_feature & X86_SEP); 1776 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1777 1778 /* 1779 * Setting the SYSENTER_CS_MSR register to 0 causes software executing 1780 * the sysenter or sysexit instruction to trigger a #gp fault. 1781 */ 1782 wrmsr(MSR_INTC_SEP_CS, 0); 1783 } 1784 1785 static void 1786 cpu_asysc_enable(void) 1787 { 1788 ASSERT(x86_feature & X86_ASYSC); 1789 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1790 1791 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) | 1792 (uint64_t)(uintptr_t)AMD_EFER_SCE); 1793 } 1794 1795 static void 1796 cpu_asysc_disable(void) 1797 { 1798 ASSERT(x86_feature & X86_ASYSC); 1799 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1800 1801 /* 1802 * Turn off the SCE (syscall enable) bit in the EFER register. Software 1803 * executing syscall or sysret with this bit off will incur a #ud trap. 1804 */ 1805 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) & 1806 ~((uint64_t)(uintptr_t)AMD_EFER_SCE)); 1807 } 1808