1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/thread.h> 31 #include <sys/cpuvar.h> 32 #include <sys/t_lock.h> 33 #include <sys/param.h> 34 #include <sys/proc.h> 35 #include <sys/disp.h> 36 #include <sys/class.h> 37 #include <sys/cmn_err.h> 38 #include <sys/debug.h> 39 #include <sys/asm_linkage.h> 40 #include <sys/x_call.h> 41 #include <sys/systm.h> 42 #include <sys/var.h> 43 #include <sys/vtrace.h> 44 #include <vm/hat.h> 45 #include <vm/as.h> 46 #include <vm/seg_kmem.h> 47 #include <vm/seg_kp.h> 48 #include <sys/segments.h> 49 #include <sys/kmem.h> 50 #include <sys/stack.h> 51 #include <sys/smp_impldefs.h> 52 #include <sys/x86_archext.h> 53 #include <sys/machsystm.h> 54 #include <sys/traptrace.h> 55 #include <sys/clock.h> 56 #include <sys/cpc_impl.h> 57 #include <sys/pg.h> 58 #include <sys/cmt.h> 59 #include <sys/dtrace.h> 60 #include <sys/archsystm.h> 61 #include <sys/fp.h> 62 #include <sys/reboot.h> 63 #include <sys/kdi_machimpl.h> 64 #include <vm/hat_i86.h> 65 #include <sys/memnode.h> 66 #include <sys/pci_cfgspace.h> 67 #include <sys/mach_mmu.h> 68 #include <sys/sysmacros.h> 69 #include <sys/cpu_module.h> 70 71 struct cpu cpus[1]; /* CPU data */ 72 struct cpu *cpu[NCPU] = {&cpus[0]}; /* pointers to all CPUs */ 73 cpu_core_t cpu_core[NCPU]; /* cpu_core structures */ 74 75 /* 76 * Useful for disabling MP bring-up on a MP capable system. 77 */ 78 int use_mp = 1; 79 80 /* 81 * to be set by a PSM to indicate what cpus 82 * are sitting around on the system. 83 */ 84 cpuset_t mp_cpus; 85 86 /* 87 * This variable is used by the hat layer to decide whether or not 88 * critical sections are needed to prevent race conditions. For sun4m, 89 * this variable is set once enough MP initialization has been done in 90 * order to allow cross calls. 91 */ 92 int flushes_require_xcalls; 93 cpuset_t cpu_ready_set = 1; 94 95 static void mp_startup(void); 96 97 static void cpu_sep_enable(void); 98 static void cpu_sep_disable(void); 99 static void cpu_asysc_enable(void); 100 static void cpu_asysc_disable(void); 101 102 extern int tsc_gethrtime_enable; 103 104 /* 105 * Init CPU info - get CPU type info for processor_info system call. 106 */ 107 void 108 init_cpu_info(struct cpu *cp) 109 { 110 processor_info_t *pi = &cp->cpu_type_info; 111 char buf[CPU_IDSTRLEN]; 112 113 /* 114 * Get clock-frequency property for the CPU. 115 */ 116 pi->pi_clock = cpu_freq; 117 118 /* 119 * Current frequency in Hz. 120 */ 121 cp->cpu_curr_clock = cpu_freq_hz; 122 123 /* 124 * Supported frequencies. 125 */ 126 cpu_set_supp_freqs(cp, NULL); 127 128 (void) strcpy(pi->pi_processor_type, "i386"); 129 if (fpu_exists) 130 (void) strcpy(pi->pi_fputypes, "i387 compatible"); 131 132 (void) cpuid_getidstr(cp, buf, sizeof (buf)); 133 134 cp->cpu_idstr = kmem_alloc(strlen(buf) + 1, KM_SLEEP); 135 (void) strcpy(cp->cpu_idstr, buf); 136 137 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr); 138 139 (void) cpuid_getbrandstr(cp, buf, sizeof (buf)); 140 cp->cpu_brandstr = kmem_alloc(strlen(buf) + 1, KM_SLEEP); 141 (void) strcpy(cp->cpu_brandstr, buf); 142 143 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr); 144 } 145 146 /* 147 * Configure syscall support on this CPU. 148 */ 149 /*ARGSUSED*/ 150 static void 151 init_cpu_syscall(struct cpu *cp) 152 { 153 kpreempt_disable(); 154 155 #if defined(__amd64) 156 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) { 157 158 #if !defined(__lint) 159 /* 160 * The syscall instruction imposes a certain ordering on 161 * segment selectors, so we double-check that ordering 162 * here. 163 */ 164 ASSERT(KDS_SEL == KCS_SEL + 8); 165 ASSERT(UDS_SEL == U32CS_SEL + 8); 166 ASSERT(UCS_SEL == U32CS_SEL + 16); 167 #endif 168 /* 169 * Turn syscall/sysret extensions on. 170 */ 171 cpu_asysc_enable(); 172 173 /* 174 * Program the magic registers .. 175 */ 176 wrmsr(MSR_AMD_STAR, 177 ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32); 178 wrmsr(MSR_AMD_LSTAR, (uint64_t)(uintptr_t)sys_syscall); 179 wrmsr(MSR_AMD_CSTAR, (uint64_t)(uintptr_t)sys_syscall32); 180 181 /* 182 * This list of flags is masked off the incoming 183 * %rfl when we enter the kernel. 184 */ 185 wrmsr(MSR_AMD_SFMASK, (uint64_t)(uintptr_t)(PS_IE | PS_T)); 186 } 187 #endif 188 189 /* 190 * On 32-bit kernels, we use sysenter/sysexit because it's too 191 * hard to use syscall/sysret, and it is more portable anyway. 192 * 193 * On 64-bit kernels on Nocona machines, the 32-bit syscall 194 * variant isn't available to 32-bit applications, but sysenter is. 195 */ 196 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) { 197 198 #if !defined(__lint) 199 /* 200 * The sysenter instruction imposes a certain ordering on 201 * segment selectors, so we double-check that ordering 202 * here. See "sysenter" in Intel document 245471-012, "IA-32 203 * Intel Architecture Software Developer's Manual Volume 2: 204 * Instruction Set Reference" 205 */ 206 ASSERT(KDS_SEL == KCS_SEL + 8); 207 208 ASSERT32(UCS_SEL == ((KCS_SEL + 16) | 3)); 209 ASSERT32(UDS_SEL == UCS_SEL + 8); 210 211 ASSERT64(U32CS_SEL == ((KCS_SEL + 16) | 3)); 212 ASSERT64(UDS_SEL == U32CS_SEL + 8); 213 #endif 214 215 cpu_sep_enable(); 216 217 /* 218 * resume() sets this value to the base of the threads stack 219 * via a context handler. 220 */ 221 wrmsr(MSR_INTC_SEP_ESP, 0); 222 wrmsr(MSR_INTC_SEP_EIP, (uint64_t)(uintptr_t)sys_sysenter); 223 } 224 225 kpreempt_enable(); 226 } 227 228 /* 229 * Multiprocessor initialization. 230 * 231 * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the 232 * startup and idle threads for the specified CPU. 233 */ 234 struct cpu * 235 mp_startup_init(int cpun) 236 { 237 struct cpu *cp; 238 kthread_id_t tp; 239 caddr_t sp; 240 proc_t *procp; 241 extern void idle(); 242 243 #ifdef TRAPTRACE 244 trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun]; 245 #endif 246 247 ASSERT(cpun < NCPU && cpu[cpun] == NULL); 248 249 cp = kmem_zalloc(sizeof (*cp), KM_SLEEP); 250 if (x86_feature & X86_MWAIT) 251 cp->cpu_m.mcpu_mwait = mach_alloc_mwait(CPU); 252 253 procp = curthread->t_procp; 254 255 mutex_enter(&cpu_lock); 256 /* 257 * Initialize the dispatcher first. 258 */ 259 disp_cpu_init(cp); 260 mutex_exit(&cpu_lock); 261 262 cpu_vm_data_init(cp); 263 264 /* 265 * Allocate and initialize the startup thread for this CPU. 266 * Interrupt and process switch stacks get allocated later 267 * when the CPU starts running. 268 */ 269 tp = thread_create(NULL, 0, NULL, NULL, 0, procp, 270 TS_STOPPED, maxclsyspri); 271 272 /* 273 * Set state to TS_ONPROC since this thread will start running 274 * as soon as the CPU comes online. 275 * 276 * All the other fields of the thread structure are setup by 277 * thread_create(). 278 */ 279 THREAD_ONPROC(tp, cp); 280 tp->t_preempt = 1; 281 tp->t_bound_cpu = cp; 282 tp->t_affinitycnt = 1; 283 tp->t_cpu = cp; 284 tp->t_disp_queue = cp->cpu_disp; 285 286 /* 287 * Setup thread to start in mp_startup. 288 */ 289 sp = tp->t_stk; 290 tp->t_pc = (uintptr_t)mp_startup; 291 tp->t_sp = (uintptr_t)(sp - MINFRAME); 292 #if defined(__amd64) 293 tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */ 294 #endif 295 296 cp->cpu_id = cpun; 297 cp->cpu_self = cp; 298 cp->cpu_thread = tp; 299 cp->cpu_lwp = NULL; 300 cp->cpu_dispthread = tp; 301 cp->cpu_dispatch_pri = DISP_PRIO(tp); 302 303 /* 304 * cpu_base_spl must be set explicitly here to prevent any blocking 305 * operations in mp_startup from causing the spl of the cpu to drop 306 * to 0 (allowing device interrupts before we're ready) in resume(). 307 * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY. 308 * As an extra bit of security on DEBUG kernels, this is enforced with 309 * an assertion in mp_startup() -- before cpu_base_spl is set to its 310 * proper value. 311 */ 312 cp->cpu_base_spl = ipltospl(LOCK_LEVEL); 313 314 /* 315 * Now, initialize per-CPU idle thread for this CPU. 316 */ 317 tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1); 318 319 cp->cpu_idle_thread = tp; 320 321 tp->t_preempt = 1; 322 tp->t_bound_cpu = cp; 323 tp->t_affinitycnt = 1; 324 tp->t_cpu = cp; 325 tp->t_disp_queue = cp->cpu_disp; 326 327 /* 328 * Bootstrap the CPU's PG data 329 */ 330 pg_cpu_bootstrap(cp); 331 332 /* 333 * Perform CPC initialization on the new CPU. 334 */ 335 kcpc_hw_init(cp); 336 337 /* 338 * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2 339 * for each CPU. 340 */ 341 setup_vaddr_for_ppcopy(cp); 342 343 /* 344 * Allocate page for new GDT and initialize from current GDT. 345 */ 346 #if !defined(__lint) 347 ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE); 348 #endif 349 cp->cpu_m.mcpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP); 350 bcopy(CPU->cpu_m.mcpu_gdt, cp->cpu_m.mcpu_gdt, 351 (sizeof (*cp->cpu_m.mcpu_gdt) * NGDT)); 352 353 #if defined(__i386) 354 /* 355 * setup kernel %gs. 356 */ 357 set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA, 358 SEL_KPL, 0, 1); 359 #endif 360 361 /* 362 * If we have more than one node, each cpu gets a copy of IDT 363 * local to its node. If this is a Pentium box, we use cpu 0's 364 * IDT. cpu 0's IDT has been made read-only to workaround the 365 * cmpxchgl register bug 366 */ 367 if (system_hardware.hd_nodes && x86_type != X86_TYPE_P5) { 368 struct machcpu *mcpu = &cp->cpu_m; 369 370 mcpu->mcpu_idt = kmem_alloc(sizeof (idt0), KM_SLEEP); 371 bcopy(idt0, mcpu->mcpu_idt, sizeof (idt0)); 372 } else { 373 cp->cpu_m.mcpu_idt = CPU->cpu_m.mcpu_idt; 374 } 375 376 /* 377 * Get interrupt priority data from cpu 0. 378 */ 379 cp->cpu_pri_data = CPU->cpu_pri_data; 380 381 /* 382 * alloc space for cpuid info 383 */ 384 cpuid_alloc_space(cp); 385 386 /* 387 * alloc space for ucode_info 388 */ 389 ucode_alloc_space(cp); 390 391 hat_cpu_online(cp); 392 393 #ifdef TRAPTRACE 394 /* 395 * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers 396 */ 397 ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP); 398 ttc->ttc_next = ttc->ttc_first; 399 ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize; 400 #endif 401 /* 402 * Record that we have another CPU. 403 */ 404 mutex_enter(&cpu_lock); 405 /* 406 * Initialize the interrupt threads for this CPU 407 */ 408 cpu_intr_alloc(cp, NINTR_THREADS); 409 /* 410 * Add CPU to list of available CPUs. It'll be on the active list 411 * after mp_startup(). 412 */ 413 cpu_add_unit(cp); 414 mutex_exit(&cpu_lock); 415 416 return (cp); 417 } 418 419 /* 420 * Undo what was done in mp_startup_init 421 */ 422 static void 423 mp_startup_fini(struct cpu *cp, int error) 424 { 425 mutex_enter(&cpu_lock); 426 427 /* 428 * Remove the CPU from the list of available CPUs. 429 */ 430 cpu_del_unit(cp->cpu_id); 431 432 if (error == ETIMEDOUT) { 433 /* 434 * The cpu was started, but never *seemed* to run any 435 * code in the kernel; it's probably off spinning in its 436 * own private world, though with potential references to 437 * our kmem-allocated IDTs and GDTs (for example). 438 * 439 * Worse still, it may actually wake up some time later, 440 * so rather than guess what it might or might not do, we 441 * leave the fundamental data structures intact. 442 */ 443 cp->cpu_flags = 0; 444 mutex_exit(&cpu_lock); 445 return; 446 } 447 448 /* 449 * At this point, the only threads bound to this CPU should 450 * special per-cpu threads: it's idle thread, it's pause threads, 451 * and it's interrupt threads. Clean these up. 452 */ 453 cpu_destroy_bound_threads(cp); 454 cp->cpu_idle_thread = NULL; 455 456 /* 457 * Free the interrupt stack. 458 */ 459 segkp_release(segkp, 460 cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME))); 461 462 mutex_exit(&cpu_lock); 463 464 #ifdef TRAPTRACE 465 /* 466 * Discard the trap trace buffer 467 */ 468 { 469 trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id]; 470 471 kmem_free((void *)ttc->ttc_first, trap_trace_bufsize); 472 ttc->ttc_first = NULL; 473 } 474 #endif 475 476 hat_cpu_offline(cp); 477 478 cpuid_free_space(cp); 479 480 ucode_free_space(cp); 481 482 if (cp->cpu_m.mcpu_idt != CPU->cpu_m.mcpu_idt) 483 kmem_free(cp->cpu_m.mcpu_idt, sizeof (idt0)); 484 cp->cpu_m.mcpu_idt = NULL; 485 486 kmem_free(cp->cpu_m.mcpu_gdt, PAGESIZE); 487 cp->cpu_m.mcpu_gdt = NULL; 488 489 teardown_vaddr_for_ppcopy(cp); 490 491 kcpc_hw_fini(cp); 492 493 cp->cpu_dispthread = NULL; 494 cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */ 495 496 cpu_vm_data_destroy(cp); 497 498 mutex_enter(&cpu_lock); 499 disp_cpu_fini(cp); 500 mutex_exit(&cpu_lock); 501 502 kmem_free(cp, sizeof (*cp)); 503 } 504 505 /* 506 * Apply workarounds for known errata, and warn about those that are absent. 507 * 508 * System vendors occasionally create configurations which contain different 509 * revisions of the CPUs that are almost but not exactly the same. At the 510 * time of writing, this meant that their clock rates were the same, their 511 * feature sets were the same, but the required workaround were -not- 512 * necessarily the same. So, this routine is invoked on -every- CPU soon 513 * after starting to make sure that the resulting system contains the most 514 * pessimal set of workarounds needed to cope with *any* of the CPUs in the 515 * system. 516 * 517 * workaround_errata is invoked early in mlsetup() for CPU 0, and in 518 * mp_startup() for all slave CPUs. Slaves process workaround_errata prior 519 * to acknowledging their readiness to the master, so this routine will 520 * never be executed by multiple CPUs in parallel, thus making updates to 521 * global data safe. 522 * 523 * These workarounds are based on Rev 3.57 of the Revision Guide for 524 * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005. 525 */ 526 527 #if defined(OPTERON_ERRATUM_88) 528 int opteron_erratum_88; /* if non-zero -> at least one cpu has it */ 529 #endif 530 531 #if defined(OPTERON_ERRATUM_91) 532 int opteron_erratum_91; /* if non-zero -> at least one cpu has it */ 533 #endif 534 535 #if defined(OPTERON_ERRATUM_93) 536 int opteron_erratum_93; /* if non-zero -> at least one cpu has it */ 537 #endif 538 539 #if defined(OPTERON_ERRATUM_95) 540 int opteron_erratum_95; /* if non-zero -> at least one cpu has it */ 541 #endif 542 543 #if defined(OPTERON_ERRATUM_100) 544 int opteron_erratum_100; /* if non-zero -> at least one cpu has it */ 545 #endif 546 547 #if defined(OPTERON_ERRATUM_108) 548 int opteron_erratum_108; /* if non-zero -> at least one cpu has it */ 549 #endif 550 551 #if defined(OPTERON_ERRATUM_109) 552 int opteron_erratum_109; /* if non-zero -> at least one cpu has it */ 553 #endif 554 555 #if defined(OPTERON_ERRATUM_121) 556 int opteron_erratum_121; /* if non-zero -> at least one cpu has it */ 557 #endif 558 559 #if defined(OPTERON_ERRATUM_122) 560 int opteron_erratum_122; /* if non-zero -> at least one cpu has it */ 561 #endif 562 563 #if defined(OPTERON_ERRATUM_123) 564 int opteron_erratum_123; /* if non-zero -> at least one cpu has it */ 565 #endif 566 567 #if defined(OPTERON_ERRATUM_131) 568 int opteron_erratum_131; /* if non-zero -> at least one cpu has it */ 569 #endif 570 571 #if defined(OPTERON_WORKAROUND_6336786) 572 int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */ 573 int opteron_workaround_6336786_UP = 0; /* Not needed for UP */ 574 #endif 575 576 #if defined(OPTERON_WORKAROUND_6323525) 577 int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */ 578 #endif 579 580 static void 581 workaround_warning(cpu_t *cp, uint_t erratum) 582 { 583 cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u", 584 cp->cpu_id, erratum); 585 } 586 587 static void 588 workaround_applied(uint_t erratum) 589 { 590 if (erratum > 1000000) 591 cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n", 592 erratum); 593 else 594 cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n", 595 erratum); 596 } 597 598 static void 599 msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error) 600 { 601 cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d", 602 cp->cpu_id, rw, msr, error); 603 } 604 605 uint_t 606 workaround_errata(struct cpu *cpu) 607 { 608 uint_t missing = 0; 609 610 ASSERT(cpu == CPU); 611 612 /*LINTED*/ 613 if (cpuid_opteron_erratum(cpu, 88) > 0) { 614 /* 615 * SWAPGS May Fail To Read Correct GS Base 616 */ 617 #if defined(OPTERON_ERRATUM_88) 618 /* 619 * The workaround is an mfence in the relevant assembler code 620 */ 621 opteron_erratum_88++; 622 #else 623 workaround_warning(cpu, 88); 624 missing++; 625 #endif 626 } 627 628 if (cpuid_opteron_erratum(cpu, 91) > 0) { 629 /* 630 * Software Prefetches May Report A Page Fault 631 */ 632 #if defined(OPTERON_ERRATUM_91) 633 /* 634 * fix is in trap.c 635 */ 636 opteron_erratum_91++; 637 #else 638 workaround_warning(cpu, 91); 639 missing++; 640 #endif 641 } 642 643 if (cpuid_opteron_erratum(cpu, 93) > 0) { 644 /* 645 * RSM Auto-Halt Restart Returns to Incorrect RIP 646 */ 647 #if defined(OPTERON_ERRATUM_93) 648 /* 649 * fix is in trap.c 650 */ 651 opteron_erratum_93++; 652 #else 653 workaround_warning(cpu, 93); 654 missing++; 655 #endif 656 } 657 658 /*LINTED*/ 659 if (cpuid_opteron_erratum(cpu, 95) > 0) { 660 /* 661 * RET Instruction May Return to Incorrect EIP 662 */ 663 #if defined(OPTERON_ERRATUM_95) 664 #if defined(_LP64) 665 /* 666 * Workaround this by ensuring that 32-bit user code and 667 * 64-bit kernel code never occupy the same address 668 * range mod 4G. 669 */ 670 if (_userlimit32 > 0xc0000000ul) 671 *(uintptr_t *)&_userlimit32 = 0xc0000000ul; 672 673 /*LINTED*/ 674 ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u); 675 opteron_erratum_95++; 676 #endif /* _LP64 */ 677 #else 678 workaround_warning(cpu, 95); 679 missing++; 680 #endif 681 } 682 683 if (cpuid_opteron_erratum(cpu, 100) > 0) { 684 /* 685 * Compatibility Mode Branches Transfer to Illegal Address 686 */ 687 #if defined(OPTERON_ERRATUM_100) 688 /* 689 * fix is in trap.c 690 */ 691 opteron_erratum_100++; 692 #else 693 workaround_warning(cpu, 100); 694 missing++; 695 #endif 696 } 697 698 /*LINTED*/ 699 if (cpuid_opteron_erratum(cpu, 108) > 0) { 700 /* 701 * CPUID Instruction May Return Incorrect Model Number In 702 * Some Processors 703 */ 704 #if defined(OPTERON_ERRATUM_108) 705 /* 706 * (Our cpuid-handling code corrects the model number on 707 * those processors) 708 */ 709 #else 710 workaround_warning(cpu, 108); 711 missing++; 712 #endif 713 } 714 715 /*LINTED*/ 716 if (cpuid_opteron_erratum(cpu, 109) > 0) do { 717 /* 718 * Certain Reverse REP MOVS May Produce Unpredictable Behaviour 719 */ 720 #if defined(OPTERON_ERRATUM_109) 721 /* 722 * The "workaround" is to print a warning to upgrade the BIOS 723 */ 724 uint64_t value; 725 const uint_t msr = MSR_AMD_PATCHLEVEL; 726 int err; 727 728 if ((err = checked_rdmsr(msr, &value)) != 0) { 729 msr_warning(cpu, "rd", msr, err); 730 workaround_warning(cpu, 109); 731 missing++; 732 } 733 if (value == 0) 734 opteron_erratum_109++; 735 #else 736 workaround_warning(cpu, 109); 737 missing++; 738 #endif 739 /*CONSTANTCONDITION*/ 740 } while (0); 741 742 /*LINTED*/ 743 if (cpuid_opteron_erratum(cpu, 121) > 0) { 744 /* 745 * Sequential Execution Across Non_Canonical Boundary Caused 746 * Processor Hang 747 */ 748 #if defined(OPTERON_ERRATUM_121) 749 #if defined(_LP64) 750 /* 751 * Erratum 121 is only present in long (64 bit) mode. 752 * Workaround is to include the page immediately before the 753 * va hole to eliminate the possibility of system hangs due to 754 * sequential execution across the va hole boundary. 755 */ 756 if (opteron_erratum_121) 757 opteron_erratum_121++; 758 else { 759 if (hole_start) { 760 hole_start -= PAGESIZE; 761 } else { 762 /* 763 * hole_start not yet initialized by 764 * mmu_init. Initialize hole_start 765 * with value to be subtracted. 766 */ 767 hole_start = PAGESIZE; 768 } 769 opteron_erratum_121++; 770 } 771 #endif /* _LP64 */ 772 #else 773 workaround_warning(cpu, 121); 774 missing++; 775 #endif 776 } 777 778 /*LINTED*/ 779 if (cpuid_opteron_erratum(cpu, 122) > 0) do { 780 /* 781 * TLB Flush Filter May Cause Coherency Problem in 782 * Multiprocessor Systems 783 */ 784 #if defined(OPTERON_ERRATUM_122) 785 uint64_t value; 786 const uint_t msr = MSR_AMD_HWCR; 787 int error; 788 789 /* 790 * Erratum 122 is only present in MP configurations (multi-core 791 * or multi-processor). 792 */ 793 if (!opteron_erratum_122 && lgrp_plat_node_cnt == 1 && 794 cpuid_get_ncpu_per_chip(cpu) == 1) 795 break; 796 797 /* disable TLB Flush Filter */ 798 799 if ((error = checked_rdmsr(msr, &value)) != 0) { 800 msr_warning(cpu, "rd", msr, error); 801 workaround_warning(cpu, 122); 802 missing++; 803 } else { 804 value |= (uint64_t)AMD_HWCR_FFDIS; 805 if ((error = checked_wrmsr(msr, value)) != 0) { 806 msr_warning(cpu, "wr", msr, error); 807 workaround_warning(cpu, 122); 808 missing++; 809 } 810 } 811 opteron_erratum_122++; 812 #else 813 workaround_warning(cpu, 122); 814 missing++; 815 #endif 816 /*CONSTANTCONDITION*/ 817 } while (0); 818 819 /*LINTED*/ 820 if (cpuid_opteron_erratum(cpu, 123) > 0) do { 821 /* 822 * Bypassed Reads May Cause Data Corruption of System Hang in 823 * Dual Core Processors 824 */ 825 #if defined(OPTERON_ERRATUM_123) 826 uint64_t value; 827 const uint_t msr = MSR_AMD_PATCHLEVEL; 828 int err; 829 830 /* 831 * Erratum 123 applies only to multi-core cpus. 832 */ 833 if (cpuid_get_ncpu_per_chip(cpu) < 2) 834 break; 835 836 /* 837 * The "workaround" is to print a warning to upgrade the BIOS 838 */ 839 if ((err = checked_rdmsr(msr, &value)) != 0) { 840 msr_warning(cpu, "rd", msr, err); 841 workaround_warning(cpu, 123); 842 missing++; 843 } 844 if (value == 0) 845 opteron_erratum_123++; 846 #else 847 workaround_warning(cpu, 123); 848 missing++; 849 850 #endif 851 /*CONSTANTCONDITION*/ 852 } while (0); 853 854 /*LINTED*/ 855 if (cpuid_opteron_erratum(cpu, 131) > 0) do { 856 /* 857 * Multiprocessor Systems with Four or More Cores May Deadlock 858 * Waiting for a Probe Response 859 */ 860 #if defined(OPTERON_ERRATUM_131) 861 uint64_t nbcfg; 862 const uint_t msr = MSR_AMD_NB_CFG; 863 const uint64_t wabits = 864 AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR; 865 int error; 866 867 /* 868 * Erratum 131 applies to any system with four or more cores. 869 */ 870 if (opteron_erratum_131) 871 break; 872 873 if (lgrp_plat_node_cnt * cpuid_get_ncpu_per_chip(cpu) < 4) 874 break; 875 876 /* 877 * Print a warning if neither of the workarounds for 878 * erratum 131 is present. 879 */ 880 if ((error = checked_rdmsr(msr, &nbcfg)) != 0) { 881 msr_warning(cpu, "rd", msr, error); 882 workaround_warning(cpu, 131); 883 missing++; 884 } else if ((nbcfg & wabits) == 0) { 885 opteron_erratum_131++; 886 } else { 887 /* cannot have both workarounds set */ 888 ASSERT((nbcfg & wabits) != wabits); 889 } 890 #else 891 workaround_warning(cpu, 131); 892 missing++; 893 #endif 894 /*CONSTANTCONDITION*/ 895 } while (0); 896 897 /* 898 * This isn't really an erratum, but for convenience the 899 * detection/workaround code lives here and in cpuid_opteron_erratum. 900 */ 901 if (cpuid_opteron_erratum(cpu, 6336786) > 0) { 902 #if defined(OPTERON_WORKAROUND_6336786) 903 /* 904 * Disable C1-Clock ramping on multi-core/multi-processor 905 * K8 platforms to guard against TSC drift. 906 */ 907 if (opteron_workaround_6336786) { 908 opteron_workaround_6336786++; 909 } else if ((lgrp_plat_node_cnt * 910 cpuid_get_ncpu_per_chip(cpu) > 1) || 911 opteron_workaround_6336786_UP) { 912 int node; 913 uint8_t data; 914 915 for (node = 0; node < lgrp_plat_node_cnt; node++) { 916 /* 917 * Clear PMM7[1:0] (function 3, offset 0x87) 918 * Northbridge device is the node id + 24. 919 */ 920 data = pci_getb_func(0, node + 24, 3, 0x87); 921 data &= 0xFC; 922 pci_putb_func(0, node + 24, 3, 0x87, data); 923 } 924 opteron_workaround_6336786++; 925 } 926 #else 927 workaround_warning(cpu, 6336786); 928 missing++; 929 #endif 930 } 931 932 /*LINTED*/ 933 /* 934 * Mutex primitives don't work as expected. 935 */ 936 if (cpuid_opteron_erratum(cpu, 6323525) > 0) { 937 #if defined(OPTERON_WORKAROUND_6323525) 938 /* 939 * This problem only occurs with 2 or more cores. If bit in 940 * MSR_BU_CFG set, then not applicable. The workaround 941 * is to patch the semaphone routines with the lfence 942 * instruction to provide necessary load memory barrier with 943 * possible subsequent read-modify-write ops. 944 * 945 * It is too early in boot to call the patch routine so 946 * set erratum variable to be done in startup_end(). 947 */ 948 if (opteron_workaround_6323525) { 949 opteron_workaround_6323525++; 950 } else if ((x86_feature & X86_SSE2) && ((lgrp_plat_node_cnt * 951 cpuid_get_ncpu_per_chip(cpu)) > 1)) { 952 if ((xrdmsr(MSR_BU_CFG) & 0x02) == 0) 953 opteron_workaround_6323525++; 954 } 955 #else 956 workaround_warning(cpu, 6323525); 957 missing++; 958 #endif 959 } 960 961 return (missing); 962 } 963 964 void 965 workaround_errata_end() 966 { 967 #if defined(OPTERON_ERRATUM_88) 968 if (opteron_erratum_88) 969 workaround_applied(88); 970 #endif 971 #if defined(OPTERON_ERRATUM_91) 972 if (opteron_erratum_91) 973 workaround_applied(91); 974 #endif 975 #if defined(OPTERON_ERRATUM_93) 976 if (opteron_erratum_93) 977 workaround_applied(93); 978 #endif 979 #if defined(OPTERON_ERRATUM_95) 980 if (opteron_erratum_95) 981 workaround_applied(95); 982 #endif 983 #if defined(OPTERON_ERRATUM_100) 984 if (opteron_erratum_100) 985 workaround_applied(100); 986 #endif 987 #if defined(OPTERON_ERRATUM_108) 988 if (opteron_erratum_108) 989 workaround_applied(108); 990 #endif 991 #if defined(OPTERON_ERRATUM_109) 992 if (opteron_erratum_109) { 993 cmn_err(CE_WARN, 994 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 995 " processor\nerratum 109 was not detected; updating your" 996 " system's BIOS to a version\ncontaining this" 997 " microcode patch is HIGHLY recommended or erroneous" 998 " system\noperation may occur.\n"); 999 } 1000 #endif 1001 #if defined(OPTERON_ERRATUM_121) 1002 if (opteron_erratum_121) 1003 workaround_applied(121); 1004 #endif 1005 #if defined(OPTERON_ERRATUM_122) 1006 if (opteron_erratum_122) 1007 workaround_applied(122); 1008 #endif 1009 #if defined(OPTERON_ERRATUM_123) 1010 if (opteron_erratum_123) { 1011 cmn_err(CE_WARN, 1012 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1013 " processor\nerratum 123 was not detected; updating your" 1014 " system's BIOS to a version\ncontaining this" 1015 " microcode patch is HIGHLY recommended or erroneous" 1016 " system\noperation may occur.\n"); 1017 } 1018 #endif 1019 #if defined(OPTERON_ERRATUM_131) 1020 if (opteron_erratum_131) { 1021 cmn_err(CE_WARN, 1022 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1023 " processor\nerratum 131 was not detected; updating your" 1024 " system's BIOS to a version\ncontaining this" 1025 " microcode patch is HIGHLY recommended or erroneous" 1026 " system\noperation may occur.\n"); 1027 } 1028 #endif 1029 #if defined(OPTERON_WORKAROUND_6336786) 1030 if (opteron_workaround_6336786) 1031 workaround_applied(6336786); 1032 #endif 1033 #if defined(OPTERON_WORKAROUND_6323525) 1034 if (opteron_workaround_6323525) 1035 workaround_applied(6323525); 1036 #endif 1037 } 1038 1039 static cpuset_t procset; 1040 1041 /* 1042 * Start a single cpu, assuming that the kernel context is available 1043 * to successfully start another cpu. 1044 * 1045 * (For example, real mode code is mapped into the right place 1046 * in memory and is ready to be run.) 1047 */ 1048 int 1049 start_cpu(processorid_t who) 1050 { 1051 void *ctx; 1052 cpu_t *cp; 1053 int delays; 1054 int error = 0; 1055 1056 ASSERT(who != 0); 1057 1058 /* 1059 * Check if there's at least a Mbyte of kmem available 1060 * before attempting to start the cpu. 1061 */ 1062 if (kmem_avail() < 1024 * 1024) { 1063 /* 1064 * Kick off a reap in case that helps us with 1065 * later attempts .. 1066 */ 1067 kmem_reap(); 1068 return (ENOMEM); 1069 } 1070 1071 cp = mp_startup_init(who); 1072 if ((ctx = mach_cpucontext_alloc(cp)) == NULL || 1073 (error = mach_cpu_start(cp, ctx)) != 0) { 1074 1075 /* 1076 * Something went wrong before we even started it 1077 */ 1078 if (ctx) 1079 cmn_err(CE_WARN, 1080 "cpu%d: failed to start error %d", 1081 cp->cpu_id, error); 1082 else 1083 cmn_err(CE_WARN, 1084 "cpu%d: failed to allocate context", cp->cpu_id); 1085 1086 if (ctx) 1087 mach_cpucontext_free(cp, ctx, error); 1088 else 1089 error = EAGAIN; /* hmm. */ 1090 mp_startup_fini(cp, error); 1091 return (error); 1092 } 1093 1094 for (delays = 0; !CPU_IN_SET(procset, who); delays++) { 1095 if (delays == 500) { 1096 /* 1097 * After five seconds, things are probably looking 1098 * a bit bleak - explain the hang. 1099 */ 1100 cmn_err(CE_NOTE, "cpu%d: started, " 1101 "but not running in the kernel yet", who); 1102 } else if (delays > 2000) { 1103 /* 1104 * We waited at least 20 seconds, bail .. 1105 */ 1106 error = ETIMEDOUT; 1107 cmn_err(CE_WARN, "cpu%d: timed out", who); 1108 mach_cpucontext_free(cp, ctx, error); 1109 mp_startup_fini(cp, error); 1110 return (error); 1111 } 1112 1113 /* 1114 * wait at least 10ms, then check again.. 1115 */ 1116 delay(USEC_TO_TICK_ROUNDUP(10000)); 1117 } 1118 1119 mach_cpucontext_free(cp, ctx, 0); 1120 1121 if (tsc_gethrtime_enable) 1122 tsc_sync_master(who); 1123 1124 if (dtrace_cpu_init != NULL) { 1125 /* 1126 * DTrace CPU initialization expects cpu_lock to be held. 1127 */ 1128 mutex_enter(&cpu_lock); 1129 (*dtrace_cpu_init)(who); 1130 mutex_exit(&cpu_lock); 1131 } 1132 1133 while (!CPU_IN_SET(cpu_ready_set, who)) 1134 delay(1); 1135 1136 return (0); 1137 } 1138 1139 1140 /*ARGSUSED*/ 1141 void 1142 start_other_cpus(int cprboot) 1143 { 1144 uint_t who; 1145 uint_t skipped = 0; 1146 uint_t bootcpuid = 0; 1147 1148 /* 1149 * Initialize our own cpu_info. 1150 */ 1151 init_cpu_info(CPU); 1152 1153 /* 1154 * Initialize our syscall handlers 1155 */ 1156 init_cpu_syscall(CPU); 1157 1158 /* 1159 * Take the boot cpu out of the mp_cpus set because we know 1160 * it's already running. Add it to the cpu_ready_set for 1161 * precisely the same reason. 1162 */ 1163 CPUSET_DEL(mp_cpus, bootcpuid); 1164 CPUSET_ADD(cpu_ready_set, bootcpuid); 1165 1166 /* 1167 * if only 1 cpu or not using MP, skip the rest of this 1168 */ 1169 if (CPUSET_ISNULL(mp_cpus) || use_mp == 0) { 1170 if (use_mp == 0) 1171 cmn_err(CE_CONT, "?***** Not in MP mode\n"); 1172 goto done; 1173 } 1174 1175 /* 1176 * perform such initialization as is needed 1177 * to be able to take CPUs on- and off-line. 1178 */ 1179 cpu_pause_init(); 1180 1181 xc_init(); /* initialize processor crosscalls */ 1182 1183 if (mach_cpucontext_init() != 0) 1184 goto done; 1185 1186 flushes_require_xcalls = 1; 1187 1188 /* 1189 * We lock our affinity to the master CPU to ensure that all slave CPUs 1190 * do their TSC syncs with the same CPU. 1191 */ 1192 affinity_set(CPU_CURRENT); 1193 1194 for (who = 0; who < NCPU; who++) { 1195 1196 if (!CPU_IN_SET(mp_cpus, who)) 1197 continue; 1198 ASSERT(who != bootcpuid); 1199 if (ncpus >= max_ncpus) { 1200 skipped = who; 1201 continue; 1202 } 1203 if (start_cpu(who) != 0) 1204 CPUSET_DEL(mp_cpus, who); 1205 } 1206 1207 /* Free the space allocated to hold the microcode file */ 1208 ucode_free(); 1209 1210 affinity_clear(); 1211 1212 if (skipped) { 1213 cmn_err(CE_NOTE, 1214 "System detected %d cpus, but " 1215 "only %d cpu(s) were enabled during boot.", 1216 skipped + 1, ncpus); 1217 cmn_err(CE_NOTE, 1218 "Use \"boot-ncpus\" parameter to enable more CPU(s). " 1219 "See eeprom(1M)."); 1220 } 1221 1222 done: 1223 workaround_errata_end(); 1224 mach_cpucontext_fini(); 1225 1226 cmi_post_mpstartup(); 1227 } 1228 1229 /* 1230 * Dummy functions - no i86pc platforms support dynamic cpu allocation. 1231 */ 1232 /*ARGSUSED*/ 1233 int 1234 mp_cpu_configure(int cpuid) 1235 { 1236 return (ENOTSUP); /* not supported */ 1237 } 1238 1239 /*ARGSUSED*/ 1240 int 1241 mp_cpu_unconfigure(int cpuid) 1242 { 1243 return (ENOTSUP); /* not supported */ 1244 } 1245 1246 /* 1247 * Startup function for 'other' CPUs (besides boot cpu). 1248 * Called from real_mode_start. 1249 * 1250 * WARNING: until CPU_READY is set, mp_startup and routines called by 1251 * mp_startup should not call routines (e.g. kmem_free) that could call 1252 * hat_unload which requires CPU_READY to be set. 1253 */ 1254 void 1255 mp_startup(void) 1256 { 1257 struct cpu *cp = CPU; 1258 uint_t new_x86_feature; 1259 1260 /* 1261 * We need to get TSC on this proc synced (i.e., any delta 1262 * from cpu0 accounted for) as soon as we can, because many 1263 * many things use gethrtime/pc_gethrestime, including 1264 * interrupts, cmn_err, etc. 1265 */ 1266 1267 /* Let cpu0 continue into tsc_sync_master() */ 1268 CPUSET_ATOMIC_ADD(procset, cp->cpu_id); 1269 1270 if (tsc_gethrtime_enable) 1271 tsc_sync_slave(); 1272 1273 /* 1274 * Once this was done from assembly, but it's safer here; if 1275 * it blocks, we need to be able to swtch() to and from, and 1276 * since we get here by calling t_pc, we need to do that call 1277 * before swtch() overwrites it. 1278 */ 1279 1280 (void) (*ap_mlsetup)(); 1281 1282 new_x86_feature = cpuid_pass1(cp); 1283 1284 /* 1285 * We need to Sync MTRR with cpu0's MTRR. We have to do 1286 * this with interrupts disabled. 1287 */ 1288 if (x86_feature & X86_MTRR) 1289 mtrr_sync(); 1290 1291 /* 1292 * Set up TSC_AUX to contain the cpuid for this processor 1293 * for the rdtscp instruction. 1294 */ 1295 if (x86_feature & X86_TSCP) 1296 (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id); 1297 1298 /* 1299 * Initialize this CPU's syscall handlers 1300 */ 1301 init_cpu_syscall(cp); 1302 1303 /* 1304 * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the 1305 * highest level at which a routine is permitted to block on 1306 * an adaptive mutex (allows for cpu poke interrupt in case 1307 * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks 1308 * device interrupts that may end up in the hat layer issuing cross 1309 * calls before CPU_READY is set. 1310 */ 1311 splx(ipltospl(LOCK_LEVEL)); 1312 sti(); 1313 1314 /* 1315 * Do a sanity check to make sure this new CPU is a sane thing 1316 * to add to the collection of processors running this system. 1317 * 1318 * XXX Clearly this needs to get more sophisticated, if x86 1319 * systems start to get built out of heterogenous CPUs; as is 1320 * likely to happen once the number of processors in a configuration 1321 * gets large enough. 1322 */ 1323 if ((x86_feature & new_x86_feature) != x86_feature) { 1324 cmn_err(CE_CONT, "?cpu%d: %b\n", 1325 cp->cpu_id, new_x86_feature, FMT_X86_FEATURE); 1326 cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id); 1327 } 1328 1329 /* 1330 * We do not support cpus with mixed monitor/mwait support if the 1331 * boot cpu supports monitor/mwait. 1332 */ 1333 if ((x86_feature & ~new_x86_feature) & X86_MWAIT) 1334 panic("unsupported mixed cpu monitor/mwait support detected"); 1335 1336 /* 1337 * We could be more sophisticated here, and just mark the CPU 1338 * as "faulted" but at this point we'll opt for the easier 1339 * answer of dieing horribly. Provided the boot cpu is ok, 1340 * the system can be recovered by booting with use_mp set to zero. 1341 */ 1342 if (workaround_errata(cp) != 0) 1343 panic("critical workaround(s) missing for cpu%d", cp->cpu_id); 1344 1345 cpuid_pass2(cp); 1346 cpuid_pass3(cp); 1347 (void) cpuid_pass4(cp); 1348 1349 init_cpu_info(cp); 1350 1351 mutex_enter(&cpu_lock); 1352 /* 1353 * Processor group initialization for this CPU is dependent on the 1354 * cpuid probing, which must be done in the context of the current 1355 * CPU. 1356 */ 1357 pghw_physid_create(cp); 1358 pg_cpu_init(cp); 1359 pg_cmt_cpu_startup(cp); 1360 1361 cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_ENABLE | CPU_EXISTS; 1362 cpu_add_active(cp); 1363 1364 if (dtrace_cpu_init != NULL) { 1365 (*dtrace_cpu_init)(cp->cpu_id); 1366 } 1367 1368 /* 1369 * Fill out cpu_ucode_info. Update microcode if necessary. 1370 */ 1371 ucode_check(cp); 1372 1373 mutex_exit(&cpu_lock); 1374 1375 /* 1376 * Enable preemption here so that contention for any locks acquired 1377 * later in mp_startup may be preempted if the thread owning those 1378 * locks is continously executing on other CPUs (for example, this 1379 * CPU must be preemptible to allow other CPUs to pause it during their 1380 * startup phases). It's safe to enable preemption here because the 1381 * CPU state is pretty-much fully constructed. 1382 */ 1383 curthread->t_preempt = 0; 1384 1385 add_cpunode2devtree(cp->cpu_id, cp->cpu_m.mcpu_cpi); 1386 1387 /* The base spl should still be at LOCK LEVEL here */ 1388 ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL)); 1389 set_base_spl(); /* Restore the spl to its proper value */ 1390 1391 (void) spl0(); /* enable interrupts */ 1392 1393 /* 1394 * Set up the CPU module for this CPU. This can't be done before 1395 * this CPU is made CPU_READY, because we may (in heterogeneous systems) 1396 * need to go load another CPU module. The act of attempting to load 1397 * a module may trigger a cross-call, which will ASSERT unless this 1398 * cpu is CPU_READY. 1399 */ 1400 cmi_init(); 1401 1402 if (x86_feature & X86_MCA) 1403 cmi_mca_init(); 1404 1405 if (boothowto & RB_DEBUG) 1406 kdi_cpu_init(); 1407 1408 /* 1409 * Setting the bit in cpu_ready_set must be the last operation in 1410 * processor initialization; the boot CPU will continue to boot once 1411 * it sees this bit set for all active CPUs. 1412 */ 1413 CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id); 1414 1415 /* 1416 * Because mp_startup() gets fired off after init() starts, we 1417 * can't use the '?' trick to do 'boot -v' printing - so we 1418 * always direct the 'cpu .. online' messages to the log. 1419 */ 1420 cmn_err(CE_CONT, "!cpu%d initialization complete - online\n", 1421 cp->cpu_id); 1422 1423 /* 1424 * Now we are done with the startup thread, so free it up. 1425 */ 1426 thread_exit(); 1427 panic("mp_startup: cannot return"); 1428 /*NOTREACHED*/ 1429 } 1430 1431 1432 /* 1433 * Start CPU on user request. 1434 */ 1435 /* ARGSUSED */ 1436 int 1437 mp_cpu_start(struct cpu *cp) 1438 { 1439 ASSERT(MUTEX_HELD(&cpu_lock)); 1440 return (0); 1441 } 1442 1443 /* 1444 * Stop CPU on user request. 1445 */ 1446 /* ARGSUSED */ 1447 int 1448 mp_cpu_stop(struct cpu *cp) 1449 { 1450 extern int cbe_psm_timer_mode; 1451 ASSERT(MUTEX_HELD(&cpu_lock)); 1452 1453 /* 1454 * If TIMER_PERIODIC mode is used, CPU0 is the one running it; 1455 * can't stop it. (This is true only for machines with no TSC.) 1456 */ 1457 1458 if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0)) 1459 return (1); 1460 1461 return (0); 1462 } 1463 1464 /* 1465 * Take the specified CPU out of participation in interrupts. 1466 */ 1467 int 1468 cpu_disable_intr(struct cpu *cp) 1469 { 1470 if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS) 1471 return (EBUSY); 1472 1473 cp->cpu_flags &= ~CPU_ENABLE; 1474 return (0); 1475 } 1476 1477 /* 1478 * Allow the specified CPU to participate in interrupts. 1479 */ 1480 void 1481 cpu_enable_intr(struct cpu *cp) 1482 { 1483 ASSERT(MUTEX_HELD(&cpu_lock)); 1484 cp->cpu_flags |= CPU_ENABLE; 1485 psm_enable_intr(cp->cpu_id); 1486 } 1487 1488 1489 1490 void 1491 mp_cpu_faulted_enter(struct cpu *cp) 1492 { 1493 cmi_faulted_enter(cp); 1494 } 1495 1496 void 1497 mp_cpu_faulted_exit(struct cpu *cp) 1498 { 1499 cmi_faulted_exit(cp); 1500 } 1501 1502 /* 1503 * The following two routines are used as context operators on threads belonging 1504 * to processes with a private LDT (see sysi86). Due to the rarity of such 1505 * processes, these routines are currently written for best code readability and 1506 * organization rather than speed. We could avoid checking x86_feature at every 1507 * context switch by installing different context ops, depending on the 1508 * x86_feature flags, at LDT creation time -- one for each combination of fast 1509 * syscall feature flags. 1510 */ 1511 1512 /*ARGSUSED*/ 1513 void 1514 cpu_fast_syscall_disable(void *arg) 1515 { 1516 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) 1517 cpu_sep_disable(); 1518 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) 1519 cpu_asysc_disable(); 1520 } 1521 1522 /*ARGSUSED*/ 1523 void 1524 cpu_fast_syscall_enable(void *arg) 1525 { 1526 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) 1527 cpu_sep_enable(); 1528 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) 1529 cpu_asysc_enable(); 1530 } 1531 1532 static void 1533 cpu_sep_enable(void) 1534 { 1535 ASSERT(x86_feature & X86_SEP); 1536 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1537 1538 wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL); 1539 } 1540 1541 static void 1542 cpu_sep_disable(void) 1543 { 1544 ASSERT(x86_feature & X86_SEP); 1545 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1546 1547 /* 1548 * Setting the SYSENTER_CS_MSR register to 0 causes software executing 1549 * the sysenter or sysexit instruction to trigger a #gp fault. 1550 */ 1551 wrmsr(MSR_INTC_SEP_CS, 0); 1552 } 1553 1554 static void 1555 cpu_asysc_enable(void) 1556 { 1557 ASSERT(x86_feature & X86_ASYSC); 1558 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1559 1560 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) | 1561 (uint64_t)(uintptr_t)AMD_EFER_SCE); 1562 } 1563 1564 static void 1565 cpu_asysc_disable(void) 1566 { 1567 ASSERT(x86_feature & X86_ASYSC); 1568 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1569 1570 /* 1571 * Turn off the SCE (syscall enable) bit in the EFER register. Software 1572 * executing syscall or sysret with this bit off will incur a #ud trap. 1573 */ 1574 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) & 1575 ~((uint64_t)(uintptr_t)AMD_EFER_SCE)); 1576 } 1577