1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2012 Gary Mills 23 * 24 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved. 25 * Copyright (c) 2011 by Delphix. All rights reserved. 26 * Copyright 2019, Joyent, Inc. 27 */ 28 /* 29 * Copyright (c) 2010, Intel Corporation. 30 * All rights reserved. 31 */ 32 33 #include <sys/types.h> 34 #include <sys/sysmacros.h> 35 #include <sys/disp.h> 36 #include <sys/promif.h> 37 #include <sys/clock.h> 38 #include <sys/cpuvar.h> 39 #include <sys/stack.h> 40 #include <vm/as.h> 41 #include <vm/hat.h> 42 #include <sys/reboot.h> 43 #include <sys/avintr.h> 44 #include <sys/vtrace.h> 45 #include <sys/proc.h> 46 #include <sys/thread.h> 47 #include <sys/cpupart.h> 48 #include <sys/pset.h> 49 #include <sys/copyops.h> 50 #include <sys/pg.h> 51 #include <sys/disp.h> 52 #include <sys/debug.h> 53 #include <sys/sunddi.h> 54 #include <sys/x86_archext.h> 55 #include <sys/privregs.h> 56 #include <sys/machsystm.h> 57 #include <sys/ontrap.h> 58 #include <sys/bootconf.h> 59 #include <sys/boot_console.h> 60 #include <sys/kdi_machimpl.h> 61 #include <sys/archsystm.h> 62 #include <sys/promif.h> 63 #include <sys/pci_cfgspace.h> 64 #include <sys/apic.h> 65 #include <sys/apic_common.h> 66 #include <sys/bootvfs.h> 67 #include <sys/tsc.h> 68 #ifdef __xpv 69 #include <sys/hypervisor.h> 70 #else 71 #include <sys/xpv_support.h> 72 #endif 73 74 /* 75 * some globals for patching the result of cpuid 76 * to solve problems w/ creative cpu vendors 77 */ 78 79 extern uint32_t cpuid_feature_ecx_include; 80 extern uint32_t cpuid_feature_ecx_exclude; 81 extern uint32_t cpuid_feature_edx_include; 82 extern uint32_t cpuid_feature_edx_exclude; 83 84 nmi_action_t nmi_action = NMI_ACTION_UNSET; 85 86 /* 87 * Set console mode 88 */ 89 static void 90 set_console_mode(uint8_t val) 91 { 92 struct bop_regs rp = {0}; 93 94 rp.eax.byte.ah = 0x0; 95 rp.eax.byte.al = val; 96 rp.ebx.word.bx = 0x0; 97 98 BOP_DOINT(bootops, 0x10, &rp); 99 } 100 101 102 /* 103 * Setup routine called right before main(). Interposing this function 104 * before main() allows us to call it in a machine-independent fashion. 105 */ 106 void 107 mlsetup(struct regs *rp) 108 { 109 u_longlong_t prop_value; 110 char prop_str[BP_MAX_STRLEN]; 111 extern struct classfuncs sys_classfuncs; 112 extern disp_t cpu0_disp; 113 extern char t0stack[]; 114 extern int post_fastreboot; 115 extern uint64_t plat_dr_options; 116 117 ASSERT_STACK_ALIGNED(); 118 119 /* 120 * initialize cpu_self 121 */ 122 cpu[0]->cpu_self = cpu[0]; 123 124 #if defined(__xpv) 125 /* 126 * Point at the hypervisor's virtual cpu structure 127 */ 128 cpu[0]->cpu_m.mcpu_vcpu_info = &HYPERVISOR_shared_info->vcpu_info[0]; 129 #endif 130 131 /* 132 * check if we've got special bits to clear or set 133 * when checking cpu features 134 */ 135 136 if (bootprop_getval("cpuid_feature_ecx_include", &prop_value) != 0) 137 cpuid_feature_ecx_include = 0; 138 else 139 cpuid_feature_ecx_include = (uint32_t)prop_value; 140 141 if (bootprop_getval("cpuid_feature_ecx_exclude", &prop_value) != 0) 142 cpuid_feature_ecx_exclude = 0; 143 else 144 cpuid_feature_ecx_exclude = (uint32_t)prop_value; 145 146 if (bootprop_getval("cpuid_feature_edx_include", &prop_value) != 0) 147 cpuid_feature_edx_include = 0; 148 else 149 cpuid_feature_edx_include = (uint32_t)prop_value; 150 151 if (bootprop_getval("cpuid_feature_edx_exclude", &prop_value) != 0) 152 cpuid_feature_edx_exclude = 0; 153 else 154 cpuid_feature_edx_exclude = (uint32_t)prop_value; 155 156 #if !defined(__xpv) 157 if (bootprop_getstr("nmi", prop_str, sizeof (prop_str)) == 0) { 158 if (strcmp(prop_str, "ignore") == 0) { 159 nmi_action = NMI_ACTION_IGNORE; 160 } else if (strcmp(prop_str, "panic") == 0) { 161 nmi_action = NMI_ACTION_PANIC; 162 } else if (strcmp(prop_str, "kmdb") == 0) { 163 nmi_action = NMI_ACTION_KMDB; 164 } else { 165 prom_printf("unix: ignoring unknown nmi=%s\n", 166 prop_str); 167 } 168 } 169 170 /* 171 * Check to see if KPTI has been explicitly enabled or disabled. 172 * We have to check this before init_desctbls(). 173 */ 174 if (bootprop_getval("kpti", &prop_value) == 0) { 175 kpti_enable = (uint64_t)(prop_value == 1); 176 prom_printf("unix: forcing kpti to %s due to boot argument\n", 177 (kpti_enable == 1) ? "ON" : "OFF"); 178 } else { 179 kpti_enable = 1; 180 } 181 182 if (bootprop_getval("pcid", &prop_value) == 0 && prop_value == 0) { 183 prom_printf("unix: forcing pcid to OFF due to boot argument\n"); 184 x86_use_pcid = 0; 185 } else if (kpti_enable != 1) { 186 x86_use_pcid = 0; 187 } 188 #endif 189 190 /* 191 * Initialize idt0, gdt0, ldt0_default, ktss0 and dftss. 192 */ 193 init_desctbls(); 194 195 /* 196 * lgrp_init() and possibly cpuid_pass1() need PCI config 197 * space access 198 */ 199 #if defined(__xpv) 200 if (DOMAIN_IS_INITDOMAIN(xen_info)) 201 pci_cfgspace_init(); 202 #else 203 pci_cfgspace_init(); 204 /* 205 * Initialize the platform type from CPU 0 to ensure that 206 * determine_platform() is only ever called once. 207 */ 208 determine_platform(); 209 #endif 210 211 /* 212 * The first lightweight pass (pass0) through the cpuid data 213 * was done in locore before mlsetup was called. Do the next 214 * pass in C code. 215 * 216 * The x86_featureset is initialized here based on the capabilities 217 * of the boot CPU. Note that if we choose to support CPUs that have 218 * different feature sets (at which point we would almost certainly 219 * want to set the feature bits to correspond to the feature 220 * minimum) this value may be altered. 221 */ 222 cpuid_pass1(cpu[0], x86_featureset); 223 224 #if !defined(__xpv) 225 if ((get_hwenv() & HW_XEN_HVM) != 0) 226 xen_hvm_init(); 227 228 /* 229 * Before we do anything with the TSCs, we need to work around 230 * Intel erratum BT81. On some CPUs, warm reset does not 231 * clear the TSC. If we are on such a CPU, we will clear TSC ourselves 232 * here. Other CPUs will clear it when we boot them later, and the 233 * resulting skew will be handled by tsc_sync_master()/_slave(); 234 * note that such skew already exists and has to be handled anyway. 235 * 236 * We do this only on metal. This same problem can occur with a 237 * hypervisor that does not happen to virtualise a TSC that starts from 238 * zero, regardless of CPU type; however, we do not expect hypervisors 239 * that do not virtualise TSC that way to handle writes to TSC 240 * correctly, either. 241 */ 242 if (get_hwenv() == HW_NATIVE && 243 cpuid_getvendor(CPU) == X86_VENDOR_Intel && 244 cpuid_getfamily(CPU) == 6 && 245 (cpuid_getmodel(CPU) == 0x2d || cpuid_getmodel(CPU) == 0x3e) && 246 is_x86_feature(x86_featureset, X86FSET_TSC)) { 247 (void) wrmsr(REG_TSC, 0UL); 248 } 249 250 /* 251 * Patch the tsc_read routine with appropriate set of instructions, 252 * depending on the processor family and architecure, to read the 253 * time-stamp counter while ensuring no out-of-order execution. 254 * Patch it while the kernel text is still writable. 255 * 256 * Note: tsc_read is not patched for intel processors whose family 257 * is >6 and for amd whose family >f (in case they don't support rdtscp 258 * instruction, unlikely). By default tsc_read will use cpuid for 259 * serialization in such cases. The following code needs to be 260 * revisited if intel processors of family >= f retains the 261 * instruction serialization nature of mfence instruction. 262 * Note: tsc_read is not patched for x86 processors which do 263 * not support "mfence". By default tsc_read will use cpuid for 264 * serialization in such cases. 265 * 266 * The Xen hypervisor does not correctly report whether rdtscp is 267 * supported or not, so we must assume that it is not. 268 */ 269 if ((get_hwenv() & HW_XEN_HVM) == 0 && 270 is_x86_feature(x86_featureset, X86FSET_TSCP)) 271 patch_tsc_read(TSC_TSCP); 272 else if (cpuid_getvendor(CPU) == X86_VENDOR_AMD && 273 cpuid_getfamily(CPU) <= 0xf && 274 is_x86_feature(x86_featureset, X86FSET_SSE2)) 275 patch_tsc_read(TSC_RDTSC_MFENCE); 276 else if (cpuid_getvendor(CPU) == X86_VENDOR_Intel && 277 cpuid_getfamily(CPU) <= 6 && 278 is_x86_feature(x86_featureset, X86FSET_SSE2)) 279 patch_tsc_read(TSC_RDTSC_LFENCE); 280 281 #endif /* !__xpv */ 282 283 #if defined(__i386) && !defined(__xpv) 284 /* 285 * Some i386 processors do not implement the rdtsc instruction, 286 * or at least they do not implement it correctly. Patch them to 287 * return 0. 288 */ 289 if (!is_x86_feature(x86_featureset, X86FSET_TSC)) 290 patch_tsc_read(TSC_NONE); 291 #endif /* __i386 && !__xpv */ 292 293 #if defined(__amd64) && !defined(__xpv) 294 patch_memops(cpuid_getvendor(CPU)); 295 #endif /* __amd64 && !__xpv */ 296 297 #if !defined(__xpv) 298 /* XXPV what, if anything, should be dorked with here under xen? */ 299 300 /* 301 * While we're thinking about the TSC, let's set up %cr4 so that 302 * userland can issue rdtsc, and initialize the TSC_AUX value 303 * (the cpuid) for the rdtscp instruction on appropriately 304 * capable hardware. 305 */ 306 if (is_x86_feature(x86_featureset, X86FSET_TSC)) 307 setcr4(getcr4() & ~CR4_TSD); 308 309 if (is_x86_feature(x86_featureset, X86FSET_TSCP)) 310 (void) wrmsr(MSR_AMD_TSCAUX, 0); 311 312 /* 313 * Let's get the other %cr4 stuff while we're here. Note, we defer 314 * enabling CR4_SMAP until startup_end(); however, that's importantly 315 * before we start other CPUs. That ensures that it will be synced out 316 * to other CPUs. 317 */ 318 if (is_x86_feature(x86_featureset, X86FSET_DE)) 319 setcr4(getcr4() | CR4_DE); 320 321 if (is_x86_feature(x86_featureset, X86FSET_SMEP)) 322 setcr4(getcr4() | CR4_SMEP); 323 #endif /* __xpv */ 324 325 /* 326 * initialize t0 327 */ 328 t0.t_stk = (caddr_t)rp - MINFRAME; 329 t0.t_stkbase = t0stack; 330 t0.t_pri = maxclsyspri - 3; 331 t0.t_schedflag = TS_LOAD | TS_DONT_SWAP; 332 t0.t_procp = &p0; 333 t0.t_plockp = &p0lock.pl_lock; 334 t0.t_lwp = &lwp0; 335 t0.t_forw = &t0; 336 t0.t_back = &t0; 337 t0.t_next = &t0; 338 t0.t_prev = &t0; 339 t0.t_cpu = cpu[0]; 340 t0.t_disp_queue = &cpu0_disp; 341 t0.t_bind_cpu = PBIND_NONE; 342 t0.t_bind_pset = PS_NONE; 343 t0.t_bindflag = (uchar_t)default_binding_mode; 344 t0.t_cpupart = &cp_default; 345 t0.t_clfuncs = &sys_classfuncs.thread; 346 t0.t_copyops = NULL; 347 THREAD_ONPROC(&t0, CPU); 348 349 lwp0.lwp_thread = &t0; 350 lwp0.lwp_regs = (void *)rp; 351 lwp0.lwp_procp = &p0; 352 t0.t_tid = p0.p_lwpcnt = p0.p_lwprcnt = p0.p_lwpid = 1; 353 354 p0.p_exec = NULL; 355 p0.p_stat = SRUN; 356 p0.p_flag = SSYS; 357 p0.p_tlist = &t0; 358 p0.p_stksize = 2*PAGESIZE; 359 p0.p_stkpageszc = 0; 360 p0.p_as = &kas; 361 p0.p_lockp = &p0lock; 362 p0.p_brkpageszc = 0; 363 p0.p_t1_lgrpid = LGRP_NONE; 364 p0.p_tr_lgrpid = LGRP_NONE; 365 psecflags_default(&p0.p_secflags); 366 367 sigorset(&p0.p_ignore, &ignoredefault); 368 369 CPU->cpu_thread = &t0; 370 bzero(&cpu0_disp, sizeof (disp_t)); 371 CPU->cpu_disp = &cpu0_disp; 372 CPU->cpu_disp->disp_cpu = CPU; 373 CPU->cpu_dispthread = &t0; 374 CPU->cpu_idle_thread = &t0; 375 CPU->cpu_flags = CPU_READY | CPU_RUNNING | CPU_EXISTS | CPU_ENABLE; 376 CPU->cpu_dispatch_pri = t0.t_pri; 377 378 CPU->cpu_id = 0; 379 380 CPU->cpu_pri = 12; /* initial PIL for the boot CPU */ 381 382 /* 383 * Initialize thread/cpu microstate accounting 384 */ 385 init_mstate(&t0, LMS_SYSTEM); 386 init_cpu_mstate(CPU, CMS_SYSTEM); 387 388 /* 389 * Initialize lists of available and active CPUs. 390 */ 391 cpu_list_init(CPU); 392 393 pg_cpu_bootstrap(CPU); 394 395 /* 396 * Now that we have taken over the GDT, IDT and have initialized 397 * active CPU list it's time to inform kmdb if present. 398 */ 399 if (boothowto & RB_DEBUG) 400 kdi_idt_sync(); 401 402 if (BOP_GETPROPLEN(bootops, "efi-systab") < 0) { 403 /* 404 * In BIOS system, explicitly set console to text mode (0x3) 405 * if this is a boot post Fast Reboot, and the console is set 406 * to CONS_SCREEN_TEXT. 407 */ 408 if (post_fastreboot && 409 boot_console_type(NULL) == CONS_SCREEN_TEXT) { 410 set_console_mode(0x3); 411 } 412 } 413 414 /* 415 * If requested (boot -d) drop into kmdb. 416 * 417 * This must be done after cpu_list_init() on the 64-bit kernel 418 * since taking a trap requires that we re-compute gsbase based 419 * on the cpu list. 420 */ 421 if (boothowto & RB_DEBUGENTER) 422 kmdb_enter(); 423 424 cpu_vm_data_init(CPU); 425 426 rp->r_fp = 0; /* terminate kernel stack traces! */ 427 428 prom_init("kernel", (void *)NULL); 429 430 /* User-set option overrides firmware value. */ 431 if (bootprop_getval(PLAT_DR_OPTIONS_NAME, &prop_value) == 0) { 432 plat_dr_options = (uint64_t)prop_value; 433 } 434 #if defined(__xpv) 435 /* No support of DR operations on xpv */ 436 plat_dr_options = 0; 437 #else /* __xpv */ 438 /* Flag PLAT_DR_FEATURE_ENABLED should only be set by DR driver. */ 439 plat_dr_options &= ~PLAT_DR_FEATURE_ENABLED; 440 #ifndef __amd64 441 /* Only enable CPU/memory DR on 64 bits kernel. */ 442 plat_dr_options &= ~PLAT_DR_FEATURE_MEMORY; 443 plat_dr_options &= ~PLAT_DR_FEATURE_CPU; 444 #endif /* __amd64 */ 445 #endif /* __xpv */ 446 447 /* 448 * Get value of "plat_dr_physmax" boot option. 449 * It overrides values calculated from MSCT or SRAT table. 450 */ 451 if (bootprop_getval(PLAT_DR_PHYSMAX_NAME, &prop_value) == 0) { 452 plat_dr_physmax = ((uint64_t)prop_value) >> PAGESHIFT; 453 } 454 455 /* Get value of boot_ncpus. */ 456 if (bootprop_getval(BOOT_NCPUS_NAME, &prop_value) != 0) { 457 boot_ncpus = NCPU; 458 } else { 459 boot_ncpus = (int)prop_value; 460 if (boot_ncpus <= 0 || boot_ncpus > NCPU) 461 boot_ncpus = NCPU; 462 } 463 464 /* 465 * Set max_ncpus and boot_max_ncpus to boot_ncpus if platform doesn't 466 * support CPU DR operations. 467 */ 468 if (plat_dr_support_cpu() == 0) { 469 max_ncpus = boot_max_ncpus = boot_ncpus; 470 } else { 471 if (bootprop_getval(PLAT_MAX_NCPUS_NAME, &prop_value) != 0) { 472 max_ncpus = NCPU; 473 } else { 474 max_ncpus = (int)prop_value; 475 if (max_ncpus <= 0 || max_ncpus > NCPU) { 476 max_ncpus = NCPU; 477 } 478 if (boot_ncpus > max_ncpus) { 479 boot_ncpus = max_ncpus; 480 } 481 } 482 483 if (bootprop_getval(BOOT_MAX_NCPUS_NAME, &prop_value) != 0) { 484 boot_max_ncpus = boot_ncpus; 485 } else { 486 boot_max_ncpus = (int)prop_value; 487 if (boot_max_ncpus <= 0 || boot_max_ncpus > NCPU) { 488 boot_max_ncpus = boot_ncpus; 489 } else if (boot_max_ncpus > max_ncpus) { 490 boot_max_ncpus = max_ncpus; 491 } 492 } 493 } 494 495 /* 496 * Initialize the lgrp framework 497 */ 498 lgrp_init(LGRP_INIT_STAGE1); 499 500 if (boothowto & RB_HALT) { 501 prom_printf("unix: kernel halted by -h flag\n"); 502 prom_enter_mon(); 503 } 504 505 ASSERT_STACK_ALIGNED(); 506 507 /* 508 * Fill out cpu_ucode_info. Update microcode if necessary. 509 */ 510 ucode_check(CPU); 511 cpuid_pass_ucode(CPU, x86_featureset); 512 513 if (workaround_errata(CPU) != 0) 514 panic("critical workaround(s) missing for boot cpu"); 515 } 516 517 518 void 519 mach_modpath(char *path, const char *filename) 520 { 521 /* 522 * Construct the directory path from the filename. 523 */ 524 525 int len; 526 char *p; 527 const char isastr[] = "/amd64"; 528 size_t isalen = strlen(isastr); 529 530 len = strlen(SYSTEM_BOOT_PATH "/kernel"); 531 (void) strcpy(path, SYSTEM_BOOT_PATH "/kernel "); 532 path += len + 1; 533 534 if ((p = strrchr(filename, '/')) == NULL) 535 return; 536 537 while (p > filename && *(p - 1) == '/') 538 p--; /* remove trailing '/' characters */ 539 if (p == filename) 540 p++; /* so "/" -is- the modpath in this case */ 541 542 /* 543 * Remove optional isa-dependent directory name - the module 544 * subsystem will put this back again (!) 545 */ 546 len = p - filename; 547 if (len > isalen && 548 strncmp(&filename[len - isalen], isastr, isalen) == 0) 549 p -= isalen; 550 551 /* 552 * "/platform/mumblefrotz" + " " + MOD_DEFPATH 553 */ 554 len += (p - filename) + 1 + strlen(MOD_DEFPATH) + 1; 555 (void) strncpy(path, filename, p - filename); 556 } 557