1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2012 Gary Mills 23 * 24 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved. 25 * Copyright (c) 2011 by Delphix. All rights reserved. 26 * Copyright 2019 Joyent, Inc. 27 * Copyright 2024 Oxide Computer Company 28 */ 29 /* 30 * Copyright (c) 2010, Intel Corporation. 31 * All rights reserved. 32 */ 33 34 #include <sys/types.h> 35 #include <sys/sysmacros.h> 36 #include <sys/disp.h> 37 #include <sys/promif.h> 38 #include <sys/clock.h> 39 #include <sys/cpuvar.h> 40 #include <sys/stack.h> 41 #include <vm/as.h> 42 #include <vm/hat.h> 43 #include <sys/reboot.h> 44 #include <sys/avintr.h> 45 #include <sys/vtrace.h> 46 #include <sys/proc.h> 47 #include <sys/thread.h> 48 #include <sys/cpupart.h> 49 #include <sys/pset.h> 50 #include <sys/copyops.h> 51 #include <sys/pg.h> 52 #include <sys/disp.h> 53 #include <sys/debug.h> 54 #include <sys/sunddi.h> 55 #include <sys/x86_archext.h> 56 #include <sys/privregs.h> 57 #include <sys/machsystm.h> 58 #include <sys/ontrap.h> 59 #include <sys/bootconf.h> 60 #include <sys/boot_console.h> 61 #include <sys/kdi_machimpl.h> 62 #include <sys/archsystm.h> 63 #include <sys/promif.h> 64 #include <sys/pci_cfgspace.h> 65 #include <sys/apic.h> 66 #include <sys/apic_common.h> 67 #include <sys/bootvfs.h> 68 #include <sys/tsc.h> 69 #include <sys/smt.h> 70 #ifdef __xpv 71 #include <sys/hypervisor.h> 72 #else 73 #include <sys/xpv_support.h> 74 #endif 75 76 /* 77 * some globals for patching the result of cpuid 78 * to solve problems w/ creative cpu vendors 79 */ 80 81 extern uint32_t cpuid_feature_ecx_include; 82 extern uint32_t cpuid_feature_ecx_exclude; 83 extern uint32_t cpuid_feature_edx_include; 84 extern uint32_t cpuid_feature_edx_exclude; 85 86 nmi_action_t nmi_action = NMI_ACTION_UNSET; 87 88 /* 89 * Set console mode 90 */ 91 static void 92 set_console_mode(uint8_t val) 93 { 94 struct bop_regs rp = {0}; 95 96 rp.eax.byte.ah = 0x0; 97 rp.eax.byte.al = val; 98 rp.ebx.word.bx = 0x0; 99 100 BOP_DOINT(bootops, 0x10, &rp); 101 } 102 103 104 /* 105 * Setup routine called right before main(). Interposing this function 106 * before main() allows us to call it in a machine-independent fashion. 107 */ 108 void 109 mlsetup(struct regs *rp) 110 { 111 u_longlong_t prop_value; 112 char prop_str[BP_MAX_STRLEN]; 113 extern struct classfuncs sys_classfuncs; 114 extern disp_t cpu0_disp; 115 extern char t0stack[]; 116 extern int post_fastreboot; 117 extern uint64_t plat_dr_options; 118 119 ASSERT_STACK_ALIGNED(); 120 121 /* 122 * initialize cpu_self 123 */ 124 cpu[0]->cpu_self = cpu[0]; 125 126 #if defined(__xpv) 127 /* 128 * Point at the hypervisor's virtual cpu structure 129 */ 130 cpu[0]->cpu_m.mcpu_vcpu_info = &HYPERVISOR_shared_info->vcpu_info[0]; 131 #endif 132 133 /* 134 * check if we've got special bits to clear or set 135 * when checking cpu features 136 */ 137 138 if (bootprop_getval("cpuid_feature_ecx_include", &prop_value) != 0) 139 cpuid_feature_ecx_include = 0; 140 else 141 cpuid_feature_ecx_include = (uint32_t)prop_value; 142 143 if (bootprop_getval("cpuid_feature_ecx_exclude", &prop_value) != 0) 144 cpuid_feature_ecx_exclude = 0; 145 else 146 cpuid_feature_ecx_exclude = (uint32_t)prop_value; 147 148 if (bootprop_getval("cpuid_feature_edx_include", &prop_value) != 0) 149 cpuid_feature_edx_include = 0; 150 else 151 cpuid_feature_edx_include = (uint32_t)prop_value; 152 153 if (bootprop_getval("cpuid_feature_edx_exclude", &prop_value) != 0) 154 cpuid_feature_edx_exclude = 0; 155 else 156 cpuid_feature_edx_exclude = (uint32_t)prop_value; 157 158 #if !defined(__xpv) 159 if (bootprop_getstr("nmi", prop_str, sizeof (prop_str)) == 0) { 160 if (strcmp(prop_str, "ignore") == 0) { 161 nmi_action = NMI_ACTION_IGNORE; 162 } else if (strcmp(prop_str, "panic") == 0) { 163 nmi_action = NMI_ACTION_PANIC; 164 } else if (strcmp(prop_str, "kmdb") == 0) { 165 nmi_action = NMI_ACTION_KMDB; 166 } else { 167 prom_printf("unix: ignoring unknown nmi=%s\n", 168 prop_str); 169 } 170 } 171 172 /* 173 * Check to see if KPTI has been explicitly enabled or disabled. 174 * We have to check this before init_desctbls(). 175 */ 176 if (bootprop_getval("kpti", &prop_value) == 0) { 177 kpti_enable = (uint64_t)(prop_value == 1); 178 prom_printf("unix: forcing kpti to %s due to boot argument\n", 179 (kpti_enable == 1) ? "ON" : "OFF"); 180 } else { 181 kpti_enable = 1; 182 } 183 184 if (bootprop_getval("pcid", &prop_value) == 0 && prop_value == 0) { 185 prom_printf("unix: forcing pcid to OFF due to boot argument\n"); 186 x86_use_pcid = 0; 187 } else if (kpti_enable != 1) { 188 x86_use_pcid = 0; 189 } 190 191 /* 192 * While we don't need to check this until later, we might as well do it 193 * here. 194 */ 195 if (bootprop_getstr("smt_enabled", prop_str, sizeof (prop_str)) == 0) { 196 if (strcasecmp(prop_str, "false") == 0 || 197 strcmp(prop_str, "0") == 0) 198 smt_boot_disable = 1; 199 } 200 201 #endif 202 203 /* 204 * Initialize idt0, gdt0, ldt0_default, ktss0 and dftss. 205 */ 206 init_desctbls(); 207 208 /* 209 * initialize t0 210 */ 211 t0.t_stk = (caddr_t)rp - MINFRAME; 212 t0.t_stkbase = t0stack; 213 t0.t_pri = maxclsyspri - 3; 214 t0.t_schedflag = TS_LOAD | TS_DONT_SWAP; 215 t0.t_procp = &p0; 216 t0.t_plockp = &p0lock.pl_lock; 217 t0.t_lwp = &lwp0; 218 t0.t_forw = &t0; 219 t0.t_back = &t0; 220 t0.t_next = &t0; 221 t0.t_prev = &t0; 222 t0.t_cpu = cpu[0]; 223 t0.t_disp_queue = &cpu0_disp; 224 t0.t_bind_cpu = PBIND_NONE; 225 t0.t_bind_pset = PS_NONE; 226 t0.t_bindflag = (uchar_t)default_binding_mode; 227 t0.t_cpupart = &cp_default; 228 t0.t_clfuncs = &sys_classfuncs.thread; 229 t0.t_copyops = NULL; 230 THREAD_ONPROC(&t0, CPU); 231 232 lwp0.lwp_thread = &t0; 233 lwp0.lwp_regs = (void *)rp; 234 lwp0.lwp_procp = &p0; 235 t0.t_tid = p0.p_lwpcnt = p0.p_lwprcnt = p0.p_lwpid = 1; 236 237 p0.p_exec = NULL; 238 p0.p_stat = SRUN; 239 p0.p_flag = SSYS; 240 p0.p_tlist = &t0; 241 p0.p_stksize = 2*PAGESIZE; 242 p0.p_stkpageszc = 0; 243 p0.p_as = &kas; 244 p0.p_lockp = &p0lock; 245 p0.p_brkpageszc = 0; 246 p0.p_t1_lgrpid = LGRP_NONE; 247 p0.p_tr_lgrpid = LGRP_NONE; 248 psecflags_default(&p0.p_secflags); 249 250 sigorset(&p0.p_ignore, &ignoredefault); 251 252 CPU->cpu_thread = &t0; 253 bzero(&cpu0_disp, sizeof (disp_t)); 254 CPU->cpu_disp = &cpu0_disp; 255 CPU->cpu_disp->disp_cpu = CPU; 256 CPU->cpu_dispthread = &t0; 257 CPU->cpu_idle_thread = &t0; 258 CPU->cpu_flags = CPU_READY | CPU_RUNNING | CPU_EXISTS | CPU_ENABLE; 259 CPU->cpu_dispatch_pri = t0.t_pri; 260 261 CPU->cpu_id = 0; 262 263 CPU->cpu_pri = 12; /* initial PIL for the boot CPU */ 264 265 /* 266 * Ensure that we have set the necessary feature bits before setting up 267 * PCI config space access. 268 */ 269 cpuid_execpass(cpu[0], CPUID_PASS_PRELUDE, x86_featureset); 270 271 /* 272 * lgrp_init() and possibly cpuid_pass1() need PCI config 273 * space access 274 */ 275 #if defined(__xpv) 276 if (DOMAIN_IS_INITDOMAIN(xen_info)) 277 pci_cfgspace_init(); 278 #else 279 pci_cfgspace_init(); 280 /* 281 * Initialize the platform type from CPU 0 to ensure that 282 * determine_platform() is only ever called once. 283 */ 284 determine_platform(); 285 #endif 286 287 /* 288 * While the BIOS may have already applied some microcode updates, we 289 * may have more recent updates available that we'd like to apply. The 290 * application of said microcode may end up resulting in architecturally 291 * visible changes (e.g., changed MSR or CPUID bits) which we'd like to 292 * have in place before we start querying the CPU for its capabilities. 293 * So we first run the IDENT pass to determine the specific CPU vendor, 294 * model, rev etc., fill out cpu_ucode_info and update the microcode, if 295 * necessary. 296 */ 297 cpuid_execpass(cpu[0], CPUID_PASS_IDENT, NULL); 298 ucode_init(); 299 ucode_check_boot(); 300 301 /* 302 * Now we're ready to run the BASIC cpuid pass. 303 * 304 * The x86_featureset is initialized here based on the capabilities of 305 * the boot CPU. Note that if we choose to support CPUs that have 306 * different feature sets (at which point we would almost certainly want 307 * to set the feature bits to correspond to the feature minimum) this 308 * value may be altered. 309 */ 310 cpuid_execpass(cpu[0], CPUID_PASS_BASIC, x86_featureset); 311 312 #if !defined(__xpv) 313 if ((get_hwenv() & HW_XEN_HVM) != 0) 314 xen_hvm_init(); 315 316 /* 317 * Before we do anything with the TSCs, we need to work around 318 * Intel erratum BT81. On some CPUs, warm reset does not 319 * clear the TSC. If we are on such a CPU, we will clear TSC ourselves 320 * here. Other CPUs will clear it when we boot them later, and the 321 * resulting skew will be handled by tsc_sync_master()/_slave(); 322 * note that such skew already exists and has to be handled anyway. 323 * 324 * We do this only on metal. This same problem can occur with a 325 * hypervisor that does not happen to virtualise a TSC that starts from 326 * zero, regardless of CPU type; however, we do not expect hypervisors 327 * that do not virtualise TSC that way to handle writes to TSC 328 * correctly, either. 329 */ 330 if (get_hwenv() == HW_NATIVE && 331 cpuid_getvendor(CPU) == X86_VENDOR_Intel && 332 cpuid_getfamily(CPU) == 6 && 333 (cpuid_getmodel(CPU) == 0x2d || cpuid_getmodel(CPU) == 0x3e) && 334 is_x86_feature(x86_featureset, X86FSET_TSC)) { 335 (void) wrmsr(REG_TSC, 0UL); 336 } 337 338 /* 339 * Patch the tsc_read routine with appropriate set of instructions, 340 * depending on the processor family and architecure, to read the 341 * time-stamp counter while ensuring no out-of-order execution. 342 * Patch it while the kernel text is still writable. 343 * 344 * The Xen hypervisor does not correctly report whether rdtscp is 345 * supported or not, so we must assume that it is not. 346 */ 347 if ((get_hwenv() & HW_XEN_HVM) == 0 && 348 is_x86_feature(x86_featureset, X86FSET_TSCP)) { 349 patch_tsc_read(TSC_TSCP); 350 } else if (is_x86_feature(x86_featureset, X86FSET_LFENCE_SER)) { 351 ASSERT(is_x86_feature(x86_featureset, X86FSET_SSE2)); 352 patch_tsc_read(TSC_RDTSC_LFENCE); 353 } 354 355 #endif /* !__xpv */ 356 357 358 #if !defined(__xpv) 359 patch_memops(cpuid_getvendor(CPU)); 360 #endif /* !__xpv */ 361 362 #if !defined(__xpv) 363 /* XXPV what, if anything, should be dorked with here under xen? */ 364 365 /* 366 * While we're thinking about the TSC, let's set up %cr4 so that 367 * userland can issue rdtsc, and initialize the TSC_AUX value 368 * (the cpuid) for the rdtscp instruction on appropriately 369 * capable hardware. 370 */ 371 if (is_x86_feature(x86_featureset, X86FSET_TSC)) 372 setcr4(getcr4() & ~CR4_TSD); 373 374 if (is_x86_feature(x86_featureset, X86FSET_TSCP)) 375 (void) wrmsr(MSR_AMD_TSCAUX, 0); 376 377 /* 378 * Let's get the other %cr4 stuff while we're here. Note, we defer 379 * enabling CR4_SMAP until startup_end(); however, that's importantly 380 * before we start other CPUs. That ensures that it will be synced out 381 * to other CPUs. 382 */ 383 if (is_x86_feature(x86_featureset, X86FSET_DE)) 384 setcr4(getcr4() | CR4_DE); 385 386 if (is_x86_feature(x86_featureset, X86FSET_SMEP)) 387 setcr4(getcr4() | CR4_SMEP); 388 #endif /* __xpv */ 389 390 391 /* 392 * Initialize thread/cpu microstate accounting 393 */ 394 init_mstate(&t0, LMS_SYSTEM); 395 init_cpu_mstate(CPU, CMS_SYSTEM); 396 397 /* 398 * Initialize lists of available and active CPUs. 399 */ 400 cpu_list_init(CPU); 401 402 pg_cpu_bootstrap(CPU); 403 404 /* 405 * Now that we have taken over the GDT, IDT and have initialized 406 * active CPU list it's time to inform kmdb if present. 407 */ 408 if (boothowto & RB_DEBUG) 409 kdi_idt_sync(); 410 411 if (BOP_GETPROPLEN(bootops, "efi-systab") < 0) { 412 /* 413 * In BIOS system, explicitly set console to text mode (0x3) 414 * if this is a boot post Fast Reboot, and the console is set 415 * to CONS_SCREEN_TEXT. 416 */ 417 if (post_fastreboot && 418 boot_console_type(NULL) == CONS_SCREEN_TEXT) { 419 set_console_mode(0x3); 420 } 421 } 422 423 /* 424 * If requested (boot -d) drop into kmdb. 425 * 426 * This must be done after cpu_list_init() on the 64-bit kernel 427 * since taking a trap requires that we re-compute gsbase based 428 * on the cpu list. 429 */ 430 if (boothowto & RB_DEBUGENTER) 431 kmdb_enter(); 432 433 cpu_vm_data_init(CPU); 434 435 rp->r_fp = 0; /* terminate kernel stack traces! */ 436 437 prom_init("kernel", (void *)NULL); 438 439 /* User-set option overrides firmware value. */ 440 if (bootprop_getval(PLAT_DR_OPTIONS_NAME, &prop_value) == 0) { 441 plat_dr_options = (uint64_t)prop_value; 442 } 443 #if defined(__xpv) 444 /* No support of DR operations on xpv */ 445 plat_dr_options = 0; 446 #else /* __xpv */ 447 /* Flag PLAT_DR_FEATURE_ENABLED should only be set by DR driver. */ 448 plat_dr_options &= ~PLAT_DR_FEATURE_ENABLED; 449 #endif /* __xpv */ 450 451 /* 452 * Get value of "plat_dr_physmax" boot option. 453 * It overrides values calculated from MSCT or SRAT table. 454 */ 455 if (bootprop_getval(PLAT_DR_PHYSMAX_NAME, &prop_value) == 0) { 456 plat_dr_physmax = ((uint64_t)prop_value) >> PAGESHIFT; 457 } 458 459 /* Get value of boot_ncpus. */ 460 if (bootprop_getval(BOOT_NCPUS_NAME, &prop_value) != 0) { 461 boot_ncpus = NCPU; 462 } else { 463 boot_ncpus = (int)prop_value; 464 if (boot_ncpus <= 0 || boot_ncpus > NCPU) 465 boot_ncpus = NCPU; 466 } 467 468 /* 469 * Set max_ncpus and boot_max_ncpus to boot_ncpus if platform doesn't 470 * support CPU DR operations. 471 */ 472 if (plat_dr_support_cpu() == 0) { 473 max_ncpus = boot_max_ncpus = boot_ncpus; 474 } else { 475 if (bootprop_getval(PLAT_MAX_NCPUS_NAME, &prop_value) != 0) { 476 max_ncpus = NCPU; 477 } else { 478 max_ncpus = (int)prop_value; 479 if (max_ncpus <= 0 || max_ncpus > NCPU) { 480 max_ncpus = NCPU; 481 } 482 if (boot_ncpus > max_ncpus) { 483 boot_ncpus = max_ncpus; 484 } 485 } 486 487 if (bootprop_getval(BOOT_MAX_NCPUS_NAME, &prop_value) != 0) { 488 boot_max_ncpus = boot_ncpus; 489 } else { 490 boot_max_ncpus = (int)prop_value; 491 if (boot_max_ncpus <= 0 || boot_max_ncpus > NCPU) { 492 boot_max_ncpus = boot_ncpus; 493 } else if (boot_max_ncpus > max_ncpus) { 494 boot_max_ncpus = max_ncpus; 495 } 496 } 497 } 498 499 /* 500 * Initialize the lgrp framework 501 */ 502 lgrp_init(LGRP_INIT_STAGE1); 503 504 if (boothowto & RB_HALT) { 505 prom_printf("unix: kernel halted by -h flag\n"); 506 prom_enter_mon(); 507 } 508 509 ASSERT_STACK_ALIGNED(); 510 511 if (workaround_errata(CPU) != 0) 512 panic("critical workaround(s) missing for boot cpu"); 513 } 514 515 516 void 517 mach_modpath(char *path, const char *filename) 518 { 519 /* 520 * Construct the directory path from the filename. 521 */ 522 523 int len; 524 char *p; 525 const char isastr[] = "/amd64"; 526 size_t isalen = strlen(isastr); 527 528 len = strlen(SYSTEM_BOOT_PATH "/kernel"); 529 (void) strcpy(path, SYSTEM_BOOT_PATH "/kernel "); 530 path += len + 1; 531 532 if ((p = strrchr(filename, '/')) == NULL) 533 return; 534 535 while (p > filename && *(p - 1) == '/') 536 p--; /* remove trailing '/' characters */ 537 if (p == filename) 538 p++; /* so "/" -is- the modpath in this case */ 539 540 /* 541 * Remove optional isa-dependent directory name - the module 542 * subsystem will put this back again (!) 543 */ 544 len = p - filename; 545 if (len > isalen && 546 strncmp(&filename[len - isalen], isastr, isalen) == 0) 547 p -= isalen; 548 549 /* 550 * "/platform/mumblefrotz" + " " + MOD_DEFPATH 551 */ 552 len += (p - filename) + 1 + strlen(MOD_DEFPATH) + 1; 553 (void) strncpy(path, filename, p - filename); 554 } 555