1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2012 Gary Mills 23 * 24 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved. 25 * Copyright (c) 2011 by Delphix. All rights reserved. 26 * Copyright 2019 Joyent, Inc. 27 * Copyright 2020 Oxide Computer Company 28 */ 29 /* 30 * Copyright (c) 2010, Intel Corporation. 31 * All rights reserved. 32 */ 33 34 #include <sys/types.h> 35 #include <sys/sysmacros.h> 36 #include <sys/disp.h> 37 #include <sys/promif.h> 38 #include <sys/clock.h> 39 #include <sys/cpuvar.h> 40 #include <sys/stack.h> 41 #include <vm/as.h> 42 #include <vm/hat.h> 43 #include <sys/reboot.h> 44 #include <sys/avintr.h> 45 #include <sys/vtrace.h> 46 #include <sys/proc.h> 47 #include <sys/thread.h> 48 #include <sys/cpupart.h> 49 #include <sys/pset.h> 50 #include <sys/copyops.h> 51 #include <sys/pg.h> 52 #include <sys/disp.h> 53 #include <sys/debug.h> 54 #include <sys/sunddi.h> 55 #include <sys/x86_archext.h> 56 #include <sys/privregs.h> 57 #include <sys/machsystm.h> 58 #include <sys/ontrap.h> 59 #include <sys/bootconf.h> 60 #include <sys/boot_console.h> 61 #include <sys/kdi_machimpl.h> 62 #include <sys/archsystm.h> 63 #include <sys/promif.h> 64 #include <sys/pci_cfgspace.h> 65 #include <sys/apic.h> 66 #include <sys/apic_common.h> 67 #include <sys/bootvfs.h> 68 #include <sys/tsc.h> 69 #include <sys/smt.h> 70 #ifdef __xpv 71 #include <sys/hypervisor.h> 72 #else 73 #include <sys/xpv_support.h> 74 #endif 75 76 /* 77 * some globals for patching the result of cpuid 78 * to solve problems w/ creative cpu vendors 79 */ 80 81 extern uint32_t cpuid_feature_ecx_include; 82 extern uint32_t cpuid_feature_ecx_exclude; 83 extern uint32_t cpuid_feature_edx_include; 84 extern uint32_t cpuid_feature_edx_exclude; 85 86 nmi_action_t nmi_action = NMI_ACTION_UNSET; 87 88 /* 89 * Set console mode 90 */ 91 static void 92 set_console_mode(uint8_t val) 93 { 94 struct bop_regs rp = {0}; 95 96 rp.eax.byte.ah = 0x0; 97 rp.eax.byte.al = val; 98 rp.ebx.word.bx = 0x0; 99 100 BOP_DOINT(bootops, 0x10, &rp); 101 } 102 103 104 /* 105 * Setup routine called right before main(). Interposing this function 106 * before main() allows us to call it in a machine-independent fashion. 107 */ 108 void 109 mlsetup(struct regs *rp) 110 { 111 u_longlong_t prop_value; 112 char prop_str[BP_MAX_STRLEN]; 113 extern struct classfuncs sys_classfuncs; 114 extern disp_t cpu0_disp; 115 extern char t0stack[]; 116 extern int post_fastreboot; 117 extern uint64_t plat_dr_options; 118 119 ASSERT_STACK_ALIGNED(); 120 121 /* 122 * initialize cpu_self 123 */ 124 cpu[0]->cpu_self = cpu[0]; 125 126 #if defined(__xpv) 127 /* 128 * Point at the hypervisor's virtual cpu structure 129 */ 130 cpu[0]->cpu_m.mcpu_vcpu_info = &HYPERVISOR_shared_info->vcpu_info[0]; 131 #endif 132 133 /* 134 * check if we've got special bits to clear or set 135 * when checking cpu features 136 */ 137 138 if (bootprop_getval("cpuid_feature_ecx_include", &prop_value) != 0) 139 cpuid_feature_ecx_include = 0; 140 else 141 cpuid_feature_ecx_include = (uint32_t)prop_value; 142 143 if (bootprop_getval("cpuid_feature_ecx_exclude", &prop_value) != 0) 144 cpuid_feature_ecx_exclude = 0; 145 else 146 cpuid_feature_ecx_exclude = (uint32_t)prop_value; 147 148 if (bootprop_getval("cpuid_feature_edx_include", &prop_value) != 0) 149 cpuid_feature_edx_include = 0; 150 else 151 cpuid_feature_edx_include = (uint32_t)prop_value; 152 153 if (bootprop_getval("cpuid_feature_edx_exclude", &prop_value) != 0) 154 cpuid_feature_edx_exclude = 0; 155 else 156 cpuid_feature_edx_exclude = (uint32_t)prop_value; 157 158 #if !defined(__xpv) 159 if (bootprop_getstr("nmi", prop_str, sizeof (prop_str)) == 0) { 160 if (strcmp(prop_str, "ignore") == 0) { 161 nmi_action = NMI_ACTION_IGNORE; 162 } else if (strcmp(prop_str, "panic") == 0) { 163 nmi_action = NMI_ACTION_PANIC; 164 } else if (strcmp(prop_str, "kmdb") == 0) { 165 nmi_action = NMI_ACTION_KMDB; 166 } else { 167 prom_printf("unix: ignoring unknown nmi=%s\n", 168 prop_str); 169 } 170 } 171 172 /* 173 * Check to see if KPTI has been explicitly enabled or disabled. 174 * We have to check this before init_desctbls(). 175 */ 176 if (bootprop_getval("kpti", &prop_value) == 0) { 177 kpti_enable = (uint64_t)(prop_value == 1); 178 prom_printf("unix: forcing kpti to %s due to boot argument\n", 179 (kpti_enable == 1) ? "ON" : "OFF"); 180 } else { 181 kpti_enable = 1; 182 } 183 184 if (bootprop_getval("pcid", &prop_value) == 0 && prop_value == 0) { 185 prom_printf("unix: forcing pcid to OFF due to boot argument\n"); 186 x86_use_pcid = 0; 187 } else if (kpti_enable != 1) { 188 x86_use_pcid = 0; 189 } 190 191 /* 192 * While we don't need to check this until later, we might as well do it 193 * here. 194 */ 195 if (bootprop_getstr("smt_enabled", prop_str, sizeof (prop_str)) == 0) { 196 if (strcasecmp(prop_str, "false") == 0 || 197 strcmp(prop_str, "0") == 0) 198 smt_boot_disable = 1; 199 } 200 201 #endif 202 203 /* 204 * Initialize idt0, gdt0, ldt0_default, ktss0 and dftss. 205 */ 206 init_desctbls(); 207 208 /* 209 * lgrp_init() and possibly cpuid_pass1() need PCI config 210 * space access 211 */ 212 #if defined(__xpv) 213 if (DOMAIN_IS_INITDOMAIN(xen_info)) 214 pci_cfgspace_init(); 215 #else 216 pci_cfgspace_init(); 217 /* 218 * Initialize the platform type from CPU 0 to ensure that 219 * determine_platform() is only ever called once. 220 */ 221 determine_platform(); 222 #endif 223 224 /* 225 * The first lightweight pass (pass0) through the cpuid data 226 * was done in locore before mlsetup was called. Do the next 227 * pass in C code. 228 * 229 * The x86_featureset is initialized here based on the capabilities 230 * of the boot CPU. Note that if we choose to support CPUs that have 231 * different feature sets (at which point we would almost certainly 232 * want to set the feature bits to correspond to the feature 233 * minimum) this value may be altered. 234 */ 235 cpuid_pass1(cpu[0], x86_featureset); 236 237 #if !defined(__xpv) 238 if ((get_hwenv() & HW_XEN_HVM) != 0) 239 xen_hvm_init(); 240 241 /* 242 * Before we do anything with the TSCs, we need to work around 243 * Intel erratum BT81. On some CPUs, warm reset does not 244 * clear the TSC. If we are on such a CPU, we will clear TSC ourselves 245 * here. Other CPUs will clear it when we boot them later, and the 246 * resulting skew will be handled by tsc_sync_master()/_slave(); 247 * note that such skew already exists and has to be handled anyway. 248 * 249 * We do this only on metal. This same problem can occur with a 250 * hypervisor that does not happen to virtualise a TSC that starts from 251 * zero, regardless of CPU type; however, we do not expect hypervisors 252 * that do not virtualise TSC that way to handle writes to TSC 253 * correctly, either. 254 */ 255 if (get_hwenv() == HW_NATIVE && 256 cpuid_getvendor(CPU) == X86_VENDOR_Intel && 257 cpuid_getfamily(CPU) == 6 && 258 (cpuid_getmodel(CPU) == 0x2d || cpuid_getmodel(CPU) == 0x3e) && 259 is_x86_feature(x86_featureset, X86FSET_TSC)) { 260 (void) wrmsr(REG_TSC, 0UL); 261 } 262 263 /* 264 * Patch the tsc_read routine with appropriate set of instructions, 265 * depending on the processor family and architecure, to read the 266 * time-stamp counter while ensuring no out-of-order execution. 267 * Patch it while the kernel text is still writable. 268 * 269 * The Xen hypervisor does not correctly report whether rdtscp is 270 * supported or not, so we must assume that it is not. 271 */ 272 if ((get_hwenv() & HW_XEN_HVM) == 0 && 273 is_x86_feature(x86_featureset, X86FSET_TSCP)) { 274 patch_tsc_read(TSC_TSCP); 275 } else if (is_x86_feature(x86_featureset, X86FSET_LFENCE_SER)) { 276 ASSERT(is_x86_feature(x86_featureset, X86FSET_SSE2)); 277 patch_tsc_read(TSC_RDTSC_LFENCE); 278 } 279 280 #endif /* !__xpv */ 281 282 #if defined(__i386) && !defined(__xpv) 283 /* 284 * Some i386 processors do not implement the rdtsc instruction, 285 * or at least they do not implement it correctly. Patch them to 286 * return 0. 287 */ 288 if (!is_x86_feature(x86_featureset, X86FSET_TSC)) 289 patch_tsc_read(TSC_NONE); 290 #endif /* __i386 && !__xpv */ 291 292 #if defined(__amd64) && !defined(__xpv) 293 patch_memops(cpuid_getvendor(CPU)); 294 #endif /* __amd64 && !__xpv */ 295 296 #if !defined(__xpv) 297 /* XXPV what, if anything, should be dorked with here under xen? */ 298 299 /* 300 * While we're thinking about the TSC, let's set up %cr4 so that 301 * userland can issue rdtsc, and initialize the TSC_AUX value 302 * (the cpuid) for the rdtscp instruction on appropriately 303 * capable hardware. 304 */ 305 if (is_x86_feature(x86_featureset, X86FSET_TSC)) 306 setcr4(getcr4() & ~CR4_TSD); 307 308 if (is_x86_feature(x86_featureset, X86FSET_TSCP)) 309 (void) wrmsr(MSR_AMD_TSCAUX, 0); 310 311 /* 312 * Let's get the other %cr4 stuff while we're here. Note, we defer 313 * enabling CR4_SMAP until startup_end(); however, that's importantly 314 * before we start other CPUs. That ensures that it will be synced out 315 * to other CPUs. 316 */ 317 if (is_x86_feature(x86_featureset, X86FSET_DE)) 318 setcr4(getcr4() | CR4_DE); 319 320 if (is_x86_feature(x86_featureset, X86FSET_SMEP)) 321 setcr4(getcr4() | CR4_SMEP); 322 #endif /* __xpv */ 323 324 /* 325 * initialize t0 326 */ 327 t0.t_stk = (caddr_t)rp - MINFRAME; 328 t0.t_stkbase = t0stack; 329 t0.t_pri = maxclsyspri - 3; 330 t0.t_schedflag = TS_LOAD | TS_DONT_SWAP; 331 t0.t_procp = &p0; 332 t0.t_plockp = &p0lock.pl_lock; 333 t0.t_lwp = &lwp0; 334 t0.t_forw = &t0; 335 t0.t_back = &t0; 336 t0.t_next = &t0; 337 t0.t_prev = &t0; 338 t0.t_cpu = cpu[0]; 339 t0.t_disp_queue = &cpu0_disp; 340 t0.t_bind_cpu = PBIND_NONE; 341 t0.t_bind_pset = PS_NONE; 342 t0.t_bindflag = (uchar_t)default_binding_mode; 343 t0.t_cpupart = &cp_default; 344 t0.t_clfuncs = &sys_classfuncs.thread; 345 t0.t_copyops = NULL; 346 THREAD_ONPROC(&t0, CPU); 347 348 lwp0.lwp_thread = &t0; 349 lwp0.lwp_regs = (void *)rp; 350 lwp0.lwp_procp = &p0; 351 t0.t_tid = p0.p_lwpcnt = p0.p_lwprcnt = p0.p_lwpid = 1; 352 353 p0.p_exec = NULL; 354 p0.p_stat = SRUN; 355 p0.p_flag = SSYS; 356 p0.p_tlist = &t0; 357 p0.p_stksize = 2*PAGESIZE; 358 p0.p_stkpageszc = 0; 359 p0.p_as = &kas; 360 p0.p_lockp = &p0lock; 361 p0.p_brkpageszc = 0; 362 p0.p_t1_lgrpid = LGRP_NONE; 363 p0.p_tr_lgrpid = LGRP_NONE; 364 psecflags_default(&p0.p_secflags); 365 366 sigorset(&p0.p_ignore, &ignoredefault); 367 368 CPU->cpu_thread = &t0; 369 bzero(&cpu0_disp, sizeof (disp_t)); 370 CPU->cpu_disp = &cpu0_disp; 371 CPU->cpu_disp->disp_cpu = CPU; 372 CPU->cpu_dispthread = &t0; 373 CPU->cpu_idle_thread = &t0; 374 CPU->cpu_flags = CPU_READY | CPU_RUNNING | CPU_EXISTS | CPU_ENABLE; 375 CPU->cpu_dispatch_pri = t0.t_pri; 376 377 CPU->cpu_id = 0; 378 379 CPU->cpu_pri = 12; /* initial PIL for the boot CPU */ 380 381 /* 382 * Initialize thread/cpu microstate accounting 383 */ 384 init_mstate(&t0, LMS_SYSTEM); 385 init_cpu_mstate(CPU, CMS_SYSTEM); 386 387 /* 388 * Initialize lists of available and active CPUs. 389 */ 390 cpu_list_init(CPU); 391 392 pg_cpu_bootstrap(CPU); 393 394 /* 395 * Now that we have taken over the GDT, IDT and have initialized 396 * active CPU list it's time to inform kmdb if present. 397 */ 398 if (boothowto & RB_DEBUG) 399 kdi_idt_sync(); 400 401 if (BOP_GETPROPLEN(bootops, "efi-systab") < 0) { 402 /* 403 * In BIOS system, explicitly set console to text mode (0x3) 404 * if this is a boot post Fast Reboot, and the console is set 405 * to CONS_SCREEN_TEXT. 406 */ 407 if (post_fastreboot && 408 boot_console_type(NULL) == CONS_SCREEN_TEXT) { 409 set_console_mode(0x3); 410 } 411 } 412 413 /* 414 * If requested (boot -d) drop into kmdb. 415 * 416 * This must be done after cpu_list_init() on the 64-bit kernel 417 * since taking a trap requires that we re-compute gsbase based 418 * on the cpu list. 419 */ 420 if (boothowto & RB_DEBUGENTER) 421 kmdb_enter(); 422 423 cpu_vm_data_init(CPU); 424 425 rp->r_fp = 0; /* terminate kernel stack traces! */ 426 427 prom_init("kernel", (void *)NULL); 428 429 /* User-set option overrides firmware value. */ 430 if (bootprop_getval(PLAT_DR_OPTIONS_NAME, &prop_value) == 0) { 431 plat_dr_options = (uint64_t)prop_value; 432 } 433 #if defined(__xpv) 434 /* No support of DR operations on xpv */ 435 plat_dr_options = 0; 436 #else /* __xpv */ 437 /* Flag PLAT_DR_FEATURE_ENABLED should only be set by DR driver. */ 438 plat_dr_options &= ~PLAT_DR_FEATURE_ENABLED; 439 #ifndef __amd64 440 /* Only enable CPU/memory DR on 64 bits kernel. */ 441 plat_dr_options &= ~PLAT_DR_FEATURE_MEMORY; 442 plat_dr_options &= ~PLAT_DR_FEATURE_CPU; 443 #endif /* __amd64 */ 444 #endif /* __xpv */ 445 446 /* 447 * Get value of "plat_dr_physmax" boot option. 448 * It overrides values calculated from MSCT or SRAT table. 449 */ 450 if (bootprop_getval(PLAT_DR_PHYSMAX_NAME, &prop_value) == 0) { 451 plat_dr_physmax = ((uint64_t)prop_value) >> PAGESHIFT; 452 } 453 454 /* Get value of boot_ncpus. */ 455 if (bootprop_getval(BOOT_NCPUS_NAME, &prop_value) != 0) { 456 boot_ncpus = NCPU; 457 } else { 458 boot_ncpus = (int)prop_value; 459 if (boot_ncpus <= 0 || boot_ncpus > NCPU) 460 boot_ncpus = NCPU; 461 } 462 463 /* 464 * Set max_ncpus and boot_max_ncpus to boot_ncpus if platform doesn't 465 * support CPU DR operations. 466 */ 467 if (plat_dr_support_cpu() == 0) { 468 max_ncpus = boot_max_ncpus = boot_ncpus; 469 } else { 470 if (bootprop_getval(PLAT_MAX_NCPUS_NAME, &prop_value) != 0) { 471 max_ncpus = NCPU; 472 } else { 473 max_ncpus = (int)prop_value; 474 if (max_ncpus <= 0 || max_ncpus > NCPU) { 475 max_ncpus = NCPU; 476 } 477 if (boot_ncpus > max_ncpus) { 478 boot_ncpus = max_ncpus; 479 } 480 } 481 482 if (bootprop_getval(BOOT_MAX_NCPUS_NAME, &prop_value) != 0) { 483 boot_max_ncpus = boot_ncpus; 484 } else { 485 boot_max_ncpus = (int)prop_value; 486 if (boot_max_ncpus <= 0 || boot_max_ncpus > NCPU) { 487 boot_max_ncpus = boot_ncpus; 488 } else if (boot_max_ncpus > max_ncpus) { 489 boot_max_ncpus = max_ncpus; 490 } 491 } 492 } 493 494 /* 495 * Initialize the lgrp framework 496 */ 497 lgrp_init(LGRP_INIT_STAGE1); 498 499 if (boothowto & RB_HALT) { 500 prom_printf("unix: kernel halted by -h flag\n"); 501 prom_enter_mon(); 502 } 503 504 ASSERT_STACK_ALIGNED(); 505 506 /* 507 * Fill out cpu_ucode_info. Update microcode if necessary. 508 */ 509 ucode_check(CPU); 510 cpuid_pass_ucode(CPU, x86_featureset); 511 512 if (workaround_errata(CPU) != 0) 513 panic("critical workaround(s) missing for boot cpu"); 514 } 515 516 517 void 518 mach_modpath(char *path, const char *filename) 519 { 520 /* 521 * Construct the directory path from the filename. 522 */ 523 524 int len; 525 char *p; 526 const char isastr[] = "/amd64"; 527 size_t isalen = strlen(isastr); 528 529 len = strlen(SYSTEM_BOOT_PATH "/kernel"); 530 (void) strcpy(path, SYSTEM_BOOT_PATH "/kernel "); 531 path += len + 1; 532 533 if ((p = strrchr(filename, '/')) == NULL) 534 return; 535 536 while (p > filename && *(p - 1) == '/') 537 p--; /* remove trailing '/' characters */ 538 if (p == filename) 539 p++; /* so "/" -is- the modpath in this case */ 540 541 /* 542 * Remove optional isa-dependent directory name - the module 543 * subsystem will put this back again (!) 544 */ 545 len = p - filename; 546 if (len > isalen && 547 strncmp(&filename[len - isalen], isastr, isalen) == 0) 548 p -= isalen; 549 550 /* 551 * "/platform/mumblefrotz" + " " + MOD_DEFPATH 552 */ 553 len += (p - filename) + 1 + strlen(MOD_DEFPATH) + 1; 554 (void) strncpy(path, filename, p - filename); 555 } 556