1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/cpuvar.h> 27 #include <sys/psm.h> 28 #include <sys/archsystm.h> 29 #include <sys/apic.h> 30 #include <sys/sunddi.h> 31 #include <sys/ddi_impldefs.h> 32 #include <sys/mach_intr.h> 33 #include <sys/sysmacros.h> 34 #include <sys/trap.h> 35 #include <sys/x86_archext.h> 36 #include <sys/privregs.h> 37 #include <sys/psm_common.h> 38 39 /* Function prototypes of local apic and x2apic */ 40 static uint64_t local_apic_read(uint32_t reg); 41 static void local_apic_write(uint32_t reg, uint64_t value); 42 static int get_local_apic_pri(void); 43 static void local_apic_write_task_reg(uint64_t value); 44 static void local_apic_write_int_cmd(uint32_t cpu_id, uint32_t cmd1); 45 static uint64_t local_x2apic_read(uint32_t msr); 46 static void local_x2apic_write(uint32_t msr, uint64_t value); 47 static int get_local_x2apic_pri(void); 48 static void local_x2apic_write_task_reg(uint64_t value); 49 static void local_x2apic_write_int_cmd(uint32_t cpu_id, uint32_t cmd1); 50 51 /* 52 * According to the x2APIC specification: 53 * 54 * xAPIC global enable x2APIC enable Description 55 * (IA32_APIC_BASE[11]) (IA32_APIC_BASE[10]) 56 * ----------------------------------------------------------- 57 * 0 0 APIC is disabled 58 * 0 1 Invalid 59 * 1 0 APIC is enabled in xAPIC mode 60 * 1 1 APIC is enabled in x2APIC mode 61 * ----------------------------------------------------------- 62 */ 63 int x2apic_enable = 1; 64 int apic_mode = LOCAL_APIC; /* Default mode is Local APIC */ 65 66 /* Uses MMIO (Memory Mapped IO) */ 67 static apic_reg_ops_t local_apic_regs_ops = { 68 local_apic_read, 69 local_apic_write, 70 get_local_apic_pri, 71 local_apic_write_task_reg, 72 local_apic_write_int_cmd, 73 apic_send_EOI, 74 }; 75 76 /* x2APIC : Uses RDMSR/WRMSR instructions to access APIC registers */ 77 static apic_reg_ops_t x2apic_regs_ops = { 78 local_x2apic_read, 79 local_x2apic_write, 80 get_local_x2apic_pri, 81 local_x2apic_write_task_reg, 82 local_x2apic_write_int_cmd, 83 apic_send_EOI, 84 }; 85 86 87 /* The default ops is local APIC (Memory Mapped IO) */ 88 apic_reg_ops_t *apic_reg_ops = &local_apic_regs_ops; 89 90 /* 91 * APIC register ops related data sturctures and functions. 92 */ 93 int apic_direct_EOI = 0; /* Directed EOI Support */ 94 95 void apic_send_EOI(); 96 void apic_send_directed_EOI(uint32_t irq); 97 98 #define X2APIC_CPUID_BIT 21 99 #define X2APIC_ENABLE_BIT 10 100 101 /* 102 * Local APIC Implementation 103 */ 104 static uint64_t 105 local_apic_read(uint32_t reg) 106 { 107 return ((uint32_t)apicadr[reg]); 108 } 109 110 static void 111 local_apic_write(uint32_t reg, uint64_t value) 112 { 113 apicadr[reg] = (uint32_t)value; 114 } 115 116 static int 117 get_local_apic_pri(void) 118 { 119 #if defined(__amd64) 120 return ((int)getcr8()); 121 #else 122 return (apicadr[APIC_TASK_REG]); 123 #endif 124 } 125 126 static void 127 local_apic_write_task_reg(uint64_t value) 128 { 129 #if defined(__amd64) 130 setcr8((ulong_t)(value >> APIC_IPL_SHIFT)); 131 #else 132 apicadr[APIC_TASK_REG] = (uint32_t)value; 133 #endif 134 } 135 136 static void 137 local_apic_write_int_cmd(uint32_t cpu_id, uint32_t cmd1) 138 { 139 apicadr[APIC_INT_CMD2] = cpu_id << APIC_ICR_ID_BIT_OFFSET; 140 apicadr[APIC_INT_CMD1] = cmd1; 141 } 142 143 /* 144 * x2APIC Implementation. 145 */ 146 static uint64_t 147 local_x2apic_read(uint32_t msr) 148 { 149 uint64_t i; 150 151 i = (uint64_t)(rdmsr(REG_X2APIC_BASE_MSR + (msr >> 2)) & 0xffffffff); 152 return (i); 153 } 154 155 static void 156 local_x2apic_write(uint32_t msr, uint64_t value) 157 { 158 uint64_t tmp; 159 160 if (msr != APIC_EOI_REG) { 161 tmp = rdmsr(REG_X2APIC_BASE_MSR + (msr >> 2)); 162 tmp = (tmp & 0xffffffff00000000) | value; 163 } else { 164 tmp = 0; 165 } 166 167 wrmsr((REG_X2APIC_BASE_MSR + (msr >> 2)), tmp); 168 } 169 170 static int 171 get_local_x2apic_pri(void) 172 { 173 return (rdmsr(REG_X2APIC_BASE_MSR + (APIC_TASK_REG >> 2))); 174 } 175 176 static void 177 local_x2apic_write_task_reg(uint64_t value) 178 { 179 X2APIC_WRITE(APIC_TASK_REG, value); 180 } 181 182 static void 183 local_x2apic_write_int_cmd(uint32_t cpu_id, uint32_t cmd1) 184 { 185 wrmsr((REG_X2APIC_BASE_MSR + (APIC_INT_CMD1 >> 2)), 186 (((uint64_t)cpu_id << 32) | cmd1)); 187 } 188 189 /*ARGSUSED*/ 190 void 191 apic_send_EOI(uint32_t irq) 192 { 193 apic_reg_ops->apic_write(APIC_EOI_REG, 0); 194 } 195 196 void 197 apic_send_directed_EOI(uint32_t irq) 198 { 199 uchar_t ioapicindex; 200 uchar_t vector; 201 apic_irq_t *apic_irq; 202 short intr_index; 203 204 ASSERT(apic_mode == LOCAL_X2APIC); 205 206 apic_irq = apic_irq_table[irq]; 207 208 while (apic_irq) { 209 intr_index = apic_irq->airq_mps_intr_index; 210 if (intr_index == ACPI_INDEX || intr_index >= 0) { 211 ioapicindex = apic_irq->airq_ioapicindex; 212 vector = apic_irq->airq_vector; 213 ioapic_write_eoi(ioapicindex, vector); 214 } 215 apic_irq = apic_irq->airq_next; 216 } 217 } 218 219 int 220 apic_detect_x2apic(void) 221 { 222 struct cpuid_regs cp; 223 224 if (x2apic_enable == 0) 225 return (0); 226 227 cp.cp_eax = 1; 228 (void) __cpuid_insn(&cp); 229 230 return ((cp.cp_ecx & (0x1 << X2APIC_CPUID_BIT)) ? 1 : 0); 231 } 232 233 void 234 apic_enable_x2apic(void) 235 { 236 uint64_t apic_base_msr; 237 238 apic_base_msr = rdmsr(REG_APIC_BASE_MSR); 239 apic_base_msr = apic_base_msr | (0x1 << X2APIC_ENABLE_BIT); 240 241 wrmsr(REG_APIC_BASE_MSR, apic_base_msr); 242 243 /* change the mode and ops */ 244 if (apic_mode != LOCAL_X2APIC) { 245 apic_mode = LOCAL_X2APIC; 246 apic_reg_ops = &x2apic_regs_ops; 247 x2apic_update_psm(); 248 } 249 } 250 251 /* 252 * Generates an interprocessor interrupt to another CPU when x2APIC mode is 253 * enabled. 254 */ 255 void 256 x2apic_send_ipi(int cpun, int ipl) 257 { 258 int vector; 259 ulong_t flag; 260 261 ASSERT(apic_mode == LOCAL_X2APIC); 262 263 /* 264 * With X2APIC, Intel relaxed the semantics of the 265 * WRMSR instruction such that references to the X2APIC 266 * MSR registers are no longer serializing instructions. 267 * The code that initiates IPIs assumes that some sort 268 * of memory serialization occurs. The old APIC code 269 * did a write to uncachable memory mapped registers. 270 * Any reference to uncached memory is a serializing 271 * operation. To mimic those semantics here, we do an 272 * atomic operation, which translates to a LOCK OR instruction, 273 * which is serializing. 274 */ 275 atomic_or_ulong(&flag, 1); 276 277 vector = apic_resv_vector[ipl]; 278 279 flag = intr_clear(); 280 281 /* 282 * According to x2APIC specification in section '2.3.5.1' of 283 * Interrupt Command Register Semantics, the semantics of 284 * programming Interrupt Command Register to dispatch an interrupt 285 * is simplified. A single MSR write to the 64-bit ICR is required 286 * for dispatching an interrupt. Specifically with the 64-bit MSR 287 * interface to ICR, system software is not required to check the 288 * status of the delivery status bit prior to writing to the ICR 289 * to send an IPI. With the removal of the Delivery Status bit, 290 * system software no longer has a reason to read the ICR. It remains 291 * readable only to aid in debugging. 292 */ 293 #ifdef DEBUG 294 APIC_AV_PENDING_SET(); 295 #endif /* DEBUG */ 296 297 if ((cpun == psm_get_cpu_id())) 298 apic_reg_ops->apic_write(X2APIC_SELF_IPI, vector); 299 else 300 apic_reg_ops->apic_write_int_cmd( 301 apic_cpus[cpun].aci_local_id, vector); 302 303 intr_restore(flag); 304 } 305 306 307 void 308 apic_change_eoi() 309 { 310 apic_reg_ops->apic_send_eoi = apic_send_directed_EOI; 311 } 312