1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 /* 26 * Copyright (c) 2010, Intel Corporation. 27 * All rights reserved. 28 * Copyright 2018 Joyent, Inc. 29 */ 30 31 /* 32 * To understand how the pcplusmp module interacts with the interrupt subsystem 33 * read the theory statement in uts/i86pc/os/intr.c. 34 */ 35 36 /* 37 * PSMI 1.1 extensions are supported only in 2.6 and later versions. 38 * PSMI 1.2 extensions are supported only in 2.7 and later versions. 39 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10. 40 * PSMI 1.5 extensions are supported in Solaris Nevada. 41 * PSMI 1.6 extensions are supported in Solaris Nevada. 42 * PSMI 1.7 extensions are supported in Solaris Nevada. 43 */ 44 #define PSMI_1_7 45 46 #include <sys/processor.h> 47 #include <sys/time.h> 48 #include <sys/psm.h> 49 #include <sys/smp_impldefs.h> 50 #include <sys/cram.h> 51 #include <sys/acpi/acpi.h> 52 #include <sys/acpica.h> 53 #include <sys/psm_common.h> 54 #include <sys/apic.h> 55 #include <sys/pit.h> 56 #include <sys/ddi.h> 57 #include <sys/sunddi.h> 58 #include <sys/ddi_impldefs.h> 59 #include <sys/pci.h> 60 #include <sys/promif.h> 61 #include <sys/x86_archext.h> 62 #include <sys/cpc_impl.h> 63 #include <sys/uadmin.h> 64 #include <sys/panic.h> 65 #include <sys/debug.h> 66 #include <sys/archsystm.h> 67 #include <sys/trap.h> 68 #include <sys/machsystm.h> 69 #include <sys/sysmacros.h> 70 #include <sys/cpuvar.h> 71 #include <sys/rm_platter.h> 72 #include <sys/privregs.h> 73 #include <sys/note.h> 74 #include <sys/pci_intr_lib.h> 75 #include <sys/spl.h> 76 #include <sys/clock.h> 77 #include <sys/cyclic.h> 78 #include <sys/dditypes.h> 79 #include <sys/sunddi.h> 80 #include <sys/x_call.h> 81 #include <sys/reboot.h> 82 #include <sys/hpet.h> 83 #include <sys/apic_common.h> 84 #include <sys/apic_timer.h> 85 86 /* 87 * Local Function Prototypes 88 */ 89 static void apic_init_intr(void); 90 91 /* 92 * standard MP entries 93 */ 94 static int apic_probe(void); 95 static int apic_getclkirq(int ipl); 96 static void apic_init(void); 97 static void apic_picinit(void); 98 static int apic_post_cpu_start(void); 99 static int apic_intr_enter(int ipl, int *vect); 100 static void apic_setspl(int ipl); 101 static int apic_addspl(int ipl, int vector, int min_ipl, int max_ipl); 102 static int apic_delspl(int ipl, int vector, int min_ipl, int max_ipl); 103 static int apic_disable_intr(processorid_t cpun); 104 static void apic_enable_intr(processorid_t cpun); 105 static int apic_get_ipivect(int ipl, int type); 106 static void apic_post_cyclic_setup(void *arg); 107 108 #define UCHAR_MAX UINT8_MAX 109 110 /* 111 * The following vector assignments influence the value of ipltopri and 112 * vectortoipl. Note that vectors 0 - 0x1f are not used. We can program 113 * idle to 0 and IPL 0 to 0xf to differentiate idle in case 114 * we care to do so in future. Note some IPLs which are rarely used 115 * will share the vector ranges and heavily used IPLs (5 and 6) have 116 * a wide range. 117 * 118 * This array is used to initialize apic_ipls[] (in apic_init()). 119 * 120 * IPL Vector range. as passed to intr_enter 121 * 0 none. 122 * 1,2,3 0x20-0x2f 0x0-0xf 123 * 4 0x30-0x3f 0x10-0x1f 124 * 5 0x40-0x5f 0x20-0x3f 125 * 6 0x60-0x7f 0x40-0x5f 126 * 7,8,9 0x80-0x8f 0x60-0x6f 127 * 10 0x90-0x9f 0x70-0x7f 128 * 11 0xa0-0xaf 0x80-0x8f 129 * ... ... 130 * 15 0xe0-0xef 0xc0-0xcf 131 * 15 0xf0-0xff 0xd0-0xdf 132 */ 133 uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL] = { 134 3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15 135 }; 136 /* 137 * The ipl of an ISR at vector X is apic_vectortoipl[X>>4] 138 * NOTE that this is vector as passed into intr_enter which is 139 * programmed vector - 0x20 (APIC_BASE_VECT) 140 */ 141 142 uchar_t apic_ipltopri[MAXIPL + 1]; /* unix ipl to apic pri */ 143 /* The taskpri to be programmed into apic to mask given ipl */ 144 145 /* 146 * Correlation of the hardware vector to the IPL in use, initialized 147 * from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate 148 * to the IPLs in apic_vectortoipl on some systems that share interrupt lines 149 * connected to errata-stricken IOAPICs 150 */ 151 uchar_t apic_ipls[APIC_AVAIL_VECTOR]; 152 153 /* 154 * Patchable global variables. 155 */ 156 int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */ 157 int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */ 158 159 /* 160 * Local static data 161 */ 162 static struct psm_ops apic_ops = { 163 apic_probe, 164 165 apic_init, 166 apic_picinit, 167 apic_intr_enter, 168 apic_intr_exit, 169 apic_setspl, 170 apic_addspl, 171 apic_delspl, 172 apic_disable_intr, 173 apic_enable_intr, 174 (int (*)(int))NULL, /* psm_softlvl_to_irq */ 175 (void (*)(int))NULL, /* psm_set_softintr */ 176 177 apic_set_idlecpu, 178 apic_unset_idlecpu, 179 180 apic_clkinit, 181 apic_getclkirq, 182 (void (*)(void))NULL, /* psm_hrtimeinit */ 183 apic_gethrtime, 184 185 apic_get_next_processorid, 186 apic_cpu_start, 187 apic_post_cpu_start, 188 apic_shutdown, 189 apic_get_ipivect, 190 apic_send_ipi, 191 192 (int (*)(dev_info_t *, int))NULL, /* psm_translate_irq */ 193 (void (*)(int, char *))NULL, /* psm_notify_error */ 194 (void (*)(int))NULL, /* psm_notify_func */ 195 apic_timer_reprogram, 196 apic_timer_enable, 197 apic_timer_disable, 198 apic_post_cyclic_setup, 199 apic_preshutdown, 200 apic_intr_ops, /* Advanced DDI Interrupt framework */ 201 apic_state, /* save, restore apic state for S3 */ 202 apic_cpu_ops, /* CPU control interface. */ 203 204 apic_get_pir_ipivect, 205 apic_send_pir_ipi, 206 }; 207 208 struct psm_ops *psmops = &apic_ops; 209 210 static struct psm_info apic_psm_info = { 211 PSM_INFO_VER01_7, /* version */ 212 PSM_OWN_EXCLUSIVE, /* ownership */ 213 (struct psm_ops *)&apic_ops, /* operation */ 214 APIC_PCPLUSMP_NAME, /* machine name */ 215 "pcplusmp v1.4 compatible", 216 }; 217 218 static void *apic_hdlp; 219 220 /* to gather intr data and redistribute */ 221 static void apic_redistribute_compute(void); 222 223 /* 224 * This is the loadable module wrapper 225 */ 226 227 int 228 _init(void) 229 { 230 if (apic_coarse_hrtime) 231 apic_ops.psm_gethrtime = &apic_gettime; 232 return (psm_mod_init(&apic_hdlp, &apic_psm_info)); 233 } 234 235 int 236 _fini(void) 237 { 238 return (psm_mod_fini(&apic_hdlp, &apic_psm_info)); 239 } 240 241 int 242 _info(struct modinfo *modinfop) 243 { 244 return (psm_mod_info(&apic_hdlp, &apic_psm_info, modinfop)); 245 } 246 247 static int 248 apic_probe(void) 249 { 250 /* check if apix is initialized */ 251 if (apix_enable && apix_loaded()) 252 return (PSM_FAILURE); 253 254 /* 255 * Check whether x2APIC mode was activated by BIOS. We don't support 256 * that in pcplusmp as apix normally handles that. 257 */ 258 if (apic_local_mode() == LOCAL_X2APIC) 259 return (PSM_FAILURE); 260 261 /* continue using pcplusmp PSM */ 262 apix_enable = 0; 263 264 return (apic_probe_common(apic_psm_info.p_mach_idstring)); 265 } 266 267 static uchar_t 268 apic_xlate_vector_by_irq(uchar_t irq) 269 { 270 if (apic_irq_table[irq] == NULL) 271 return (0); 272 273 return (apic_irq_table[irq]->airq_vector); 274 } 275 276 void 277 apic_init(void) 278 { 279 int i; 280 int j = 1; 281 282 psm_get_ioapicid = apic_get_ioapicid; 283 psm_get_localapicid = apic_get_localapicid; 284 psm_xlate_vector_by_irq = apic_xlate_vector_by_irq; 285 286 apic_ipltopri[0] = APIC_VECTOR_PER_IPL; /* leave 0 for idle */ 287 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) { 288 if ((i < ((APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL) - 1)) && 289 (apic_vectortoipl[i + 1] == apic_vectortoipl[i])) 290 /* get to highest vector at the same ipl */ 291 continue; 292 for (; j <= apic_vectortoipl[i]; j++) { 293 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + 294 APIC_BASE_VECT; 295 } 296 } 297 for (; j < MAXIPL + 1; j++) 298 /* fill up any empty ipltopri slots */ 299 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + APIC_BASE_VECT; 300 apic_init_common(); 301 302 apic_pir_vect = apic_get_ipivect(XC_CPUPOKE_PIL, -1); 303 304 #if !defined(__amd64) 305 if (cpuid_have_cr8access(CPU)) 306 apic_have_32bit_cr8 = 1; 307 #endif 308 } 309 310 static void 311 apic_init_intr(void) 312 { 313 processorid_t cpun = psm_get_cpu_id(); 314 uint_t nlvt; 315 uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR; 316 317 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL); 318 319 ASSERT(apic_mode == LOCAL_APIC); 320 321 /* 322 * We are running APIC in MMIO mode. 323 */ 324 if (apic_flat_model) { 325 apic_reg_ops->apic_write(APIC_FORMAT_REG, APIC_FLAT_MODEL); 326 } else { 327 apic_reg_ops->apic_write(APIC_FORMAT_REG, APIC_CLUSTER_MODEL); 328 } 329 330 apic_reg_ops->apic_write(APIC_DEST_REG, AV_HIGH_ORDER >> cpun); 331 332 if (apic_directed_EOI_supported()) { 333 /* 334 * Setting the 12th bit in the Spurious Interrupt Vector 335 * Register suppresses broadcast EOIs generated by the local 336 * APIC. The suppression of broadcast EOIs happens only when 337 * interrupts are level-triggered. 338 */ 339 svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI; 340 } 341 342 /* need to enable APIC before unmasking NMI */ 343 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr); 344 345 /* 346 * Presence of an invalid vector with delivery mode AV_FIXED can 347 * cause an error interrupt, even if the entry is masked...so 348 * write a valid vector to LVT entries along with the mask bit 349 */ 350 351 /* All APICs have timer and LINT0/1 */ 352 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ); 353 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ); 354 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */ 355 356 /* 357 * On integrated APICs, the number of LVT entries is 358 * 'Max LVT entry' + 1; on 82489DX's (non-integrated 359 * APICs), nlvt is "3" (LINT0, LINT1, and timer) 360 */ 361 362 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) { 363 nlvt = 3; 364 } else { 365 nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) & 366 0xFF) + 1; 367 } 368 369 if (nlvt >= 5) { 370 /* Enable performance counter overflow interrupt */ 371 372 if (!is_x86_feature(x86_featureset, X86FSET_MSR)) 373 apic_enable_cpcovf_intr = 0; 374 if (apic_enable_cpcovf_intr) { 375 if (apic_cpcovf_vect == 0) { 376 int ipl = APIC_PCINT_IPL; 377 int irq = apic_get_ipivect(ipl, -1); 378 379 ASSERT(irq != -1); 380 apic_cpcovf_vect = 381 apic_irq_table[irq]->airq_vector; 382 ASSERT(apic_cpcovf_vect); 383 (void) add_avintr(NULL, ipl, 384 (avfunc)kcpc_hw_overflow_intr, 385 "apic pcint", irq, NULL, NULL, NULL, NULL); 386 kcpc_hw_overflow_intr_installed = 1; 387 kcpc_hw_enable_cpc_intr = 388 apic_cpcovf_mask_clear; 389 } 390 apic_reg_ops->apic_write(APIC_PCINT_VECT, 391 apic_cpcovf_vect); 392 } 393 } 394 395 if (nlvt >= 6) { 396 /* Only mask TM intr if the BIOS apparently doesn't use it */ 397 398 uint32_t lvtval; 399 400 lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT); 401 if (((lvtval & AV_MASK) == AV_MASK) || 402 ((lvtval & AV_DELIV_MODE) != AV_SMI)) { 403 apic_reg_ops->apic_write(APIC_THERM_VECT, 404 AV_MASK|APIC_RESV_IRQ); 405 } 406 } 407 408 /* Enable error interrupt */ 409 410 if (nlvt >= 4 && apic_enable_error_intr) { 411 if (apic_errvect == 0) { 412 int ipl = 0xf; /* get highest priority intr */ 413 int irq = apic_get_ipivect(ipl, -1); 414 415 ASSERT(irq != -1); 416 apic_errvect = apic_irq_table[irq]->airq_vector; 417 ASSERT(apic_errvect); 418 /* 419 * Not PSMI compliant, but we are going to merge 420 * with ON anyway 421 */ 422 (void) add_avintr((void *)NULL, ipl, 423 (avfunc)apic_error_intr, "apic error intr", 424 irq, NULL, NULL, NULL, NULL); 425 } 426 apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect); 427 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 428 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 429 } 430 431 /* Enable CMCI interrupt */ 432 if (cmi_enable_cmci) { 433 434 mutex_enter(&cmci_cpu_setup_lock); 435 if (cmci_cpu_setup_registered == 0) { 436 mutex_enter(&cpu_lock); 437 register_cpu_setup_func(cmci_cpu_setup, NULL); 438 mutex_exit(&cpu_lock); 439 cmci_cpu_setup_registered = 1; 440 } 441 mutex_exit(&cmci_cpu_setup_lock); 442 443 if (apic_cmci_vect == 0) { 444 int ipl = 0x2; 445 int irq = apic_get_ipivect(ipl, -1); 446 447 ASSERT(irq != -1); 448 apic_cmci_vect = apic_irq_table[irq]->airq_vector; 449 ASSERT(apic_cmci_vect); 450 451 (void) add_avintr(NULL, ipl, 452 (avfunc)cmi_cmci_trap, 453 "apic cmci intr", irq, NULL, NULL, NULL, NULL); 454 } 455 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect); 456 } 457 } 458 459 static void 460 apic_picinit(void) 461 { 462 int i, j; 463 uint_t isr; 464 465 /* 466 * Initialize and enable interrupt remapping before apic 467 * hardware initialization 468 */ 469 apic_intrmap_init(apic_mode); 470 471 /* 472 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr 473 * bit on without clearing it with EOI. Since softint 474 * uses vector 0x20 to interrupt itself, so softint will 475 * not work on this machine. In order to fix this problem 476 * a check is made to verify all the isr bits are clear. 477 * If not, EOIs are issued to clear the bits. 478 */ 479 for (i = 7; i >= 1; i--) { 480 isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4)); 481 if (isr != 0) 482 for (j = 0; ((j < 32) && (isr != 0)); j++) 483 if (isr & (1 << j)) { 484 apic_reg_ops->apic_write( 485 APIC_EOI_REG, 0); 486 isr &= ~(1 << j); 487 apic_error |= APIC_ERR_BOOT_EOI; 488 } 489 } 490 491 /* set a flag so we know we have run apic_picinit() */ 492 apic_picinit_called = 1; 493 LOCK_INIT_CLEAR(&apic_gethrtime_lock); 494 LOCK_INIT_CLEAR(&apic_ioapic_lock); 495 LOCK_INIT_CLEAR(&apic_error_lock); 496 LOCK_INIT_CLEAR(&apic_mode_switch_lock); 497 498 picsetup(); /* initialise the 8259 */ 499 500 /* add nmi handler - least priority nmi handler */ 501 LOCK_INIT_CLEAR(&apic_nmi_lock); 502 503 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr, 504 "pcplusmp NMI handler", (caddr_t)NULL)) 505 cmn_err(CE_WARN, "pcplusmp: Unable to add nmi handler"); 506 507 /* 508 * Check for directed-EOI capability in the local APIC. 509 */ 510 if (apic_directed_EOI_supported() == 1) { 511 apic_set_directed_EOI_handler(); 512 } 513 514 apic_init_intr(); 515 516 /* enable apic mode if imcr present */ 517 if (apic_imcrp) { 518 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT); 519 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC); 520 } 521 522 ioapic_init_intr(IOAPIC_MASK); 523 } 524 525 #ifdef DEBUG 526 void 527 apic_break(void) 528 { 529 } 530 #endif /* DEBUG */ 531 532 /* 533 * platform_intr_enter 534 * 535 * Called at the beginning of the interrupt service routine to 536 * mask all level equal to and below the interrupt priority 537 * of the interrupting vector. An EOI should be given to 538 * the interrupt controller to enable other HW interrupts. 539 * 540 * Return -1 for spurious interrupts 541 * 542 */ 543 /*ARGSUSED*/ 544 static int 545 apic_intr_enter(int ipl, int *vectorp) 546 { 547 uchar_t vector; 548 int nipl; 549 int irq; 550 ulong_t iflag; 551 apic_cpus_info_t *cpu_infop; 552 553 /* 554 * The real vector delivered is (*vectorp + 0x20), but our caller 555 * subtracts 0x20 from the vector before passing it to us. 556 * (That's why APIC_BASE_VECT is 0x20.) 557 */ 558 vector = (uchar_t)*vectorp; 559 560 /* if interrupted by the clock, increment apic_nsec_since_boot */ 561 if (vector == apic_clkvect) { 562 if (!apic_oneshot) { 563 /* NOTE: this is not MT aware */ 564 apic_hrtime_stamp++; 565 apic_nsec_since_boot += apic_nsec_per_intr; 566 apic_hrtime_stamp++; 567 last_count_read = apic_hertz_count; 568 apic_redistribute_compute(); 569 } 570 571 /* We will avoid all the book keeping overhead for clock */ 572 nipl = apic_ipls[vector]; 573 574 *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT]; 575 576 apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]); 577 apic_reg_ops->apic_send_eoi(0); 578 579 return (nipl); 580 } 581 582 cpu_infop = &apic_cpus[psm_get_cpu_id()]; 583 584 if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) { 585 cpu_infop->aci_spur_cnt++; 586 return (APIC_INT_SPURIOUS); 587 } 588 589 /* Check if the vector we got is really what we need */ 590 if (apic_revector_pending) { 591 /* 592 * Disable interrupts for the duration of 593 * the vector translation to prevent a self-race for 594 * the apic_revector_lock. This cannot be done 595 * in apic_xlate_vector because it is recursive and 596 * we want the vector translation to be atomic with 597 * respect to other (higher-priority) interrupts. 598 */ 599 iflag = intr_clear(); 600 vector = apic_xlate_vector(vector + APIC_BASE_VECT) - 601 APIC_BASE_VECT; 602 intr_restore(iflag); 603 } 604 605 nipl = apic_ipls[vector]; 606 *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT]; 607 608 apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]); 609 610 cpu_infop->aci_current[nipl] = (uchar_t)irq; 611 cpu_infop->aci_curipl = (uchar_t)nipl; 612 cpu_infop->aci_ISR_in_progress |= 1 << nipl; 613 614 /* 615 * apic_level_intr could have been assimilated into the irq struct. 616 * but, having it as a character array is more efficient in terms of 617 * cache usage. So, we leave it as is. 618 */ 619 if (!apic_level_intr[irq]) { 620 apic_reg_ops->apic_send_eoi(0); 621 } 622 623 #ifdef DEBUG 624 APIC_DEBUG_BUF_PUT(vector); 625 APIC_DEBUG_BUF_PUT(irq); 626 APIC_DEBUG_BUF_PUT(nipl); 627 APIC_DEBUG_BUF_PUT(psm_get_cpu_id()); 628 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl))) 629 drv_usecwait(apic_stretch_interrupts); 630 631 if (apic_break_on_cpu == psm_get_cpu_id()) 632 apic_break(); 633 #endif /* DEBUG */ 634 return (nipl); 635 } 636 637 void 638 apic_intr_exit(int prev_ipl, int irq) 639 { 640 apic_cpus_info_t *cpu_infop; 641 642 apic_reg_ops->apic_write_task_reg(apic_ipltopri[prev_ipl]); 643 644 cpu_infop = &apic_cpus[psm_get_cpu_id()]; 645 if (apic_level_intr[irq]) 646 apic_reg_ops->apic_send_eoi(irq); 647 cpu_infop->aci_curipl = (uchar_t)prev_ipl; 648 /* ISR above current pri could not be in progress */ 649 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1; 650 } 651 652 intr_exit_fn_t 653 psm_intr_exit_fn(void) 654 { 655 return (apic_intr_exit); 656 } 657 658 /* 659 * Mask all interrupts below or equal to the given IPL. 660 */ 661 static void 662 apic_setspl(int ipl) 663 { 664 apic_reg_ops->apic_write_task_reg(apic_ipltopri[ipl]); 665 666 /* interrupts at ipl above this cannot be in progress */ 667 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1; 668 /* 669 * this is a patch fix for the ALR QSMP P5 machine, so that interrupts 670 * have enough time to come in before the priority is raised again 671 * during the idle() loop. 672 */ 673 if (apic_setspl_delay) 674 (void) apic_reg_ops->apic_get_pri(); 675 } 676 677 /*ARGSUSED*/ 678 static int 679 apic_addspl(int irqno, int ipl, int min_ipl, int max_ipl) 680 { 681 return (apic_addspl_common(irqno, ipl, min_ipl, max_ipl)); 682 } 683 684 static int 685 apic_delspl(int irqno, int ipl, int min_ipl, int max_ipl) 686 { 687 return (apic_delspl_common(irqno, ipl, min_ipl, max_ipl)); 688 } 689 690 static int 691 apic_post_cpu_start(void) 692 { 693 int cpun; 694 static int cpus_started = 1; 695 696 /* We know this CPU + BSP started successfully. */ 697 cpus_started++; 698 699 splx(ipltospl(LOCK_LEVEL)); 700 apic_init_intr(); 701 702 /* 703 * since some systems don't enable the internal cache on the non-boot 704 * cpus, so we have to enable them here 705 */ 706 setcr0(getcr0() & ~(CR0_CD | CR0_NW)); 707 708 APIC_AV_PENDING_SET(); 709 710 /* 711 * We may be booting, or resuming from suspend; aci_status will 712 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the 713 * APIC_CPU_ONLINE flag here rather than setting aci_status completely. 714 */ 715 cpun = psm_get_cpu_id(); 716 apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE; 717 718 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init); 719 return (PSM_SUCCESS); 720 } 721 722 /* 723 * type == -1 indicates it is an internal request. Do not change 724 * resv_vector for these requests 725 */ 726 static int 727 apic_get_ipivect(int ipl, int type) 728 { 729 uchar_t vector; 730 int irq; 731 732 if ((irq = apic_allocate_irq(APIC_VECTOR(ipl))) != -1) { 733 if ((vector = apic_allocate_vector(ipl, irq, 1))) { 734 apic_irq_table[irq]->airq_mps_intr_index = 735 RESERVE_INDEX; 736 apic_irq_table[irq]->airq_vector = vector; 737 if (type != -1) { 738 apic_resv_vector[ipl] = vector; 739 } 740 return (irq); 741 } 742 } 743 apic_error |= APIC_ERR_GET_IPIVECT_FAIL; 744 return (-1); /* shouldn't happen */ 745 } 746 747 static int 748 apic_getclkirq(int ipl) 749 { 750 int irq; 751 752 if ((irq = apic_get_ipivect(ipl, -1)) == -1) 753 return (-1); 754 /* 755 * Note the vector in apic_clkvect for per clock handling. 756 */ 757 apic_clkvect = apic_irq_table[irq]->airq_vector - APIC_BASE_VECT; 758 APIC_VERBOSE_IOAPIC((CE_NOTE, "get_clkirq: vector = %x\n", 759 apic_clkvect)); 760 return (irq); 761 } 762 763 /* 764 * Try and disable all interrupts. We just assign interrupts to other 765 * processors based on policy. If any were bound by user request, we 766 * let them continue and return failure. We do not bother to check 767 * for cache affinity while rebinding. 768 */ 769 770 static int 771 apic_disable_intr(processorid_t cpun) 772 { 773 int bind_cpu = 0, i, hardbound = 0; 774 apic_irq_t *irq_ptr; 775 ulong_t iflag; 776 777 iflag = intr_clear(); 778 lock_set(&apic_ioapic_lock); 779 780 for (i = 0; i <= APIC_MAX_VECTOR; i++) { 781 if (apic_reprogram_info[i].done == B_FALSE) { 782 if (apic_reprogram_info[i].bindcpu == cpun) { 783 /* 784 * CPU is busy -- it's the target of 785 * a pending reprogramming attempt 786 */ 787 lock_clear(&apic_ioapic_lock); 788 intr_restore(iflag); 789 return (PSM_FAILURE); 790 } 791 } 792 } 793 794 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE; 795 796 apic_cpus[cpun].aci_curipl = 0; 797 798 i = apic_min_device_irq; 799 for (; i <= apic_max_device_irq; i++) { 800 /* 801 * If there are bound interrupts on this cpu, then 802 * rebind them to other processors. 803 */ 804 if ((irq_ptr = apic_irq_table[i]) != NULL) { 805 ASSERT((irq_ptr->airq_temp_cpu == IRQ_UNBOUND) || 806 (irq_ptr->airq_temp_cpu == IRQ_UNINIT) || 807 (apic_cpu_in_range(irq_ptr->airq_temp_cpu))); 808 809 if (irq_ptr->airq_temp_cpu == (cpun | IRQ_USER_BOUND)) { 810 hardbound = 1; 811 continue; 812 } 813 814 if (irq_ptr->airq_temp_cpu == cpun) { 815 do { 816 bind_cpu = 817 apic_find_cpu(APIC_CPU_INTR_ENABLE); 818 } while (apic_rebind_all(irq_ptr, bind_cpu)); 819 } 820 } 821 } 822 823 lock_clear(&apic_ioapic_lock); 824 intr_restore(iflag); 825 826 if (hardbound) { 827 cmn_err(CE_WARN, "Could not disable interrupts on %d" 828 "due to user bound interrupts", cpun); 829 return (PSM_FAILURE); 830 } 831 else 832 return (PSM_SUCCESS); 833 } 834 835 /* 836 * Bind interrupts to the CPU's local APIC. 837 * Interrupts should not be bound to a CPU's local APIC until the CPU 838 * is ready to receive interrupts. 839 */ 840 static void 841 apic_enable_intr(processorid_t cpun) 842 { 843 int i; 844 apic_irq_t *irq_ptr; 845 ulong_t iflag; 846 847 iflag = intr_clear(); 848 lock_set(&apic_ioapic_lock); 849 850 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE; 851 852 i = apic_min_device_irq; 853 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) { 854 if ((irq_ptr = apic_irq_table[i]) != NULL) { 855 if ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) == cpun) { 856 (void) apic_rebind_all(irq_ptr, 857 irq_ptr->airq_cpu); 858 } 859 } 860 } 861 862 if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND) 863 apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND; 864 865 lock_clear(&apic_ioapic_lock); 866 intr_restore(iflag); 867 } 868 869 /* 870 * If this module needs a periodic handler for the interrupt distribution, it 871 * can be added here. The argument to the periodic handler is not currently 872 * used, but is reserved for future. 873 */ 874 static void 875 apic_post_cyclic_setup(void *arg) 876 { 877 _NOTE(ARGUNUSED(arg)) 878 879 cyc_handler_t cyh; 880 cyc_time_t cyt; 881 882 /* cpu_lock is held */ 883 /* set up a periodic handler for intr redistribution */ 884 885 /* 886 * In peridoc mode intr redistribution processing is done in 887 * apic_intr_enter during clk intr processing 888 */ 889 if (!apic_oneshot) 890 return; 891 892 /* 893 * Register a periodical handler for the redistribution processing. 894 * Though we would generally prefer to use the DDI interface for 895 * periodic handler invocation, ddi_periodic_add(9F), we are 896 * unfortunately already holding cpu_lock, which ddi_periodic_add will 897 * attempt to take for us. Thus, we add our own cyclic directly: 898 */ 899 cyh.cyh_func = (void (*)(void *))apic_redistribute_compute; 900 cyh.cyh_arg = NULL; 901 cyh.cyh_level = CY_LOW_LEVEL; 902 903 cyt.cyt_when = 0; 904 cyt.cyt_interval = apic_redistribute_sample_interval; 905 906 apic_cyclic_id = cyclic_add(&cyh, &cyt); 907 } 908 909 static void 910 apic_redistribute_compute(void) 911 { 912 int i, j, max_busy; 913 914 if (apic_enable_dynamic_migration) { 915 if (++apic_nticks == apic_sample_factor_redistribution) { 916 /* 917 * Time to call apic_intr_redistribute(). 918 * reset apic_nticks. This will cause max_busy 919 * to be calculated below and if it is more than 920 * apic_int_busy, we will do the whole thing 921 */ 922 apic_nticks = 0; 923 } 924 max_busy = 0; 925 for (i = 0; i < apic_nproc; i++) { 926 if (!apic_cpu_in_range(i)) 927 continue; 928 929 /* 930 * Check if curipl is non zero & if ISR is in 931 * progress 932 */ 933 if (((j = apic_cpus[i].aci_curipl) != 0) && 934 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) { 935 936 int irq; 937 apic_cpus[i].aci_busy++; 938 irq = apic_cpus[i].aci_current[j]; 939 apic_irq_table[irq]->airq_busy++; 940 } 941 942 if (!apic_nticks && 943 (apic_cpus[i].aci_busy > max_busy)) 944 max_busy = apic_cpus[i].aci_busy; 945 } 946 if (!apic_nticks) { 947 if (max_busy > apic_int_busy_mark) { 948 /* 949 * We could make the following check be 950 * skipped > 1 in which case, we get a 951 * redistribution at half the busy mark (due to 952 * double interval). Need to be able to collect 953 * more empirical data to decide if that is a 954 * good strategy. Punt for now. 955 */ 956 if (apic_skipped_redistribute) { 957 apic_cleanup_busy(); 958 apic_skipped_redistribute = 0; 959 } else { 960 apic_intr_redistribute(); 961 } 962 } else 963 apic_skipped_redistribute++; 964 } 965 } 966 } 967 968 969 /* 970 * The following functions are in the platform specific file so that they 971 * can be different functions depending on whether we are running on 972 * bare metal or a hypervisor. 973 */ 974 975 /* 976 * Check to make sure there are enough irq slots 977 */ 978 int 979 apic_check_free_irqs(int count) 980 { 981 int i, avail; 982 983 avail = 0; 984 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) { 985 if ((apic_irq_table[i] == NULL) || 986 apic_irq_table[i]->airq_mps_intr_index == FREE_INDEX) { 987 if (++avail >= count) 988 return (PSM_SUCCESS); 989 } 990 } 991 return (PSM_FAILURE); 992 } 993 994 /* 995 * This function allocates "count" MSI vector(s) for the given "dip/pri/type" 996 */ 997 int 998 apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, int pri, 999 int behavior) 1000 { 1001 int rcount, i; 1002 uchar_t start, irqno; 1003 uint32_t cpu = 0; 1004 major_t major; 1005 apic_irq_t *irqptr; 1006 1007 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: dip=0x%p " 1008 "inum=0x%x pri=0x%x count=0x%x behavior=%d\n", 1009 (void *)dip, inum, pri, count, behavior)); 1010 1011 if (count > 1) { 1012 if (behavior == DDI_INTR_ALLOC_STRICT && 1013 apic_multi_msi_enable == 0) 1014 return (0); 1015 if (apic_multi_msi_enable == 0) 1016 count = 1; 1017 } 1018 1019 if ((rcount = apic_navail_vector(dip, pri)) > count) 1020 rcount = count; 1021 else if (rcount == 0 || (rcount < count && 1022 behavior == DDI_INTR_ALLOC_STRICT)) 1023 return (0); 1024 1025 /* if not ISP2, then round it down */ 1026 if (!ISP2(rcount)) 1027 rcount = 1 << (highbit(rcount) - 1); 1028 1029 mutex_enter(&airq_mutex); 1030 1031 for (start = 0; rcount > 0; rcount >>= 1) { 1032 if ((start = apic_find_multi_vectors(pri, rcount)) != 0 || 1033 behavior == DDI_INTR_ALLOC_STRICT) 1034 break; 1035 } 1036 1037 if (start == 0) { 1038 /* no vector available */ 1039 mutex_exit(&airq_mutex); 1040 return (0); 1041 } 1042 1043 if (apic_check_free_irqs(rcount) == PSM_FAILURE) { 1044 /* not enough free irq slots available */ 1045 mutex_exit(&airq_mutex); 1046 return (0); 1047 } 1048 1049 major = (dip != NULL) ? ddi_driver_major(dip) : 0; 1050 for (i = 0; i < rcount; i++) { 1051 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) == 1052 (uchar_t)-1) { 1053 /* 1054 * shouldn't happen because of the 1055 * apic_check_free_irqs() check earlier 1056 */ 1057 mutex_exit(&airq_mutex); 1058 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: " 1059 "apic_allocate_irq failed\n")); 1060 return (i); 1061 } 1062 apic_max_device_irq = max(irqno, apic_max_device_irq); 1063 apic_min_device_irq = min(irqno, apic_min_device_irq); 1064 irqptr = apic_irq_table[irqno]; 1065 #ifdef DEBUG 1066 if (apic_vector_to_irq[start + i] != APIC_RESV_IRQ) 1067 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: " 1068 "apic_vector_to_irq is not APIC_RESV_IRQ\n")); 1069 #endif 1070 apic_vector_to_irq[start + i] = (uchar_t)irqno; 1071 1072 irqptr->airq_vector = (uchar_t)(start + i); 1073 irqptr->airq_ioapicindex = (uchar_t)inum; /* start */ 1074 irqptr->airq_intin_no = (uchar_t)rcount; 1075 ASSERT(pri >= 0 && pri <= UCHAR_MAX); 1076 irqptr->airq_ipl = (uchar_t)pri; 1077 irqptr->airq_vector = start + i; 1078 irqptr->airq_origirq = (uchar_t)(inum + i); 1079 irqptr->airq_share_id = 0; 1080 irqptr->airq_mps_intr_index = MSI_INDEX; 1081 irqptr->airq_dip = dip; 1082 irqptr->airq_major = major; 1083 if (i == 0) /* they all bound to the same cpu */ 1084 cpu = irqptr->airq_cpu = apic_bind_intr(dip, irqno, 1085 0xff, 0xff); 1086 else 1087 irqptr->airq_cpu = cpu; 1088 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: irq=0x%x " 1089 "dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno, 1090 (void *)irqptr->airq_dip, irqptr->airq_vector, 1091 irqptr->airq_origirq, pri)); 1092 } 1093 mutex_exit(&airq_mutex); 1094 return (rcount); 1095 } 1096 1097 /* 1098 * This function allocates "count" MSI-X vector(s) for the given "dip/pri/type" 1099 */ 1100 int 1101 apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, int pri, 1102 int behavior) 1103 { 1104 int rcount, i; 1105 major_t major; 1106 1107 mutex_enter(&airq_mutex); 1108 1109 if ((rcount = apic_navail_vector(dip, pri)) > count) 1110 rcount = count; 1111 else if (rcount == 0 || (rcount < count && 1112 behavior == DDI_INTR_ALLOC_STRICT)) { 1113 rcount = 0; 1114 goto out; 1115 } 1116 1117 if (apic_check_free_irqs(rcount) == PSM_FAILURE) { 1118 /* not enough free irq slots available */ 1119 rcount = 0; 1120 goto out; 1121 } 1122 1123 major = (dip != NULL) ? ddi_driver_major(dip) : 0; 1124 for (i = 0; i < rcount; i++) { 1125 uchar_t vector, irqno; 1126 apic_irq_t *irqptr; 1127 1128 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) == 1129 (uchar_t)-1) { 1130 /* 1131 * shouldn't happen because of the 1132 * apic_check_free_irqs() check earlier 1133 */ 1134 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: " 1135 "apic_allocate_irq failed\n")); 1136 rcount = i; 1137 goto out; 1138 } 1139 if ((vector = apic_allocate_vector(pri, irqno, 1)) == 0) { 1140 /* 1141 * shouldn't happen because of the 1142 * apic_navail_vector() call earlier 1143 */ 1144 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: " 1145 "apic_allocate_vector failed\n")); 1146 rcount = i; 1147 goto out; 1148 } 1149 apic_max_device_irq = max(irqno, apic_max_device_irq); 1150 apic_min_device_irq = min(irqno, apic_min_device_irq); 1151 irqptr = apic_irq_table[irqno]; 1152 irqptr->airq_vector = (uchar_t)vector; 1153 ASSERT(pri >= 0 && pri <= UCHAR_MAX); 1154 irqptr->airq_ipl = (uchar_t)pri; 1155 irqptr->airq_origirq = (uchar_t)(inum + i); 1156 irqptr->airq_share_id = 0; 1157 irqptr->airq_mps_intr_index = MSIX_INDEX; 1158 irqptr->airq_dip = dip; 1159 irqptr->airq_major = major; 1160 irqptr->airq_cpu = apic_bind_intr(dip, irqno, 0xff, 0xff); 1161 } 1162 out: 1163 mutex_exit(&airq_mutex); 1164 return (rcount); 1165 } 1166 1167 /* 1168 * Allocate a free vector for irq at ipl. Takes care of merging of multiple 1169 * IPLs into a single APIC level as well as stretching some IPLs onto multiple 1170 * levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority 1171 * requests and allocated only when pri is set. 1172 */ 1173 uchar_t 1174 apic_allocate_vector(int ipl, int irq, int pri) 1175 { 1176 int lowest, highest, i; 1177 1178 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK; 1179 lowest = apic_ipltopri[ipl - 1] + APIC_VECTOR_PER_IPL; 1180 1181 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */ 1182 lowest -= APIC_VECTOR_PER_IPL; 1183 1184 #ifdef DEBUG 1185 if (apic_restrict_vector) /* for testing shared interrupt logic */ 1186 highest = lowest + apic_restrict_vector + APIC_HI_PRI_VECTS; 1187 #endif /* DEBUG */ 1188 if (pri == 0) 1189 highest -= APIC_HI_PRI_VECTS; 1190 1191 for (i = lowest; i <= highest; i++) { 1192 if (APIC_CHECK_RESERVE_VECTORS(i)) 1193 continue; 1194 if (apic_vector_to_irq[i] == APIC_RESV_IRQ) { 1195 apic_vector_to_irq[i] = (uchar_t)irq; 1196 ASSERT(i >= 0 && i <= UCHAR_MAX); 1197 return ((uchar_t)i); 1198 } 1199 } 1200 1201 return (0); 1202 } 1203 1204 /* Mark vector as not being used by any irq */ 1205 void 1206 apic_free_vector(uchar_t vector) 1207 { 1208 apic_vector_to_irq[vector] = APIC_RESV_IRQ; 1209 } 1210 1211 /* 1212 * Call rebind to do the actual programming. 1213 * Must be called with interrupts disabled and apic_ioapic_lock held 1214 * 'p' is polymorphic -- if this function is called to process a deferred 1215 * reprogramming, p is of type 'struct ioapic_reprogram_data *', from which 1216 * the irq pointer is retrieved. If not doing deferred reprogramming, 1217 * p is of the type 'apic_irq_t *'. 1218 * 1219 * apic_ioapic_lock must be held across this call, as it protects apic_rebind 1220 * and it protects apic_get_next_bind_cpu() from a race in which a CPU can be 1221 * taken offline after a cpu is selected, but before apic_rebind is called to 1222 * bind interrupts to it. 1223 */ 1224 int 1225 apic_setup_io_intr(void *p, int irq, boolean_t deferred) 1226 { 1227 apic_irq_t *irqptr; 1228 struct ioapic_reprogram_data *drep = NULL; 1229 int rv; 1230 1231 if (deferred) { 1232 drep = (struct ioapic_reprogram_data *)p; 1233 ASSERT(drep != NULL); 1234 irqptr = drep->irqp; 1235 } else 1236 irqptr = (apic_irq_t *)p; 1237 1238 ASSERT(irqptr != NULL); 1239 1240 rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, drep); 1241 if (rv) { 1242 /* 1243 * CPU is not up or interrupts are disabled. Fall back to 1244 * the first available CPU 1245 */ 1246 rv = apic_rebind(irqptr, apic_find_cpu(APIC_CPU_INTR_ENABLE), 1247 drep); 1248 } 1249 1250 return (rv); 1251 } 1252 1253 1254 uchar_t 1255 apic_modify_vector(uchar_t vector, int irq) 1256 { 1257 apic_vector_to_irq[vector] = (uchar_t)irq; 1258 return (vector); 1259 } 1260 1261 char * 1262 apic_get_apic_type(void) 1263 { 1264 return (apic_psm_info.p_mach_idstring); 1265 } 1266 1267 void 1268 apic_switch_ipi_callback(boolean_t enter) 1269 { 1270 ASSERT(enter == B_TRUE); 1271 } 1272 1273 int 1274 apic_detect_x2apic(void) 1275 { 1276 return (0); 1277 } 1278 1279 void 1280 apic_enable_x2apic(void) 1281 { 1282 cmn_err(CE_PANIC, "apic_enable_x2apic() called in pcplusmp"); 1283 } 1284 1285 void 1286 x2apic_update_psm(void) 1287 { 1288 cmn_err(CE_PANIC, "x2apic_update_psm() called in pcplusmp"); 1289 } 1290