1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 /* 26 * Copyright (c) 2010, Intel Corporation. 27 * All rights reserved. 28 */ 29 /* 30 * Copyright (c) 2017, Joyent, Inc. All rights reserved. 31 */ 32 33 /* 34 * To understand how the pcplusmp module interacts with the interrupt subsystem 35 * read the theory statement in uts/i86pc/os/intr.c. 36 */ 37 38 /* 39 * PSMI 1.1 extensions are supported only in 2.6 and later versions. 40 * PSMI 1.2 extensions are supported only in 2.7 and later versions. 41 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10. 42 * PSMI 1.5 extensions are supported in Solaris Nevada. 43 * PSMI 1.6 extensions are supported in Solaris Nevada. 44 * PSMI 1.7 extensions are supported in Solaris Nevada. 45 */ 46 #define PSMI_1_7 47 48 #include <sys/processor.h> 49 #include <sys/time.h> 50 #include <sys/psm.h> 51 #include <sys/smp_impldefs.h> 52 #include <sys/cram.h> 53 #include <sys/acpi/acpi.h> 54 #include <sys/acpica.h> 55 #include <sys/psm_common.h> 56 #include <sys/apic.h> 57 #include <sys/pit.h> 58 #include <sys/ddi.h> 59 #include <sys/sunddi.h> 60 #include <sys/ddi_impldefs.h> 61 #include <sys/pci.h> 62 #include <sys/promif.h> 63 #include <sys/x86_archext.h> 64 #include <sys/cpc_impl.h> 65 #include <sys/uadmin.h> 66 #include <sys/panic.h> 67 #include <sys/debug.h> 68 #include <sys/archsystm.h> 69 #include <sys/trap.h> 70 #include <sys/machsystm.h> 71 #include <sys/sysmacros.h> 72 #include <sys/cpuvar.h> 73 #include <sys/rm_platter.h> 74 #include <sys/privregs.h> 75 #include <sys/note.h> 76 #include <sys/pci_intr_lib.h> 77 #include <sys/spl.h> 78 #include <sys/clock.h> 79 #include <sys/cyclic.h> 80 #include <sys/dditypes.h> 81 #include <sys/sunddi.h> 82 #include <sys/x_call.h> 83 #include <sys/reboot.h> 84 #include <sys/hpet.h> 85 #include <sys/apic_common.h> 86 #include <sys/apic_timer.h> 87 88 /* 89 * Local Function Prototypes 90 */ 91 static void apic_init_intr(void); 92 93 /* 94 * standard MP entries 95 */ 96 static int apic_probe(void); 97 static int apic_getclkirq(int ipl); 98 static void apic_init(void); 99 static void apic_picinit(void); 100 static int apic_post_cpu_start(void); 101 static int apic_intr_enter(int ipl, int *vect); 102 static void apic_setspl(int ipl); 103 static int apic_addspl(int ipl, int vector, int min_ipl, int max_ipl); 104 static int apic_delspl(int ipl, int vector, int min_ipl, int max_ipl); 105 static int apic_disable_intr(processorid_t cpun); 106 static void apic_enable_intr(processorid_t cpun); 107 static int apic_get_ipivect(int ipl, int type); 108 static void apic_post_cyclic_setup(void *arg); 109 110 #define UCHAR_MAX UINT8_MAX 111 112 /* 113 * The following vector assignments influence the value of ipltopri and 114 * vectortoipl. Note that vectors 0 - 0x1f are not used. We can program 115 * idle to 0 and IPL 0 to 0xf to differentiate idle in case 116 * we care to do so in future. Note some IPLs which are rarely used 117 * will share the vector ranges and heavily used IPLs (5 and 6) have 118 * a wide range. 119 * 120 * This array is used to initialize apic_ipls[] (in apic_init()). 121 * 122 * IPL Vector range. as passed to intr_enter 123 * 0 none. 124 * 1,2,3 0x20-0x2f 0x0-0xf 125 * 4 0x30-0x3f 0x10-0x1f 126 * 5 0x40-0x5f 0x20-0x3f 127 * 6 0x60-0x7f 0x40-0x5f 128 * 7,8,9 0x80-0x8f 0x60-0x6f 129 * 10 0x90-0x9f 0x70-0x7f 130 * 11 0xa0-0xaf 0x80-0x8f 131 * ... ... 132 * 15 0xe0-0xef 0xc0-0xcf 133 * 15 0xf0-0xff 0xd0-0xdf 134 */ 135 uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL] = { 136 3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15 137 }; 138 /* 139 * The ipl of an ISR at vector X is apic_vectortoipl[X>>4] 140 * NOTE that this is vector as passed into intr_enter which is 141 * programmed vector - 0x20 (APIC_BASE_VECT) 142 */ 143 144 uchar_t apic_ipltopri[MAXIPL + 1]; /* unix ipl to apic pri */ 145 /* The taskpri to be programmed into apic to mask given ipl */ 146 147 /* 148 * Correlation of the hardware vector to the IPL in use, initialized 149 * from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate 150 * to the IPLs in apic_vectortoipl on some systems that share interrupt lines 151 * connected to errata-stricken IOAPICs 152 */ 153 uchar_t apic_ipls[APIC_AVAIL_VECTOR]; 154 155 /* 156 * Patchable global variables. 157 */ 158 int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */ 159 int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */ 160 161 /* 162 * Local static data 163 */ 164 static struct psm_ops apic_ops = { 165 apic_probe, 166 167 apic_init, 168 apic_picinit, 169 apic_intr_enter, 170 apic_intr_exit, 171 apic_setspl, 172 apic_addspl, 173 apic_delspl, 174 apic_disable_intr, 175 apic_enable_intr, 176 (int (*)(int))NULL, /* psm_softlvl_to_irq */ 177 (void (*)(int))NULL, /* psm_set_softintr */ 178 179 apic_set_idlecpu, 180 apic_unset_idlecpu, 181 182 apic_clkinit, 183 apic_getclkirq, 184 (void (*)(void))NULL, /* psm_hrtimeinit */ 185 apic_gethrtime, 186 187 apic_get_next_processorid, 188 apic_cpu_start, 189 apic_post_cpu_start, 190 apic_shutdown, 191 apic_get_ipivect, 192 apic_send_ipi, 193 194 (int (*)(dev_info_t *, int))NULL, /* psm_translate_irq */ 195 (void (*)(int, char *))NULL, /* psm_notify_error */ 196 (void (*)(int))NULL, /* psm_notify_func */ 197 apic_timer_reprogram, 198 apic_timer_enable, 199 apic_timer_disable, 200 apic_post_cyclic_setup, 201 apic_preshutdown, 202 apic_intr_ops, /* Advanced DDI Interrupt framework */ 203 apic_state, /* save, restore apic state for S3 */ 204 apic_cpu_ops, /* CPU control interface. */ 205 }; 206 207 struct psm_ops *psmops = &apic_ops; 208 209 static struct psm_info apic_psm_info = { 210 PSM_INFO_VER01_7, /* version */ 211 PSM_OWN_EXCLUSIVE, /* ownership */ 212 (struct psm_ops *)&apic_ops, /* operation */ 213 APIC_PCPLUSMP_NAME, /* machine name */ 214 "pcplusmp v1.4 compatible", 215 }; 216 217 static void *apic_hdlp; 218 219 /* to gather intr data and redistribute */ 220 static void apic_redistribute_compute(void); 221 222 /* 223 * This is the loadable module wrapper 224 */ 225 226 int 227 _init(void) 228 { 229 if (apic_coarse_hrtime) 230 apic_ops.psm_gethrtime = &apic_gettime; 231 return (psm_mod_init(&apic_hdlp, &apic_psm_info)); 232 } 233 234 int 235 _fini(void) 236 { 237 return (psm_mod_fini(&apic_hdlp, &apic_psm_info)); 238 } 239 240 int 241 _info(struct modinfo *modinfop) 242 { 243 return (psm_mod_info(&apic_hdlp, &apic_psm_info, modinfop)); 244 } 245 246 static int 247 apic_probe(void) 248 { 249 /* check if apix is initialized */ 250 if (apix_enable && apix_loaded()) 251 return (PSM_FAILURE); 252 253 /* 254 * Check whether x2APIC mode was activated by BIOS. We don't support 255 * that in pcplusmp as apix normally handles that. 256 */ 257 if (apic_local_mode() == LOCAL_X2APIC) 258 return (PSM_FAILURE); 259 260 /* continue using pcplusmp PSM */ 261 apix_enable = 0; 262 263 return (apic_probe_common(apic_psm_info.p_mach_idstring)); 264 } 265 266 static uchar_t 267 apic_xlate_vector_by_irq(uchar_t irq) 268 { 269 if (apic_irq_table[irq] == NULL) 270 return (0); 271 272 return (apic_irq_table[irq]->airq_vector); 273 } 274 275 void 276 apic_init(void) 277 { 278 int i; 279 int j = 1; 280 281 psm_get_ioapicid = apic_get_ioapicid; 282 psm_get_localapicid = apic_get_localapicid; 283 psm_xlate_vector_by_irq = apic_xlate_vector_by_irq; 284 285 apic_ipltopri[0] = APIC_VECTOR_PER_IPL; /* leave 0 for idle */ 286 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) { 287 if ((i < ((APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL) - 1)) && 288 (apic_vectortoipl[i + 1] == apic_vectortoipl[i])) 289 /* get to highest vector at the same ipl */ 290 continue; 291 for (; j <= apic_vectortoipl[i]; j++) { 292 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + 293 APIC_BASE_VECT; 294 } 295 } 296 for (; j < MAXIPL + 1; j++) 297 /* fill up any empty ipltopri slots */ 298 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + APIC_BASE_VECT; 299 apic_init_common(); 300 301 #if !defined(__amd64) 302 if (cpuid_have_cr8access(CPU)) 303 apic_have_32bit_cr8 = 1; 304 #endif 305 } 306 307 static void 308 apic_init_intr(void) 309 { 310 processorid_t cpun = psm_get_cpu_id(); 311 uint_t nlvt; 312 uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR; 313 314 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL); 315 316 ASSERT(apic_mode == LOCAL_APIC); 317 318 /* 319 * We are running APIC in MMIO mode. 320 */ 321 if (apic_flat_model) { 322 apic_reg_ops->apic_write(APIC_FORMAT_REG, APIC_FLAT_MODEL); 323 } else { 324 apic_reg_ops->apic_write(APIC_FORMAT_REG, APIC_CLUSTER_MODEL); 325 } 326 327 apic_reg_ops->apic_write(APIC_DEST_REG, AV_HIGH_ORDER >> cpun); 328 329 if (apic_directed_EOI_supported()) { 330 /* 331 * Setting the 12th bit in the Spurious Interrupt Vector 332 * Register suppresses broadcast EOIs generated by the local 333 * APIC. The suppression of broadcast EOIs happens only when 334 * interrupts are level-triggered. 335 */ 336 svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI; 337 } 338 339 /* need to enable APIC before unmasking NMI */ 340 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr); 341 342 /* 343 * Presence of an invalid vector with delivery mode AV_FIXED can 344 * cause an error interrupt, even if the entry is masked...so 345 * write a valid vector to LVT entries along with the mask bit 346 */ 347 348 /* All APICs have timer and LINT0/1 */ 349 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ); 350 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ); 351 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */ 352 353 /* 354 * On integrated APICs, the number of LVT entries is 355 * 'Max LVT entry' + 1; on 82489DX's (non-integrated 356 * APICs), nlvt is "3" (LINT0, LINT1, and timer) 357 */ 358 359 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) { 360 nlvt = 3; 361 } else { 362 nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) & 363 0xFF) + 1; 364 } 365 366 if (nlvt >= 5) { 367 /* Enable performance counter overflow interrupt */ 368 369 if (!is_x86_feature(x86_featureset, X86FSET_MSR)) 370 apic_enable_cpcovf_intr = 0; 371 if (apic_enable_cpcovf_intr) { 372 if (apic_cpcovf_vect == 0) { 373 int ipl = APIC_PCINT_IPL; 374 int irq = apic_get_ipivect(ipl, -1); 375 376 ASSERT(irq != -1); 377 apic_cpcovf_vect = 378 apic_irq_table[irq]->airq_vector; 379 ASSERT(apic_cpcovf_vect); 380 (void) add_avintr(NULL, ipl, 381 (avfunc)kcpc_hw_overflow_intr, 382 "apic pcint", irq, NULL, NULL, NULL, NULL); 383 kcpc_hw_overflow_intr_installed = 1; 384 kcpc_hw_enable_cpc_intr = 385 apic_cpcovf_mask_clear; 386 } 387 apic_reg_ops->apic_write(APIC_PCINT_VECT, 388 apic_cpcovf_vect); 389 } 390 } 391 392 if (nlvt >= 6) { 393 /* Only mask TM intr if the BIOS apparently doesn't use it */ 394 395 uint32_t lvtval; 396 397 lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT); 398 if (((lvtval & AV_MASK) == AV_MASK) || 399 ((lvtval & AV_DELIV_MODE) != AV_SMI)) { 400 apic_reg_ops->apic_write(APIC_THERM_VECT, 401 AV_MASK|APIC_RESV_IRQ); 402 } 403 } 404 405 /* Enable error interrupt */ 406 407 if (nlvt >= 4 && apic_enable_error_intr) { 408 if (apic_errvect == 0) { 409 int ipl = 0xf; /* get highest priority intr */ 410 int irq = apic_get_ipivect(ipl, -1); 411 412 ASSERT(irq != -1); 413 apic_errvect = apic_irq_table[irq]->airq_vector; 414 ASSERT(apic_errvect); 415 /* 416 * Not PSMI compliant, but we are going to merge 417 * with ON anyway 418 */ 419 (void) add_avintr((void *)NULL, ipl, 420 (avfunc)apic_error_intr, "apic error intr", 421 irq, NULL, NULL, NULL, NULL); 422 } 423 apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect); 424 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 425 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 426 } 427 428 /* Enable CMCI interrupt */ 429 if (cmi_enable_cmci) { 430 431 mutex_enter(&cmci_cpu_setup_lock); 432 if (cmci_cpu_setup_registered == 0) { 433 mutex_enter(&cpu_lock); 434 register_cpu_setup_func(cmci_cpu_setup, NULL); 435 mutex_exit(&cpu_lock); 436 cmci_cpu_setup_registered = 1; 437 } 438 mutex_exit(&cmci_cpu_setup_lock); 439 440 if (apic_cmci_vect == 0) { 441 int ipl = 0x2; 442 int irq = apic_get_ipivect(ipl, -1); 443 444 ASSERT(irq != -1); 445 apic_cmci_vect = apic_irq_table[irq]->airq_vector; 446 ASSERT(apic_cmci_vect); 447 448 (void) add_avintr(NULL, ipl, 449 (avfunc)cmi_cmci_trap, 450 "apic cmci intr", irq, NULL, NULL, NULL, NULL); 451 } 452 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect); 453 } 454 } 455 456 static void 457 apic_picinit(void) 458 { 459 int i, j; 460 uint_t isr; 461 462 /* 463 * Initialize and enable interrupt remapping before apic 464 * hardware initialization 465 */ 466 apic_intrmap_init(apic_mode); 467 468 /* 469 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr 470 * bit on without clearing it with EOI. Since softint 471 * uses vector 0x20 to interrupt itself, so softint will 472 * not work on this machine. In order to fix this problem 473 * a check is made to verify all the isr bits are clear. 474 * If not, EOIs are issued to clear the bits. 475 */ 476 for (i = 7; i >= 1; i--) { 477 isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4)); 478 if (isr != 0) 479 for (j = 0; ((j < 32) && (isr != 0)); j++) 480 if (isr & (1 << j)) { 481 apic_reg_ops->apic_write( 482 APIC_EOI_REG, 0); 483 isr &= ~(1 << j); 484 apic_error |= APIC_ERR_BOOT_EOI; 485 } 486 } 487 488 /* set a flag so we know we have run apic_picinit() */ 489 apic_picinit_called = 1; 490 LOCK_INIT_CLEAR(&apic_gethrtime_lock); 491 LOCK_INIT_CLEAR(&apic_ioapic_lock); 492 LOCK_INIT_CLEAR(&apic_error_lock); 493 LOCK_INIT_CLEAR(&apic_mode_switch_lock); 494 495 picsetup(); /* initialise the 8259 */ 496 497 /* add nmi handler - least priority nmi handler */ 498 LOCK_INIT_CLEAR(&apic_nmi_lock); 499 500 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr, 501 "pcplusmp NMI handler", (caddr_t)NULL)) 502 cmn_err(CE_WARN, "pcplusmp: Unable to add nmi handler"); 503 504 /* 505 * Check for directed-EOI capability in the local APIC. 506 */ 507 if (apic_directed_EOI_supported() == 1) { 508 apic_set_directed_EOI_handler(); 509 } 510 511 apic_init_intr(); 512 513 /* enable apic mode if imcr present */ 514 if (apic_imcrp) { 515 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT); 516 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC); 517 } 518 519 ioapic_init_intr(IOAPIC_MASK); 520 } 521 522 #ifdef DEBUG 523 void 524 apic_break(void) 525 { 526 } 527 #endif /* DEBUG */ 528 529 /* 530 * platform_intr_enter 531 * 532 * Called at the beginning of the interrupt service routine to 533 * mask all level equal to and below the interrupt priority 534 * of the interrupting vector. An EOI should be given to 535 * the interrupt controller to enable other HW interrupts. 536 * 537 * Return -1 for spurious interrupts 538 * 539 */ 540 /*ARGSUSED*/ 541 static int 542 apic_intr_enter(int ipl, int *vectorp) 543 { 544 uchar_t vector; 545 int nipl; 546 int irq; 547 ulong_t iflag; 548 apic_cpus_info_t *cpu_infop; 549 550 /* 551 * The real vector delivered is (*vectorp + 0x20), but our caller 552 * subtracts 0x20 from the vector before passing it to us. 553 * (That's why APIC_BASE_VECT is 0x20.) 554 */ 555 vector = (uchar_t)*vectorp; 556 557 /* if interrupted by the clock, increment apic_nsec_since_boot */ 558 if (vector == apic_clkvect) { 559 if (!apic_oneshot) { 560 /* NOTE: this is not MT aware */ 561 apic_hrtime_stamp++; 562 apic_nsec_since_boot += apic_nsec_per_intr; 563 apic_hrtime_stamp++; 564 last_count_read = apic_hertz_count; 565 apic_redistribute_compute(); 566 } 567 568 /* We will avoid all the book keeping overhead for clock */ 569 nipl = apic_ipls[vector]; 570 571 *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT]; 572 573 apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]); 574 apic_reg_ops->apic_send_eoi(0); 575 576 return (nipl); 577 } 578 579 cpu_infop = &apic_cpus[psm_get_cpu_id()]; 580 581 if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) { 582 cpu_infop->aci_spur_cnt++; 583 return (APIC_INT_SPURIOUS); 584 } 585 586 /* Check if the vector we got is really what we need */ 587 if (apic_revector_pending) { 588 /* 589 * Disable interrupts for the duration of 590 * the vector translation to prevent a self-race for 591 * the apic_revector_lock. This cannot be done 592 * in apic_xlate_vector because it is recursive and 593 * we want the vector translation to be atomic with 594 * respect to other (higher-priority) interrupts. 595 */ 596 iflag = intr_clear(); 597 vector = apic_xlate_vector(vector + APIC_BASE_VECT) - 598 APIC_BASE_VECT; 599 intr_restore(iflag); 600 } 601 602 nipl = apic_ipls[vector]; 603 *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT]; 604 605 apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]); 606 607 cpu_infop->aci_current[nipl] = (uchar_t)irq; 608 cpu_infop->aci_curipl = (uchar_t)nipl; 609 cpu_infop->aci_ISR_in_progress |= 1 << nipl; 610 611 /* 612 * apic_level_intr could have been assimilated into the irq struct. 613 * but, having it as a character array is more efficient in terms of 614 * cache usage. So, we leave it as is. 615 */ 616 if (!apic_level_intr[irq]) { 617 apic_reg_ops->apic_send_eoi(0); 618 } 619 620 #ifdef DEBUG 621 APIC_DEBUG_BUF_PUT(vector); 622 APIC_DEBUG_BUF_PUT(irq); 623 APIC_DEBUG_BUF_PUT(nipl); 624 APIC_DEBUG_BUF_PUT(psm_get_cpu_id()); 625 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl))) 626 drv_usecwait(apic_stretch_interrupts); 627 628 if (apic_break_on_cpu == psm_get_cpu_id()) 629 apic_break(); 630 #endif /* DEBUG */ 631 return (nipl); 632 } 633 634 void 635 apic_intr_exit(int prev_ipl, int irq) 636 { 637 apic_cpus_info_t *cpu_infop; 638 639 apic_reg_ops->apic_write_task_reg(apic_ipltopri[prev_ipl]); 640 641 cpu_infop = &apic_cpus[psm_get_cpu_id()]; 642 if (apic_level_intr[irq]) 643 apic_reg_ops->apic_send_eoi(irq); 644 cpu_infop->aci_curipl = (uchar_t)prev_ipl; 645 /* ISR above current pri could not be in progress */ 646 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1; 647 } 648 649 intr_exit_fn_t 650 psm_intr_exit_fn(void) 651 { 652 return (apic_intr_exit); 653 } 654 655 /* 656 * Mask all interrupts below or equal to the given IPL. 657 */ 658 static void 659 apic_setspl(int ipl) 660 { 661 apic_reg_ops->apic_write_task_reg(apic_ipltopri[ipl]); 662 663 /* interrupts at ipl above this cannot be in progress */ 664 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1; 665 /* 666 * this is a patch fix for the ALR QSMP P5 machine, so that interrupts 667 * have enough time to come in before the priority is raised again 668 * during the idle() loop. 669 */ 670 if (apic_setspl_delay) 671 (void) apic_reg_ops->apic_get_pri(); 672 } 673 674 /*ARGSUSED*/ 675 static int 676 apic_addspl(int irqno, int ipl, int min_ipl, int max_ipl) 677 { 678 return (apic_addspl_common(irqno, ipl, min_ipl, max_ipl)); 679 } 680 681 static int 682 apic_delspl(int irqno, int ipl, int min_ipl, int max_ipl) 683 { 684 return (apic_delspl_common(irqno, ipl, min_ipl, max_ipl)); 685 } 686 687 static int 688 apic_post_cpu_start(void) 689 { 690 int cpun; 691 static int cpus_started = 1; 692 693 /* We know this CPU + BSP started successfully. */ 694 cpus_started++; 695 696 splx(ipltospl(LOCK_LEVEL)); 697 apic_init_intr(); 698 699 /* 700 * since some systems don't enable the internal cache on the non-boot 701 * cpus, so we have to enable them here 702 */ 703 setcr0(getcr0() & ~(CR0_CD | CR0_NW)); 704 705 APIC_AV_PENDING_SET(); 706 707 /* 708 * We may be booting, or resuming from suspend; aci_status will 709 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the 710 * APIC_CPU_ONLINE flag here rather than setting aci_status completely. 711 */ 712 cpun = psm_get_cpu_id(); 713 apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE; 714 715 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init); 716 return (PSM_SUCCESS); 717 } 718 719 /* 720 * type == -1 indicates it is an internal request. Do not change 721 * resv_vector for these requests 722 */ 723 static int 724 apic_get_ipivect(int ipl, int type) 725 { 726 uchar_t vector; 727 int irq; 728 729 if ((irq = apic_allocate_irq(APIC_VECTOR(ipl))) != -1) { 730 if ((vector = apic_allocate_vector(ipl, irq, 1))) { 731 apic_irq_table[irq]->airq_mps_intr_index = 732 RESERVE_INDEX; 733 apic_irq_table[irq]->airq_vector = vector; 734 if (type != -1) { 735 apic_resv_vector[ipl] = vector; 736 } 737 return (irq); 738 } 739 } 740 apic_error |= APIC_ERR_GET_IPIVECT_FAIL; 741 return (-1); /* shouldn't happen */ 742 } 743 744 static int 745 apic_getclkirq(int ipl) 746 { 747 int irq; 748 749 if ((irq = apic_get_ipivect(ipl, -1)) == -1) 750 return (-1); 751 /* 752 * Note the vector in apic_clkvect for per clock handling. 753 */ 754 apic_clkvect = apic_irq_table[irq]->airq_vector - APIC_BASE_VECT; 755 APIC_VERBOSE_IOAPIC((CE_NOTE, "get_clkirq: vector = %x\n", 756 apic_clkvect)); 757 return (irq); 758 } 759 760 /* 761 * Try and disable all interrupts. We just assign interrupts to other 762 * processors based on policy. If any were bound by user request, we 763 * let them continue and return failure. We do not bother to check 764 * for cache affinity while rebinding. 765 */ 766 767 static int 768 apic_disable_intr(processorid_t cpun) 769 { 770 int bind_cpu = 0, i, hardbound = 0; 771 apic_irq_t *irq_ptr; 772 ulong_t iflag; 773 774 iflag = intr_clear(); 775 lock_set(&apic_ioapic_lock); 776 777 for (i = 0; i <= APIC_MAX_VECTOR; i++) { 778 if (apic_reprogram_info[i].done == B_FALSE) { 779 if (apic_reprogram_info[i].bindcpu == cpun) { 780 /* 781 * CPU is busy -- it's the target of 782 * a pending reprogramming attempt 783 */ 784 lock_clear(&apic_ioapic_lock); 785 intr_restore(iflag); 786 return (PSM_FAILURE); 787 } 788 } 789 } 790 791 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE; 792 793 apic_cpus[cpun].aci_curipl = 0; 794 795 i = apic_min_device_irq; 796 for (; i <= apic_max_device_irq; i++) { 797 /* 798 * If there are bound interrupts on this cpu, then 799 * rebind them to other processors. 800 */ 801 if ((irq_ptr = apic_irq_table[i]) != NULL) { 802 ASSERT((irq_ptr->airq_temp_cpu == IRQ_UNBOUND) || 803 (irq_ptr->airq_temp_cpu == IRQ_UNINIT) || 804 (apic_cpu_in_range(irq_ptr->airq_temp_cpu))); 805 806 if (irq_ptr->airq_temp_cpu == (cpun | IRQ_USER_BOUND)) { 807 hardbound = 1; 808 continue; 809 } 810 811 if (irq_ptr->airq_temp_cpu == cpun) { 812 do { 813 bind_cpu = 814 apic_find_cpu(APIC_CPU_INTR_ENABLE); 815 } while (apic_rebind_all(irq_ptr, bind_cpu)); 816 } 817 } 818 } 819 820 lock_clear(&apic_ioapic_lock); 821 intr_restore(iflag); 822 823 if (hardbound) { 824 cmn_err(CE_WARN, "Could not disable interrupts on %d" 825 "due to user bound interrupts", cpun); 826 return (PSM_FAILURE); 827 } 828 else 829 return (PSM_SUCCESS); 830 } 831 832 /* 833 * Bind interrupts to the CPU's local APIC. 834 * Interrupts should not be bound to a CPU's local APIC until the CPU 835 * is ready to receive interrupts. 836 */ 837 static void 838 apic_enable_intr(processorid_t cpun) 839 { 840 int i; 841 apic_irq_t *irq_ptr; 842 ulong_t iflag; 843 844 iflag = intr_clear(); 845 lock_set(&apic_ioapic_lock); 846 847 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE; 848 849 i = apic_min_device_irq; 850 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) { 851 if ((irq_ptr = apic_irq_table[i]) != NULL) { 852 if ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) == cpun) { 853 (void) apic_rebind_all(irq_ptr, 854 irq_ptr->airq_cpu); 855 } 856 } 857 } 858 859 if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND) 860 apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND; 861 862 lock_clear(&apic_ioapic_lock); 863 intr_restore(iflag); 864 } 865 866 /* 867 * If this module needs a periodic handler for the interrupt distribution, it 868 * can be added here. The argument to the periodic handler is not currently 869 * used, but is reserved for future. 870 */ 871 static void 872 apic_post_cyclic_setup(void *arg) 873 { 874 _NOTE(ARGUNUSED(arg)) 875 876 cyc_handler_t cyh; 877 cyc_time_t cyt; 878 879 /* cpu_lock is held */ 880 /* set up a periodic handler for intr redistribution */ 881 882 /* 883 * In peridoc mode intr redistribution processing is done in 884 * apic_intr_enter during clk intr processing 885 */ 886 if (!apic_oneshot) 887 return; 888 889 /* 890 * Register a periodical handler for the redistribution processing. 891 * Though we would generally prefer to use the DDI interface for 892 * periodic handler invocation, ddi_periodic_add(9F), we are 893 * unfortunately already holding cpu_lock, which ddi_periodic_add will 894 * attempt to take for us. Thus, we add our own cyclic directly: 895 */ 896 cyh.cyh_func = (void (*)(void *))apic_redistribute_compute; 897 cyh.cyh_arg = NULL; 898 cyh.cyh_level = CY_LOW_LEVEL; 899 900 cyt.cyt_when = 0; 901 cyt.cyt_interval = apic_redistribute_sample_interval; 902 903 apic_cyclic_id = cyclic_add(&cyh, &cyt); 904 } 905 906 static void 907 apic_redistribute_compute(void) 908 { 909 int i, j, max_busy; 910 911 if (apic_enable_dynamic_migration) { 912 if (++apic_nticks == apic_sample_factor_redistribution) { 913 /* 914 * Time to call apic_intr_redistribute(). 915 * reset apic_nticks. This will cause max_busy 916 * to be calculated below and if it is more than 917 * apic_int_busy, we will do the whole thing 918 */ 919 apic_nticks = 0; 920 } 921 max_busy = 0; 922 for (i = 0; i < apic_nproc; i++) { 923 if (!apic_cpu_in_range(i)) 924 continue; 925 926 /* 927 * Check if curipl is non zero & if ISR is in 928 * progress 929 */ 930 if (((j = apic_cpus[i].aci_curipl) != 0) && 931 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) { 932 933 int irq; 934 apic_cpus[i].aci_busy++; 935 irq = apic_cpus[i].aci_current[j]; 936 apic_irq_table[irq]->airq_busy++; 937 } 938 939 if (!apic_nticks && 940 (apic_cpus[i].aci_busy > max_busy)) 941 max_busy = apic_cpus[i].aci_busy; 942 } 943 if (!apic_nticks) { 944 if (max_busy > apic_int_busy_mark) { 945 /* 946 * We could make the following check be 947 * skipped > 1 in which case, we get a 948 * redistribution at half the busy mark (due to 949 * double interval). Need to be able to collect 950 * more empirical data to decide if that is a 951 * good strategy. Punt for now. 952 */ 953 if (apic_skipped_redistribute) { 954 apic_cleanup_busy(); 955 apic_skipped_redistribute = 0; 956 } else { 957 apic_intr_redistribute(); 958 } 959 } else 960 apic_skipped_redistribute++; 961 } 962 } 963 } 964 965 966 /* 967 * The following functions are in the platform specific file so that they 968 * can be different functions depending on whether we are running on 969 * bare metal or a hypervisor. 970 */ 971 972 /* 973 * Check to make sure there are enough irq slots 974 */ 975 int 976 apic_check_free_irqs(int count) 977 { 978 int i, avail; 979 980 avail = 0; 981 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) { 982 if ((apic_irq_table[i] == NULL) || 983 apic_irq_table[i]->airq_mps_intr_index == FREE_INDEX) { 984 if (++avail >= count) 985 return (PSM_SUCCESS); 986 } 987 } 988 return (PSM_FAILURE); 989 } 990 991 /* 992 * This function allocates "count" MSI vector(s) for the given "dip/pri/type" 993 */ 994 int 995 apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, int pri, 996 int behavior) 997 { 998 int rcount, i; 999 uchar_t start, irqno; 1000 uint32_t cpu = 0; 1001 major_t major; 1002 apic_irq_t *irqptr; 1003 1004 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: dip=0x%p " 1005 "inum=0x%x pri=0x%x count=0x%x behavior=%d\n", 1006 (void *)dip, inum, pri, count, behavior)); 1007 1008 if (count > 1) { 1009 if (behavior == DDI_INTR_ALLOC_STRICT && 1010 apic_multi_msi_enable == 0) 1011 return (0); 1012 if (apic_multi_msi_enable == 0) 1013 count = 1; 1014 } 1015 1016 if ((rcount = apic_navail_vector(dip, pri)) > count) 1017 rcount = count; 1018 else if (rcount == 0 || (rcount < count && 1019 behavior == DDI_INTR_ALLOC_STRICT)) 1020 return (0); 1021 1022 /* if not ISP2, then round it down */ 1023 if (!ISP2(rcount)) 1024 rcount = 1 << (highbit(rcount) - 1); 1025 1026 mutex_enter(&airq_mutex); 1027 1028 for (start = 0; rcount > 0; rcount >>= 1) { 1029 if ((start = apic_find_multi_vectors(pri, rcount)) != 0 || 1030 behavior == DDI_INTR_ALLOC_STRICT) 1031 break; 1032 } 1033 1034 if (start == 0) { 1035 /* no vector available */ 1036 mutex_exit(&airq_mutex); 1037 return (0); 1038 } 1039 1040 if (apic_check_free_irqs(rcount) == PSM_FAILURE) { 1041 /* not enough free irq slots available */ 1042 mutex_exit(&airq_mutex); 1043 return (0); 1044 } 1045 1046 major = (dip != NULL) ? ddi_driver_major(dip) : 0; 1047 for (i = 0; i < rcount; i++) { 1048 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) == 1049 (uchar_t)-1) { 1050 /* 1051 * shouldn't happen because of the 1052 * apic_check_free_irqs() check earlier 1053 */ 1054 mutex_exit(&airq_mutex); 1055 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: " 1056 "apic_allocate_irq failed\n")); 1057 return (i); 1058 } 1059 apic_max_device_irq = max(irqno, apic_max_device_irq); 1060 apic_min_device_irq = min(irqno, apic_min_device_irq); 1061 irqptr = apic_irq_table[irqno]; 1062 #ifdef DEBUG 1063 if (apic_vector_to_irq[start + i] != APIC_RESV_IRQ) 1064 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: " 1065 "apic_vector_to_irq is not APIC_RESV_IRQ\n")); 1066 #endif 1067 apic_vector_to_irq[start + i] = (uchar_t)irqno; 1068 1069 irqptr->airq_vector = (uchar_t)(start + i); 1070 irqptr->airq_ioapicindex = (uchar_t)inum; /* start */ 1071 irqptr->airq_intin_no = (uchar_t)rcount; 1072 ASSERT(pri >= 0 && pri <= UCHAR_MAX); 1073 irqptr->airq_ipl = (uchar_t)pri; 1074 irqptr->airq_vector = start + i; 1075 irqptr->airq_origirq = (uchar_t)(inum + i); 1076 irqptr->airq_share_id = 0; 1077 irqptr->airq_mps_intr_index = MSI_INDEX; 1078 irqptr->airq_dip = dip; 1079 irqptr->airq_major = major; 1080 if (i == 0) /* they all bound to the same cpu */ 1081 cpu = irqptr->airq_cpu = apic_bind_intr(dip, irqno, 1082 0xff, 0xff); 1083 else 1084 irqptr->airq_cpu = cpu; 1085 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: irq=0x%x " 1086 "dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno, 1087 (void *)irqptr->airq_dip, irqptr->airq_vector, 1088 irqptr->airq_origirq, pri)); 1089 } 1090 mutex_exit(&airq_mutex); 1091 return (rcount); 1092 } 1093 1094 /* 1095 * This function allocates "count" MSI-X vector(s) for the given "dip/pri/type" 1096 */ 1097 int 1098 apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, int pri, 1099 int behavior) 1100 { 1101 int rcount, i; 1102 major_t major; 1103 1104 mutex_enter(&airq_mutex); 1105 1106 if ((rcount = apic_navail_vector(dip, pri)) > count) 1107 rcount = count; 1108 else if (rcount == 0 || (rcount < count && 1109 behavior == DDI_INTR_ALLOC_STRICT)) { 1110 rcount = 0; 1111 goto out; 1112 } 1113 1114 if (apic_check_free_irqs(rcount) == PSM_FAILURE) { 1115 /* not enough free irq slots available */ 1116 rcount = 0; 1117 goto out; 1118 } 1119 1120 major = (dip != NULL) ? ddi_driver_major(dip) : 0; 1121 for (i = 0; i < rcount; i++) { 1122 uchar_t vector, irqno; 1123 apic_irq_t *irqptr; 1124 1125 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) == 1126 (uchar_t)-1) { 1127 /* 1128 * shouldn't happen because of the 1129 * apic_check_free_irqs() check earlier 1130 */ 1131 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: " 1132 "apic_allocate_irq failed\n")); 1133 rcount = i; 1134 goto out; 1135 } 1136 if ((vector = apic_allocate_vector(pri, irqno, 1)) == 0) { 1137 /* 1138 * shouldn't happen because of the 1139 * apic_navail_vector() call earlier 1140 */ 1141 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: " 1142 "apic_allocate_vector failed\n")); 1143 rcount = i; 1144 goto out; 1145 } 1146 apic_max_device_irq = max(irqno, apic_max_device_irq); 1147 apic_min_device_irq = min(irqno, apic_min_device_irq); 1148 irqptr = apic_irq_table[irqno]; 1149 irqptr->airq_vector = (uchar_t)vector; 1150 ASSERT(pri >= 0 && pri <= UCHAR_MAX); 1151 irqptr->airq_ipl = (uchar_t)pri; 1152 irqptr->airq_origirq = (uchar_t)(inum + i); 1153 irqptr->airq_share_id = 0; 1154 irqptr->airq_mps_intr_index = MSIX_INDEX; 1155 irqptr->airq_dip = dip; 1156 irqptr->airq_major = major; 1157 irqptr->airq_cpu = apic_bind_intr(dip, irqno, 0xff, 0xff); 1158 } 1159 out: 1160 mutex_exit(&airq_mutex); 1161 return (rcount); 1162 } 1163 1164 /* 1165 * Allocate a free vector for irq at ipl. Takes care of merging of multiple 1166 * IPLs into a single APIC level as well as stretching some IPLs onto multiple 1167 * levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority 1168 * requests and allocated only when pri is set. 1169 */ 1170 uchar_t 1171 apic_allocate_vector(int ipl, int irq, int pri) 1172 { 1173 int lowest, highest, i; 1174 1175 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK; 1176 lowest = apic_ipltopri[ipl - 1] + APIC_VECTOR_PER_IPL; 1177 1178 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */ 1179 lowest -= APIC_VECTOR_PER_IPL; 1180 1181 #ifdef DEBUG 1182 if (apic_restrict_vector) /* for testing shared interrupt logic */ 1183 highest = lowest + apic_restrict_vector + APIC_HI_PRI_VECTS; 1184 #endif /* DEBUG */ 1185 if (pri == 0) 1186 highest -= APIC_HI_PRI_VECTS; 1187 1188 for (i = lowest; i <= highest; i++) { 1189 if (APIC_CHECK_RESERVE_VECTORS(i)) 1190 continue; 1191 if (apic_vector_to_irq[i] == APIC_RESV_IRQ) { 1192 apic_vector_to_irq[i] = (uchar_t)irq; 1193 ASSERT(i >= 0 && i <= UCHAR_MAX); 1194 return ((uchar_t)i); 1195 } 1196 } 1197 1198 return (0); 1199 } 1200 1201 /* Mark vector as not being used by any irq */ 1202 void 1203 apic_free_vector(uchar_t vector) 1204 { 1205 apic_vector_to_irq[vector] = APIC_RESV_IRQ; 1206 } 1207 1208 /* 1209 * Call rebind to do the actual programming. 1210 * Must be called with interrupts disabled and apic_ioapic_lock held 1211 * 'p' is polymorphic -- if this function is called to process a deferred 1212 * reprogramming, p is of type 'struct ioapic_reprogram_data *', from which 1213 * the irq pointer is retrieved. If not doing deferred reprogramming, 1214 * p is of the type 'apic_irq_t *'. 1215 * 1216 * apic_ioapic_lock must be held across this call, as it protects apic_rebind 1217 * and it protects apic_get_next_bind_cpu() from a race in which a CPU can be 1218 * taken offline after a cpu is selected, but before apic_rebind is called to 1219 * bind interrupts to it. 1220 */ 1221 int 1222 apic_setup_io_intr(void *p, int irq, boolean_t deferred) 1223 { 1224 apic_irq_t *irqptr; 1225 struct ioapic_reprogram_data *drep = NULL; 1226 int rv; 1227 1228 if (deferred) { 1229 drep = (struct ioapic_reprogram_data *)p; 1230 ASSERT(drep != NULL); 1231 irqptr = drep->irqp; 1232 } else 1233 irqptr = (apic_irq_t *)p; 1234 1235 ASSERT(irqptr != NULL); 1236 1237 rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, drep); 1238 if (rv) { 1239 /* 1240 * CPU is not up or interrupts are disabled. Fall back to 1241 * the first available CPU 1242 */ 1243 rv = apic_rebind(irqptr, apic_find_cpu(APIC_CPU_INTR_ENABLE), 1244 drep); 1245 } 1246 1247 return (rv); 1248 } 1249 1250 1251 uchar_t 1252 apic_modify_vector(uchar_t vector, int irq) 1253 { 1254 apic_vector_to_irq[vector] = (uchar_t)irq; 1255 return (vector); 1256 } 1257 1258 char * 1259 apic_get_apic_type(void) 1260 { 1261 return (apic_psm_info.p_mach_idstring); 1262 } 1263 1264 void 1265 apic_switch_ipi_callback(boolean_t enter) 1266 { 1267 ASSERT(enter == B_TRUE); 1268 } 1269 1270 int 1271 apic_detect_x2apic(void) 1272 { 1273 return (0); 1274 } 1275 1276 void 1277 apic_enable_x2apic(void) 1278 { 1279 cmn_err(CE_PANIC, "apic_enable_x2apic() called in pcplusmp"); 1280 } 1281 1282 void 1283 x2apic_update_psm(void) 1284 { 1285 cmn_err(CE_PANIC, "x2apic_update_psm() called in pcplusmp"); 1286 } 1287