1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * PSMI 1.1 extensions are supported only in 2.6 and later versions. 29 * PSMI 1.2 extensions are supported only in 2.7 and later versions. 30 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10. 31 * PSMI 1.5 extensions are supported in Solaris Nevada. 32 * PSMI 1.6 extensions are supported in Solaris Nevada. 33 */ 34 #define PSMI_1_6 35 36 #include <sys/processor.h> 37 #include <sys/time.h> 38 #include <sys/psm.h> 39 #include <sys/smp_impldefs.h> 40 #include <sys/cram.h> 41 #include <sys/acpi/acpi.h> 42 #include <sys/acpica.h> 43 #include <sys/psm_common.h> 44 #include <sys/apic.h> 45 #include <sys/pit.h> 46 #include <sys/ddi.h> 47 #include <sys/sunddi.h> 48 #include <sys/ddi_impldefs.h> 49 #include <sys/pci.h> 50 #include <sys/promif.h> 51 #include <sys/x86_archext.h> 52 #include <sys/cpc_impl.h> 53 #include <sys/uadmin.h> 54 #include <sys/panic.h> 55 #include <sys/debug.h> 56 #include <sys/archsystm.h> 57 #include <sys/trap.h> 58 #include <sys/machsystm.h> 59 #include <sys/sysmacros.h> 60 #include <sys/cpuvar.h> 61 #include <sys/rm_platter.h> 62 #include <sys/privregs.h> 63 #include <sys/note.h> 64 #include <sys/pci_intr_lib.h> 65 #include <sys/spl.h> 66 #include <sys/clock.h> 67 #include <sys/dditypes.h> 68 #include <sys/sunddi.h> 69 #include <sys/x_call.h> 70 #include <sys/reboot.h> 71 72 /* 73 * Local Function Prototypes 74 */ 75 static void apic_init_intr(); 76 static void apic_nmi_intr(caddr_t arg, struct regs *rp); 77 78 /* 79 * standard MP entries 80 */ 81 static int apic_probe(); 82 static int apic_clkinit(); 83 static int apic_getclkirq(int ipl); 84 static uint_t apic_calibrate(volatile uint32_t *addr, 85 uint16_t *pit_ticks_adj); 86 static hrtime_t apic_gettime(); 87 static hrtime_t apic_gethrtime(); 88 static void apic_init(); 89 static void apic_picinit(void); 90 static int apic_cpu_start(processorid_t, caddr_t); 91 static int apic_post_cpu_start(void); 92 static void apic_send_ipi(int cpun, int ipl); 93 static void apic_set_idlecpu(processorid_t cpun); 94 static void apic_unset_idlecpu(processorid_t cpun); 95 static int apic_intr_enter(int ipl, int *vect); 96 static void apic_setspl(int ipl); 97 static void x2apic_setspl(int ipl); 98 static int apic_addspl(int ipl, int vector, int min_ipl, int max_ipl); 99 static int apic_delspl(int ipl, int vector, int min_ipl, int max_ipl); 100 static void apic_shutdown(int cmd, int fcn); 101 static void apic_preshutdown(int cmd, int fcn); 102 static int apic_disable_intr(processorid_t cpun); 103 static void apic_enable_intr(processorid_t cpun); 104 static processorid_t apic_get_next_processorid(processorid_t cpun); 105 static int apic_get_ipivect(int ipl, int type); 106 static void apic_timer_reprogram(hrtime_t time); 107 static void apic_timer_enable(void); 108 static void apic_timer_disable(void); 109 static void apic_post_cyclic_setup(void *arg); 110 static void apic_intrr_init(int apic_mode); 111 static void apic_record_ioapic_rdt(apic_irq_t *irq_ptr, ioapic_rdt_t *irdt); 112 static void apic_record_msi(apic_irq_t *irq_ptr, msi_regs_t *mregs); 113 114 static int apic_oneshot = 0; 115 int apic_oneshot_enable = 1; /* to allow disabling one-shot capability */ 116 117 /* Now the ones for Dynamic Interrupt distribution */ 118 int apic_enable_dynamic_migration = 0; 119 120 121 /* 122 * These variables are frequently accessed in apic_intr_enter(), 123 * apic_intr_exit and apic_setspl, so group them together 124 */ 125 volatile uint32_t *apicadr = NULL; /* virtual addr of local APIC */ 126 int apic_setspl_delay = 1; /* apic_setspl - delay enable */ 127 int apic_clkvect; 128 129 /* vector at which error interrupts come in */ 130 int apic_errvect; 131 int apic_enable_error_intr = 1; 132 int apic_error_display_delay = 100; 133 134 /* vector at which performance counter overflow interrupts come in */ 135 int apic_cpcovf_vect; 136 int apic_enable_cpcovf_intr = 1; 137 138 /* vector at which CMCI interrupts come in */ 139 int apic_cmci_vect; 140 extern int cmi_enable_cmci; 141 extern void cmi_cmci_trap(void); 142 143 static kmutex_t cmci_cpu_setup_lock; /* protects cmci_cpu_setup_registered */ 144 static int cmci_cpu_setup_registered; 145 146 /* 147 * The following vector assignments influence the value of ipltopri and 148 * vectortoipl. Note that vectors 0 - 0x1f are not used. We can program 149 * idle to 0 and IPL 0 to 0xf to differentiate idle in case 150 * we care to do so in future. Note some IPLs which are rarely used 151 * will share the vector ranges and heavily used IPLs (5 and 6) have 152 * a wide range. 153 * 154 * This array is used to initialize apic_ipls[] (in apic_init()). 155 * 156 * IPL Vector range. as passed to intr_enter 157 * 0 none. 158 * 1,2,3 0x20-0x2f 0x0-0xf 159 * 4 0x30-0x3f 0x10-0x1f 160 * 5 0x40-0x5f 0x20-0x3f 161 * 6 0x60-0x7f 0x40-0x5f 162 * 7,8,9 0x80-0x8f 0x60-0x6f 163 * 10 0x90-0x9f 0x70-0x7f 164 * 11 0xa0-0xaf 0x80-0x8f 165 * ... ... 166 * 15 0xe0-0xef 0xc0-0xcf 167 * 15 0xf0-0xff 0xd0-0xdf 168 */ 169 uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL] = { 170 3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15 171 }; 172 /* 173 * The ipl of an ISR at vector X is apic_vectortoipl[X>>4] 174 * NOTE that this is vector as passed into intr_enter which is 175 * programmed vector - 0x20 (APIC_BASE_VECT) 176 */ 177 178 uchar_t apic_ipltopri[MAXIPL + 1]; /* unix ipl to apic pri */ 179 /* The taskpri to be programmed into apic to mask given ipl */ 180 181 #if defined(__amd64) 182 uchar_t apic_cr8pri[MAXIPL + 1]; /* unix ipl to cr8 pri */ 183 #endif 184 185 /* 186 * Correlation of the hardware vector to the IPL in use, initialized 187 * from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate 188 * to the IPLs in apic_vectortoipl on some systems that share interrupt lines 189 * connected to errata-stricken IOAPICs 190 */ 191 uchar_t apic_ipls[APIC_AVAIL_VECTOR]; 192 193 /* 194 * Patchable global variables. 195 */ 196 int apic_forceload = 0; 197 198 int apic_coarse_hrtime = 1; /* 0 - use accurate slow gethrtime() */ 199 /* 1 - use gettime() for performance */ 200 int apic_flat_model = 0; /* 0 - clustered. 1 - flat */ 201 int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */ 202 int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */ 203 int apic_panic_on_nmi = 0; 204 int apic_panic_on_apic_error = 0; 205 206 int apic_verbose = 0; 207 208 /* minimum number of timer ticks to program to */ 209 int apic_min_timer_ticks = 1; 210 /* 211 * Local static data 212 */ 213 static struct psm_ops apic_ops = { 214 apic_probe, 215 216 apic_init, 217 apic_picinit, 218 apic_intr_enter, 219 apic_intr_exit, 220 apic_setspl, 221 apic_addspl, 222 apic_delspl, 223 apic_disable_intr, 224 apic_enable_intr, 225 (int (*)(int))NULL, /* psm_softlvl_to_irq */ 226 (void (*)(int))NULL, /* psm_set_softintr */ 227 228 apic_set_idlecpu, 229 apic_unset_idlecpu, 230 231 apic_clkinit, 232 apic_getclkirq, 233 (void (*)(void))NULL, /* psm_hrtimeinit */ 234 apic_gethrtime, 235 236 apic_get_next_processorid, 237 apic_cpu_start, 238 apic_post_cpu_start, 239 apic_shutdown, 240 apic_get_ipivect, 241 apic_send_ipi, 242 243 (int (*)(dev_info_t *, int))NULL, /* psm_translate_irq */ 244 (void (*)(int, char *))NULL, /* psm_notify_error */ 245 (void (*)(int))NULL, /* psm_notify_func */ 246 apic_timer_reprogram, 247 apic_timer_enable, 248 apic_timer_disable, 249 apic_post_cyclic_setup, 250 apic_preshutdown, 251 apic_intr_ops, /* Advanced DDI Interrupt framework */ 252 apic_state, /* save, restore apic state for S3 */ 253 }; 254 255 256 static struct psm_info apic_psm_info = { 257 PSM_INFO_VER01_6, /* version */ 258 PSM_OWN_EXCLUSIVE, /* ownership */ 259 (struct psm_ops *)&apic_ops, /* operation */ 260 APIC_PCPLUSMP_NAME, /* machine name */ 261 "pcplusmp v1.4 compatible", 262 }; 263 264 static void *apic_hdlp; 265 266 #ifdef DEBUG 267 int apic_debug = 0; 268 int apic_restrict_vector = 0; 269 270 int apic_debug_msgbuf[APIC_DEBUG_MSGBUFSIZE]; 271 int apic_debug_msgbufindex = 0; 272 273 #endif /* DEBUG */ 274 275 apic_cpus_info_t *apic_cpus; 276 277 cpuset_t apic_cpumask; 278 uint_t apic_picinit_called; 279 280 /* Flag to indicate that we need to shut down all processors */ 281 static uint_t apic_shutdown_processors; 282 283 uint_t apic_nsec_per_intr = 0; 284 285 /* 286 * apic_let_idle_redistribute can have the following values: 287 * 0 - If clock decremented it from 1 to 0, clock has to call redistribute. 288 * apic_redistribute_lock prevents multiple idle cpus from redistributing 289 */ 290 int apic_num_idle_redistributions = 0; 291 static int apic_let_idle_redistribute = 0; 292 static uint_t apic_nticks = 0; 293 static uint_t apic_skipped_redistribute = 0; 294 295 /* to gather intr data and redistribute */ 296 static void apic_redistribute_compute(void); 297 298 static uint_t last_count_read = 0; 299 static lock_t apic_gethrtime_lock; 300 volatile int apic_hrtime_stamp = 0; 301 volatile hrtime_t apic_nsec_since_boot = 0; 302 static uint_t apic_hertz_count; 303 304 uint64_t apic_ticks_per_SFnsecs; /* # of ticks in SF nsecs */ 305 306 static hrtime_t apic_nsec_max; 307 308 static hrtime_t apic_last_hrtime = 0; 309 int apic_hrtime_error = 0; 310 int apic_remote_hrterr = 0; 311 int apic_num_nmis = 0; 312 int apic_apic_error = 0; 313 int apic_num_apic_errors = 0; 314 int apic_num_cksum_errors = 0; 315 316 int apic_error = 0; 317 static int apic_cmos_ssb_set = 0; 318 319 /* use to make sure only one cpu handles the nmi */ 320 static lock_t apic_nmi_lock; 321 /* use to make sure only one cpu handles the error interrupt */ 322 static lock_t apic_error_lock; 323 324 static struct { 325 uchar_t cntl; 326 uchar_t data; 327 } aspen_bmc[] = { 328 { CC_SMS_WR_START, 0x18 }, /* NetFn/LUN */ 329 { CC_SMS_WR_NEXT, 0x24 }, /* Cmd SET_WATCHDOG_TIMER */ 330 { CC_SMS_WR_NEXT, 0x84 }, /* DataByte 1: SMS/OS no log */ 331 { CC_SMS_WR_NEXT, 0x2 }, /* DataByte 2: Power Down */ 332 { CC_SMS_WR_NEXT, 0x0 }, /* DataByte 3: no pre-timeout */ 333 { CC_SMS_WR_NEXT, 0x0 }, /* DataByte 4: timer expir. */ 334 { CC_SMS_WR_NEXT, 0xa }, /* DataByte 5: init countdown */ 335 { CC_SMS_WR_END, 0x0 }, /* DataByte 6: init countdown */ 336 337 { CC_SMS_WR_START, 0x18 }, /* NetFn/LUN */ 338 { CC_SMS_WR_END, 0x22 } /* Cmd RESET_WATCHDOG_TIMER */ 339 }; 340 341 static struct { 342 int port; 343 uchar_t data; 344 } sitka_bmc[] = { 345 { SMS_COMMAND_REGISTER, SMS_WRITE_START }, 346 { SMS_DATA_REGISTER, 0x18 }, /* NetFn/LUN */ 347 { SMS_DATA_REGISTER, 0x24 }, /* Cmd SET_WATCHDOG_TIMER */ 348 { SMS_DATA_REGISTER, 0x84 }, /* DataByte 1: SMS/OS no log */ 349 { SMS_DATA_REGISTER, 0x2 }, /* DataByte 2: Power Down */ 350 { SMS_DATA_REGISTER, 0x0 }, /* DataByte 3: no pre-timeout */ 351 { SMS_DATA_REGISTER, 0x0 }, /* DataByte 4: timer expir. */ 352 { SMS_DATA_REGISTER, 0xa }, /* DataByte 5: init countdown */ 353 { SMS_COMMAND_REGISTER, SMS_WRITE_END }, 354 { SMS_DATA_REGISTER, 0x0 }, /* DataByte 6: init countdown */ 355 356 { SMS_COMMAND_REGISTER, SMS_WRITE_START }, 357 { SMS_DATA_REGISTER, 0x18 }, /* NetFn/LUN */ 358 { SMS_COMMAND_REGISTER, SMS_WRITE_END }, 359 { SMS_DATA_REGISTER, 0x22 } /* Cmd RESET_WATCHDOG_TIMER */ 360 }; 361 362 /* Patchable global variables. */ 363 int apic_kmdb_on_nmi = 0; /* 0 - no, 1 - yes enter kmdb */ 364 uint32_t apic_divide_reg_init = 0; /* 0 - divide by 2 */ 365 366 /* default apic ops without interrupt remapping */ 367 static apic_intrr_ops_t apic_nointrr_ops = { 368 (int (*)(int))return_instr, 369 (void (*)(void))return_instr, 370 (void (*)(apic_irq_t *))return_instr, 371 (void (*)(apic_irq_t *, void *))return_instr, 372 (void (*)(apic_irq_t *))return_instr, 373 apic_record_ioapic_rdt, 374 apic_record_msi, 375 }; 376 377 apic_intrr_ops_t *apic_vt_ops = &apic_nointrr_ops; 378 379 /* 380 * This is the loadable module wrapper 381 */ 382 383 int 384 _init(void) 385 { 386 if (apic_coarse_hrtime) 387 apic_ops.psm_gethrtime = &apic_gettime; 388 return (psm_mod_init(&apic_hdlp, &apic_psm_info)); 389 } 390 391 int 392 _fini(void) 393 { 394 return (psm_mod_fini(&apic_hdlp, &apic_psm_info)); 395 } 396 397 int 398 _info(struct modinfo *modinfop) 399 { 400 return (psm_mod_info(&apic_hdlp, &apic_psm_info, modinfop)); 401 } 402 403 404 static int 405 apic_probe() 406 { 407 return (apic_probe_common(apic_psm_info.p_mach_idstring)); 408 } 409 410 void 411 apic_init() 412 { 413 int i; 414 int j = 1; 415 416 apic_ipltopri[0] = APIC_VECTOR_PER_IPL; /* leave 0 for idle */ 417 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) { 418 if ((i < ((APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL) - 1)) && 419 (apic_vectortoipl[i + 1] == apic_vectortoipl[i])) 420 /* get to highest vector at the same ipl */ 421 continue; 422 for (; j <= apic_vectortoipl[i]; j++) { 423 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + 424 APIC_BASE_VECT; 425 } 426 } 427 for (; j < MAXIPL + 1; j++) 428 /* fill up any empty ipltopri slots */ 429 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + APIC_BASE_VECT; 430 apic_init_common(); 431 #if defined(__amd64) 432 /* 433 * Make cpu-specific interrupt info point to cr8pri vector 434 */ 435 for (i = 0; i <= MAXIPL; i++) 436 apic_cr8pri[i] = apic_ipltopri[i] >> APIC_IPL_SHIFT; 437 CPU->cpu_pri_data = apic_cr8pri; 438 #endif /* __amd64 */ 439 440 /* 441 * initialize interrupt remapping before apic 442 * hardware initialization 443 */ 444 apic_intrr_init(apic_mode); 445 } 446 447 /* 448 * handler for APIC Error interrupt. Just print a warning and continue 449 */ 450 static int 451 apic_error_intr() 452 { 453 uint_t error0, error1, error; 454 uint_t i; 455 456 /* 457 * We need to write before read as per 7.4.17 of system prog manual. 458 * We do both and or the results to be safe 459 */ 460 error0 = apic_reg_ops->apic_read(APIC_ERROR_STATUS); 461 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 462 error1 = apic_reg_ops->apic_read(APIC_ERROR_STATUS); 463 error = error0 | error1; 464 465 /* 466 * Clear the APIC error status (do this on all cpus that enter here) 467 * (two writes are required due to the semantics of accessing the 468 * error status register.) 469 */ 470 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 471 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 472 473 /* 474 * Prevent more than 1 CPU from handling error interrupt causing 475 * double printing (interleave of characters from multiple 476 * CPU's when using prom_printf) 477 */ 478 if (lock_try(&apic_error_lock) == 0) 479 return (error ? DDI_INTR_CLAIMED : DDI_INTR_UNCLAIMED); 480 if (error) { 481 #if DEBUG 482 if (apic_debug) 483 debug_enter("pcplusmp: APIC Error interrupt received"); 484 #endif /* DEBUG */ 485 if (apic_panic_on_apic_error) 486 cmn_err(CE_PANIC, 487 "APIC Error interrupt on CPU %d. Status = %x\n", 488 psm_get_cpu_id(), error); 489 else { 490 if ((error & ~APIC_CS_ERRORS) == 0) { 491 /* cksum error only */ 492 apic_error |= APIC_ERR_APIC_ERROR; 493 apic_apic_error |= error; 494 apic_num_apic_errors++; 495 apic_num_cksum_errors++; 496 } else { 497 /* 498 * prom_printf is the best shot we have of 499 * something which is problem free from 500 * high level/NMI type of interrupts 501 */ 502 prom_printf("APIC Error interrupt on CPU %d. " 503 "Status 0 = %x, Status 1 = %x\n", 504 psm_get_cpu_id(), error0, error1); 505 apic_error |= APIC_ERR_APIC_ERROR; 506 apic_apic_error |= error; 507 apic_num_apic_errors++; 508 for (i = 0; i < apic_error_display_delay; i++) { 509 tenmicrosec(); 510 } 511 /* 512 * provide more delay next time limited to 513 * roughly 1 clock tick time 514 */ 515 if (apic_error_display_delay < 500) 516 apic_error_display_delay *= 2; 517 } 518 } 519 lock_clear(&apic_error_lock); 520 return (DDI_INTR_CLAIMED); 521 } else { 522 lock_clear(&apic_error_lock); 523 return (DDI_INTR_UNCLAIMED); 524 } 525 /* NOTREACHED */ 526 } 527 528 /* 529 * Turn off the mask bit in the performance counter Local Vector Table entry. 530 */ 531 static void 532 apic_cpcovf_mask_clear(void) 533 { 534 apic_reg_ops->apic_write(APIC_PCINT_VECT, 535 (apic_reg_ops->apic_read(APIC_PCINT_VECT) & ~APIC_LVT_MASK)); 536 } 537 538 /*ARGSUSED*/ 539 static int 540 apic_cmci_enable(xc_arg_t arg1, xc_arg_t arg2, xc_arg_t arg3) 541 { 542 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect); 543 return (0); 544 } 545 546 /*ARGSUSED*/ 547 static int 548 apic_cmci_disable(xc_arg_t arg1, xc_arg_t arg2, xc_arg_t arg3) 549 { 550 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect | AV_MASK); 551 return (0); 552 } 553 554 /*ARGSUSED*/ 555 static int 556 cmci_cpu_setup(cpu_setup_t what, int cpuid, void *arg) 557 { 558 cpuset_t cpu_set; 559 560 CPUSET_ONLY(cpu_set, cpuid); 561 562 switch (what) { 563 case CPU_ON: 564 xc_call(NULL, NULL, NULL, X_CALL_HIPRI, cpu_set, 565 (xc_func_t)apic_cmci_enable); 566 break; 567 568 case CPU_OFF: 569 xc_call(NULL, NULL, NULL, X_CALL_HIPRI, cpu_set, 570 (xc_func_t)apic_cmci_disable); 571 break; 572 573 default: 574 break; 575 } 576 577 return (0); 578 } 579 580 static void 581 apic_init_intr() 582 { 583 processorid_t cpun = psm_get_cpu_id(); 584 uint_t nlvt; 585 uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR; 586 587 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL); 588 589 if (apic_mode == LOCAL_APIC) { 590 /* 591 * We are running APIC in MMIO mode. 592 */ 593 if (apic_flat_model) { 594 apic_reg_ops->apic_write(APIC_FORMAT_REG, 595 APIC_FLAT_MODEL); 596 } else { 597 apic_reg_ops->apic_write(APIC_FORMAT_REG, 598 APIC_CLUSTER_MODEL); 599 } 600 601 apic_reg_ops->apic_write(APIC_DEST_REG, 602 AV_HIGH_ORDER >> cpun); 603 } 604 605 if (apic_direct_EOI) { 606 /* 607 * Set 12th bit in Spurious Interrupt Vector 608 * Register to support level triggered interrupt 609 * directed EOI. 610 */ 611 svr |= (0x1 << APIC_SVR); 612 } 613 614 /* need to enable APIC before unmasking NMI */ 615 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr); 616 617 /* 618 * Presence of an invalid vector with delivery mode AV_FIXED can 619 * cause an error interrupt, even if the entry is masked...so 620 * write a valid vector to LVT entries along with the mask bit 621 */ 622 623 /* All APICs have timer and LINT0/1 */ 624 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ); 625 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ); 626 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */ 627 628 /* 629 * On integrated APICs, the number of LVT entries is 630 * 'Max LVT entry' + 1; on 82489DX's (non-integrated 631 * APICs), nlvt is "3" (LINT0, LINT1, and timer) 632 */ 633 634 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) { 635 nlvt = 3; 636 } else { 637 nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) & 638 0xFF) + 1; 639 } 640 641 if (nlvt >= 5) { 642 /* Enable performance counter overflow interrupt */ 643 644 if ((x86_feature & X86_MSR) != X86_MSR) 645 apic_enable_cpcovf_intr = 0; 646 if (apic_enable_cpcovf_intr) { 647 if (apic_cpcovf_vect == 0) { 648 int ipl = APIC_PCINT_IPL; 649 int irq = apic_get_ipivect(ipl, -1); 650 651 ASSERT(irq != -1); 652 apic_cpcovf_vect = 653 apic_irq_table[irq]->airq_vector; 654 ASSERT(apic_cpcovf_vect); 655 (void) add_avintr(NULL, ipl, 656 (avfunc)kcpc_hw_overflow_intr, 657 "apic pcint", irq, NULL, NULL, NULL, NULL); 658 kcpc_hw_overflow_intr_installed = 1; 659 kcpc_hw_enable_cpc_intr = 660 apic_cpcovf_mask_clear; 661 } 662 apic_reg_ops->apic_write(APIC_PCINT_VECT, 663 apic_cpcovf_vect); 664 } 665 } 666 667 if (nlvt >= 6) { 668 /* Only mask TM intr if the BIOS apparently doesn't use it */ 669 670 uint32_t lvtval; 671 672 lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT); 673 if (((lvtval & AV_MASK) == AV_MASK) || 674 ((lvtval & AV_DELIV_MODE) != AV_SMI)) { 675 apic_reg_ops->apic_write(APIC_THERM_VECT, 676 AV_MASK|APIC_RESV_IRQ); 677 } 678 } 679 680 /* Enable error interrupt */ 681 682 if (nlvt >= 4 && apic_enable_error_intr) { 683 if (apic_errvect == 0) { 684 int ipl = 0xf; /* get highest priority intr */ 685 int irq = apic_get_ipivect(ipl, -1); 686 687 ASSERT(irq != -1); 688 apic_errvect = apic_irq_table[irq]->airq_vector; 689 ASSERT(apic_errvect); 690 /* 691 * Not PSMI compliant, but we are going to merge 692 * with ON anyway 693 */ 694 (void) add_avintr((void *)NULL, ipl, 695 (avfunc)apic_error_intr, "apic error intr", 696 irq, NULL, NULL, NULL, NULL); 697 } 698 apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect); 699 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 700 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 701 } 702 703 /* Enable CMCI interrupt */ 704 if (cmi_enable_cmci) { 705 706 mutex_enter(&cmci_cpu_setup_lock); 707 if (cmci_cpu_setup_registered == 0) { 708 mutex_enter(&cpu_lock); 709 register_cpu_setup_func(cmci_cpu_setup, NULL); 710 mutex_exit(&cpu_lock); 711 cmci_cpu_setup_registered = 1; 712 } 713 mutex_exit(&cmci_cpu_setup_lock); 714 715 if (apic_cmci_vect == 0) { 716 int ipl = 0x2; 717 int irq = apic_get_ipivect(ipl, -1); 718 719 ASSERT(irq != -1); 720 apic_cmci_vect = apic_irq_table[irq]->airq_vector; 721 ASSERT(apic_cmci_vect); 722 723 (void) add_avintr(NULL, ipl, 724 (avfunc)cmi_cmci_trap, 725 "apic cmci intr", irq, NULL, NULL, NULL, NULL); 726 } 727 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect); 728 } 729 } 730 731 static void 732 apic_disable_local_apic() 733 { 734 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL); 735 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK); 736 737 /* local intr reg 0 */ 738 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK); 739 740 /* disable NMI */ 741 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_MASK); 742 743 /* and error interrupt */ 744 apic_reg_ops->apic_write(APIC_ERR_VECT, AV_MASK); 745 746 /* and perf counter intr */ 747 apic_reg_ops->apic_write(APIC_PCINT_VECT, AV_MASK); 748 749 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, APIC_SPUR_INTR); 750 } 751 752 static void 753 apic_picinit(void) 754 { 755 int i, j; 756 uint_t isr; 757 uint32_t ver; 758 759 /* 760 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr 761 * bit on without clearing it with EOI. Since softint 762 * uses vector 0x20 to interrupt itself, so softint will 763 * not work on this machine. In order to fix this problem 764 * a check is made to verify all the isr bits are clear. 765 * If not, EOIs are issued to clear the bits. 766 */ 767 for (i = 7; i >= 1; i--) { 768 isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4)); 769 if (isr != 0) 770 for (j = 0; ((j < 32) && (isr != 0)); j++) 771 if (isr & (1 << j)) { 772 apic_reg_ops->apic_write( 773 APIC_EOI_REG, 0); 774 isr &= ~(1 << j); 775 apic_error |= APIC_ERR_BOOT_EOI; 776 } 777 } 778 779 /* set a flag so we know we have run apic_picinit() */ 780 apic_picinit_called = 1; 781 LOCK_INIT_CLEAR(&apic_gethrtime_lock); 782 LOCK_INIT_CLEAR(&apic_ioapic_lock); 783 LOCK_INIT_CLEAR(&apic_error_lock); 784 785 picsetup(); /* initialise the 8259 */ 786 787 /* add nmi handler - least priority nmi handler */ 788 LOCK_INIT_CLEAR(&apic_nmi_lock); 789 790 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr, 791 "pcplusmp NMI handler", (caddr_t)NULL)) 792 cmn_err(CE_WARN, "pcplusmp: Unable to add nmi handler"); 793 794 ver = apic_reg_ops->apic_read(APIC_VERS_REG); 795 /* 796 * In order to determine support for Directed EOI capability, 797 * we check for 24th bit in Local APIC Version Register. 798 */ 799 if (ver & (0x1 << APIC_DIRECTED_EOI)) { 800 apic_direct_EOI = 1; 801 apic_change_eoi(); 802 } 803 804 apic_init_intr(); 805 806 /* enable apic mode if imcr present */ 807 if (apic_imcrp) { 808 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT); 809 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC); 810 } 811 812 ioapic_init_intr(IOAPIC_MASK); 813 } 814 815 816 /*ARGSUSED1*/ 817 static int 818 apic_cpu_start(processorid_t cpun, caddr_t arg) 819 { 820 int loop_count; 821 uint32_t vector; 822 uint_t cpu_id; 823 ulong_t iflag; 824 825 cpu_id = apic_cpus[cpun].aci_local_id; 826 827 apic_cmos_ssb_set = 1; 828 829 /* 830 * Interrupts on BSP cpu will be disabled during these startup 831 * steps in order to avoid unwanted side effects from 832 * executing interrupt handlers on a problematic BIOS. 833 */ 834 835 iflag = intr_clear(); 836 outb(CMOS_ADDR, SSB); 837 outb(CMOS_DATA, BIOS_SHUTDOWN); 838 839 /* 840 * According to X2APIC specification in section '2.3.5.1' of 841 * Interrupt Command Register Semantics, the semantics of 842 * programming the Interrupt Command Register to dispatch an interrupt 843 * is simplified. A single MSR write to the 64-bit ICR is required 844 * for dispatching an interrupt. Specifically, with the 64-bit MSR 845 * interface to ICR, system software is not required to check the 846 * status of the delivery status bit prior to writing to the ICR 847 * to send an IPI. With the removal of the Delivery Status bit, 848 * system software no longer has a reason to read the ICR. It remains 849 * readable only to aid in debugging. 850 */ 851 #ifdef DEBUG 852 APIC_AV_PENDING_SET(); 853 #else 854 if (apic_mode == LOCAL_APIC) { 855 APIC_AV_PENDING_SET(); 856 } 857 #endif /* DEBUG */ 858 859 /* for integrated - make sure there is one INIT IPI in buffer */ 860 /* for external - it will wake up the cpu */ 861 apic_reg_ops->apic_write_int_cmd(cpu_id, AV_ASSERT | AV_RESET); 862 863 /* If only 1 CPU is installed, PENDING bit will not go low */ 864 for (loop_count = 0x1000; loop_count; loop_count--) { 865 if (apic_mode == LOCAL_APIC && 866 apic_reg_ops->apic_read(APIC_INT_CMD1) & AV_PENDING) 867 apic_ret(); 868 else 869 break; 870 } 871 872 apic_reg_ops->apic_write_int_cmd(cpu_id, AV_DEASSERT | AV_RESET); 873 874 drv_usecwait(20000); /* 20 milli sec */ 875 876 if (apic_cpus[cpun].aci_local_ver >= APIC_INTEGRATED_VERS) { 877 /* integrated apic */ 878 879 vector = (rm_platter_pa >> MMU_PAGESHIFT) & 880 (APIC_VECTOR_MASK | APIC_IPL_MASK); 881 882 /* to offset the INIT IPI queue up in the buffer */ 883 apic_reg_ops->apic_write_int_cmd(cpu_id, vector | AV_STARTUP); 884 885 drv_usecwait(200); /* 20 micro sec */ 886 887 apic_reg_ops->apic_write_int_cmd(cpu_id, vector | AV_STARTUP); 888 889 drv_usecwait(200); /* 20 micro sec */ 890 } 891 intr_restore(iflag); 892 return (0); 893 } 894 895 896 #ifdef DEBUG 897 int apic_break_on_cpu = 9; 898 int apic_stretch_interrupts = 0; 899 int apic_stretch_ISR = 1 << 3; /* IPL of 3 matches nothing now */ 900 901 void 902 apic_break() 903 { 904 } 905 #endif /* DEBUG */ 906 907 /* 908 * platform_intr_enter 909 * 910 * Called at the beginning of the interrupt service routine to 911 * mask all level equal to and below the interrupt priority 912 * of the interrupting vector. An EOI should be given to 913 * the interrupt controller to enable other HW interrupts. 914 * 915 * Return -1 for spurious interrupts 916 * 917 */ 918 /*ARGSUSED*/ 919 static int 920 apic_intr_enter(int ipl, int *vectorp) 921 { 922 uchar_t vector; 923 int nipl; 924 int irq; 925 ulong_t iflag; 926 apic_cpus_info_t *cpu_infop; 927 928 /* 929 * The real vector delivered is (*vectorp + 0x20), but our caller 930 * subtracts 0x20 from the vector before passing it to us. 931 * (That's why APIC_BASE_VECT is 0x20.) 932 */ 933 vector = (uchar_t)*vectorp; 934 935 /* if interrupted by the clock, increment apic_nsec_since_boot */ 936 if (vector == apic_clkvect) { 937 if (!apic_oneshot) { 938 /* NOTE: this is not MT aware */ 939 apic_hrtime_stamp++; 940 apic_nsec_since_boot += apic_nsec_per_intr; 941 apic_hrtime_stamp++; 942 last_count_read = apic_hertz_count; 943 apic_redistribute_compute(); 944 } 945 946 /* We will avoid all the book keeping overhead for clock */ 947 nipl = apic_ipls[vector]; 948 949 *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT]; 950 if (apic_mode == LOCAL_APIC) { 951 #if defined(__amd64) 952 setcr8((ulong_t)(apic_ipltopri[nipl] >> 953 APIC_IPL_SHIFT)); 954 #else 955 LOCAL_APIC_WRITE_REG(APIC_TASK_REG, 956 (uint32_t)apic_ipltopri[nipl]); 957 #endif 958 LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0); 959 } else { 960 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[nipl]); 961 X2APIC_WRITE(APIC_EOI_REG, 0); 962 } 963 964 return (nipl); 965 } 966 967 cpu_infop = &apic_cpus[psm_get_cpu_id()]; 968 969 if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) { 970 cpu_infop->aci_spur_cnt++; 971 return (APIC_INT_SPURIOUS); 972 } 973 974 /* Check if the vector we got is really what we need */ 975 if (apic_revector_pending) { 976 /* 977 * Disable interrupts for the duration of 978 * the vector translation to prevent a self-race for 979 * the apic_revector_lock. This cannot be done 980 * in apic_xlate_vector because it is recursive and 981 * we want the vector translation to be atomic with 982 * respect to other (higher-priority) interrupts. 983 */ 984 iflag = intr_clear(); 985 vector = apic_xlate_vector(vector + APIC_BASE_VECT) - 986 APIC_BASE_VECT; 987 intr_restore(iflag); 988 } 989 990 nipl = apic_ipls[vector]; 991 *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT]; 992 993 if (apic_mode == LOCAL_APIC) { 994 #if defined(__amd64) 995 setcr8((ulong_t)(apic_ipltopri[nipl] >> APIC_IPL_SHIFT)); 996 #else 997 LOCAL_APIC_WRITE_REG(APIC_TASK_REG, 998 (uint32_t)apic_ipltopri[nipl]); 999 #endif 1000 } else { 1001 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[nipl]); 1002 } 1003 1004 cpu_infop->aci_current[nipl] = (uchar_t)irq; 1005 cpu_infop->aci_curipl = (uchar_t)nipl; 1006 cpu_infop->aci_ISR_in_progress |= 1 << nipl; 1007 1008 /* 1009 * apic_level_intr could have been assimilated into the irq struct. 1010 * but, having it as a character array is more efficient in terms of 1011 * cache usage. So, we leave it as is. 1012 */ 1013 if (!apic_level_intr[irq]) { 1014 if (apic_mode == LOCAL_APIC) 1015 LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0); 1016 else 1017 X2APIC_WRITE(APIC_EOI_REG, 0); 1018 } 1019 1020 #ifdef DEBUG 1021 APIC_DEBUG_BUF_PUT(vector); 1022 APIC_DEBUG_BUF_PUT(irq); 1023 APIC_DEBUG_BUF_PUT(nipl); 1024 APIC_DEBUG_BUF_PUT(psm_get_cpu_id()); 1025 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl))) 1026 drv_usecwait(apic_stretch_interrupts); 1027 1028 if (apic_break_on_cpu == psm_get_cpu_id()) 1029 apic_break(); 1030 #endif /* DEBUG */ 1031 return (nipl); 1032 } 1033 1034 /* 1035 * This macro is a common code used by MMIO local apic and X2APIC 1036 * local apic. 1037 */ 1038 #define APIC_INTR_EXIT() \ 1039 { \ 1040 cpu_infop = &apic_cpus[psm_get_cpu_id()]; \ 1041 if (apic_level_intr[irq]) \ 1042 apic_reg_ops->apic_send_eoi(irq); \ 1043 cpu_infop->aci_curipl = (uchar_t)prev_ipl; \ 1044 /* ISR above current pri could not be in progress */ \ 1045 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1; \ 1046 } 1047 1048 /* 1049 * Any changes made to this function must also change X2APIC 1050 * version of intr_exit. 1051 */ 1052 void 1053 apic_intr_exit(int prev_ipl, int irq) 1054 { 1055 apic_cpus_info_t *cpu_infop; 1056 1057 #if defined(__amd64) 1058 setcr8((ulong_t)apic_cr8pri[prev_ipl]); 1059 #else 1060 apicadr[APIC_TASK_REG] = apic_ipltopri[prev_ipl]; 1061 #endif 1062 1063 APIC_INTR_EXIT(); 1064 } 1065 1066 /* 1067 * Same as apic_intr_exit() except it uses MSR rather than MMIO 1068 * to access local apic registers. 1069 */ 1070 void 1071 x2apic_intr_exit(int prev_ipl, int irq) 1072 { 1073 apic_cpus_info_t *cpu_infop; 1074 1075 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[prev_ipl]); 1076 APIC_INTR_EXIT(); 1077 } 1078 1079 intr_exit_fn_t 1080 psm_intr_exit_fn(void) 1081 { 1082 if (apic_mode == LOCAL_X2APIC) 1083 return (x2apic_intr_exit); 1084 1085 return (apic_intr_exit); 1086 } 1087 1088 /* 1089 * Mask all interrupts below or equal to the given IPL. 1090 * Any changes made to this function must also change X2APIC 1091 * version of setspl. 1092 */ 1093 static void 1094 apic_setspl(int ipl) 1095 { 1096 #if defined(__amd64) 1097 setcr8((ulong_t)apic_cr8pri[ipl]); 1098 #else 1099 apicadr[APIC_TASK_REG] = apic_ipltopri[ipl]; 1100 #endif 1101 1102 /* interrupts at ipl above this cannot be in progress */ 1103 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1; 1104 /* 1105 * this is a patch fix for the ALR QSMP P5 machine, so that interrupts 1106 * have enough time to come in before the priority is raised again 1107 * during the idle() loop. 1108 */ 1109 if (apic_setspl_delay) 1110 (void) apic_reg_ops->apic_get_pri(); 1111 } 1112 1113 /* 1114 * X2APIC version of setspl. 1115 * Mask all interrupts below or equal to the given IPL 1116 */ 1117 static void 1118 x2apic_setspl(int ipl) 1119 { 1120 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[ipl]); 1121 1122 /* interrupts at ipl above this cannot be in progress */ 1123 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1; 1124 } 1125 1126 /* 1127 * generates an interprocessor interrupt to another CPU. Any changes made to 1128 * this routine must be accompanied by similar changes to 1129 * apic_common_send_ipi(). 1130 */ 1131 static void 1132 apic_send_ipi(int cpun, int ipl) 1133 { 1134 int vector; 1135 ulong_t flag; 1136 1137 vector = apic_resv_vector[ipl]; 1138 1139 ASSERT((vector >= APIC_BASE_VECT) && (vector <= APIC_SPUR_INTR)); 1140 1141 flag = intr_clear(); 1142 1143 APIC_AV_PENDING_SET(); 1144 1145 apic_reg_ops->apic_write_int_cmd(apic_cpus[cpun].aci_local_id, 1146 vector); 1147 1148 intr_restore(flag); 1149 } 1150 1151 1152 /*ARGSUSED*/ 1153 static void 1154 apic_set_idlecpu(processorid_t cpun) 1155 { 1156 } 1157 1158 /*ARGSUSED*/ 1159 static void 1160 apic_unset_idlecpu(processorid_t cpun) 1161 { 1162 } 1163 1164 1165 void 1166 apic_ret() 1167 { 1168 } 1169 1170 /* 1171 * If apic_coarse_time == 1, then apic_gettime() is used instead of 1172 * apic_gethrtime(). This is used for performance instead of accuracy. 1173 */ 1174 1175 static hrtime_t 1176 apic_gettime() 1177 { 1178 int old_hrtime_stamp; 1179 hrtime_t temp; 1180 1181 /* 1182 * In one-shot mode, we do not keep time, so if anyone 1183 * calls psm_gettime() directly, we vector over to 1184 * gethrtime(). 1185 * one-shot mode MUST NOT be enabled if this psm is the source of 1186 * hrtime. 1187 */ 1188 1189 if (apic_oneshot) 1190 return (gethrtime()); 1191 1192 1193 gettime_again: 1194 while ((old_hrtime_stamp = apic_hrtime_stamp) & 1) 1195 apic_ret(); 1196 1197 temp = apic_nsec_since_boot; 1198 1199 if (apic_hrtime_stamp != old_hrtime_stamp) { /* got an interrupt */ 1200 goto gettime_again; 1201 } 1202 return (temp); 1203 } 1204 1205 /* 1206 * Here we return the number of nanoseconds since booting. Note every 1207 * clock interrupt increments apic_nsec_since_boot by the appropriate 1208 * amount. 1209 */ 1210 static hrtime_t 1211 apic_gethrtime() 1212 { 1213 int curr_timeval, countval, elapsed_ticks; 1214 int old_hrtime_stamp, status; 1215 hrtime_t temp; 1216 uint32_t cpun; 1217 ulong_t oflags; 1218 1219 /* 1220 * In one-shot mode, we do not keep time, so if anyone 1221 * calls psm_gethrtime() directly, we vector over to 1222 * gethrtime(). 1223 * one-shot mode MUST NOT be enabled if this psm is the source of 1224 * hrtime. 1225 */ 1226 1227 if (apic_oneshot) 1228 return (gethrtime()); 1229 1230 oflags = intr_clear(); /* prevent migration */ 1231 1232 cpun = apic_reg_ops->apic_read(APIC_LID_REG); 1233 if (apic_mode == LOCAL_APIC) 1234 cpun >>= APIC_ID_BIT_OFFSET; 1235 1236 lock_set(&apic_gethrtime_lock); 1237 1238 gethrtime_again: 1239 while ((old_hrtime_stamp = apic_hrtime_stamp) & 1) 1240 apic_ret(); 1241 1242 /* 1243 * Check to see which CPU we are on. Note the time is kept on 1244 * the local APIC of CPU 0. If on CPU 0, simply read the current 1245 * counter. If on another CPU, issue a remote read command to CPU 0. 1246 */ 1247 if (cpun == apic_cpus[0].aci_local_id) { 1248 countval = apic_reg_ops->apic_read(APIC_CURR_COUNT); 1249 } else { 1250 #ifdef DEBUG 1251 APIC_AV_PENDING_SET(); 1252 #else 1253 if (apic_mode == LOCAL_APIC) 1254 APIC_AV_PENDING_SET(); 1255 #endif /* DEBUG */ 1256 1257 apic_reg_ops->apic_write_int_cmd( 1258 apic_cpus[0].aci_local_id, APIC_CURR_ADD | AV_REMOTE); 1259 1260 while ((status = apic_reg_ops->apic_read(APIC_INT_CMD1)) 1261 & AV_READ_PENDING) { 1262 apic_ret(); 1263 } 1264 1265 if (status & AV_REMOTE_STATUS) /* 1 = valid */ 1266 countval = apic_reg_ops->apic_read(APIC_REMOTE_READ); 1267 else { /* 0 = invalid */ 1268 apic_remote_hrterr++; 1269 /* 1270 * return last hrtime right now, will need more 1271 * testing if change to retry 1272 */ 1273 temp = apic_last_hrtime; 1274 1275 lock_clear(&apic_gethrtime_lock); 1276 1277 intr_restore(oflags); 1278 1279 return (temp); 1280 } 1281 } 1282 if (countval > last_count_read) 1283 countval = 0; 1284 else 1285 last_count_read = countval; 1286 1287 elapsed_ticks = apic_hertz_count - countval; 1288 1289 curr_timeval = APIC_TICKS_TO_NSECS(elapsed_ticks); 1290 temp = apic_nsec_since_boot + curr_timeval; 1291 1292 if (apic_hrtime_stamp != old_hrtime_stamp) { /* got an interrupt */ 1293 /* we might have clobbered last_count_read. Restore it */ 1294 last_count_read = apic_hertz_count; 1295 goto gethrtime_again; 1296 } 1297 1298 if (temp < apic_last_hrtime) { 1299 /* return last hrtime if error occurs */ 1300 apic_hrtime_error++; 1301 temp = apic_last_hrtime; 1302 } 1303 else 1304 apic_last_hrtime = temp; 1305 1306 lock_clear(&apic_gethrtime_lock); 1307 intr_restore(oflags); 1308 1309 return (temp); 1310 } 1311 1312 /* apic NMI handler */ 1313 /*ARGSUSED*/ 1314 static void 1315 apic_nmi_intr(caddr_t arg, struct regs *rp) 1316 { 1317 if (apic_shutdown_processors) { 1318 apic_disable_local_apic(); 1319 return; 1320 } 1321 1322 apic_error |= APIC_ERR_NMI; 1323 1324 if (!lock_try(&apic_nmi_lock)) 1325 return; 1326 apic_num_nmis++; 1327 1328 if (apic_kmdb_on_nmi && psm_debugger()) { 1329 debug_enter("NMI received: entering kmdb\n"); 1330 } else if (apic_panic_on_nmi) { 1331 /* Keep panic from entering kmdb. */ 1332 nopanicdebug = 1; 1333 panic("NMI received\n"); 1334 } else { 1335 /* 1336 * prom_printf is the best shot we have of something which is 1337 * problem free from high level/NMI type of interrupts 1338 */ 1339 prom_printf("NMI received\n"); 1340 } 1341 1342 lock_clear(&apic_nmi_lock); 1343 } 1344 1345 /*ARGSUSED*/ 1346 static int 1347 apic_addspl(int irqno, int ipl, int min_ipl, int max_ipl) 1348 { 1349 return (apic_addspl_common(irqno, ipl, min_ipl, max_ipl)); 1350 } 1351 1352 static int 1353 apic_delspl(int irqno, int ipl, int min_ipl, int max_ipl) 1354 { 1355 return (apic_delspl_common(irqno, ipl, min_ipl, max_ipl)); 1356 } 1357 1358 static int 1359 apic_post_cpu_start() 1360 { 1361 int cpun; 1362 static int cpus_started = 1; 1363 struct psm_ops *pops = &apic_ops; 1364 1365 /* We know this CPU + BSP started successfully. */ 1366 cpus_started++; 1367 1368 /* 1369 * On BSP we would have enabled X2APIC, if supported by processor, 1370 * in acpi_probe(), but on AP we do it here. 1371 * 1372 * We enable X2APIC mode only if BSP is running in X2APIC & the 1373 * local APIC mode of the current CPU is MMIO (xAPIC). 1374 */ 1375 if (apic_mode == LOCAL_X2APIC && apic_detect_x2apic() && 1376 apic_local_mode() == LOCAL_APIC) { 1377 apic_enable_x2apic(); 1378 } 1379 1380 /* 1381 * We change psm_send_ipi and send_dirintf only if Solaris 1382 * is booted in kmdb & the current CPU is the last CPU being 1383 * brought up. We don't need to do anything if Solaris is running 1384 * in MMIO mode (xAPIC). 1385 */ 1386 if ((boothowto & RB_DEBUG) && 1387 (cpus_started == boot_ncpus || cpus_started == apic_nproc) && 1388 apic_mode == LOCAL_X2APIC) { 1389 /* 1390 * We no longer need help from apic_common_send_ipi() 1391 * since we will not start any more CPUs. 1392 * 1393 * We will need to revisit this if we start supporting 1394 * hot-plugging of CPUs. 1395 */ 1396 pops->psm_send_ipi = x2apic_send_ipi; 1397 send_dirintf = pops->psm_send_ipi; 1398 } 1399 1400 splx(ipltospl(LOCK_LEVEL)); 1401 apic_init_intr(); 1402 1403 /* 1404 * since some systems don't enable the internal cache on the non-boot 1405 * cpus, so we have to enable them here 1406 */ 1407 setcr0(getcr0() & ~(CR0_CD | CR0_NW)); 1408 1409 #ifdef DEBUG 1410 APIC_AV_PENDING_SET(); 1411 #else 1412 if (apic_mode == LOCAL_APIC) 1413 APIC_AV_PENDING_SET(); 1414 #endif /* DEBUG */ 1415 1416 /* 1417 * We may be booting, or resuming from suspend; aci_status will 1418 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the 1419 * APIC_CPU_ONLINE flag here rather than setting aci_status completely. 1420 */ 1421 cpun = psm_get_cpu_id(); 1422 apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE; 1423 1424 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init); 1425 return (PSM_SUCCESS); 1426 } 1427 1428 processorid_t 1429 apic_get_next_processorid(processorid_t cpu_id) 1430 { 1431 1432 int i; 1433 1434 if (cpu_id == -1) 1435 return ((processorid_t)0); 1436 1437 for (i = cpu_id + 1; i < NCPU; i++) { 1438 if (CPU_IN_SET(apic_cpumask, i)) 1439 return (i); 1440 } 1441 1442 return ((processorid_t)-1); 1443 } 1444 1445 1446 /* 1447 * type == -1 indicates it is an internal request. Do not change 1448 * resv_vector for these requests 1449 */ 1450 static int 1451 apic_get_ipivect(int ipl, int type) 1452 { 1453 uchar_t vector; 1454 int irq; 1455 1456 if (irq = apic_allocate_irq(APIC_VECTOR(ipl))) { 1457 if (vector = apic_allocate_vector(ipl, irq, 1)) { 1458 apic_irq_table[irq]->airq_mps_intr_index = 1459 RESERVE_INDEX; 1460 apic_irq_table[irq]->airq_vector = vector; 1461 if (type != -1) { 1462 apic_resv_vector[ipl] = vector; 1463 } 1464 return (irq); 1465 } 1466 } 1467 apic_error |= APIC_ERR_GET_IPIVECT_FAIL; 1468 return (-1); /* shouldn't happen */ 1469 } 1470 1471 static int 1472 apic_getclkirq(int ipl) 1473 { 1474 int irq; 1475 1476 if ((irq = apic_get_ipivect(ipl, -1)) == -1) 1477 return (-1); 1478 /* 1479 * Note the vector in apic_clkvect for per clock handling. 1480 */ 1481 apic_clkvect = apic_irq_table[irq]->airq_vector - APIC_BASE_VECT; 1482 APIC_VERBOSE_IOAPIC((CE_NOTE, "get_clkirq: vector = %x\n", 1483 apic_clkvect)); 1484 return (irq); 1485 } 1486 1487 1488 /* 1489 * Return the number of APIC clock ticks elapsed for 8245 to decrement 1490 * (APIC_TIME_COUNT + pit_ticks_adj) ticks. 1491 */ 1492 static uint_t 1493 apic_calibrate(volatile uint32_t *addr, uint16_t *pit_ticks_adj) 1494 { 1495 uint8_t pit_tick_lo; 1496 uint16_t pit_tick, target_pit_tick; 1497 uint32_t start_apic_tick, end_apic_tick; 1498 ulong_t iflag; 1499 uint32_t reg; 1500 1501 reg = addr + APIC_CURR_COUNT - apicadr; 1502 1503 iflag = intr_clear(); 1504 1505 do { 1506 pit_tick_lo = inb(PITCTR0_PORT); 1507 pit_tick = (inb(PITCTR0_PORT) << 8) | pit_tick_lo; 1508 } while (pit_tick < APIC_TIME_MIN || 1509 pit_tick_lo <= APIC_LB_MIN || pit_tick_lo >= APIC_LB_MAX); 1510 1511 /* 1512 * Wait for the 8254 to decrement by 5 ticks to ensure 1513 * we didn't start in the middle of a tick. 1514 * Compare with 0x10 for the wrap around case. 1515 */ 1516 target_pit_tick = pit_tick - 5; 1517 do { 1518 pit_tick_lo = inb(PITCTR0_PORT); 1519 pit_tick = (inb(PITCTR0_PORT) << 8) | pit_tick_lo; 1520 } while (pit_tick > target_pit_tick || pit_tick_lo < 0x10); 1521 1522 start_apic_tick = apic_reg_ops->apic_read(reg); 1523 1524 /* 1525 * Wait for the 8254 to decrement by 1526 * (APIC_TIME_COUNT + pit_ticks_adj) ticks 1527 */ 1528 target_pit_tick = pit_tick - APIC_TIME_COUNT; 1529 do { 1530 pit_tick_lo = inb(PITCTR0_PORT); 1531 pit_tick = (inb(PITCTR0_PORT) << 8) | pit_tick_lo; 1532 } while (pit_tick > target_pit_tick || pit_tick_lo < 0x10); 1533 1534 end_apic_tick = apic_reg_ops->apic_read(reg); 1535 1536 *pit_ticks_adj = target_pit_tick - pit_tick; 1537 1538 intr_restore(iflag); 1539 1540 return (start_apic_tick - end_apic_tick); 1541 } 1542 1543 /* 1544 * Initialise the APIC timer on the local APIC of CPU 0 to the desired 1545 * frequency. Note at this stage in the boot sequence, the boot processor 1546 * is the only active processor. 1547 * hertz value of 0 indicates a one-shot mode request. In this case 1548 * the function returns the resolution (in nanoseconds) for the hardware 1549 * timer interrupt. If one-shot mode capability is not available, 1550 * the return value will be 0. apic_enable_oneshot is a global switch 1551 * for disabling the functionality. 1552 * A non-zero positive value for hertz indicates a periodic mode request. 1553 * In this case the hardware will be programmed to generate clock interrupts 1554 * at hertz frequency and returns the resolution of interrupts in 1555 * nanosecond. 1556 */ 1557 1558 static int 1559 apic_clkinit(int hertz) 1560 { 1561 uint_t apic_ticks = 0; 1562 uint_t pit_ticks; 1563 int ret; 1564 uint16_t pit_ticks_adj; 1565 static int firsttime = 1; 1566 1567 if (firsttime) { 1568 /* first time calibrate on CPU0 only */ 1569 1570 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init); 1571 apic_reg_ops->apic_write(APIC_INIT_COUNT, APIC_MAXVAL); 1572 apic_ticks = apic_calibrate(apicadr, &pit_ticks_adj); 1573 1574 /* total number of PIT ticks corresponding to apic_ticks */ 1575 pit_ticks = APIC_TIME_COUNT + pit_ticks_adj; 1576 1577 /* 1578 * Determine the number of nanoseconds per APIC clock tick 1579 * and then determine how many APIC ticks to interrupt at the 1580 * desired frequency 1581 * apic_ticks / (pitticks / PIT_HZ) = apic_ticks_per_s 1582 * (apic_ticks * PIT_HZ) / pitticks = apic_ticks_per_s 1583 * apic_ticks_per_ns = (apic_ticks * PIT_HZ) / (pitticks * 10^9) 1584 * pic_ticks_per_SFns = 1585 * (SF * apic_ticks * PIT_HZ) / (pitticks * 10^9) 1586 */ 1587 apic_ticks_per_SFnsecs = 1588 ((SF * apic_ticks * PIT_HZ) / 1589 ((uint64_t)pit_ticks * NANOSEC)); 1590 1591 /* the interval timer initial count is 32 bit max */ 1592 apic_nsec_max = APIC_TICKS_TO_NSECS(APIC_MAXVAL); 1593 firsttime = 0; 1594 } 1595 1596 if (hertz != 0) { 1597 /* periodic */ 1598 apic_nsec_per_intr = NANOSEC / hertz; 1599 apic_hertz_count = APIC_NSECS_TO_TICKS(apic_nsec_per_intr); 1600 } 1601 1602 apic_int_busy_mark = (apic_int_busy_mark * 1603 apic_sample_factor_redistribution) / 100; 1604 apic_int_free_mark = (apic_int_free_mark * 1605 apic_sample_factor_redistribution) / 100; 1606 apic_diff_for_redistribution = (apic_diff_for_redistribution * 1607 apic_sample_factor_redistribution) / 100; 1608 1609 if (hertz == 0) { 1610 /* requested one_shot */ 1611 if (!tsc_gethrtime_enable || !apic_oneshot_enable) 1612 return (0); 1613 apic_oneshot = 1; 1614 ret = (int)APIC_TICKS_TO_NSECS(1); 1615 } else { 1616 /* program the local APIC to interrupt at the given frequency */ 1617 apic_reg_ops->apic_write(APIC_INIT_COUNT, apic_hertz_count); 1618 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, 1619 (apic_clkvect + APIC_BASE_VECT) | AV_TIME); 1620 apic_oneshot = 0; 1621 ret = NANOSEC / hertz; 1622 } 1623 1624 return (ret); 1625 1626 } 1627 1628 /* 1629 * apic_preshutdown: 1630 * Called early in shutdown whilst we can still access filesystems to do 1631 * things like loading modules which will be required to complete shutdown 1632 * after filesystems are all unmounted. 1633 */ 1634 static void 1635 apic_preshutdown(int cmd, int fcn) 1636 { 1637 APIC_VERBOSE_POWEROFF(("apic_preshutdown(%d,%d); m=%d a=%d\n", 1638 cmd, fcn, apic_poweroff_method, apic_enable_acpi)); 1639 1640 if ((cmd != A_SHUTDOWN) || (fcn != AD_POWEROFF)) { 1641 return; 1642 } 1643 } 1644 1645 static void 1646 apic_shutdown(int cmd, int fcn) 1647 { 1648 int restarts, attempts; 1649 int i; 1650 uchar_t byte; 1651 ulong_t iflag; 1652 1653 /* Send NMI to all CPUs except self to do per processor shutdown */ 1654 iflag = intr_clear(); 1655 #ifdef DEBUG 1656 APIC_AV_PENDING_SET(); 1657 #else 1658 if (apic_mode == LOCAL_APIC) 1659 APIC_AV_PENDING_SET(); 1660 #endif /* DEBUG */ 1661 apic_shutdown_processors = 1; 1662 apic_reg_ops->apic_write(APIC_INT_CMD1, 1663 AV_NMI | AV_LEVEL | AV_SH_ALL_EXCSELF); 1664 1665 /* restore cmos shutdown byte before reboot */ 1666 if (apic_cmos_ssb_set) { 1667 outb(CMOS_ADDR, SSB); 1668 outb(CMOS_DATA, 0); 1669 } 1670 1671 ioapic_disable_redirection(); 1672 1673 /* disable apic mode if imcr present */ 1674 if (apic_imcrp) { 1675 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT); 1676 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_PIC); 1677 } 1678 1679 apic_disable_local_apic(); 1680 1681 intr_restore(iflag); 1682 1683 /* remainder of function is for shutdown cases only */ 1684 if (cmd != A_SHUTDOWN) 1685 return; 1686 1687 /* 1688 * Switch system back into Legacy-Mode if using ACPI and 1689 * not powering-off. Some BIOSes need to remain in ACPI-mode 1690 * for power-off to succeed (Dell Dimension 4600) 1691 * Do not disable ACPI while doing fastreboot 1692 */ 1693 if (apic_enable_acpi && fcn != AD_POWEROFF && fcn != AD_FASTREBOOT) 1694 (void) AcpiDisable(); 1695 1696 if (fcn == AD_FASTREBOOT) { 1697 apic_reg_ops->apic_write(APIC_INT_CMD1, 1698 AV_ASSERT | AV_RESET | AV_SH_ALL_EXCSELF); 1699 } 1700 1701 /* remainder of function is for shutdown+poweroff case only */ 1702 if (fcn != AD_POWEROFF) 1703 return; 1704 1705 switch (apic_poweroff_method) { 1706 case APIC_POWEROFF_VIA_RTC: 1707 1708 /* select the extended NVRAM bank in the RTC */ 1709 outb(CMOS_ADDR, RTC_REGA); 1710 byte = inb(CMOS_DATA); 1711 outb(CMOS_DATA, (byte | EXT_BANK)); 1712 1713 outb(CMOS_ADDR, PFR_REG); 1714 1715 /* for Predator must toggle the PAB bit */ 1716 byte = inb(CMOS_DATA); 1717 1718 /* 1719 * clear power active bar, wakeup alarm and 1720 * kickstart 1721 */ 1722 byte &= ~(PAB_CBIT | WF_FLAG | KS_FLAG); 1723 outb(CMOS_DATA, byte); 1724 1725 /* delay before next write */ 1726 drv_usecwait(1000); 1727 1728 /* for S40 the following would suffice */ 1729 byte = inb(CMOS_DATA); 1730 1731 /* power active bar control bit */ 1732 byte |= PAB_CBIT; 1733 outb(CMOS_DATA, byte); 1734 1735 break; 1736 1737 case APIC_POWEROFF_VIA_ASPEN_BMC: 1738 restarts = 0; 1739 restart_aspen_bmc: 1740 if (++restarts == 3) 1741 break; 1742 attempts = 0; 1743 do { 1744 byte = inb(MISMIC_FLAG_REGISTER); 1745 byte &= MISMIC_BUSY_MASK; 1746 if (byte != 0) { 1747 drv_usecwait(1000); 1748 if (attempts >= 3) 1749 goto restart_aspen_bmc; 1750 ++attempts; 1751 } 1752 } while (byte != 0); 1753 outb(MISMIC_CNTL_REGISTER, CC_SMS_GET_STATUS); 1754 byte = inb(MISMIC_FLAG_REGISTER); 1755 byte |= 0x1; 1756 outb(MISMIC_FLAG_REGISTER, byte); 1757 i = 0; 1758 for (; i < (sizeof (aspen_bmc)/sizeof (aspen_bmc[0])); 1759 i++) { 1760 attempts = 0; 1761 do { 1762 byte = inb(MISMIC_FLAG_REGISTER); 1763 byte &= MISMIC_BUSY_MASK; 1764 if (byte != 0) { 1765 drv_usecwait(1000); 1766 if (attempts >= 3) 1767 goto restart_aspen_bmc; 1768 ++attempts; 1769 } 1770 } while (byte != 0); 1771 outb(MISMIC_CNTL_REGISTER, aspen_bmc[i].cntl); 1772 outb(MISMIC_DATA_REGISTER, aspen_bmc[i].data); 1773 byte = inb(MISMIC_FLAG_REGISTER); 1774 byte |= 0x1; 1775 outb(MISMIC_FLAG_REGISTER, byte); 1776 } 1777 break; 1778 1779 case APIC_POWEROFF_VIA_SITKA_BMC: 1780 restarts = 0; 1781 restart_sitka_bmc: 1782 if (++restarts == 3) 1783 break; 1784 attempts = 0; 1785 do { 1786 byte = inb(SMS_STATUS_REGISTER); 1787 byte &= SMS_STATE_MASK; 1788 if ((byte == SMS_READ_STATE) || 1789 (byte == SMS_WRITE_STATE)) { 1790 drv_usecwait(1000); 1791 if (attempts >= 3) 1792 goto restart_sitka_bmc; 1793 ++attempts; 1794 } 1795 } while ((byte == SMS_READ_STATE) || 1796 (byte == SMS_WRITE_STATE)); 1797 outb(SMS_COMMAND_REGISTER, SMS_GET_STATUS); 1798 i = 0; 1799 for (; i < (sizeof (sitka_bmc)/sizeof (sitka_bmc[0])); 1800 i++) { 1801 attempts = 0; 1802 do { 1803 byte = inb(SMS_STATUS_REGISTER); 1804 byte &= SMS_IBF_MASK; 1805 if (byte != 0) { 1806 drv_usecwait(1000); 1807 if (attempts >= 3) 1808 goto restart_sitka_bmc; 1809 ++attempts; 1810 } 1811 } while (byte != 0); 1812 outb(sitka_bmc[i].port, sitka_bmc[i].data); 1813 } 1814 break; 1815 1816 case APIC_POWEROFF_NONE: 1817 1818 /* If no APIC direct method, we will try using ACPI */ 1819 if (apic_enable_acpi) { 1820 if (acpi_poweroff() == 1) 1821 return; 1822 } else 1823 return; 1824 1825 break; 1826 } 1827 /* 1828 * Wait a limited time here for power to go off. 1829 * If the power does not go off, then there was a 1830 * problem and we should continue to the halt which 1831 * prints a message for the user to press a key to 1832 * reboot. 1833 */ 1834 drv_usecwait(7000000); /* wait seven seconds */ 1835 1836 } 1837 1838 /* 1839 * Try and disable all interrupts. We just assign interrupts to other 1840 * processors based on policy. If any were bound by user request, we 1841 * let them continue and return failure. We do not bother to check 1842 * for cache affinity while rebinding. 1843 */ 1844 1845 static int 1846 apic_disable_intr(processorid_t cpun) 1847 { 1848 int bind_cpu = 0, i, hardbound = 0; 1849 apic_irq_t *irq_ptr; 1850 ulong_t iflag; 1851 1852 iflag = intr_clear(); 1853 lock_set(&apic_ioapic_lock); 1854 1855 for (i = 0; i <= APIC_MAX_VECTOR; i++) { 1856 if (apic_reprogram_info[i].done == B_FALSE) { 1857 if (apic_reprogram_info[i].bindcpu == cpun) { 1858 /* 1859 * CPU is busy -- it's the target of 1860 * a pending reprogramming attempt 1861 */ 1862 lock_clear(&apic_ioapic_lock); 1863 intr_restore(iflag); 1864 return (PSM_FAILURE); 1865 } 1866 } 1867 } 1868 1869 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE; 1870 1871 apic_cpus[cpun].aci_curipl = 0; 1872 1873 i = apic_min_device_irq; 1874 for (; i <= apic_max_device_irq; i++) { 1875 /* 1876 * If there are bound interrupts on this cpu, then 1877 * rebind them to other processors. 1878 */ 1879 if ((irq_ptr = apic_irq_table[i]) != NULL) { 1880 ASSERT((irq_ptr->airq_temp_cpu == IRQ_UNBOUND) || 1881 (irq_ptr->airq_temp_cpu == IRQ_UNINIT) || 1882 ((irq_ptr->airq_temp_cpu & ~IRQ_USER_BOUND) < 1883 apic_nproc)); 1884 1885 if (irq_ptr->airq_temp_cpu == (cpun | IRQ_USER_BOUND)) { 1886 hardbound = 1; 1887 continue; 1888 } 1889 1890 if (irq_ptr->airq_temp_cpu == cpun) { 1891 do { 1892 bind_cpu = apic_next_bind_cpu++; 1893 if (bind_cpu >= apic_nproc) { 1894 apic_next_bind_cpu = 1; 1895 bind_cpu = 0; 1896 1897 } 1898 } while (apic_rebind_all(irq_ptr, bind_cpu)); 1899 } 1900 } 1901 } 1902 1903 lock_clear(&apic_ioapic_lock); 1904 intr_restore(iflag); 1905 1906 if (hardbound) { 1907 cmn_err(CE_WARN, "Could not disable interrupts on %d" 1908 "due to user bound interrupts", cpun); 1909 return (PSM_FAILURE); 1910 } 1911 else 1912 return (PSM_SUCCESS); 1913 } 1914 1915 /* 1916 * Bind interrupts to the CPU's local APIC. 1917 * Interrupts should not be bound to a CPU's local APIC until the CPU 1918 * is ready to receive interrupts. 1919 */ 1920 static void 1921 apic_enable_intr(processorid_t cpun) 1922 { 1923 int i; 1924 apic_irq_t *irq_ptr; 1925 ulong_t iflag; 1926 1927 iflag = intr_clear(); 1928 lock_set(&apic_ioapic_lock); 1929 1930 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE; 1931 1932 i = apic_min_device_irq; 1933 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) { 1934 if ((irq_ptr = apic_irq_table[i]) != NULL) { 1935 if ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) == cpun) { 1936 (void) apic_rebind_all(irq_ptr, 1937 irq_ptr->airq_cpu); 1938 } 1939 } 1940 } 1941 1942 lock_clear(&apic_ioapic_lock); 1943 intr_restore(iflag); 1944 } 1945 1946 1947 /* 1948 * This function will reprogram the timer. 1949 * 1950 * When in oneshot mode the argument is the absolute time in future to 1951 * generate the interrupt at. 1952 * 1953 * When in periodic mode, the argument is the interval at which the 1954 * interrupts should be generated. There is no need to support the periodic 1955 * mode timer change at this time. 1956 */ 1957 static void 1958 apic_timer_reprogram(hrtime_t time) 1959 { 1960 hrtime_t now; 1961 uint_t ticks; 1962 int64_t delta; 1963 1964 /* 1965 * We should be called from high PIL context (CBE_HIGH_PIL), 1966 * so kpreempt is disabled. 1967 */ 1968 1969 if (!apic_oneshot) { 1970 /* time is the interval for periodic mode */ 1971 ticks = APIC_NSECS_TO_TICKS(time); 1972 } else { 1973 /* one shot mode */ 1974 1975 now = gethrtime(); 1976 delta = time - now; 1977 1978 if (delta <= 0) { 1979 /* 1980 * requested to generate an interrupt in the past 1981 * generate an interrupt as soon as possible 1982 */ 1983 ticks = apic_min_timer_ticks; 1984 } else if (delta > apic_nsec_max) { 1985 /* 1986 * requested to generate an interrupt at a time 1987 * further than what we are capable of. Set to max 1988 * the hardware can handle 1989 */ 1990 1991 ticks = APIC_MAXVAL; 1992 #ifdef DEBUG 1993 cmn_err(CE_CONT, "apic_timer_reprogram, request at" 1994 " %lld too far in future, current time" 1995 " %lld \n", time, now); 1996 #endif 1997 } else 1998 ticks = APIC_NSECS_TO_TICKS(delta); 1999 } 2000 2001 if (ticks < apic_min_timer_ticks) 2002 ticks = apic_min_timer_ticks; 2003 2004 apic_reg_ops->apic_write(APIC_INIT_COUNT, ticks); 2005 } 2006 2007 /* 2008 * This function will enable timer interrupts. 2009 */ 2010 static void 2011 apic_timer_enable(void) 2012 { 2013 /* 2014 * We should be Called from high PIL context (CBE_HIGH_PIL), 2015 * so kpreempt is disabled. 2016 */ 2017 2018 if (!apic_oneshot) { 2019 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, 2020 (apic_clkvect + APIC_BASE_VECT) | AV_TIME); 2021 } else { 2022 /* one shot */ 2023 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, 2024 (apic_clkvect + APIC_BASE_VECT)); 2025 } 2026 } 2027 2028 /* 2029 * This function will disable timer interrupts. 2030 */ 2031 static void 2032 apic_timer_disable(void) 2033 { 2034 /* 2035 * We should be Called from high PIL context (CBE_HIGH_PIL), 2036 * so kpreempt is disabled. 2037 */ 2038 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, 2039 (apic_clkvect + APIC_BASE_VECT) | AV_MASK); 2040 } 2041 2042 2043 ddi_periodic_t apic_periodic_id; 2044 2045 /* 2046 * If this module needs a periodic handler for the interrupt distribution, it 2047 * can be added here. The argument to the periodic handler is not currently 2048 * used, but is reserved for future. 2049 */ 2050 static void 2051 apic_post_cyclic_setup(void *arg) 2052 { 2053 _NOTE(ARGUNUSED(arg)) 2054 /* cpu_lock is held */ 2055 /* set up a periodic handler for intr redistribution */ 2056 2057 /* 2058 * In peridoc mode intr redistribution processing is done in 2059 * apic_intr_enter during clk intr processing 2060 */ 2061 if (!apic_oneshot) 2062 return; 2063 /* 2064 * Register a periodical handler for the redistribution processing. 2065 * On X86, CY_LOW_LEVEL is mapped to the level 2 interrupt, so 2066 * DDI_IPL_2 should be passed to ddi_periodic_add() here. 2067 */ 2068 apic_periodic_id = ddi_periodic_add( 2069 (void (*)(void *))apic_redistribute_compute, NULL, 2070 apic_redistribute_sample_interval, DDI_IPL_2); 2071 } 2072 2073 static void 2074 apic_redistribute_compute(void) 2075 { 2076 int i, j, max_busy; 2077 2078 if (apic_enable_dynamic_migration) { 2079 if (++apic_nticks == apic_sample_factor_redistribution) { 2080 /* 2081 * Time to call apic_intr_redistribute(). 2082 * reset apic_nticks. This will cause max_busy 2083 * to be calculated below and if it is more than 2084 * apic_int_busy, we will do the whole thing 2085 */ 2086 apic_nticks = 0; 2087 } 2088 max_busy = 0; 2089 for (i = 0; i < apic_nproc; i++) { 2090 2091 /* 2092 * Check if curipl is non zero & if ISR is in 2093 * progress 2094 */ 2095 if (((j = apic_cpus[i].aci_curipl) != 0) && 2096 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) { 2097 2098 int irq; 2099 apic_cpus[i].aci_busy++; 2100 irq = apic_cpus[i].aci_current[j]; 2101 apic_irq_table[irq]->airq_busy++; 2102 } 2103 2104 if (!apic_nticks && 2105 (apic_cpus[i].aci_busy > max_busy)) 2106 max_busy = apic_cpus[i].aci_busy; 2107 } 2108 if (!apic_nticks) { 2109 if (max_busy > apic_int_busy_mark) { 2110 /* 2111 * We could make the following check be 2112 * skipped > 1 in which case, we get a 2113 * redistribution at half the busy mark (due to 2114 * double interval). Need to be able to collect 2115 * more empirical data to decide if that is a 2116 * good strategy. Punt for now. 2117 */ 2118 if (apic_skipped_redistribute) { 2119 apic_cleanup_busy(); 2120 apic_skipped_redistribute = 0; 2121 } else { 2122 apic_intr_redistribute(); 2123 } 2124 } else 2125 apic_skipped_redistribute++; 2126 } 2127 } 2128 } 2129 2130 2131 /* 2132 * The following functions are in the platform specific file so that they 2133 * can be different functions depending on whether we are running on 2134 * bare metal or a hypervisor. 2135 */ 2136 2137 /* 2138 * map an apic for memory-mapped access 2139 */ 2140 uint32_t * 2141 mapin_apic(uint32_t addr, size_t len, int flags) 2142 { 2143 /*LINTED: pointer cast may result in improper alignment */ 2144 return ((uint32_t *)psm_map_phys(addr, len, flags)); 2145 } 2146 2147 uint32_t * 2148 mapin_ioapic(uint32_t addr, size_t len, int flags) 2149 { 2150 return (mapin_apic(addr, len, flags)); 2151 } 2152 2153 /* 2154 * unmap an apic 2155 */ 2156 void 2157 mapout_apic(caddr_t addr, size_t len) 2158 { 2159 psm_unmap_phys(addr, len); 2160 } 2161 2162 void 2163 mapout_ioapic(caddr_t addr, size_t len) 2164 { 2165 mapout_apic(addr, len); 2166 } 2167 2168 /* 2169 * Check to make sure there are enough irq slots 2170 */ 2171 int 2172 apic_check_free_irqs(int count) 2173 { 2174 int i, avail; 2175 2176 avail = 0; 2177 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) { 2178 if ((apic_irq_table[i] == NULL) || 2179 apic_irq_table[i]->airq_mps_intr_index == FREE_INDEX) { 2180 if (++avail >= count) 2181 return (PSM_SUCCESS); 2182 } 2183 } 2184 return (PSM_FAILURE); 2185 } 2186 2187 /* 2188 * This function allocates "count" MSI vector(s) for the given "dip/pri/type" 2189 */ 2190 int 2191 apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, int pri, 2192 int behavior) 2193 { 2194 int rcount, i; 2195 uchar_t start, irqno; 2196 uint32_t cpu; 2197 major_t major; 2198 apic_irq_t *irqptr; 2199 2200 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: dip=0x%p " 2201 "inum=0x%x pri=0x%x count=0x%x behavior=%d\n", 2202 (void *)dip, inum, pri, count, behavior)); 2203 2204 if (count > 1) { 2205 if (behavior == DDI_INTR_ALLOC_STRICT && 2206 (apic_multi_msi_enable == 0 || count > apic_multi_msi_max)) 2207 return (0); 2208 2209 if (apic_multi_msi_enable == 0) 2210 count = 1; 2211 else if (count > apic_multi_msi_max) 2212 count = apic_multi_msi_max; 2213 } 2214 2215 if ((rcount = apic_navail_vector(dip, pri)) > count) 2216 rcount = count; 2217 else if (rcount == 0 || (rcount < count && 2218 behavior == DDI_INTR_ALLOC_STRICT)) 2219 return (0); 2220 2221 /* if not ISP2, then round it down */ 2222 if (!ISP2(rcount)) 2223 rcount = 1 << (highbit(rcount) - 1); 2224 2225 mutex_enter(&airq_mutex); 2226 2227 for (start = 0; rcount > 0; rcount >>= 1) { 2228 if ((start = apic_find_multi_vectors(pri, rcount)) != 0 || 2229 behavior == DDI_INTR_ALLOC_STRICT) 2230 break; 2231 } 2232 2233 if (start == 0) { 2234 /* no vector available */ 2235 mutex_exit(&airq_mutex); 2236 return (0); 2237 } 2238 2239 if (apic_check_free_irqs(rcount) == PSM_FAILURE) { 2240 /* not enough free irq slots available */ 2241 mutex_exit(&airq_mutex); 2242 return (0); 2243 } 2244 2245 major = (dip != NULL) ? ddi_driver_major(dip) : 0; 2246 for (i = 0; i < rcount; i++) { 2247 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) == 2248 (uchar_t)-1) { 2249 /* 2250 * shouldn't happen because of the 2251 * apic_check_free_irqs() check earlier 2252 */ 2253 mutex_exit(&airq_mutex); 2254 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: " 2255 "apic_allocate_irq failed\n")); 2256 return (i); 2257 } 2258 apic_max_device_irq = max(irqno, apic_max_device_irq); 2259 apic_min_device_irq = min(irqno, apic_min_device_irq); 2260 irqptr = apic_irq_table[irqno]; 2261 #ifdef DEBUG 2262 if (apic_vector_to_irq[start + i] != APIC_RESV_IRQ) 2263 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: " 2264 "apic_vector_to_irq is not APIC_RESV_IRQ\n")); 2265 #endif 2266 apic_vector_to_irq[start + i] = (uchar_t)irqno; 2267 2268 irqptr->airq_vector = (uchar_t)(start + i); 2269 irqptr->airq_ioapicindex = (uchar_t)inum; /* start */ 2270 irqptr->airq_intin_no = (uchar_t)rcount; 2271 irqptr->airq_ipl = pri; 2272 irqptr->airq_vector = start + i; 2273 irqptr->airq_origirq = (uchar_t)(inum + i); 2274 irqptr->airq_share_id = 0; 2275 irqptr->airq_mps_intr_index = MSI_INDEX; 2276 irqptr->airq_dip = dip; 2277 irqptr->airq_major = major; 2278 if (i == 0) /* they all bound to the same cpu */ 2279 cpu = irqptr->airq_cpu = apic_bind_intr(dip, irqno, 2280 0xff, 0xff); 2281 else 2282 irqptr->airq_cpu = cpu; 2283 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: irq=0x%x " 2284 "dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno, 2285 (void *)irqptr->airq_dip, irqptr->airq_vector, 2286 irqptr->airq_origirq, pri)); 2287 } 2288 mutex_exit(&airq_mutex); 2289 return (rcount); 2290 } 2291 2292 /* 2293 * This function allocates "count" MSI-X vector(s) for the given "dip/pri/type" 2294 */ 2295 int 2296 apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, int pri, 2297 int behavior) 2298 { 2299 int rcount, i; 2300 major_t major; 2301 2302 if (count > 1) { 2303 if (behavior == DDI_INTR_ALLOC_STRICT) { 2304 if (count > apic_msix_max) 2305 return (0); 2306 } else if (count > apic_msix_max) 2307 count = apic_msix_max; 2308 } 2309 2310 mutex_enter(&airq_mutex); 2311 2312 if ((rcount = apic_navail_vector(dip, pri)) > count) 2313 rcount = count; 2314 else if (rcount == 0 || (rcount < count && 2315 behavior == DDI_INTR_ALLOC_STRICT)) { 2316 rcount = 0; 2317 goto out; 2318 } 2319 2320 if (apic_check_free_irqs(rcount) == PSM_FAILURE) { 2321 /* not enough free irq slots available */ 2322 rcount = 0; 2323 goto out; 2324 } 2325 2326 major = (dip != NULL) ? ddi_driver_major(dip) : 0; 2327 for (i = 0; i < rcount; i++) { 2328 uchar_t vector, irqno; 2329 apic_irq_t *irqptr; 2330 2331 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) == 2332 (uchar_t)-1) { 2333 /* 2334 * shouldn't happen because of the 2335 * apic_check_free_irqs() check earlier 2336 */ 2337 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: " 2338 "apic_allocate_irq failed\n")); 2339 rcount = i; 2340 goto out; 2341 } 2342 if ((vector = apic_allocate_vector(pri, irqno, 1)) == 0) { 2343 /* 2344 * shouldn't happen because of the 2345 * apic_navail_vector() call earlier 2346 */ 2347 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: " 2348 "apic_allocate_vector failed\n")); 2349 rcount = i; 2350 goto out; 2351 } 2352 apic_max_device_irq = max(irqno, apic_max_device_irq); 2353 apic_min_device_irq = min(irqno, apic_min_device_irq); 2354 irqptr = apic_irq_table[irqno]; 2355 irqptr->airq_vector = (uchar_t)vector; 2356 irqptr->airq_ipl = pri; 2357 irqptr->airq_origirq = (uchar_t)(inum + i); 2358 irqptr->airq_share_id = 0; 2359 irqptr->airq_mps_intr_index = MSIX_INDEX; 2360 irqptr->airq_dip = dip; 2361 irqptr->airq_major = major; 2362 irqptr->airq_cpu = apic_bind_intr(dip, irqno, 0xff, 0xff); 2363 } 2364 out: 2365 mutex_exit(&airq_mutex); 2366 return (rcount); 2367 } 2368 2369 /* 2370 * Allocate a free vector for irq at ipl. Takes care of merging of multiple 2371 * IPLs into a single APIC level as well as stretching some IPLs onto multiple 2372 * levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority 2373 * requests and allocated only when pri is set. 2374 */ 2375 uchar_t 2376 apic_allocate_vector(int ipl, int irq, int pri) 2377 { 2378 int lowest, highest, i; 2379 2380 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK; 2381 lowest = apic_ipltopri[ipl - 1] + APIC_VECTOR_PER_IPL; 2382 2383 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */ 2384 lowest -= APIC_VECTOR_PER_IPL; 2385 2386 #ifdef DEBUG 2387 if (apic_restrict_vector) /* for testing shared interrupt logic */ 2388 highest = lowest + apic_restrict_vector + APIC_HI_PRI_VECTS; 2389 #endif /* DEBUG */ 2390 if (pri == 0) 2391 highest -= APIC_HI_PRI_VECTS; 2392 2393 for (i = lowest; i < highest; i++) { 2394 if (APIC_CHECK_RESERVE_VECTORS(i)) 2395 continue; 2396 if (apic_vector_to_irq[i] == APIC_RESV_IRQ) { 2397 apic_vector_to_irq[i] = (uchar_t)irq; 2398 return (i); 2399 } 2400 } 2401 2402 return (0); 2403 } 2404 2405 /* Mark vector as not being used by any irq */ 2406 void 2407 apic_free_vector(uchar_t vector) 2408 { 2409 apic_vector_to_irq[vector] = APIC_RESV_IRQ; 2410 } 2411 2412 uint32_t 2413 ioapic_read(int ioapic_ix, uint32_t reg) 2414 { 2415 volatile uint32_t *ioapic; 2416 2417 ioapic = apicioadr[ioapic_ix]; 2418 ioapic[APIC_IO_REG] = reg; 2419 return (ioapic[APIC_IO_DATA]); 2420 } 2421 2422 void 2423 ioapic_write(int ioapic_ix, uint32_t reg, uint32_t value) 2424 { 2425 volatile uint32_t *ioapic; 2426 2427 ioapic = apicioadr[ioapic_ix]; 2428 ioapic[APIC_IO_REG] = reg; 2429 ioapic[APIC_IO_DATA] = value; 2430 } 2431 2432 void 2433 ioapic_write_eoi(int ioapic_ix, uint32_t value) 2434 { 2435 volatile uint32_t *ioapic; 2436 2437 ioapic = apicioadr[ioapic_ix]; 2438 ioapic[APIC_IO_EOI] = value; 2439 } 2440 2441 static processorid_t 2442 apic_find_cpu(int flag) 2443 { 2444 processorid_t acid = 0; 2445 int i; 2446 2447 /* Find the first CPU with the passed-in flag set */ 2448 for (i = 0; i < apic_nproc; i++) { 2449 if (apic_cpus[i].aci_status & flag) { 2450 acid = i; 2451 break; 2452 } 2453 } 2454 2455 ASSERT((apic_cpus[acid].aci_status & flag) != 0); 2456 return (acid); 2457 } 2458 2459 /* 2460 * Call rebind to do the actual programming. 2461 * Must be called with interrupts disabled and apic_ioapic_lock held 2462 * 'p' is polymorphic -- if this function is called to process a deferred 2463 * reprogramming, p is of type 'struct ioapic_reprogram_data *', from which 2464 * the irq pointer is retrieved. If not doing deferred reprogramming, 2465 * p is of the type 'apic_irq_t *'. 2466 * 2467 * apic_ioapic_lock must be held across this call, as it protects apic_rebind 2468 * and it protects apic_find_cpu() from a race in which a CPU can be taken 2469 * offline after a cpu is selected, but before apic_rebind is called to 2470 * bind interrupts to it. 2471 */ 2472 int 2473 apic_setup_io_intr(void *p, int irq, boolean_t deferred) 2474 { 2475 apic_irq_t *irqptr; 2476 struct ioapic_reprogram_data *drep = NULL; 2477 int rv; 2478 2479 if (deferred) { 2480 drep = (struct ioapic_reprogram_data *)p; 2481 ASSERT(drep != NULL); 2482 irqptr = drep->irqp; 2483 } else 2484 irqptr = (apic_irq_t *)p; 2485 2486 ASSERT(irqptr != NULL); 2487 2488 rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, drep); 2489 if (rv) { 2490 /* 2491 * CPU is not up or interrupts are disabled. Fall back to 2492 * the first available CPU 2493 */ 2494 rv = apic_rebind(irqptr, apic_find_cpu(APIC_CPU_INTR_ENABLE), 2495 drep); 2496 } 2497 2498 return (rv); 2499 } 2500 2501 2502 uchar_t 2503 apic_modify_vector(uchar_t vector, int irq) 2504 { 2505 apic_vector_to_irq[vector] = (uchar_t)irq; 2506 return (vector); 2507 } 2508 2509 char * 2510 apic_get_apic_type() 2511 { 2512 return (apic_psm_info.p_mach_idstring); 2513 } 2514 2515 void 2516 x2apic_update_psm() 2517 { 2518 struct psm_ops *pops = &apic_ops; 2519 2520 ASSERT(pops != NULL); 2521 2522 /* 2523 * We don't need to do any magic if one of the following 2524 * conditions is true : 2525 * - Not being run under kernel debugger. 2526 * - MP is not set. 2527 * - Booted with one CPU only. 2528 * - One CPU configured. 2529 * 2530 * We set apic_common_send_ipi() since kernel debuggers 2531 * attempt to send IPIs to other slave CPUs during 2532 * entry (exit) from (to) debugger. 2533 */ 2534 if (!(boothowto & RB_DEBUG) || use_mp == 0 || 2535 apic_nproc == 1 || boot_ncpus == 1) { 2536 pops->psm_send_ipi = x2apic_send_ipi; 2537 } else { 2538 pops->psm_send_ipi = apic_common_send_ipi; 2539 } 2540 2541 pops->psm_intr_exit = x2apic_intr_exit; 2542 pops->psm_setspl = x2apic_setspl; 2543 2544 send_dirintf = pops->psm_send_ipi; 2545 2546 apic_mode = LOCAL_X2APIC; 2547 apic_change_ops(); 2548 } 2549 2550 static void 2551 apic_intrr_init(int apic_mode) 2552 { 2553 if (psm_vt_ops != NULL) { 2554 if (((apic_intrr_ops_t *)psm_vt_ops)->apic_intrr_init(apic_mode) 2555 == DDI_SUCCESS) { 2556 apic_vt_ops = psm_vt_ops; 2557 apic_vt_ops->apic_intrr_enable(); 2558 } 2559 } 2560 } 2561 2562 /*ARGSUSED*/ 2563 static void 2564 apic_record_ioapic_rdt(apic_irq_t *irq_ptr, ioapic_rdt_t *irdt) 2565 { 2566 irdt->ir_hi <<= APIC_ID_BIT_OFFSET; 2567 } 2568 2569 /*ARGSUSED*/ 2570 static void 2571 apic_record_msi(apic_irq_t *irq_ptr, msi_regs_t *mregs) 2572 { 2573 mregs->mr_addr = MSI_ADDR_HDR | 2574 (MSI_ADDR_RH_FIXED << MSI_ADDR_RH_SHIFT) | 2575 (MSI_ADDR_DM_PHYSICAL << MSI_ADDR_DM_SHIFT) | 2576 (mregs->mr_addr << MSI_ADDR_DEST_SHIFT); 2577 mregs->mr_data = (MSI_DATA_TM_EDGE << MSI_DATA_TM_SHIFT) | 2578 mregs->mr_data; 2579 } 2580