1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * PSMI 1.1 extensions are supported only in 2.6 and later versions. 31 * PSMI 1.2 extensions are supported only in 2.7 and later versions. 32 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10. 33 * PSMI 1.5 extensions are supported in Solaris Nevada. 34 */ 35 #define PSMI_1_5 36 37 #include <sys/processor.h> 38 #include <sys/time.h> 39 #include <sys/psm.h> 40 #include <sys/smp_impldefs.h> 41 #include <sys/cram.h> 42 #include <sys/acpi/acpi.h> 43 #include <sys/acpica.h> 44 #include <sys/psm_common.h> 45 #include "apic.h" 46 #include <sys/pit.h> 47 #include <sys/ddi.h> 48 #include <sys/sunddi.h> 49 #include <sys/ddi_impldefs.h> 50 #include <sys/pci.h> 51 #include <sys/promif.h> 52 #include <sys/x86_archext.h> 53 #include <sys/cpc_impl.h> 54 #include <sys/uadmin.h> 55 #include <sys/panic.h> 56 #include <sys/debug.h> 57 #include <sys/archsystm.h> 58 #include <sys/trap.h> 59 #include <sys/machsystm.h> 60 #include <sys/cpuvar.h> 61 #include <sys/rm_platter.h> 62 #include <sys/privregs.h> 63 #include <sys/cyclic.h> 64 #include <sys/note.h> 65 #include <sys/pci_intr_lib.h> 66 67 /* 68 * Local Function Prototypes 69 */ 70 static void apic_init_intr(); 71 static void apic_ret(); 72 static int apic_handle_defconf(); 73 static int apic_parse_mpct(caddr_t mpct, int bypass); 74 static struct apic_mpfps_hdr *apic_find_fps_sig(caddr_t fptr, int size); 75 static int apic_checksum(caddr_t bptr, int len); 76 static int get_apic_cmd1(); 77 static int get_apic_pri(); 78 static int apic_find_bus_type(char *bus); 79 static int apic_find_bus(int busid); 80 static int apic_find_bus_id(int bustype); 81 static struct apic_io_intr *apic_find_io_intr(int irqno); 82 int apic_allocate_irq(int irq); 83 static int apic_find_free_irq(int start, int end); 84 static uchar_t apic_allocate_vector(int ipl, int irq, int pri); 85 static void apic_modify_vector(uchar_t vector, int irq); 86 static void apic_mark_vector(uchar_t oldvector, uchar_t newvector); 87 static uchar_t apic_xlate_vector(uchar_t oldvector); 88 static void apic_xlate_vector_free_timeout_handler(void *arg); 89 static void apic_free_vector(uchar_t vector); 90 static void apic_reprogram_timeout_handler(void *arg); 91 static int apic_check_stuck_interrupt(apic_irq_t *irq_ptr, int old_bind_cpu, 92 int new_bind_cpu, volatile int32_t *ioapic, int intin_no, int which_irq); 93 static int apic_setup_io_intr(apic_irq_t *irqptr, int irq); 94 static int apic_setup_io_intr_deferred(apic_irq_t *irqptr, int irq); 95 static void apic_record_rdt_entry(apic_irq_t *irqptr, int irq); 96 static struct apic_io_intr *apic_find_io_intr_w_busid(int irqno, int busid); 97 static int apic_find_intin(uchar_t ioapic, uchar_t intin); 98 static int apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, 99 int child_ipin, struct apic_io_intr **intrp); 100 static int apic_setup_irq_table(dev_info_t *dip, int irqno, 101 struct apic_io_intr *intrp, struct intrspec *ispec, iflag_t *intr_flagp, 102 int type); 103 static int apic_setup_sci_irq_table(int irqno, uchar_t ipl, 104 iflag_t *intr_flagp); 105 static void apic_nmi_intr(caddr_t arg); 106 uchar_t apic_bind_intr(dev_info_t *dip, int irq, uchar_t ioapicid, 107 uchar_t intin); 108 static int apic_rebind(apic_irq_t *irq_ptr, int bind_cpu, int acquire_lock, 109 int when); 110 static int apic_rebind_all(apic_irq_t *irq_ptr, int bind_cpu, int safe); 111 static void apic_intr_redistribute(); 112 static void apic_cleanup_busy(); 113 static void apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp); 114 int apic_introp_xlate(dev_info_t *dip, struct intrspec *ispec, int type); 115 116 /* ACPI support routines */ 117 static int acpi_probe(void); 118 static int apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip, 119 int *pci_irqp, iflag_t *intr_flagp); 120 121 static int apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid, 122 int ipin, int *pci_irqp, iflag_t *intr_flagp); 123 static uchar_t acpi_find_ioapic(int irq); 124 static int acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2); 125 126 /* 127 * standard MP entries 128 */ 129 static int apic_probe(); 130 static int apic_clkinit(); 131 static int apic_getclkirq(int ipl); 132 static uint_t apic_calibrate(volatile uint32_t *addr, 133 uint16_t *pit_ticks_adj); 134 static hrtime_t apic_gettime(); 135 static hrtime_t apic_gethrtime(); 136 static void apic_init(); 137 static void apic_picinit(void); 138 static void apic_cpu_start(processorid_t cpun, caddr_t rm_code); 139 static int apic_post_cpu_start(void); 140 static void apic_send_ipi(int cpun, int ipl); 141 static void apic_set_softintr(int softintr); 142 static void apic_set_idlecpu(processorid_t cpun); 143 static void apic_unset_idlecpu(processorid_t cpun); 144 static int apic_softlvl_to_irq(int ipl); 145 static int apic_intr_enter(int ipl, int *vect); 146 static void apic_intr_exit(int ipl, int vect); 147 static void apic_setspl(int ipl); 148 static int apic_addspl(int ipl, int vector, int min_ipl, int max_ipl); 149 static int apic_delspl(int ipl, int vector, int min_ipl, int max_ipl); 150 static void apic_shutdown(int cmd, int fcn); 151 static void apic_preshutdown(int cmd, int fcn); 152 static int apic_disable_intr(processorid_t cpun); 153 static void apic_enable_intr(processorid_t cpun); 154 static processorid_t apic_get_next_processorid(processorid_t cpun); 155 static int apic_get_ipivect(int ipl, int type); 156 static void apic_timer_reprogram(hrtime_t time); 157 static void apic_timer_enable(void); 158 static void apic_timer_disable(void); 159 static void apic_post_cyclic_setup(void *arg); 160 extern int apic_intr_ops(dev_info_t *, ddi_intr_handle_impl_t *, 161 psm_intr_op_t, int *); 162 163 static int apic_oneshot = 0; 164 int apic_oneshot_enable = 1; /* to allow disabling one-shot capability */ 165 166 /* 167 * These variables are frequently accessed in apic_intr_enter(), 168 * apic_intr_exit and apic_setspl, so group them together 169 */ 170 volatile uint32_t *apicadr = NULL; /* virtual addr of local APIC */ 171 int apic_setspl_delay = 1; /* apic_setspl - delay enable */ 172 int apic_clkvect; 173 174 /* ACPI SCI interrupt configuration; -1 if SCI not used */ 175 int apic_sci_vect = -1; 176 iflag_t apic_sci_flags; 177 178 /* vector at which error interrupts come in */ 179 int apic_errvect; 180 int apic_enable_error_intr = 1; 181 int apic_error_display_delay = 100; 182 183 /* vector at which performance counter overflow interrupts come in */ 184 int apic_cpcovf_vect; 185 int apic_enable_cpcovf_intr = 1; 186 187 /* Max wait time (in microsecs) for flags to clear in an RDT entry. */ 188 static int apic_max_usecs_clear_pending = 1000; 189 190 /* Amt of usecs to wait before checking if RDT flags have reset. */ 191 #define APIC_USECS_PER_WAIT_INTERVAL 100 192 193 /* Maximum number of times to retry reprogramming via the timeout */ 194 #define APIC_REPROGRAM_MAX_TIMEOUTS 10 195 196 /* timeout delay for IOAPIC delayed reprogramming */ 197 #define APIC_REPROGRAM_TIMEOUT_DELAY 5 /* microseconds */ 198 199 /* Parameter to apic_rebind(): Should reprogramming be done now or later? */ 200 #define DEFERRED 1 201 #define IMMEDIATE 0 202 203 /* 204 * number of bits per byte, from <sys/param.h> 205 */ 206 #define UCHAR_MAX ((1 << NBBY) - 1) 207 208 uchar_t apic_reserved_irqlist[MAX_ISA_IRQ]; 209 210 /* 211 * The following vector assignments influence the value of ipltopri and 212 * vectortoipl. Note that vectors 0 - 0x1f are not used. We can program 213 * idle to 0 and IPL 0 to 0x10 to differentiate idle in case 214 * we care to do so in future. Note some IPLs which are rarely used 215 * will share the vector ranges and heavily used IPLs (5 and 6) have 216 * a wide range. 217 * IPL Vector range. as passed to intr_enter 218 * 0 none. 219 * 1,2,3 0x20-0x2f 0x0-0xf 220 * 4 0x30-0x3f 0x10-0x1f 221 * 5 0x40-0x5f 0x20-0x3f 222 * 6 0x60-0x7f 0x40-0x5f 223 * 7,8,9 0x80-0x8f 0x60-0x6f 224 * 10 0x90-0x9f 0x70-0x7f 225 * 11 0xa0-0xaf 0x80-0x8f 226 * ... ... 227 * 16 0xf0-0xff 0xd0-0xdf 228 */ 229 uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL] = { 230 3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 16 231 }; 232 /* 233 * The ipl of an ISR at vector X is apic_vectortoipl[X<<4] 234 * NOTE that this is vector as passed into intr_enter which is 235 * programmed vector - 0x20 (APIC_BASE_VECT) 236 */ 237 238 uchar_t apic_ipltopri[MAXIPL + 1]; /* unix ipl to apic pri */ 239 /* The taskpri to be programmed into apic to mask given ipl */ 240 241 #if defined(__amd64) 242 uchar_t apic_cr8pri[MAXIPL + 1]; /* unix ipl to cr8 pri */ 243 #endif 244 245 /* 246 * Patchable global variables. 247 */ 248 int apic_forceload = 0; 249 250 #define INTR_ROUND_ROBIN_WITH_AFFINITY 0 251 #define INTR_ROUND_ROBIN 1 252 #define INTR_LOWEST_PRIORITY 2 253 254 int apic_intr_policy = INTR_ROUND_ROBIN_WITH_AFFINITY; 255 256 static int apic_next_bind_cpu = 2; /* For round robin assignment */ 257 /* start with cpu 1 */ 258 259 int apic_coarse_hrtime = 1; /* 0 - use accurate slow gethrtime() */ 260 /* 1 - use gettime() for performance */ 261 int apic_flat_model = 0; /* 0 - clustered. 1 - flat */ 262 int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */ 263 int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */ 264 int apic_panic_on_nmi = 0; 265 int apic_panic_on_apic_error = 0; 266 267 int apic_verbose = 0; 268 269 /* Flag definitions for apic_verbose */ 270 #define APIC_VERBOSE_IOAPIC_FLAG 0x00000001 271 #define APIC_VERBOSE_IRQ_FLAG 0x00000002 272 #define APIC_VERBOSE_POWEROFF_FLAG 0x00000004 273 #define APIC_VERBOSE_POWEROFF_PAUSE_FLAG 0x00000008 274 275 276 #define APIC_VERBOSE_IOAPIC(fmt) \ 277 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) \ 278 cmn_err fmt; 279 280 #define APIC_VERBOSE_IRQ(fmt) \ 281 if (apic_verbose & APIC_VERBOSE_IRQ_FLAG) \ 282 cmn_err fmt; 283 284 #define APIC_VERBOSE_POWEROFF(fmt) \ 285 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) \ 286 prom_printf fmt; 287 288 289 /* Now the ones for Dynamic Interrupt distribution */ 290 int apic_enable_dynamic_migration = 1; 291 292 /* 293 * If enabled, the distribution works as follows: 294 * On every interrupt entry, the current ipl for the CPU is set in cpu_info 295 * and the irq corresponding to the ipl is also set in the aci_current array. 296 * interrupt exit and setspl (due to soft interrupts) will cause the current 297 * ipl to be be changed. This is cache friendly as these frequently used 298 * paths write into a per cpu structure. 299 * 300 * Sampling is done by checking the structures for all CPUs and incrementing 301 * the busy field of the irq (if any) executing on each CPU and the busy field 302 * of the corresponding CPU. 303 * In periodic mode this is done on every clock interrupt. 304 * In one-shot mode, this is done thru a cyclic with an interval of 305 * apic_redistribute_sample_interval (default 10 milli sec). 306 * 307 * Every apic_sample_factor_redistribution times we sample, we do computations 308 * to decide which interrupt needs to be migrated (see comments 309 * before apic_intr_redistribute(). 310 */ 311 312 /* 313 * Following 3 variables start as % and can be patched or set using an 314 * API to be defined in future. They will be scaled to 315 * sample_factor_redistribution which is in turn set to hertz+1 (in periodic 316 * mode), or 101 in one-shot mode to stagger it away from one sec processing 317 */ 318 319 int apic_int_busy_mark = 60; 320 int apic_int_free_mark = 20; 321 int apic_diff_for_redistribution = 10; 322 323 /* sampling interval for interrupt redistribution for dynamic migration */ 324 int apic_redistribute_sample_interval = NANOSEC / 100; /* 10 millisec */ 325 326 /* 327 * number of times we sample before deciding to redistribute interrupts 328 * for dynamic migration 329 */ 330 int apic_sample_factor_redistribution = 101; 331 332 /* timeout for xlate_vector, mark_vector */ 333 int apic_revector_timeout = 16 * 10000; /* 160 millisec */ 334 335 int apic_redist_cpu_skip = 0; 336 int apic_num_imbalance = 0; 337 int apic_num_rebind = 0; 338 339 int apic_nproc = 0; 340 int apic_defconf = 0; 341 int apic_irq_translate = 0; 342 int apic_spec_rev = 0; 343 int apic_imcrp = 0; 344 345 int apic_use_acpi = 1; /* 1 = use ACPI, 0 = don't use ACPI */ 346 int apic_use_acpi_madt_only = 0; /* 1=ONLY use MADT from ACPI */ 347 348 /* 349 * For interrupt link devices, if apic_unconditional_srs is set, an irq resource 350 * will be assigned (via _SRS). If it is not set, use the current 351 * irq setting (via _CRS), but only if that irq is in the set of possible 352 * irqs (returned by _PRS) for the device. 353 */ 354 int apic_unconditional_srs = 1; 355 356 /* 357 * For interrupt link devices, if apic_prefer_crs is set when we are 358 * assigning an IRQ resource to a device, prefer the current IRQ setting 359 * over other possible irq settings under same conditions. 360 */ 361 362 int apic_prefer_crs = 1; 363 364 365 /* minimum number of timer ticks to program to */ 366 int apic_min_timer_ticks = 1; 367 /* 368 * Local static data 369 */ 370 static struct psm_ops apic_ops = { 371 apic_probe, 372 373 apic_init, 374 apic_picinit, 375 apic_intr_enter, 376 apic_intr_exit, 377 apic_setspl, 378 apic_addspl, 379 apic_delspl, 380 apic_disable_intr, 381 apic_enable_intr, 382 apic_softlvl_to_irq, 383 apic_set_softintr, 384 385 apic_set_idlecpu, 386 apic_unset_idlecpu, 387 388 apic_clkinit, 389 apic_getclkirq, 390 (void (*)(void))NULL, /* psm_hrtimeinit */ 391 apic_gethrtime, 392 393 apic_get_next_processorid, 394 apic_cpu_start, 395 apic_post_cpu_start, 396 apic_shutdown, 397 apic_get_ipivect, 398 apic_send_ipi, 399 400 (int (*)(dev_info_t *, int))NULL, /* psm_translate_irq */ 401 (int (*)(todinfo_t *))NULL, /* psm_tod_get */ 402 (int (*)(todinfo_t *))NULL, /* psm_tod_set */ 403 (void (*)(int, char *))NULL, /* psm_notify_error */ 404 (void (*)(int))NULL, /* psm_notify_func */ 405 apic_timer_reprogram, 406 apic_timer_enable, 407 apic_timer_disable, 408 apic_post_cyclic_setup, 409 apic_preshutdown, 410 apic_intr_ops /* Advanced DDI Interrupt framework */ 411 }; 412 413 414 static struct psm_info apic_psm_info = { 415 PSM_INFO_VER01_5, /* version */ 416 PSM_OWN_EXCLUSIVE, /* ownership */ 417 (struct psm_ops *)&apic_ops, /* operation */ 418 "pcplusmp", /* machine name */ 419 "pcplusmp v1.4 compatible %I%", 420 }; 421 422 static void *apic_hdlp; 423 424 #ifdef DEBUG 425 #define DENT 0x0001 426 int apic_debug = 0; 427 /* 428 * set apic_restrict_vector to the # of vectors we want to allow per range 429 * useful in testing shared interrupt logic by setting it to 2 or 3 430 */ 431 int apic_restrict_vector = 0; 432 433 #define APIC_DEBUG_MSGBUFSIZE 2048 434 int apic_debug_msgbuf[APIC_DEBUG_MSGBUFSIZE]; 435 int apic_debug_msgbufindex = 0; 436 437 /* 438 * Put "int" info into debug buffer. No MP consistency, but light weight. 439 * Good enough for most debugging. 440 */ 441 #define APIC_DEBUG_BUF_PUT(x) \ 442 apic_debug_msgbuf[apic_debug_msgbufindex++] = x; \ 443 if (apic_debug_msgbufindex >= (APIC_DEBUG_MSGBUFSIZE - NCPU)) \ 444 apic_debug_msgbufindex = 0; 445 446 #endif /* DEBUG */ 447 448 apic_cpus_info_t *apic_cpus; 449 450 static uint_t apic_cpumask = 0; 451 static uint_t apic_flag; 452 453 /* Flag to indicate that we need to shut down all processors */ 454 static uint_t apic_shutdown_processors; 455 456 uint_t apic_nsec_per_intr = 0; 457 458 /* 459 * apic_let_idle_redistribute can have the following values: 460 * 0 - If clock decremented it from 1 to 0, clock has to call redistribute. 461 * apic_redistribute_lock prevents multiple idle cpus from redistributing 462 */ 463 int apic_num_idle_redistributions = 0; 464 static int apic_let_idle_redistribute = 0; 465 static uint_t apic_nticks = 0; 466 static uint_t apic_skipped_redistribute = 0; 467 468 /* to gather intr data and redistribute */ 469 static void apic_redistribute_compute(void); 470 471 static uint_t last_count_read = 0; 472 static lock_t apic_gethrtime_lock; 473 volatile int apic_hrtime_stamp = 0; 474 volatile hrtime_t apic_nsec_since_boot = 0; 475 static uint_t apic_hertz_count, apic_nsec_per_tick; 476 static hrtime_t apic_nsec_max; 477 478 static hrtime_t apic_last_hrtime = 0; 479 int apic_hrtime_error = 0; 480 int apic_remote_hrterr = 0; 481 int apic_num_nmis = 0; 482 int apic_apic_error = 0; 483 int apic_num_apic_errors = 0; 484 int apic_num_cksum_errors = 0; 485 486 static uchar_t apic_io_id[MAX_IO_APIC]; 487 static uchar_t apic_io_ver[MAX_IO_APIC]; 488 static uchar_t apic_io_vectbase[MAX_IO_APIC]; 489 static uchar_t apic_io_vectend[MAX_IO_APIC]; 490 volatile int32_t *apicioadr[MAX_IO_APIC]; 491 492 /* 493 * First available slot to be used as IRQ index into the apic_irq_table 494 * for those interrupts (like MSI/X) that don't have a physical IRQ. 495 */ 496 int apic_first_avail_irq = APIC_FIRST_FREE_IRQ; 497 498 /* 499 * apic_ioapic_lock protects the ioapics (reg select), the status, temp_bound 500 * and bound elements of cpus_info and the temp_cpu element of irq_struct 501 */ 502 lock_t apic_ioapic_lock; 503 504 /* 505 * apic_ioapic_reprogram_lock prevents a CPU from exiting 506 * apic_intr_exit before IOAPIC reprogramming information 507 * is collected. 508 */ 509 static lock_t apic_ioapic_reprogram_lock; 510 static int apic_io_max = 0; /* no. of i/o apics enabled */ 511 512 static struct apic_io_intr *apic_io_intrp = 0; 513 static struct apic_bus *apic_busp; 514 515 uchar_t apic_vector_to_irq[APIC_MAX_VECTOR+1]; 516 static uchar_t apic_resv_vector[MAXIPL+1]; 517 518 static char apic_level_intr[APIC_MAX_VECTOR+1]; 519 static int apic_error = 0; 520 /* values which apic_error can take. Not catastrophic, but may help debug */ 521 #define APIC_ERR_BOOT_EOI 0x1 522 #define APIC_ERR_GET_IPIVECT_FAIL 0x2 523 #define APIC_ERR_INVALID_INDEX 0x4 524 #define APIC_ERR_MARK_VECTOR_FAIL 0x8 525 #define APIC_ERR_APIC_ERROR 0x40000000 526 #define APIC_ERR_NMI 0x80000000 527 528 static int apic_cmos_ssb_set = 0; 529 530 static uint32_t eisa_level_intr_mask = 0; 531 /* At least MSB will be set if EISA bus */ 532 533 static int apic_pci_bus_total = 0; 534 static uchar_t apic_single_pci_busid = 0; 535 536 537 /* 538 * airq_mutex protects additions to the apic_irq_table - the first 539 * pointer and any airq_nexts off of that one. It also protects 540 * apic_max_device_irq & apic_min_device_irq. It also guarantees 541 * that share_id is unique as new ids are generated only when new 542 * irq_t structs are linked in. Once linked in the structs are never 543 * deleted. temp_cpu & mps_intr_index field indicate if it is programmed 544 * or allocated. Note that there is a slight gap between allocating in 545 * apic_introp_xlate and programming in addspl. 546 */ 547 kmutex_t airq_mutex; 548 apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1]; 549 int apic_max_device_irq = 0; 550 int apic_min_device_irq = APIC_MAX_VECTOR; 551 552 /* use to make sure only one cpu handles the nmi */ 553 static lock_t apic_nmi_lock; 554 /* use to make sure only one cpu handles the error interrupt */ 555 static lock_t apic_error_lock; 556 557 /* 558 * Following declarations are for revectoring; used when ISRs at different 559 * IPLs share an irq. 560 */ 561 static lock_t apic_revector_lock; 562 static int apic_revector_pending = 0; 563 static uchar_t *apic_oldvec_to_newvec; 564 static uchar_t *apic_newvec_to_oldvec; 565 566 /* Ensures that the IOAPIC-reprogramming timeout is not reentrant */ 567 static kmutex_t apic_reprogram_timeout_mutex; 568 569 static struct ioapic_reprogram_data { 570 int valid; /* This entry is valid */ 571 int bindcpu; /* The CPU to which the int will be bound */ 572 unsigned timeouts; /* # times the reprogram timeout was called */ 573 } apic_reprogram_info[APIC_MAX_VECTOR+1]; 574 /* 575 * APIC_MAX_VECTOR + 1 is the maximum # of IRQs as well. apic_reprogram_info 576 * is indexed by IRQ number, NOT by vector number. 577 */ 578 579 580 /* 581 * The following added to identify a software poweroff method if available. 582 */ 583 584 static struct { 585 int poweroff_method; 586 char oem_id[APIC_MPS_OEM_ID_LEN + 1]; /* MAX + 1 for NULL */ 587 char prod_id[APIC_MPS_PROD_ID_LEN + 1]; /* MAX + 1 for NULL */ 588 } apic_mps_ids[] = { 589 { APIC_POWEROFF_VIA_RTC, "INTEL", "ALDER" }, /* 4300 */ 590 { APIC_POWEROFF_VIA_RTC, "NCR", "AMC" }, /* 4300 */ 591 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "A450NX" }, /* 4400? */ 592 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AD450NX" }, /* 4400 */ 593 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AC450NX" }, /* 4400R */ 594 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "S450NX" }, /* S50 */ 595 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "SC450NX" } /* S50? */ 596 }; 597 598 int apic_poweroff_method = APIC_POWEROFF_NONE; 599 600 static struct { 601 uchar_t cntl; 602 uchar_t data; 603 } aspen_bmc[] = { 604 { CC_SMS_WR_START, 0x18 }, /* NetFn/LUN */ 605 { CC_SMS_WR_NEXT, 0x24 }, /* Cmd SET_WATCHDOG_TIMER */ 606 { CC_SMS_WR_NEXT, 0x84 }, /* DataByte 1: SMS/OS no log */ 607 { CC_SMS_WR_NEXT, 0x2 }, /* DataByte 2: Power Down */ 608 { CC_SMS_WR_NEXT, 0x0 }, /* DataByte 3: no pre-timeout */ 609 { CC_SMS_WR_NEXT, 0x0 }, /* DataByte 4: timer expir. */ 610 { CC_SMS_WR_NEXT, 0xa }, /* DataByte 5: init countdown */ 611 { CC_SMS_WR_END, 0x0 }, /* DataByte 6: init countdown */ 612 613 { CC_SMS_WR_START, 0x18 }, /* NetFn/LUN */ 614 { CC_SMS_WR_END, 0x22 } /* Cmd RESET_WATCHDOG_TIMER */ 615 }; 616 617 static struct { 618 int port; 619 uchar_t data; 620 } sitka_bmc[] = { 621 { SMS_COMMAND_REGISTER, SMS_WRITE_START }, 622 { SMS_DATA_REGISTER, 0x18 }, /* NetFn/LUN */ 623 { SMS_DATA_REGISTER, 0x24 }, /* Cmd SET_WATCHDOG_TIMER */ 624 { SMS_DATA_REGISTER, 0x84 }, /* DataByte 1: SMS/OS no log */ 625 { SMS_DATA_REGISTER, 0x2 }, /* DataByte 2: Power Down */ 626 { SMS_DATA_REGISTER, 0x0 }, /* DataByte 3: no pre-timeout */ 627 { SMS_DATA_REGISTER, 0x0 }, /* DataByte 4: timer expir. */ 628 { SMS_DATA_REGISTER, 0xa }, /* DataByte 5: init countdown */ 629 { SMS_COMMAND_REGISTER, SMS_WRITE_END }, 630 { SMS_DATA_REGISTER, 0x0 }, /* DataByte 6: init countdown */ 631 632 { SMS_COMMAND_REGISTER, SMS_WRITE_START }, 633 { SMS_DATA_REGISTER, 0x18 }, /* NetFn/LUN */ 634 { SMS_COMMAND_REGISTER, SMS_WRITE_END }, 635 { SMS_DATA_REGISTER, 0x22 } /* Cmd RESET_WATCHDOG_TIMER */ 636 }; 637 638 639 /* Patchable global variables. */ 640 int apic_kmdb_on_nmi = 0; /* 0 - no, 1 - yes enter kmdb */ 641 int apic_debug_mps_id = 0; /* 1 - print MPS ID strings */ 642 643 /* 644 * ACPI definitions 645 */ 646 /* _PIC method arguments */ 647 #define ACPI_PIC_MODE 0 648 #define ACPI_APIC_MODE 1 649 650 /* APIC error flags we care about */ 651 #define APIC_SEND_CS_ERROR 0x01 652 #define APIC_RECV_CS_ERROR 0x02 653 #define APIC_CS_ERRORS (APIC_SEND_CS_ERROR|APIC_RECV_CS_ERROR) 654 655 /* 656 * ACPI variables 657 */ 658 /* 1 = acpi is enabled & working, 0 = acpi is not enabled or not there */ 659 static int apic_enable_acpi = 0; 660 661 /* ACPI Multiple APIC Description Table ptr */ 662 static MULTIPLE_APIC_TABLE *acpi_mapic_dtp = NULL; 663 664 /* ACPI Interrupt Source Override Structure ptr */ 665 static MADT_INTERRUPT_OVERRIDE *acpi_isop = NULL; 666 static int acpi_iso_cnt = 0; 667 668 /* ACPI Non-maskable Interrupt Sources ptr */ 669 static MADT_NMI_SOURCE *acpi_nmi_sp = NULL; 670 static int acpi_nmi_scnt = 0; 671 static MADT_LOCAL_APIC_NMI *acpi_nmi_cp = NULL; 672 static int acpi_nmi_ccnt = 0; 673 674 /* 675 * extern declarations 676 */ 677 extern int intr_clear(void); 678 extern void intr_restore(uint_t); 679 #if defined(__amd64) 680 extern int intpri_use_cr8; 681 #endif /* __amd64 */ 682 683 extern int apic_pci_msi_enable_vector(dev_info_t *, int, int, 684 int, int, int); 685 extern apic_irq_t *apic_find_irq(dev_info_t *, struct intrspec *, int); 686 687 /* 688 * This is the loadable module wrapper 689 */ 690 691 int 692 _init(void) 693 { 694 if (apic_coarse_hrtime) 695 apic_ops.psm_gethrtime = &apic_gettime; 696 return (psm_mod_init(&apic_hdlp, &apic_psm_info)); 697 } 698 699 int 700 _fini(void) 701 { 702 return (psm_mod_fini(&apic_hdlp, &apic_psm_info)); 703 } 704 705 int 706 _info(struct modinfo *modinfop) 707 { 708 return (psm_mod_info(&apic_hdlp, &apic_psm_info, modinfop)); 709 } 710 711 /* 712 * Auto-configuration routines 713 */ 714 715 /* 716 * Look at MPSpec 1.4 (Intel Order # 242016-005) for details of what we do here 717 * May work with 1.1 - but not guaranteed. 718 * According to the MP Spec, the MP floating pointer structure 719 * will be searched in the order described below: 720 * 1. In the first kilobyte of Extended BIOS Data Area (EBDA) 721 * 2. Within the last kilobyte of system base memory 722 * 3. In the BIOS ROM address space between 0F0000h and 0FFFFh 723 * Once we find the right signature with proper checksum, we call 724 * either handle_defconf or parse_mpct to get all info necessary for 725 * subsequent operations. 726 */ 727 static int 728 apic_probe() 729 { 730 uint32_t mpct_addr, ebda_start = 0, base_mem_end; 731 caddr_t biosdatap; 732 caddr_t mpct; 733 caddr_t fptr; 734 int i, mpct_size, mapsize, retval = PSM_FAILURE; 735 ushort_t ebda_seg, base_mem_size; 736 struct apic_mpfps_hdr *fpsp; 737 struct apic_mp_cnf_hdr *hdrp; 738 int bypass_cpu_and_ioapics_in_mptables; 739 int acpi_user_options; 740 741 if (apic_forceload < 0) 742 return (retval); 743 744 /* Allow override for MADT-only mode */ 745 acpi_user_options = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_root_node(), 0, 746 "acpi-user-options", 0); 747 apic_use_acpi_madt_only = ((acpi_user_options & ACPI_OUSER_MADT) != 0); 748 749 /* Allow apic_use_acpi to override MADT-only mode */ 750 if (!apic_use_acpi) 751 apic_use_acpi_madt_only = 0; 752 753 retval = acpi_probe(); 754 755 /* 756 * mapin the bios data area 40:0 757 * 40:13h - two-byte location reports the base memory size 758 * 40:0Eh - two-byte location for the exact starting address of 759 * the EBDA segment for EISA 760 */ 761 biosdatap = psm_map_phys(0x400, 0x20, PROT_READ); 762 if (!biosdatap) 763 return (retval); 764 fpsp = (struct apic_mpfps_hdr *)NULL; 765 mapsize = MPFPS_RAM_WIN_LEN; 766 /*LINTED: pointer cast may result in improper alignment */ 767 ebda_seg = *((ushort_t *)(biosdatap+0xe)); 768 /* check the 1k of EBDA */ 769 if (ebda_seg) { 770 ebda_start = ((uint32_t)ebda_seg) << 4; 771 fptr = psm_map_phys(ebda_start, MPFPS_RAM_WIN_LEN, PROT_READ); 772 if (fptr) { 773 if (!(fpsp = 774 apic_find_fps_sig(fptr, MPFPS_RAM_WIN_LEN))) 775 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN); 776 } 777 } 778 /* If not in EBDA, check the last k of system base memory */ 779 if (!fpsp) { 780 /*LINTED: pointer cast may result in improper alignment */ 781 base_mem_size = *((ushort_t *)(biosdatap + 0x13)); 782 783 if (base_mem_size > 512) 784 base_mem_end = 639 * 1024; 785 else 786 base_mem_end = 511 * 1024; 787 /* if ebda == last k of base mem, skip to check BIOS ROM */ 788 if (base_mem_end != ebda_start) { 789 790 fptr = psm_map_phys(base_mem_end, MPFPS_RAM_WIN_LEN, 791 PROT_READ); 792 793 if (fptr) { 794 if (!(fpsp = apic_find_fps_sig(fptr, 795 MPFPS_RAM_WIN_LEN))) 796 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN); 797 } 798 } 799 } 800 psm_unmap_phys(biosdatap, 0x20); 801 802 /* If still cannot find it, check the BIOS ROM space */ 803 if (!fpsp) { 804 mapsize = MPFPS_ROM_WIN_LEN; 805 fptr = psm_map_phys(MPFPS_ROM_WIN_START, 806 MPFPS_ROM_WIN_LEN, PROT_READ); 807 if (fptr) { 808 if (!(fpsp = 809 apic_find_fps_sig(fptr, MPFPS_ROM_WIN_LEN))) { 810 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 811 return (retval); 812 } 813 } 814 } 815 816 if (apic_checksum((caddr_t)fpsp, fpsp->mpfps_length * 16) != 0) { 817 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 818 return (retval); 819 } 820 821 apic_spec_rev = fpsp->mpfps_spec_rev; 822 if ((apic_spec_rev != 04) && (apic_spec_rev != 01)) { 823 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 824 return (retval); 825 } 826 827 /* check IMCR is present or not */ 828 apic_imcrp = fpsp->mpfps_featinfo2 & MPFPS_FEATINFO2_IMCRP; 829 830 /* check default configuration (dual CPUs) */ 831 if ((apic_defconf = fpsp->mpfps_featinfo1) != 0) { 832 psm_unmap_phys(fptr, mapsize); 833 return (apic_handle_defconf()); 834 } 835 836 /* MP Configuration Table */ 837 mpct_addr = (uint32_t)(fpsp->mpfps_mpct_paddr); 838 839 psm_unmap_phys(fptr, mapsize); /* unmap floating ptr struct */ 840 841 /* 842 * Map in enough memory for the MP Configuration Table Header. 843 * Use this table to read the total length of the BIOS data and 844 * map in all the info 845 */ 846 /*LINTED: pointer cast may result in improper alignment */ 847 hdrp = (struct apic_mp_cnf_hdr *)psm_map_phys(mpct_addr, 848 sizeof (struct apic_mp_cnf_hdr), PROT_READ); 849 if (!hdrp) 850 return (retval); 851 852 /* check mp configuration table signature PCMP */ 853 if (hdrp->mpcnf_sig != 0x504d4350) { 854 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr)); 855 return (retval); 856 } 857 mpct_size = (int)hdrp->mpcnf_tbl_length; 858 859 apic_set_pwroff_method_from_mpcnfhdr(hdrp); 860 861 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr)); 862 863 if ((retval == PSM_SUCCESS) && !apic_use_acpi_madt_only) { 864 /* This is an ACPI machine No need for further checks */ 865 return (retval); 866 } 867 868 /* 869 * Map in the entries for this machine, ie. Processor 870 * Entry Tables, Bus Entry Tables, etc. 871 * They are in fixed order following one another 872 */ 873 mpct = psm_map_phys(mpct_addr, mpct_size, PROT_READ); 874 if (!mpct) 875 return (retval); 876 877 if (apic_checksum(mpct, mpct_size) != 0) 878 goto apic_fail1; 879 880 881 /*LINTED: pointer cast may result in improper alignment */ 882 hdrp = (struct apic_mp_cnf_hdr *)mpct; 883 /*LINTED: pointer cast may result in improper alignment */ 884 apicadr = (uint32_t *)psm_map_phys((uint32_t)hdrp->mpcnf_local_apic, 885 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE); 886 if (!apicadr) 887 goto apic_fail1; 888 889 /* Parse all information in the tables */ 890 bypass_cpu_and_ioapics_in_mptables = (retval == PSM_SUCCESS); 891 if (apic_parse_mpct(mpct, bypass_cpu_and_ioapics_in_mptables) == 892 PSM_SUCCESS) 893 return (PSM_SUCCESS); 894 895 for (i = 0; i < apic_io_max; i++) 896 psm_unmap_phys((caddr_t)apicioadr[i], APIC_IO_MEMLEN); 897 if (apic_cpus) 898 kmem_free(apic_cpus, sizeof (*apic_cpus) * apic_nproc); 899 if (apicadr) 900 psm_unmap_phys((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 901 apic_fail1: 902 psm_unmap_phys(mpct, mpct_size); 903 return (retval); 904 } 905 906 static void 907 apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp) 908 { 909 int i; 910 911 for (i = 0; i < (sizeof (apic_mps_ids) / sizeof (apic_mps_ids[0])); 912 i++) { 913 if ((strncmp(hdrp->mpcnf_oem_str, apic_mps_ids[i].oem_id, 914 strlen(apic_mps_ids[i].oem_id)) == 0) && 915 (strncmp(hdrp->mpcnf_prod_str, apic_mps_ids[i].prod_id, 916 strlen(apic_mps_ids[i].prod_id)) == 0)) { 917 918 apic_poweroff_method = apic_mps_ids[i].poweroff_method; 919 break; 920 } 921 } 922 923 if (apic_debug_mps_id != 0) { 924 cmn_err(CE_CONT, "pcplusmp: MPS OEM ID = '%c%c%c%c%c%c%c%c'" 925 "Product ID = '%c%c%c%c%c%c%c%c%c%c%c%c'\n", 926 hdrp->mpcnf_oem_str[0], 927 hdrp->mpcnf_oem_str[1], 928 hdrp->mpcnf_oem_str[2], 929 hdrp->mpcnf_oem_str[3], 930 hdrp->mpcnf_oem_str[4], 931 hdrp->mpcnf_oem_str[5], 932 hdrp->mpcnf_oem_str[6], 933 hdrp->mpcnf_oem_str[7], 934 hdrp->mpcnf_prod_str[0], 935 hdrp->mpcnf_prod_str[1], 936 hdrp->mpcnf_prod_str[2], 937 hdrp->mpcnf_prod_str[3], 938 hdrp->mpcnf_prod_str[4], 939 hdrp->mpcnf_prod_str[5], 940 hdrp->mpcnf_prod_str[6], 941 hdrp->mpcnf_prod_str[7], 942 hdrp->mpcnf_prod_str[8], 943 hdrp->mpcnf_prod_str[9], 944 hdrp->mpcnf_prod_str[10], 945 hdrp->mpcnf_prod_str[11]); 946 } 947 } 948 949 static int 950 acpi_probe(void) 951 { 952 int i, id, intmax, ver, index, rv; 953 int acpi_verboseflags = 0; 954 int madt_seen, madt_size; 955 APIC_HEADER *ap; 956 MADT_PROCESSOR_APIC *mpa; 957 MADT_IO_APIC *mia; 958 MADT_IO_SAPIC *misa; 959 MADT_INTERRUPT_OVERRIDE *mio; 960 MADT_NMI_SOURCE *mns; 961 MADT_INTERRUPT_SOURCE *mis; 962 MADT_LOCAL_APIC_NMI *mlan; 963 MADT_ADDRESS_OVERRIDE *mao; 964 ACPI_OBJECT_LIST arglist; 965 ACPI_OBJECT arg; 966 int sci; 967 iflag_t sci_flags; 968 volatile int32_t *ioapic; 969 char local_ids[NCPU]; 970 char proc_ids[NCPU]; 971 uchar_t hid; 972 973 if (!apic_use_acpi) 974 return (PSM_FAILURE); 975 976 if (AcpiGetFirmwareTable(APIC_SIG, 1, ACPI_LOGICAL_ADDRESSING, 977 (ACPI_TABLE_HEADER **) &acpi_mapic_dtp) != AE_OK) 978 return (PSM_FAILURE); 979 980 apicadr = (uint32_t *)psm_map_phys( 981 (uint32_t)acpi_mapic_dtp->LocalApicAddress, 982 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE); 983 if (!apicadr) 984 return (PSM_FAILURE); 985 986 id = apicadr[APIC_LID_REG]; 987 local_ids[0] = (uchar_t)(((uint_t)id) >> 24); 988 apic_nproc = index = 1; 989 apic_io_max = 0; 990 991 ap = (APIC_HEADER *) (acpi_mapic_dtp + 1); 992 madt_size = acpi_mapic_dtp->Length; 993 madt_seen = sizeof (*acpi_mapic_dtp); 994 995 while (madt_seen < madt_size) { 996 switch (ap->Type) { 997 case APIC_PROCESSOR: 998 mpa = (MADT_PROCESSOR_APIC *) ap; 999 if (mpa->ProcessorEnabled) { 1000 if (mpa->LocalApicId == local_ids[0]) 1001 proc_ids[0] = mpa->ProcessorId; 1002 else if (apic_nproc < NCPU) { 1003 local_ids[index] = mpa->LocalApicId; 1004 proc_ids[index] = mpa->ProcessorId; 1005 index++; 1006 apic_nproc++; 1007 } else 1008 cmn_err(CE_WARN, "pcplusmp: exceeded " 1009 "maximum no. of CPUs (= %d)", NCPU); 1010 } 1011 break; 1012 1013 case APIC_IO: 1014 mia = (MADT_IO_APIC *) ap; 1015 if (apic_io_max < MAX_IO_APIC) { 1016 apic_io_id[apic_io_max] = mia->IoApicId; 1017 apic_io_vectbase[apic_io_max] = 1018 mia->Interrupt; 1019 ioapic = apicioadr[apic_io_max] = 1020 (int32_t *)psm_map_phys( 1021 (uint32_t)mia->Address, 1022 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 1023 if (!ioapic) 1024 goto cleanup; 1025 apic_io_max++; 1026 } 1027 break; 1028 1029 case APIC_XRUPT_OVERRIDE: 1030 mio = (MADT_INTERRUPT_OVERRIDE *) ap; 1031 if (acpi_isop == NULL) 1032 acpi_isop = mio; 1033 acpi_iso_cnt++; 1034 break; 1035 1036 case APIC_NMI: 1037 /* UNIMPLEMENTED */ 1038 mns = (MADT_NMI_SOURCE *) ap; 1039 if (acpi_nmi_sp == NULL) 1040 acpi_nmi_sp = mns; 1041 acpi_nmi_scnt++; 1042 1043 cmn_err(CE_NOTE, "!apic: nmi source: %d %d %d\n", 1044 mns->Interrupt, mns->Polarity, 1045 mns->TriggerMode); 1046 break; 1047 1048 case APIC_LOCAL_NMI: 1049 /* UNIMPLEMENTED */ 1050 mlan = (MADT_LOCAL_APIC_NMI *) ap; 1051 if (acpi_nmi_cp == NULL) 1052 acpi_nmi_cp = mlan; 1053 acpi_nmi_ccnt++; 1054 1055 cmn_err(CE_NOTE, "!apic: local nmi: %d %d %d %d\n", 1056 mlan->ProcessorId, mlan->Polarity, 1057 mlan->TriggerMode, mlan->Lint); 1058 break; 1059 1060 case APIC_ADDRESS_OVERRIDE: 1061 /* UNIMPLEMENTED */ 1062 mao = (MADT_ADDRESS_OVERRIDE *) ap; 1063 cmn_err(CE_NOTE, "!apic: address override: %lx\n", 1064 (long)mao->Address); 1065 break; 1066 1067 case APIC_IO_SAPIC: 1068 /* UNIMPLEMENTED */ 1069 misa = (MADT_IO_SAPIC *) ap; 1070 1071 cmn_err(CE_NOTE, "!apic: io sapic: %d %d %lx\n", 1072 misa->IoSapicId, misa->InterruptBase, 1073 (long)misa->Address); 1074 break; 1075 1076 case APIC_XRUPT_SOURCE: 1077 /* UNIMPLEMENTED */ 1078 mis = (MADT_INTERRUPT_SOURCE *) ap; 1079 1080 cmn_err(CE_NOTE, 1081 "!apic: irq source: %d %d %d %d %d %d %d\n", 1082 mis->ProcessorId, mis->ProcessorEid, 1083 mis->Interrupt, mis->Polarity, 1084 mis->TriggerMode, mis->InterruptType, 1085 mis->IoSapicVector); 1086 break; 1087 case APIC_RESERVED: 1088 default: 1089 goto cleanup; 1090 } 1091 1092 /* advance to next entry */ 1093 madt_seen += ap->Length; 1094 ap = (APIC_HEADER *)(((char *)ap) + ap->Length); 1095 } 1096 1097 if ((apic_cpus = kmem_zalloc(sizeof (*apic_cpus) * apic_nproc, 1098 KM_NOSLEEP)) == NULL) 1099 goto cleanup; 1100 1101 apic_cpumask = (1 << apic_nproc) - 1; 1102 1103 /* 1104 * ACPI doesn't provide the local apic ver, get it directly from the 1105 * local apic 1106 */ 1107 ver = apicadr[APIC_VERS_REG]; 1108 for (i = 0; i < apic_nproc; i++) { 1109 apic_cpus[i].aci_local_id = local_ids[i]; 1110 apic_cpus[i].aci_local_ver = (uchar_t)(ver & 0xFF); 1111 } 1112 for (i = 0; i < apic_io_max; i++) { 1113 ioapic = apicioadr[i]; 1114 1115 /* 1116 * need to check Sitka on the following acpi problem 1117 * On the Sitka, the ioapic's apic_id field isn't reporting 1118 * the actual io apic id. We have reported this problem 1119 * to Intel. Until they fix the problem, we will get the 1120 * actual id directly from the ioapic. 1121 */ 1122 ioapic[APIC_IO_REG] = APIC_ID_CMD; 1123 id = ioapic[APIC_IO_DATA]; 1124 hid = (uchar_t)(((uint_t)id) >> 24); 1125 1126 if (hid != apic_io_id[i]) { 1127 if (apic_io_id[i] == 0) 1128 apic_io_id[i] = hid; 1129 else { /* set ioapic id to whatever reported by ACPI */ 1130 id = ((int32_t)apic_io_id[i]) << 24; 1131 ioapic[APIC_IO_REG] = APIC_ID_CMD; 1132 ioapic[APIC_IO_DATA] = id; 1133 } 1134 } 1135 ioapic[APIC_IO_REG] = APIC_VERS_CMD; 1136 ver = ioapic[APIC_IO_DATA]; 1137 apic_io_ver[i] = (uchar_t)(ver & 0xff); 1138 intmax = (ver >> 16) & 0xff; 1139 apic_io_vectend[i] = apic_io_vectbase[i] + intmax; 1140 if (apic_first_avail_irq <= apic_io_vectend[i]) 1141 apic_first_avail_irq = apic_io_vectend[i] + 1; 1142 } 1143 1144 1145 /* 1146 * Process SCI configuration here 1147 * An error may be returned here if 1148 * acpi-user-options specifies legacy mode 1149 * (no SCI, no ACPI mode) 1150 */ 1151 if (acpica_get_sci(&sci, &sci_flags) != AE_OK) 1152 sci = -1; 1153 1154 /* 1155 * Now call acpi_init() to generate namespaces 1156 * If this fails, we don't attempt to use ACPI 1157 * even if we were able to get a MADT above 1158 */ 1159 if (acpica_init() != AE_OK) 1160 goto cleanup; 1161 1162 /* 1163 * Squirrel away the SCI and flags for later on 1164 * in apic_picinit() when we're ready 1165 */ 1166 apic_sci_vect = sci; 1167 apic_sci_flags = sci_flags; 1168 1169 if (apic_verbose & APIC_VERBOSE_IRQ_FLAG) 1170 acpi_verboseflags |= PSM_VERBOSE_IRQ_FLAG; 1171 1172 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) 1173 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_FLAG; 1174 1175 if (apic_verbose & APIC_VERBOSE_POWEROFF_PAUSE_FLAG) 1176 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_PAUSE_FLAG; 1177 1178 if (acpi_psm_init(apic_psm_info.p_mach_idstring, acpi_verboseflags) == 1179 ACPI_PSM_FAILURE) 1180 goto cleanup; 1181 1182 /* Enable ACPI APIC interrupt routing */ 1183 arglist.Count = 1; 1184 arglist.Pointer = &arg; 1185 arg.Type = ACPI_TYPE_INTEGER; 1186 arg.Integer.Value = ACPI_APIC_MODE; /* 1 */ 1187 rv = AcpiEvaluateObject(NULL, "\\_PIC", &arglist, NULL); 1188 if (rv == AE_OK) { 1189 build_reserved_irqlist((uchar_t *)apic_reserved_irqlist); 1190 apic_enable_acpi = 1; 1191 if (apic_use_acpi_madt_only) { 1192 cmn_err(CE_CONT, 1193 "?Using ACPI for CPU/IOAPIC information ONLY\n"); 1194 } 1195 return (PSM_SUCCESS); 1196 } 1197 /* if setting APIC mode failed above, we fall through to cleanup */ 1198 1199 cleanup: 1200 if (apicadr != NULL) { 1201 psm_unmap_phys((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 1202 apicadr = NULL; 1203 } 1204 apic_nproc = 0; 1205 for (i = 0; i < apic_io_max; i++) { 1206 psm_unmap_phys((caddr_t)apicioadr[i], APIC_IO_MEMLEN); 1207 apicioadr[i] = NULL; 1208 } 1209 apic_io_max = 0; 1210 acpi_isop = NULL; 1211 acpi_iso_cnt = 0; 1212 acpi_nmi_sp = NULL; 1213 acpi_nmi_scnt = 0; 1214 acpi_nmi_cp = NULL; 1215 acpi_nmi_ccnt = 0; 1216 return (PSM_FAILURE); 1217 } 1218 1219 /* 1220 * Handle default configuration. Fill in reqd global variables & tables 1221 * Fill all details as MP table does not give any more info 1222 */ 1223 static int 1224 apic_handle_defconf() 1225 { 1226 uint_t lid; 1227 1228 /*LINTED: pointer cast may result in improper alignment */ 1229 apicioadr[0] = (int32_t *)psm_map_phys(APIC_IO_ADDR, 1230 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 1231 /*LINTED: pointer cast may result in improper alignment */ 1232 apicadr = (uint32_t *)psm_map_phys(APIC_LOCAL_ADDR, 1233 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE); 1234 apic_cpus = (apic_cpus_info_t *) 1235 kmem_zalloc(sizeof (*apic_cpus) * 2, KM_NOSLEEP); 1236 if ((!apicadr) || (!apicioadr[0]) || (!apic_cpus)) 1237 goto apic_handle_defconf_fail; 1238 apic_cpumask = 3; 1239 apic_nproc = 2; 1240 lid = apicadr[APIC_LID_REG]; 1241 apic_cpus[0].aci_local_id = (uchar_t)(lid >> APIC_ID_BIT_OFFSET); 1242 /* 1243 * According to the PC+MP spec 1.1, the local ids 1244 * for the default configuration has to be 0 or 1 1245 */ 1246 if (apic_cpus[0].aci_local_id == 1) 1247 apic_cpus[1].aci_local_id = 0; 1248 else if (apic_cpus[0].aci_local_id == 0) 1249 apic_cpus[1].aci_local_id = 1; 1250 else 1251 goto apic_handle_defconf_fail; 1252 1253 apic_io_id[0] = 2; 1254 apic_io_max = 1; 1255 if (apic_defconf >= 5) { 1256 apic_cpus[0].aci_local_ver = APIC_INTEGRATED_VERS; 1257 apic_cpus[1].aci_local_ver = APIC_INTEGRATED_VERS; 1258 apic_io_ver[0] = APIC_INTEGRATED_VERS; 1259 } else { 1260 apic_cpus[0].aci_local_ver = 0; /* 82489 DX */ 1261 apic_cpus[1].aci_local_ver = 0; 1262 apic_io_ver[0] = 0; 1263 } 1264 if (apic_defconf == 2 || apic_defconf == 3 || apic_defconf == 6) 1265 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) | 1266 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1); 1267 return (PSM_SUCCESS); 1268 1269 apic_handle_defconf_fail: 1270 if (apic_cpus) 1271 kmem_free(apic_cpus, sizeof (*apic_cpus) * 2); 1272 if (apicadr) 1273 psm_unmap_phys((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 1274 if (apicioadr[0]) 1275 psm_unmap_phys((caddr_t)apicioadr[0], APIC_IO_MEMLEN); 1276 return (PSM_FAILURE); 1277 } 1278 1279 /* Parse the entries in MP configuration table and collect info that we need */ 1280 static int 1281 apic_parse_mpct(caddr_t mpct, int bypass_cpus_and_ioapics) 1282 { 1283 struct apic_procent *procp; 1284 struct apic_bus *busp; 1285 struct apic_io_entry *ioapicp; 1286 struct apic_io_intr *intrp; 1287 volatile int32_t *ioapic; 1288 uint_t lid; 1289 int id; 1290 uchar_t hid; 1291 1292 /*LINTED: pointer cast may result in improper alignment */ 1293 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr)); 1294 1295 /* No need to count cpu entries if we won't use them */ 1296 if (!bypass_cpus_and_ioapics) { 1297 1298 /* Find max # of CPUS and allocate structure accordingly */ 1299 apic_nproc = 0; 1300 while (procp->proc_entry == APIC_CPU_ENTRY) { 1301 if (procp->proc_cpuflags & CPUFLAGS_EN) { 1302 apic_nproc++; 1303 } 1304 procp++; 1305 } 1306 if (apic_nproc > NCPU) 1307 cmn_err(CE_WARN, "pcplusmp: exceeded " 1308 "maximum no. of CPUs (= %d)", NCPU); 1309 if (!apic_nproc || !(apic_cpus = (apic_cpus_info_t *) 1310 kmem_zalloc(sizeof (*apic_cpus)*apic_nproc, KM_NOSLEEP))) 1311 return (PSM_FAILURE); 1312 } 1313 1314 /*LINTED: pointer cast may result in improper alignment */ 1315 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr)); 1316 1317 /* 1318 * start with index 1 as 0 needs to be filled in with Boot CPU, but 1319 * if we're bypassing this information, it has already been filled 1320 * in by acpi_probe(), so don't overwrite it. 1321 */ 1322 if (!bypass_cpus_and_ioapics) 1323 apic_nproc = 1; 1324 1325 while (procp->proc_entry == APIC_CPU_ENTRY) { 1326 /* check whether the cpu exists or not */ 1327 if (!bypass_cpus_and_ioapics && 1328 procp->proc_cpuflags & CPUFLAGS_EN) { 1329 if (procp->proc_cpuflags & CPUFLAGS_BP) { /* Boot CPU */ 1330 lid = apicadr[APIC_LID_REG]; 1331 apic_cpus[0].aci_local_id = procp->proc_apicid; 1332 if (apic_cpus[0].aci_local_id != 1333 (uchar_t)(lid >> APIC_ID_BIT_OFFSET)) { 1334 return (PSM_FAILURE); 1335 } 1336 apic_cpus[0].aci_local_ver = 1337 procp->proc_version; 1338 } else { 1339 1340 apic_cpus[apic_nproc].aci_local_id = 1341 procp->proc_apicid; 1342 apic_cpus[apic_nproc].aci_local_ver = 1343 procp->proc_version; 1344 apic_nproc++; 1345 1346 } 1347 } 1348 procp++; 1349 } 1350 1351 if (!bypass_cpus_and_ioapics) { 1352 /* convert the number of processors into a cpumask */ 1353 apic_cpumask = (1 << apic_nproc) - 1; 1354 } 1355 1356 /* 1357 * Save start of bus entries for later use. 1358 * Get EISA level cntrl if EISA bus is present. 1359 * Also get the CPI bus id for single CPI bus case 1360 */ 1361 apic_busp = busp = (struct apic_bus *)procp; 1362 while (busp->bus_entry == APIC_BUS_ENTRY) { 1363 lid = apic_find_bus_type((char *)&busp->bus_str1); 1364 if (lid == BUS_EISA) { 1365 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) | 1366 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1); 1367 } else if (lid == BUS_PCI) { 1368 /* 1369 * apic_single_pci_busid will be used only if 1370 * apic_pic_bus_total is equal to 1 1371 */ 1372 apic_pci_bus_total++; 1373 apic_single_pci_busid = busp->bus_id; 1374 } 1375 busp++; 1376 } 1377 1378 ioapicp = (struct apic_io_entry *)busp; 1379 1380 if (!bypass_cpus_and_ioapics) 1381 apic_io_max = 0; 1382 do { 1383 if (!bypass_cpus_and_ioapics && apic_io_max < MAX_IO_APIC) { 1384 if (ioapicp->io_flags & IOAPIC_FLAGS_EN) { 1385 apic_io_id[apic_io_max] = ioapicp->io_apicid; 1386 apic_io_ver[apic_io_max] = ioapicp->io_version; 1387 /*LINTED: pointer cast may result in improper alignment */ 1388 apicioadr[apic_io_max] = 1389 (int32_t *)psm_map_phys( 1390 (uint32_t)ioapicp->io_apic_addr, 1391 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 1392 1393 if (!apicioadr[apic_io_max]) 1394 return (PSM_FAILURE); 1395 1396 ioapic = apicioadr[apic_io_max]; 1397 ioapic[APIC_IO_REG] = APIC_ID_CMD; 1398 id = ioapic[APIC_IO_DATA]; 1399 hid = (uchar_t)(((uint_t)id) >> 24); 1400 1401 if (hid != apic_io_id[apic_io_max]) { 1402 if (apic_io_id[apic_io_max] == 0) 1403 apic_io_id[apic_io_max] = hid; 1404 else { 1405 /* 1406 * set ioapic id to whatever 1407 * reported by MPS 1408 * 1409 * may not need to set index 1410 * again ??? 1411 * take it out and try 1412 */ 1413 1414 id = ((int32_t) 1415 apic_io_id[apic_io_max]) << 1416 24; 1417 1418 ioapic[APIC_IO_REG] = 1419 APIC_ID_CMD; 1420 1421 ioapic[APIC_IO_DATA] = id; 1422 1423 } 1424 } 1425 apic_io_max++; 1426 } 1427 } 1428 ioapicp++; 1429 } while (ioapicp->io_entry == APIC_IO_ENTRY); 1430 1431 apic_io_intrp = (struct apic_io_intr *)ioapicp; 1432 1433 intrp = apic_io_intrp; 1434 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 1435 if ((intrp->intr_irq > APIC_MAX_ISA_IRQ) || 1436 (apic_find_bus(intrp->intr_busid) == BUS_PCI)) { 1437 apic_irq_translate = 1; 1438 break; 1439 } 1440 intrp++; 1441 } 1442 1443 return (PSM_SUCCESS); 1444 } 1445 1446 static struct apic_mpfps_hdr * 1447 apic_find_fps_sig(caddr_t cptr, int len) 1448 { 1449 int i; 1450 1451 /* Look for the pattern "_MP_" */ 1452 for (i = 0; i < len; i += 16) { 1453 if ((*(cptr+i) == '_') && 1454 (*(cptr+i+1) == 'M') && 1455 (*(cptr+i+2) == 'P') && 1456 (*(cptr+i+3) == '_')) 1457 /*LINTED: pointer cast may result in improper alignment */ 1458 return ((struct apic_mpfps_hdr *)(cptr + i)); 1459 } 1460 return (NULL); 1461 } 1462 1463 static int 1464 apic_checksum(caddr_t bptr, int len) 1465 { 1466 int i; 1467 uchar_t cksum; 1468 1469 cksum = 0; 1470 for (i = 0; i < len; i++) 1471 cksum += *bptr++; 1472 return ((int)cksum); 1473 } 1474 1475 1476 /* 1477 * Initialise vector->ipl and ipl->pri arrays. level_intr and irqtable 1478 * are also set to NULL. vector->irq is set to a value which cannot map 1479 * to a real irq to show that it is free. 1480 */ 1481 void 1482 apic_init() 1483 { 1484 int i; 1485 int *iptr; 1486 1487 int j = 1; 1488 apic_ipltopri[0] = APIC_VECTOR_PER_IPL; /* leave 0 for idle */ 1489 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) { 1490 if ((i < ((APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL) - 1)) && 1491 (apic_vectortoipl[i + 1] == apic_vectortoipl[i])) 1492 /* get to highest vector at the same ipl */ 1493 continue; 1494 for (; j <= apic_vectortoipl[i]; j++) { 1495 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + 1496 APIC_BASE_VECT; 1497 } 1498 } 1499 for (; j < MAXIPL + 1; j++) 1500 /* fill up any empty ipltopri slots */ 1501 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + APIC_BASE_VECT; 1502 1503 /* cpu 0 is always up */ 1504 apic_cpus[0].aci_status = APIC_CPU_ONLINE | APIC_CPU_INTR_ENABLE; 1505 1506 iptr = (int *)&apic_irq_table[0]; 1507 for (i = 0; i <= APIC_MAX_VECTOR; i++) { 1508 apic_level_intr[i] = 0; 1509 *iptr++ = NULL; 1510 apic_vector_to_irq[i] = APIC_RESV_IRQ; 1511 apic_reprogram_info[i].valid = 0; 1512 apic_reprogram_info[i].bindcpu = 0; 1513 apic_reprogram_info[i].timeouts = 0; 1514 } 1515 1516 /* 1517 * Allocate a dummy irq table entry for the reserved entry. 1518 * This takes care of the race between removing an irq and 1519 * clock detecting a CPU in that irq during interrupt load 1520 * sampling. 1521 */ 1522 apic_irq_table[APIC_RESV_IRQ] = 1523 kmem_zalloc(sizeof (apic_irq_t), KM_NOSLEEP); 1524 1525 mutex_init(&airq_mutex, NULL, MUTEX_DEFAULT, NULL); 1526 mutex_init(&apic_reprogram_timeout_mutex, NULL, MUTEX_DEFAULT, NULL); 1527 #if defined(__amd64) 1528 /* 1529 * Make cpu-specific interrupt info point to cr8pri vector 1530 */ 1531 for (i = 0; i <= MAXIPL; i++) 1532 apic_cr8pri[i] = apic_ipltopri[i] >> APIC_IPL_SHIFT; 1533 CPU->cpu_pri_data = apic_cr8pri; 1534 intpri_use_cr8 = 1; 1535 #endif /* __amd64 */ 1536 } 1537 1538 /* 1539 * handler for APIC Error interrupt. Just print a warning and continue 1540 */ 1541 static int 1542 apic_error_intr() 1543 { 1544 uint_t error0, error1, error; 1545 uint_t i; 1546 1547 /* 1548 * We need to write before read as per 7.4.17 of system prog manual. 1549 * We do both and or the results to be safe 1550 */ 1551 error0 = apicadr[APIC_ERROR_STATUS]; 1552 apicadr[APIC_ERROR_STATUS] = 0; 1553 error1 = apicadr[APIC_ERROR_STATUS]; 1554 error = error0 | error1; 1555 1556 /* 1557 * Clear the APIC error status (do this on all cpus that enter here) 1558 * (two writes are required due to the semantics of accessing the 1559 * error status register.) 1560 */ 1561 apicadr[APIC_ERROR_STATUS] = 0; 1562 apicadr[APIC_ERROR_STATUS] = 0; 1563 1564 /* 1565 * Prevent more than 1 CPU from handling error interrupt causing 1566 * double printing (interleave of characters from multiple 1567 * CPU's when using prom_printf) 1568 */ 1569 if (lock_try(&apic_error_lock) == 0) 1570 return (error ? DDI_INTR_CLAIMED : DDI_INTR_UNCLAIMED); 1571 if (error) { 1572 #if DEBUG 1573 if (apic_debug) 1574 debug_enter("pcplusmp: APIC Error interrupt received"); 1575 #endif /* DEBUG */ 1576 if (apic_panic_on_apic_error) 1577 cmn_err(CE_PANIC, 1578 "APIC Error interrupt on CPU %d. Status = %x\n", 1579 psm_get_cpu_id(), error); 1580 else { 1581 if ((error & ~APIC_CS_ERRORS) == 0) { 1582 /* cksum error only */ 1583 apic_error |= APIC_ERR_APIC_ERROR; 1584 apic_apic_error |= error; 1585 apic_num_apic_errors++; 1586 apic_num_cksum_errors++; 1587 } else { 1588 /* 1589 * prom_printf is the best shot we have of 1590 * something which is problem free from 1591 * high level/NMI type of interrupts 1592 */ 1593 prom_printf("APIC Error interrupt on CPU %d. " 1594 "Status 0 = %x, Status 1 = %x\n", 1595 psm_get_cpu_id(), error0, error1); 1596 apic_error |= APIC_ERR_APIC_ERROR; 1597 apic_apic_error |= error; 1598 apic_num_apic_errors++; 1599 for (i = 0; i < apic_error_display_delay; i++) { 1600 tenmicrosec(); 1601 } 1602 /* 1603 * provide more delay next time limited to 1604 * roughly 1 clock tick time 1605 */ 1606 if (apic_error_display_delay < 500) 1607 apic_error_display_delay *= 2; 1608 } 1609 } 1610 lock_clear(&apic_error_lock); 1611 return (DDI_INTR_CLAIMED); 1612 } else { 1613 lock_clear(&apic_error_lock); 1614 return (DDI_INTR_UNCLAIMED); 1615 } 1616 /* NOTREACHED */ 1617 } 1618 1619 /* 1620 * Turn off the mask bit in the performance counter Local Vector Table entry. 1621 */ 1622 static void 1623 apic_cpcovf_mask_clear(void) 1624 { 1625 apicadr[APIC_PCINT_VECT] &= ~APIC_LVT_MASK; 1626 } 1627 1628 static void 1629 apic_init_intr() 1630 { 1631 processorid_t cpun = psm_get_cpu_id(); 1632 1633 #if defined(__amd64) 1634 setcr8((ulong_t)(APIC_MASK_ALL >> APIC_IPL_SHIFT)); 1635 #else 1636 apicadr[APIC_TASK_REG] = APIC_MASK_ALL; 1637 #endif 1638 1639 if (apic_flat_model) 1640 apicadr[APIC_FORMAT_REG] = APIC_FLAT_MODEL; 1641 else 1642 apicadr[APIC_FORMAT_REG] = APIC_CLUSTER_MODEL; 1643 apicadr[APIC_DEST_REG] = AV_HIGH_ORDER >> cpun; 1644 1645 /* need to enable APIC before unmasking NMI */ 1646 apicadr[APIC_SPUR_INT_REG] = AV_UNIT_ENABLE | APIC_SPUR_INTR; 1647 1648 apicadr[APIC_LOCAL_TIMER] = AV_MASK; 1649 apicadr[APIC_INT_VECT0] = AV_MASK; /* local intr reg 0 */ 1650 apicadr[APIC_INT_VECT1] = AV_NMI; /* enable NMI */ 1651 1652 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) 1653 return; 1654 1655 /* Enable performance counter overflow interrupt */ 1656 1657 if ((x86_feature & X86_MSR) != X86_MSR) 1658 apic_enable_cpcovf_intr = 0; 1659 if (apic_enable_cpcovf_intr) { 1660 if (apic_cpcovf_vect == 0) { 1661 int ipl = APIC_PCINT_IPL; 1662 int irq = apic_get_ipivect(ipl, -1); 1663 1664 ASSERT(irq != -1); 1665 apic_cpcovf_vect = apic_irq_table[irq]->airq_vector; 1666 ASSERT(apic_cpcovf_vect); 1667 (void) add_avintr(NULL, ipl, 1668 (avfunc)kcpc_hw_overflow_intr, 1669 "apic pcint", irq, NULL, NULL, NULL); 1670 kcpc_hw_overflow_intr_installed = 1; 1671 kcpc_hw_enable_cpc_intr = apic_cpcovf_mask_clear; 1672 } 1673 apicadr[APIC_PCINT_VECT] = apic_cpcovf_vect; 1674 } 1675 1676 /* Enable error interrupt */ 1677 1678 if (apic_enable_error_intr) { 1679 if (apic_errvect == 0) { 1680 int ipl = 0xf; /* get highest priority intr */ 1681 int irq = apic_get_ipivect(ipl, -1); 1682 1683 ASSERT(irq != -1); 1684 apic_errvect = apic_irq_table[irq]->airq_vector; 1685 ASSERT(apic_errvect); 1686 /* 1687 * Not PSMI compliant, but we are going to merge 1688 * with ON anyway 1689 */ 1690 (void) add_avintr((void *)NULL, ipl, 1691 (avfunc)apic_error_intr, "apic error intr", 1692 irq, NULL, NULL, NULL); 1693 } 1694 apicadr[APIC_ERR_VECT] = apic_errvect; 1695 apicadr[APIC_ERROR_STATUS] = 0; 1696 apicadr[APIC_ERROR_STATUS] = 0; 1697 } 1698 } 1699 1700 static void 1701 apic_disable_local_apic() 1702 { 1703 apicadr[APIC_TASK_REG] = APIC_MASK_ALL; 1704 apicadr[APIC_LOCAL_TIMER] = AV_MASK; 1705 apicadr[APIC_INT_VECT0] = AV_MASK; /* local intr reg 0 */ 1706 apicadr[APIC_INT_VECT1] = AV_MASK; /* disable NMI */ 1707 apicadr[APIC_ERR_VECT] = AV_MASK; /* and error interrupt */ 1708 apicadr[APIC_PCINT_VECT] = AV_MASK; /* and perf counter intr */ 1709 apicadr[APIC_SPUR_INT_REG] = APIC_SPUR_INTR; 1710 } 1711 1712 static void 1713 apic_picinit(void) 1714 { 1715 int i, j; 1716 uint_t isr; 1717 volatile int32_t *ioapic; 1718 apic_irq_t *irqptr; 1719 struct intrspec ispec; 1720 1721 /* 1722 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr 1723 * bit on without clearing it with EOI. Since softint 1724 * uses vector 0x20 to interrupt itself, so softint will 1725 * not work on this machine. In order to fix this problem 1726 * a check is made to verify all the isr bits are clear. 1727 * If not, EOIs are issued to clear the bits. 1728 */ 1729 for (i = 7; i >= 1; i--) { 1730 if ((isr = apicadr[APIC_ISR_REG + (i * 4)]) != 0) 1731 for (j = 0; ((j < 32) && (isr != 0)); j++) 1732 if (isr & (1 << j)) { 1733 apicadr[APIC_EOI_REG] = 0; 1734 isr &= ~(1 << j); 1735 apic_error |= APIC_ERR_BOOT_EOI; 1736 } 1737 } 1738 1739 /* set a flag so we know we have run apic_picinit() */ 1740 apic_flag = 1; 1741 LOCK_INIT_CLEAR(&apic_gethrtime_lock); 1742 LOCK_INIT_CLEAR(&apic_ioapic_lock); 1743 LOCK_INIT_CLEAR(&apic_revector_lock); 1744 LOCK_INIT_CLEAR(&apic_ioapic_reprogram_lock); 1745 LOCK_INIT_CLEAR(&apic_error_lock); 1746 1747 picsetup(); /* initialise the 8259 */ 1748 1749 /* add nmi handler - least priority nmi handler */ 1750 LOCK_INIT_CLEAR(&apic_nmi_lock); 1751 1752 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr, 1753 "pcplusmp NMI handler", (caddr_t)NULL)) 1754 cmn_err(CE_WARN, "pcplusmp: Unable to add nmi handler"); 1755 1756 apic_init_intr(); 1757 1758 /* enable apic mode if imcr present */ 1759 if (apic_imcrp) { 1760 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT); 1761 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC); 1762 } 1763 1764 /* mask interrupt vectors */ 1765 for (j = 0; j < apic_io_max; j++) { 1766 int intin_max; 1767 ioapic = apicioadr[j]; 1768 ioapic[APIC_IO_REG] = APIC_VERS_CMD; 1769 /* Bits 23-16 define the maximum redirection entries */ 1770 intin_max = (ioapic[APIC_IO_DATA] >> 16) & 0xff; 1771 for (i = 0; i < intin_max; i++) { 1772 ioapic[APIC_IO_REG] = APIC_RDT_CMD + 2 * i; 1773 ioapic[APIC_IO_DATA] = AV_MASK; 1774 } 1775 } 1776 1777 /* 1778 * Hack alert: deal with ACPI SCI interrupt chicken/egg here 1779 */ 1780 if (apic_sci_vect > 0) { 1781 /* 1782 * acpica has already done add_avintr(); we just 1783 * to finish the job by mimicing translate_irq() 1784 * 1785 * Fake up an intrspec and setup the tables 1786 */ 1787 ispec.intrspec_vec = apic_sci_vect; 1788 ispec.intrspec_pri = SCI_IPL; 1789 1790 if (apic_setup_irq_table(NULL, apic_sci_vect, NULL, 1791 &ispec, &apic_sci_flags, DDI_INTR_TYPE_FIXED) < 0) { 1792 cmn_err(CE_WARN, "!apic: SCI setup failed"); 1793 return; 1794 } 1795 irqptr = apic_irq_table[apic_sci_vect]; 1796 1797 /* Program I/O APIC */ 1798 (void) apic_setup_io_intr(irqptr, apic_sci_vect); 1799 } 1800 } 1801 1802 1803 static void 1804 apic_cpu_start(processorid_t cpun, caddr_t rm_code) 1805 { 1806 int loop_count; 1807 uint32_t vector; 1808 uint_t cpu_id, iflag; 1809 1810 cpu_id = apic_cpus[cpun].aci_local_id; 1811 1812 apic_cmos_ssb_set = 1; 1813 1814 /* 1815 * Interrupts on BSP cpu will be disabled during these startup 1816 * steps in order to avoid unwanted side effects from 1817 * executing interrupt handlers on a problematic BIOS. 1818 */ 1819 1820 iflag = intr_clear(); 1821 outb(CMOS_ADDR, SSB); 1822 outb(CMOS_DATA, BIOS_SHUTDOWN); 1823 1824 while (get_apic_cmd1() & AV_PENDING) 1825 apic_ret(); 1826 1827 /* for integrated - make sure there is one INIT IPI in buffer */ 1828 /* for external - it will wake up the cpu */ 1829 apicadr[APIC_INT_CMD2] = cpu_id << APIC_ICR_ID_BIT_OFFSET; 1830 apicadr[APIC_INT_CMD1] = AV_ASSERT | AV_RESET; 1831 1832 /* If only 1 CPU is installed, PENDING bit will not go low */ 1833 for (loop_count = 0x1000; loop_count; loop_count--) 1834 if (get_apic_cmd1() & AV_PENDING) 1835 apic_ret(); 1836 else 1837 break; 1838 1839 apicadr[APIC_INT_CMD2] = cpu_id << APIC_ICR_ID_BIT_OFFSET; 1840 apicadr[APIC_INT_CMD1] = AV_DEASSERT | AV_RESET; 1841 1842 drv_usecwait(20000); /* 20 milli sec */ 1843 1844 if (apic_cpus[cpun].aci_local_ver >= APIC_INTEGRATED_VERS) { 1845 /* integrated apic */ 1846 1847 rm_code = (caddr_t)(uintptr_t)rm_platter_pa; 1848 vector = (rm_platter_pa >> MMU_PAGESHIFT) & 1849 (APIC_VECTOR_MASK | APIC_IPL_MASK); 1850 1851 /* to offset the INIT IPI queue up in the buffer */ 1852 apicadr[APIC_INT_CMD2] = cpu_id << APIC_ICR_ID_BIT_OFFSET; 1853 apicadr[APIC_INT_CMD1] = vector | AV_STARTUP; 1854 1855 drv_usecwait(200); /* 20 micro sec */ 1856 1857 apicadr[APIC_INT_CMD2] = cpu_id << APIC_ICR_ID_BIT_OFFSET; 1858 apicadr[APIC_INT_CMD1] = vector | AV_STARTUP; 1859 1860 drv_usecwait(200); /* 20 micro sec */ 1861 } 1862 intr_restore(iflag); 1863 } 1864 1865 1866 #ifdef DEBUG 1867 int apic_break_on_cpu = 9; 1868 int apic_stretch_interrupts = 0; 1869 int apic_stretch_ISR = 1 << 3; /* IPL of 3 matches nothing now */ 1870 1871 void 1872 apic_break() 1873 { 1874 } 1875 #endif /* DEBUG */ 1876 1877 /* 1878 * platform_intr_enter 1879 * 1880 * Called at the beginning of the interrupt service routine to 1881 * mask all level equal to and below the interrupt priority 1882 * of the interrupting vector. An EOI should be given to 1883 * the interrupt controller to enable other HW interrupts. 1884 * 1885 * Return -1 for spurious interrupts 1886 * 1887 */ 1888 /*ARGSUSED*/ 1889 static int 1890 apic_intr_enter(int ipl, int *vectorp) 1891 { 1892 uchar_t vector; 1893 int nipl; 1894 int irq, iflag; 1895 apic_cpus_info_t *cpu_infop; 1896 1897 /* 1898 * The real vector programmed in APIC is *vectorp + 0x20 1899 * But, cmnint code subtracts 0x20 before pushing it. 1900 * Hence APIC_BASE_VECT is 0x20. 1901 */ 1902 1903 vector = (uchar_t)*vectorp; 1904 1905 /* if interrupted by the clock, increment apic_nsec_since_boot */ 1906 if (vector == apic_clkvect) { 1907 if (!apic_oneshot) { 1908 /* NOTE: this is not MT aware */ 1909 apic_hrtime_stamp++; 1910 apic_nsec_since_boot += apic_nsec_per_intr; 1911 apic_hrtime_stamp++; 1912 last_count_read = apic_hertz_count; 1913 apic_redistribute_compute(); 1914 } 1915 1916 /* We will avoid all the book keeping overhead for clock */ 1917 nipl = apic_vectortoipl[vector >> APIC_IPL_SHIFT]; 1918 #if defined(__amd64) 1919 setcr8((ulong_t)apic_cr8pri[nipl]); 1920 #else 1921 apicadr[APIC_TASK_REG] = apic_ipltopri[nipl]; 1922 #endif 1923 *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT]; 1924 apicadr[APIC_EOI_REG] = 0; 1925 return (nipl); 1926 } 1927 1928 cpu_infop = &apic_cpus[psm_get_cpu_id()]; 1929 1930 if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) { 1931 cpu_infop->aci_spur_cnt++; 1932 return (APIC_INT_SPURIOUS); 1933 } 1934 1935 /* Check if the vector we got is really what we need */ 1936 if (apic_revector_pending) { 1937 /* 1938 * Disable interrupts for the duration of 1939 * the vector translation to prevent a self-race for 1940 * the apic_revector_lock. This cannot be done 1941 * in apic_xlate_vector because it is recursive and 1942 * we want the vector translation to be atomic with 1943 * respect to other (higher-priority) interrupts. 1944 */ 1945 iflag = intr_clear(); 1946 vector = apic_xlate_vector(vector + APIC_BASE_VECT) - 1947 APIC_BASE_VECT; 1948 intr_restore(iflag); 1949 } 1950 1951 nipl = apic_vectortoipl[vector >> APIC_IPL_SHIFT]; 1952 *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT]; 1953 1954 #if defined(__amd64) 1955 setcr8((ulong_t)apic_cr8pri[nipl]); 1956 #else 1957 apicadr[APIC_TASK_REG] = apic_ipltopri[nipl]; 1958 #endif 1959 1960 cpu_infop->aci_current[nipl] = (uchar_t)irq; 1961 cpu_infop->aci_curipl = (uchar_t)nipl; 1962 cpu_infop->aci_ISR_in_progress |= 1 << nipl; 1963 1964 /* 1965 * apic_level_intr could have been assimilated into the irq struct. 1966 * but, having it as a character array is more efficient in terms of 1967 * cache usage. So, we leave it as is. 1968 */ 1969 if (!apic_level_intr[irq]) 1970 apicadr[APIC_EOI_REG] = 0; 1971 1972 #ifdef DEBUG 1973 APIC_DEBUG_BUF_PUT(vector); 1974 APIC_DEBUG_BUF_PUT(irq); 1975 APIC_DEBUG_BUF_PUT(nipl); 1976 APIC_DEBUG_BUF_PUT(psm_get_cpu_id()); 1977 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl))) 1978 drv_usecwait(apic_stretch_interrupts); 1979 1980 if (apic_break_on_cpu == psm_get_cpu_id()) 1981 apic_break(); 1982 #endif /* DEBUG */ 1983 return (nipl); 1984 } 1985 1986 static void 1987 apic_intr_exit(int prev_ipl, int irq) 1988 { 1989 apic_cpus_info_t *cpu_infop; 1990 1991 #if defined(__amd64) 1992 setcr8((ulong_t)apic_cr8pri[prev_ipl]); 1993 #else 1994 apicadr[APIC_TASK_REG] = apic_ipltopri[prev_ipl]; 1995 #endif 1996 1997 cpu_infop = &apic_cpus[psm_get_cpu_id()]; 1998 if (apic_level_intr[irq]) 1999 apicadr[APIC_EOI_REG] = 0; 2000 2001 cpu_infop->aci_curipl = (uchar_t)prev_ipl; 2002 /* ISR above current pri could not be in progress */ 2003 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1; 2004 } 2005 2006 /* 2007 * Mask all interrupts below or equal to the given IPL 2008 */ 2009 static void 2010 apic_setspl(int ipl) 2011 { 2012 2013 #if defined(__amd64) 2014 setcr8((ulong_t)apic_cr8pri[ipl]); 2015 #else 2016 apicadr[APIC_TASK_REG] = apic_ipltopri[ipl]; 2017 #endif 2018 2019 /* interrupts at ipl above this cannot be in progress */ 2020 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1; 2021 /* 2022 * this is a patch fix for the ALR QSMP P5 machine, so that interrupts 2023 * have enough time to come in before the priority is raised again 2024 * during the idle() loop. 2025 */ 2026 if (apic_setspl_delay) 2027 (void) get_apic_pri(); 2028 } 2029 2030 /* 2031 * trigger a software interrupt at the given IPL 2032 */ 2033 static void 2034 apic_set_softintr(int ipl) 2035 { 2036 int vector; 2037 uint_t flag; 2038 2039 vector = apic_resv_vector[ipl]; 2040 2041 flag = intr_clear(); 2042 2043 while (get_apic_cmd1() & AV_PENDING) 2044 apic_ret(); 2045 2046 /* generate interrupt at vector on itself only */ 2047 apicadr[APIC_INT_CMD1] = AV_SH_SELF | vector; 2048 2049 intr_restore(flag); 2050 } 2051 2052 /* 2053 * generates an interprocessor interrupt to another CPU 2054 */ 2055 static void 2056 apic_send_ipi(int cpun, int ipl) 2057 { 2058 int vector; 2059 uint_t flag; 2060 2061 vector = apic_resv_vector[ipl]; 2062 2063 flag = intr_clear(); 2064 2065 while (get_apic_cmd1() & AV_PENDING) 2066 apic_ret(); 2067 2068 apicadr[APIC_INT_CMD2] = 2069 apic_cpus[cpun].aci_local_id << APIC_ICR_ID_BIT_OFFSET; 2070 apicadr[APIC_INT_CMD1] = vector; 2071 2072 intr_restore(flag); 2073 } 2074 2075 2076 /*ARGSUSED*/ 2077 static void 2078 apic_set_idlecpu(processorid_t cpun) 2079 { 2080 } 2081 2082 /*ARGSUSED*/ 2083 static void 2084 apic_unset_idlecpu(processorid_t cpun) 2085 { 2086 } 2087 2088 2089 static void 2090 apic_ret() 2091 { 2092 } 2093 2094 static int 2095 get_apic_cmd1() 2096 { 2097 return (apicadr[APIC_INT_CMD1]); 2098 } 2099 2100 static int 2101 get_apic_pri() 2102 { 2103 #if defined(__amd64) 2104 return ((int)getcr8()); 2105 #else 2106 return (apicadr[APIC_TASK_REG]); 2107 #endif 2108 } 2109 2110 /* 2111 * If apic_coarse_time == 1, then apic_gettime() is used instead of 2112 * apic_gethrtime(). This is used for performance instead of accuracy. 2113 */ 2114 2115 static hrtime_t 2116 apic_gettime() 2117 { 2118 int old_hrtime_stamp; 2119 hrtime_t temp; 2120 2121 /* 2122 * In one-shot mode, we do not keep time, so if anyone 2123 * calls psm_gettime() directly, we vector over to 2124 * gethrtime(). 2125 * one-shot mode MUST NOT be enabled if this psm is the source of 2126 * hrtime. 2127 */ 2128 2129 if (apic_oneshot) 2130 return (gethrtime()); 2131 2132 2133 gettime_again: 2134 while ((old_hrtime_stamp = apic_hrtime_stamp) & 1) 2135 apic_ret(); 2136 2137 temp = apic_nsec_since_boot; 2138 2139 if (apic_hrtime_stamp != old_hrtime_stamp) { /* got an interrupt */ 2140 goto gettime_again; 2141 } 2142 return (temp); 2143 } 2144 2145 /* 2146 * Here we return the number of nanoseconds since booting. Note every 2147 * clock interrupt increments apic_nsec_since_boot by the appropriate 2148 * amount. 2149 */ 2150 static hrtime_t 2151 apic_gethrtime() 2152 { 2153 int curr_timeval, countval, elapsed_ticks, oflags; 2154 int old_hrtime_stamp, status; 2155 hrtime_t temp; 2156 uchar_t cpun; 2157 2158 2159 /* 2160 * In one-shot mode, we do not keep time, so if anyone 2161 * calls psm_gethrtime() directly, we vector over to 2162 * gethrtime(). 2163 * one-shot mode MUST NOT be enabled if this psm is the source of 2164 * hrtime. 2165 */ 2166 2167 if (apic_oneshot) 2168 return (gethrtime()); 2169 2170 oflags = intr_clear(); /* prevent migration */ 2171 2172 cpun = (uchar_t)((uint_t)apicadr[APIC_LID_REG] >> APIC_ID_BIT_OFFSET); 2173 2174 lock_set(&apic_gethrtime_lock); 2175 2176 gethrtime_again: 2177 while ((old_hrtime_stamp = apic_hrtime_stamp) & 1) 2178 apic_ret(); 2179 2180 /* 2181 * Check to see which CPU we are on. Note the time is kept on 2182 * the local APIC of CPU 0. If on CPU 0, simply read the current 2183 * counter. If on another CPU, issue a remote read command to CPU 0. 2184 */ 2185 if (cpun == apic_cpus[0].aci_local_id) { 2186 countval = apicadr[APIC_CURR_COUNT]; 2187 } else { 2188 while (get_apic_cmd1() & AV_PENDING) 2189 apic_ret(); 2190 2191 apicadr[APIC_INT_CMD2] = 2192 apic_cpus[0].aci_local_id << APIC_ICR_ID_BIT_OFFSET; 2193 apicadr[APIC_INT_CMD1] = APIC_CURR_ADD|AV_REMOTE; 2194 2195 while ((status = get_apic_cmd1()) & AV_READ_PENDING) 2196 apic_ret(); 2197 2198 if (status & AV_REMOTE_STATUS) /* 1 = valid */ 2199 countval = apicadr[APIC_REMOTE_READ]; 2200 else { /* 0 = invalid */ 2201 apic_remote_hrterr++; 2202 /* 2203 * return last hrtime right now, will need more 2204 * testing if change to retry 2205 */ 2206 temp = apic_last_hrtime; 2207 2208 lock_clear(&apic_gethrtime_lock); 2209 2210 intr_restore(oflags); 2211 2212 return (temp); 2213 } 2214 } 2215 if (countval > last_count_read) 2216 countval = 0; 2217 else 2218 last_count_read = countval; 2219 2220 elapsed_ticks = apic_hertz_count - countval; 2221 2222 curr_timeval = elapsed_ticks * apic_nsec_per_tick; 2223 temp = apic_nsec_since_boot + curr_timeval; 2224 2225 if (apic_hrtime_stamp != old_hrtime_stamp) { /* got an interrupt */ 2226 /* we might have clobbered last_count_read. Restore it */ 2227 last_count_read = apic_hertz_count; 2228 goto gethrtime_again; 2229 } 2230 2231 if (temp < apic_last_hrtime) { 2232 /* return last hrtime if error occurs */ 2233 apic_hrtime_error++; 2234 temp = apic_last_hrtime; 2235 } 2236 else 2237 apic_last_hrtime = temp; 2238 2239 lock_clear(&apic_gethrtime_lock); 2240 intr_restore(oflags); 2241 2242 return (temp); 2243 } 2244 2245 /* apic NMI handler */ 2246 /*ARGSUSED*/ 2247 static void 2248 apic_nmi_intr(caddr_t arg) 2249 { 2250 if (apic_shutdown_processors) { 2251 apic_disable_local_apic(); 2252 return; 2253 } 2254 2255 if (lock_try(&apic_nmi_lock)) { 2256 if (apic_kmdb_on_nmi) { 2257 if (psm_debugger() == 0) { 2258 cmn_err(CE_PANIC, 2259 "NMI detected, kmdb is not available."); 2260 } else { 2261 debug_enter("\nNMI detected, entering kmdb.\n"); 2262 } 2263 } else { 2264 if (apic_panic_on_nmi) { 2265 /* Keep panic from entering kmdb. */ 2266 nopanicdebug = 1; 2267 cmn_err(CE_PANIC, "pcplusmp: NMI received"); 2268 } else { 2269 /* 2270 * prom_printf is the best shot we have 2271 * of something which is problem free from 2272 * high level/NMI type of interrupts 2273 */ 2274 prom_printf("pcplusmp: NMI received\n"); 2275 apic_error |= APIC_ERR_NMI; 2276 apic_num_nmis++; 2277 } 2278 } 2279 lock_clear(&apic_nmi_lock); 2280 } 2281 } 2282 2283 /* 2284 * Add mask bits to disable interrupt vector from happening 2285 * at or above IPL. In addition, it should remove mask bits 2286 * to enable interrupt vectors below the given IPL. 2287 * 2288 * Both add and delspl are complicated by the fact that different interrupts 2289 * may share IRQs. This can happen in two ways. 2290 * 1. The same H/W line is shared by more than 1 device 2291 * 1a. with interrupts at different IPLs 2292 * 1b. with interrupts at same IPL 2293 * 2. We ran out of vectors at a given IPL and started sharing vectors. 2294 * 1b and 2 should be handled gracefully, except for the fact some ISRs 2295 * will get called often when no interrupt is pending for the device. 2296 * For 1a, we just hope that the machine blows up with the person who 2297 * set it up that way!. In the meantime, we handle it at the higher IPL. 2298 */ 2299 /*ARGSUSED*/ 2300 static int 2301 apic_addspl(int irqno, int ipl, int min_ipl, int max_ipl) 2302 { 2303 uchar_t vector; 2304 int iflag; 2305 apic_irq_t *irqptr, *irqheadptr; 2306 int irqindex; 2307 2308 ASSERT(max_ipl <= UCHAR_MAX); 2309 irqindex = IRQINDEX(irqno); 2310 2311 if ((irqindex == -1) || (!apic_irq_table[irqindex])) 2312 return (PSM_FAILURE); 2313 2314 irqptr = irqheadptr = apic_irq_table[irqindex]; 2315 2316 DDI_INTR_IMPLDBG((CE_CONT, "apic_addspl: dip=0x%p type=%d irqno=0x%x " 2317 "vector=0x%x\n", (void *)irqptr->airq_dip, 2318 irqptr->airq_mps_intr_index, irqno, irqptr->airq_vector)); 2319 2320 while (irqptr) { 2321 if (VIRTIRQ(irqindex, irqptr->airq_share_id) == irqno) 2322 break; 2323 irqptr = irqptr->airq_next; 2324 } 2325 irqptr->airq_share++; 2326 2327 /* return if it is not hardware interrupt */ 2328 if (irqptr->airq_mps_intr_index == RESERVE_INDEX) 2329 return (PSM_SUCCESS); 2330 2331 /* Or if there are more interupts at a higher IPL */ 2332 if (ipl != max_ipl) 2333 return (PSM_SUCCESS); 2334 2335 /* 2336 * if apic_picinit() has not been called yet, just return. 2337 * At the end of apic_picinit(), we will call setup_io_intr(). 2338 */ 2339 2340 if (!apic_flag) 2341 return (PSM_SUCCESS); 2342 2343 iflag = intr_clear(); 2344 2345 /* 2346 * Upgrade vector if max_ipl is not earlier ipl. If we cannot allocate, 2347 * return failure. Not very elegant, but then we hope the 2348 * machine will blow up with ... 2349 */ 2350 if (irqptr->airq_ipl != max_ipl) { 2351 vector = apic_allocate_vector(max_ipl, irqindex, 1); 2352 if (vector == 0) { 2353 intr_restore(iflag); 2354 irqptr->airq_share--; 2355 return (PSM_FAILURE); 2356 } 2357 irqptr = irqheadptr; 2358 apic_mark_vector(irqptr->airq_vector, vector); 2359 while (irqptr) { 2360 irqptr->airq_vector = vector; 2361 irqptr->airq_ipl = (uchar_t)max_ipl; 2362 /* 2363 * reprogram irq being added and every one else 2364 * who is not in the UNINIT state 2365 */ 2366 if ((VIRTIRQ(irqindex, irqptr->airq_share_id) == 2367 irqno) || (irqptr->airq_temp_cpu != IRQ_UNINIT)) { 2368 apic_record_rdt_entry(irqptr, irqindex); 2369 (void) apic_setup_io_intr(irqptr, irqindex); 2370 } 2371 irqptr = irqptr->airq_next; 2372 } 2373 intr_restore(iflag); 2374 return (PSM_SUCCESS); 2375 } 2376 2377 ASSERT(irqptr); 2378 (void) apic_setup_io_intr(irqptr, irqindex); 2379 intr_restore(iflag); 2380 return (PSM_SUCCESS); 2381 } 2382 2383 /* 2384 * Recompute mask bits for the given interrupt vector. 2385 * If there is no interrupt servicing routine for this 2386 * vector, this function should disable interrupt vector 2387 * from happening at all IPLs. If there are still 2388 * handlers using the given vector, this function should 2389 * disable the given vector from happening below the lowest 2390 * IPL of the remaining hadlers. 2391 */ 2392 /*ARGSUSED*/ 2393 static int 2394 apic_delspl(int irqno, int ipl, int min_ipl, int max_ipl) 2395 { 2396 uchar_t vector, bind_cpu; 2397 int iflag, intin, irqindex; 2398 volatile int32_t *ioapic; 2399 apic_irq_t *irqptr, *irqheadptr; 2400 2401 irqindex = IRQINDEX(irqno); 2402 irqptr = irqheadptr = apic_irq_table[irqindex]; 2403 2404 DDI_INTR_IMPLDBG((CE_CONT, "apic_delspl: dip=0x%p type=%d irqno=0x%x " 2405 "vector=0x%x\n", (void *)irqptr->airq_dip, 2406 irqptr->airq_mps_intr_index, irqno, irqptr->airq_vector)); 2407 2408 while (irqptr) { 2409 if (VIRTIRQ(irqindex, irqptr->airq_share_id) == irqno) 2410 break; 2411 irqptr = irqptr->airq_next; 2412 } 2413 ASSERT(irqptr); 2414 2415 irqptr->airq_share--; 2416 2417 if (ipl < max_ipl) 2418 return (PSM_SUCCESS); 2419 2420 /* return if it is not hardware interrupt */ 2421 if (irqptr->airq_mps_intr_index == RESERVE_INDEX) 2422 return (PSM_SUCCESS); 2423 2424 if (!apic_flag) { 2425 /* 2426 * Clear irq_struct. If two devices shared an intpt 2427 * line & 1 unloaded before picinit, we are hosed. But, then 2428 * we hope the machine will ... 2429 */ 2430 irqptr->airq_mps_intr_index = FREE_INDEX; 2431 irqptr->airq_temp_cpu = IRQ_UNINIT; 2432 apic_free_vector(irqptr->airq_vector); 2433 return (PSM_SUCCESS); 2434 } 2435 /* 2436 * Downgrade vector to new max_ipl if needed.If we cannot allocate, 2437 * use old IPL. Not very elegant, but then we hope ... 2438 */ 2439 if ((irqptr->airq_ipl != max_ipl) && (max_ipl != PSM_INVALID_IPL)) { 2440 apic_irq_t *irqp; 2441 if (vector = apic_allocate_vector(max_ipl, irqno, 1)) { 2442 apic_mark_vector(irqheadptr->airq_vector, vector); 2443 irqp = irqheadptr; 2444 while (irqp) { 2445 irqp->airq_vector = vector; 2446 irqp->airq_ipl = (uchar_t)max_ipl; 2447 if (irqp->airq_temp_cpu != IRQ_UNINIT) { 2448 apic_record_rdt_entry(irqp, irqindex); 2449 (void) apic_setup_io_intr(irqp, 2450 irqindex); 2451 } 2452 irqp = irqp->airq_next; 2453 } 2454 } 2455 } 2456 2457 if (irqptr->airq_share) 2458 return (PSM_SUCCESS); 2459 2460 ioapic = apicioadr[irqptr->airq_ioapicindex]; 2461 intin = irqptr->airq_intin_no; 2462 iflag = intr_clear(); 2463 lock_set(&apic_ioapic_lock); 2464 ioapic[APIC_IO_REG] = APIC_RDT_CMD + 2 * intin; 2465 ioapic[APIC_IO_DATA] = AV_MASK; 2466 2467 /* Disable the MSI/X vector */ 2468 if (APIC_IS_MSI_OR_MSIX_INDEX(irqptr->airq_mps_intr_index)) { 2469 int type = (irqptr->airq_mps_intr_index == MSI_INDEX) ? 2470 DDI_INTR_TYPE_MSI : DDI_INTR_TYPE_MSIX; 2471 2472 /* 2473 * Make sure we only disable on the last 2474 * of the multi-MSI support 2475 */ 2476 if (i_ddi_intr_get_current_nintrs(irqptr->airq_dip) == 1) { 2477 (void) pci_msi_unconfigure(irqptr->airq_dip, type, 2478 irqptr->airq_ioapicindex); 2479 2480 (void) pci_msi_disable_mode(irqptr->airq_dip, type, 2481 irqptr->airq_ioapicindex); 2482 } 2483 } 2484 2485 if (max_ipl == PSM_INVALID_IPL) { 2486 ASSERT(irqheadptr == irqptr); 2487 bind_cpu = irqptr->airq_temp_cpu; 2488 if (((uchar_t)bind_cpu != IRQ_UNBOUND) && 2489 ((uchar_t)bind_cpu != IRQ_UNINIT)) { 2490 ASSERT((bind_cpu & ~IRQ_USER_BOUND) < apic_nproc); 2491 if (bind_cpu & IRQ_USER_BOUND) { 2492 /* If hardbound, temp_cpu == cpu */ 2493 bind_cpu &= ~IRQ_USER_BOUND; 2494 apic_cpus[bind_cpu].aci_bound--; 2495 } else 2496 apic_cpus[bind_cpu].aci_temp_bound--; 2497 } 2498 lock_clear(&apic_ioapic_lock); 2499 intr_restore(iflag); 2500 irqptr->airq_temp_cpu = IRQ_UNINIT; 2501 irqptr->airq_mps_intr_index = FREE_INDEX; 2502 apic_free_vector(irqptr->airq_vector); 2503 return (PSM_SUCCESS); 2504 } 2505 lock_clear(&apic_ioapic_lock); 2506 intr_restore(iflag); 2507 2508 mutex_enter(&airq_mutex); 2509 if ((irqptr == apic_irq_table[irqindex])) { 2510 apic_irq_t *oldirqptr; 2511 /* Move valid irq entry to the head */ 2512 irqheadptr = oldirqptr = irqptr; 2513 irqptr = irqptr->airq_next; 2514 ASSERT(irqptr); 2515 while (irqptr) { 2516 if (irqptr->airq_mps_intr_index != FREE_INDEX) 2517 break; 2518 oldirqptr = irqptr; 2519 irqptr = irqptr->airq_next; 2520 } 2521 /* remove all invalid ones from the beginning */ 2522 apic_irq_table[irqindex] = irqptr; 2523 /* 2524 * and link them back after the head. The invalid ones 2525 * begin with irqheadptr and end at oldirqptr 2526 */ 2527 oldirqptr->airq_next = irqptr->airq_next; 2528 irqptr->airq_next = irqheadptr; 2529 } 2530 mutex_exit(&airq_mutex); 2531 2532 irqptr->airq_temp_cpu = IRQ_UNINIT; 2533 irqptr->airq_mps_intr_index = FREE_INDEX; 2534 return (PSM_SUCCESS); 2535 } 2536 2537 /* 2538 * Return HW interrupt number corresponding to the given IPL 2539 */ 2540 /*ARGSUSED*/ 2541 static int 2542 apic_softlvl_to_irq(int ipl) 2543 { 2544 /* 2545 * Do not use apic to trigger soft interrupt. 2546 * It will cause the system to hang when 2 hardware interrupts 2547 * at the same priority with the softint are already accepted 2548 * by the apic. Cause the AV_PENDING bit will not be cleared 2549 * until one of the hardware interrupt is eoi'ed. If we need 2550 * to send an ipi at this time, we will end up looping forever 2551 * to wait for the AV_PENDING bit to clear. 2552 */ 2553 return (PSM_SV_SOFTWARE); 2554 } 2555 2556 static int 2557 apic_post_cpu_start() 2558 { 2559 int i, cpun; 2560 apic_irq_t *irq_ptr; 2561 2562 apic_init_intr(); 2563 2564 /* 2565 * since some systems don't enable the internal cache on the non-boot 2566 * cpus, so we have to enable them here 2567 */ 2568 setcr0(getcr0() & ~(0x60000000)); 2569 2570 while (get_apic_cmd1() & AV_PENDING) 2571 apic_ret(); 2572 2573 cpun = psm_get_cpu_id(); 2574 apic_cpus[cpun].aci_status = APIC_CPU_ONLINE | APIC_CPU_INTR_ENABLE; 2575 2576 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) { 2577 irq_ptr = apic_irq_table[i]; 2578 if ((irq_ptr == NULL) || 2579 ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) != cpun)) 2580 continue; 2581 2582 while (irq_ptr) { 2583 if (irq_ptr->airq_temp_cpu != IRQ_UNINIT) 2584 (void) apic_rebind(irq_ptr, cpun, 1, IMMEDIATE); 2585 irq_ptr = irq_ptr->airq_next; 2586 } 2587 } 2588 2589 return (PSM_SUCCESS); 2590 } 2591 2592 processorid_t 2593 apic_get_next_processorid(processorid_t cpu_id) 2594 { 2595 2596 int i; 2597 2598 if (cpu_id == -1) 2599 return ((processorid_t)0); 2600 2601 for (i = cpu_id + 1; i < NCPU; i++) { 2602 if (apic_cpumask & (1 << i)) 2603 return (i); 2604 } 2605 2606 return ((processorid_t)-1); 2607 } 2608 2609 2610 /* 2611 * type == -1 indicates it is an internal request. Do not change 2612 * resv_vector for these requests 2613 */ 2614 static int 2615 apic_get_ipivect(int ipl, int type) 2616 { 2617 uchar_t vector; 2618 int irq; 2619 2620 if (irq = apic_allocate_irq(APIC_VECTOR(ipl))) { 2621 if (vector = apic_allocate_vector(ipl, irq, 1)) { 2622 apic_irq_table[irq]->airq_mps_intr_index = 2623 RESERVE_INDEX; 2624 apic_irq_table[irq]->airq_vector = vector; 2625 if (type != -1) { 2626 apic_resv_vector[ipl] = vector; 2627 } 2628 return (irq); 2629 } 2630 } 2631 apic_error |= APIC_ERR_GET_IPIVECT_FAIL; 2632 return (-1); /* shouldn't happen */ 2633 } 2634 2635 static int 2636 apic_getclkirq(int ipl) 2637 { 2638 int irq; 2639 2640 if ((irq = apic_get_ipivect(ipl, -1)) == -1) 2641 return (-1); 2642 /* 2643 * Note the vector in apic_clkvect for per clock handling. 2644 */ 2645 apic_clkvect = apic_irq_table[irq]->airq_vector - APIC_BASE_VECT; 2646 APIC_VERBOSE_IOAPIC((CE_NOTE, "get_clkirq: vector = %x\n", 2647 apic_clkvect)); 2648 return (irq); 2649 } 2650 2651 /* 2652 * Return the number of APIC clock ticks elapsed for 8245 to decrement 2653 * (APIC_TIME_COUNT + pit_ticks_adj) ticks. 2654 */ 2655 static uint_t 2656 apic_calibrate(volatile uint32_t *addr, uint16_t *pit_ticks_adj) 2657 { 2658 uint8_t pit_tick_lo; 2659 uint16_t pit_tick, target_pit_tick; 2660 uint32_t start_apic_tick, end_apic_tick; 2661 int iflag; 2662 2663 addr += APIC_CURR_COUNT; 2664 2665 iflag = intr_clear(); 2666 2667 do { 2668 pit_tick_lo = inb(PITCTR0_PORT); 2669 pit_tick = (inb(PITCTR0_PORT) << 8) | pit_tick_lo; 2670 } while (pit_tick < APIC_TIME_MIN || 2671 pit_tick_lo <= APIC_LB_MIN || pit_tick_lo >= APIC_LB_MAX); 2672 2673 /* 2674 * Wait for the 8254 to decrement by 5 ticks to ensure 2675 * we didn't start in the middle of a tick. 2676 * Compare with 0x10 for the wrap around case. 2677 */ 2678 target_pit_tick = pit_tick - 5; 2679 do { 2680 pit_tick_lo = inb(PITCTR0_PORT); 2681 pit_tick = (inb(PITCTR0_PORT) << 8) | pit_tick_lo; 2682 } while (pit_tick > target_pit_tick || pit_tick_lo < 0x10); 2683 2684 start_apic_tick = *addr; 2685 2686 /* 2687 * Wait for the 8254 to decrement by 2688 * (APIC_TIME_COUNT + pit_ticks_adj) ticks 2689 */ 2690 target_pit_tick = pit_tick - APIC_TIME_COUNT; 2691 do { 2692 pit_tick_lo = inb(PITCTR0_PORT); 2693 pit_tick = (inb(PITCTR0_PORT) << 8) | pit_tick_lo; 2694 } while (pit_tick > target_pit_tick || pit_tick_lo < 0x10); 2695 2696 end_apic_tick = *addr; 2697 2698 *pit_ticks_adj = target_pit_tick - pit_tick; 2699 2700 intr_restore(iflag); 2701 2702 return (start_apic_tick - end_apic_tick); 2703 } 2704 2705 /* 2706 * Initialise the APIC timer on the local APIC of CPU 0 to the desired 2707 * frequency. Note at this stage in the boot sequence, the boot processor 2708 * is the only active processor. 2709 * hertz value of 0 indicates a one-shot mode request. In this case 2710 * the function returns the resolution (in nanoseconds) for the hardware 2711 * timer interrupt. If one-shot mode capability is not available, 2712 * the return value will be 0. apic_enable_oneshot is a global switch 2713 * for disabling the functionality. 2714 * A non-zero positive value for hertz indicates a periodic mode request. 2715 * In this case the hardware will be programmed to generate clock interrupts 2716 * at hertz frequency and returns the resolution of interrupts in 2717 * nanosecond. 2718 */ 2719 2720 static int 2721 apic_clkinit(int hertz) 2722 { 2723 2724 uint_t apic_ticks = 0; 2725 uint_t pit_time; 2726 int ret; 2727 uint16_t pit_ticks_adj; 2728 static int firsttime = 1; 2729 2730 if (firsttime) { 2731 /* first time calibrate */ 2732 2733 apicadr[APIC_DIVIDE_REG] = 0x0; 2734 apicadr[APIC_INIT_COUNT] = APIC_MAXVAL; 2735 2736 /* set periodic interrupt based on CLKIN */ 2737 apicadr[APIC_LOCAL_TIMER] = 2738 (apic_clkvect + APIC_BASE_VECT) | AV_TIME; 2739 tenmicrosec(); 2740 2741 apic_ticks = apic_calibrate(apicadr, &pit_ticks_adj); 2742 2743 apicadr[APIC_LOCAL_TIMER] = 2744 (apic_clkvect + APIC_BASE_VECT) | AV_MASK; 2745 /* 2746 * pit time is the amount of real time (in nanoseconds ) it took 2747 * the 8254 to decrement (APIC_TIME_COUNT + pit_ticks_adj) ticks 2748 */ 2749 pit_time = ((longlong_t)(APIC_TIME_COUNT + 2750 pit_ticks_adj) * NANOSEC) / PIT_HZ; 2751 2752 /* 2753 * Determine the number of nanoseconds per APIC clock tick 2754 * and then determine how many APIC ticks to interrupt at the 2755 * desired frequency 2756 */ 2757 apic_nsec_per_tick = pit_time / apic_ticks; 2758 if (apic_nsec_per_tick == 0) 2759 apic_nsec_per_tick = 1; 2760 2761 /* the interval timer initial count is 32 bit max */ 2762 apic_nsec_max = (hrtime_t)apic_nsec_per_tick * APIC_MAXVAL; 2763 firsttime = 0; 2764 } 2765 2766 if (hertz != 0) { 2767 /* periodic */ 2768 apic_nsec_per_intr = NANOSEC / hertz; 2769 apic_hertz_count = (longlong_t)apic_nsec_per_intr / 2770 apic_nsec_per_tick; 2771 apic_sample_factor_redistribution = hertz + 1; 2772 } 2773 2774 apic_int_busy_mark = (apic_int_busy_mark * 2775 apic_sample_factor_redistribution) / 100; 2776 apic_int_free_mark = (apic_int_free_mark * 2777 apic_sample_factor_redistribution) / 100; 2778 apic_diff_for_redistribution = (apic_diff_for_redistribution * 2779 apic_sample_factor_redistribution) / 100; 2780 2781 if (hertz == 0) { 2782 /* requested one_shot */ 2783 if (!apic_oneshot_enable) 2784 return (0); 2785 apic_oneshot = 1; 2786 ret = (int)apic_nsec_per_tick; 2787 } else { 2788 /* program the local APIC to interrupt at the given frequency */ 2789 apicadr[APIC_INIT_COUNT] = apic_hertz_count; 2790 apicadr[APIC_LOCAL_TIMER] = 2791 (apic_clkvect + APIC_BASE_VECT) | AV_TIME; 2792 apic_oneshot = 0; 2793 ret = NANOSEC / hertz; 2794 } 2795 2796 return (ret); 2797 2798 } 2799 2800 /* 2801 * apic_preshutdown: 2802 * Called early in shutdown whilst we can still access filesystems to do 2803 * things like loading modules which will be required to complete shutdown 2804 * after filesystems are all unmounted. 2805 */ 2806 static void 2807 apic_preshutdown(int cmd, int fcn) 2808 { 2809 APIC_VERBOSE_POWEROFF(("apic_preshutdown(%d,%d); m=%d a=%d\n", 2810 cmd, fcn, apic_poweroff_method, apic_enable_acpi)); 2811 2812 if ((cmd != A_SHUTDOWN) || (fcn != AD_POWEROFF)) { 2813 return; 2814 } 2815 } 2816 2817 static void 2818 apic_shutdown(int cmd, int fcn) 2819 { 2820 int iflag, restarts, attempts; 2821 int i, j; 2822 volatile int32_t *ioapic; 2823 uchar_t byte; 2824 2825 /* Send NMI to all CPUs except self to do per processor shutdown */ 2826 iflag = intr_clear(); 2827 while (get_apic_cmd1() & AV_PENDING) 2828 apic_ret(); 2829 apic_shutdown_processors = 1; 2830 apicadr[APIC_INT_CMD1] = AV_NMI | AV_LEVEL | AV_SH_ALL_EXCSELF; 2831 2832 /* restore cmos shutdown byte before reboot */ 2833 if (apic_cmos_ssb_set) { 2834 outb(CMOS_ADDR, SSB); 2835 outb(CMOS_DATA, 0); 2836 } 2837 /* Disable the I/O APIC redirection entries */ 2838 for (j = 0; j < apic_io_max; j++) { 2839 int intin_max; 2840 ioapic = apicioadr[j]; 2841 ioapic[APIC_IO_REG] = APIC_VERS_CMD; 2842 /* Bits 23-16 define the maximum redirection entries */ 2843 intin_max = (ioapic[APIC_IO_DATA] >> 16) & 0xff; 2844 for (i = 0; i < intin_max; i++) { 2845 ioapic[APIC_IO_REG] = APIC_RDT_CMD + 2 * i; 2846 ioapic[APIC_IO_DATA] = AV_MASK; 2847 } 2848 } 2849 2850 /* disable apic mode if imcr present */ 2851 if (apic_imcrp) { 2852 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT); 2853 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_PIC); 2854 } 2855 2856 apic_disable_local_apic(); 2857 2858 intr_restore(iflag); 2859 2860 if ((cmd != A_SHUTDOWN) || (fcn != AD_POWEROFF)) { 2861 return; 2862 } 2863 2864 switch (apic_poweroff_method) { 2865 case APIC_POWEROFF_VIA_RTC: 2866 2867 /* select the extended NVRAM bank in the RTC */ 2868 outb(CMOS_ADDR, RTC_REGA); 2869 byte = inb(CMOS_DATA); 2870 outb(CMOS_DATA, (byte | EXT_BANK)); 2871 2872 outb(CMOS_ADDR, PFR_REG); 2873 2874 /* for Predator must toggle the PAB bit */ 2875 byte = inb(CMOS_DATA); 2876 2877 /* 2878 * clear power active bar, wakeup alarm and 2879 * kickstart 2880 */ 2881 byte &= ~(PAB_CBIT | WF_FLAG | KS_FLAG); 2882 outb(CMOS_DATA, byte); 2883 2884 /* delay before next write */ 2885 drv_usecwait(1000); 2886 2887 /* for S40 the following would suffice */ 2888 byte = inb(CMOS_DATA); 2889 2890 /* power active bar control bit */ 2891 byte |= PAB_CBIT; 2892 outb(CMOS_DATA, byte); 2893 2894 break; 2895 2896 case APIC_POWEROFF_VIA_ASPEN_BMC: 2897 restarts = 0; 2898 restart_aspen_bmc: 2899 if (++restarts == 3) 2900 break; 2901 attempts = 0; 2902 do { 2903 byte = inb(MISMIC_FLAG_REGISTER); 2904 byte &= MISMIC_BUSY_MASK; 2905 if (byte != 0) { 2906 drv_usecwait(1000); 2907 if (attempts >= 3) 2908 goto restart_aspen_bmc; 2909 ++attempts; 2910 } 2911 } while (byte != 0); 2912 outb(MISMIC_CNTL_REGISTER, CC_SMS_GET_STATUS); 2913 byte = inb(MISMIC_FLAG_REGISTER); 2914 byte |= 0x1; 2915 outb(MISMIC_FLAG_REGISTER, byte); 2916 i = 0; 2917 for (; i < (sizeof (aspen_bmc)/sizeof (aspen_bmc[0])); 2918 i++) { 2919 attempts = 0; 2920 do { 2921 byte = inb(MISMIC_FLAG_REGISTER); 2922 byte &= MISMIC_BUSY_MASK; 2923 if (byte != 0) { 2924 drv_usecwait(1000); 2925 if (attempts >= 3) 2926 goto restart_aspen_bmc; 2927 ++attempts; 2928 } 2929 } while (byte != 0); 2930 outb(MISMIC_CNTL_REGISTER, aspen_bmc[i].cntl); 2931 outb(MISMIC_DATA_REGISTER, aspen_bmc[i].data); 2932 byte = inb(MISMIC_FLAG_REGISTER); 2933 byte |= 0x1; 2934 outb(MISMIC_FLAG_REGISTER, byte); 2935 } 2936 break; 2937 2938 case APIC_POWEROFF_VIA_SITKA_BMC: 2939 restarts = 0; 2940 restart_sitka_bmc: 2941 if (++restarts == 3) 2942 break; 2943 attempts = 0; 2944 do { 2945 byte = inb(SMS_STATUS_REGISTER); 2946 byte &= SMS_STATE_MASK; 2947 if ((byte == SMS_READ_STATE) || 2948 (byte == SMS_WRITE_STATE)) { 2949 drv_usecwait(1000); 2950 if (attempts >= 3) 2951 goto restart_sitka_bmc; 2952 ++attempts; 2953 } 2954 } while ((byte == SMS_READ_STATE) || 2955 (byte == SMS_WRITE_STATE)); 2956 outb(SMS_COMMAND_REGISTER, SMS_GET_STATUS); 2957 i = 0; 2958 for (; i < (sizeof (sitka_bmc)/sizeof (sitka_bmc[0])); 2959 i++) { 2960 attempts = 0; 2961 do { 2962 byte = inb(SMS_STATUS_REGISTER); 2963 byte &= SMS_IBF_MASK; 2964 if (byte != 0) { 2965 drv_usecwait(1000); 2966 if (attempts >= 3) 2967 goto restart_sitka_bmc; 2968 ++attempts; 2969 } 2970 } while (byte != 0); 2971 outb(sitka_bmc[i].port, sitka_bmc[i].data); 2972 } 2973 break; 2974 2975 case APIC_POWEROFF_NONE: 2976 2977 /* If no APIC direct method, we will try using ACPI */ 2978 if (apic_enable_acpi) { 2979 if (acpi_poweroff() == 1) 2980 return; 2981 } else 2982 return; 2983 2984 break; 2985 } 2986 /* 2987 * Wait a limited time here for power to go off. 2988 * If the power does not go off, then there was a 2989 * problem and we should continue to the halt which 2990 * prints a message for the user to press a key to 2991 * reboot. 2992 */ 2993 drv_usecwait(7000000); /* wait seven seconds */ 2994 2995 } 2996 2997 /* 2998 * Try and disable all interrupts. We just assign interrupts to other 2999 * processors based on policy. If any were bound by user request, we 3000 * let them continue and return failure. We do not bother to check 3001 * for cache affinity while rebinding. 3002 */ 3003 3004 static int 3005 apic_disable_intr(processorid_t cpun) 3006 { 3007 int bind_cpu = 0, i, hardbound = 0, iflag; 3008 apic_irq_t *irq_ptr; 3009 3010 if (cpun == 0) 3011 return (PSM_FAILURE); 3012 3013 iflag = intr_clear(); 3014 lock_set(&apic_ioapic_lock); 3015 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE; 3016 lock_clear(&apic_ioapic_lock); 3017 intr_restore(iflag); 3018 apic_cpus[cpun].aci_curipl = 0; 3019 i = apic_min_device_irq; 3020 for (; i <= apic_max_device_irq; i++) { 3021 /* 3022 * If there are bound interrupts on this cpu, then 3023 * rebind them to other processors. 3024 */ 3025 if ((irq_ptr = apic_irq_table[i]) != NULL) { 3026 ASSERT((irq_ptr->airq_temp_cpu == IRQ_UNBOUND) || 3027 (irq_ptr->airq_temp_cpu == IRQ_UNINIT) || 3028 ((irq_ptr->airq_temp_cpu & ~IRQ_USER_BOUND) < 3029 apic_nproc)); 3030 3031 if (irq_ptr->airq_temp_cpu == (cpun | IRQ_USER_BOUND)) { 3032 hardbound = 1; 3033 continue; 3034 } 3035 3036 if (irq_ptr->airq_temp_cpu == cpun) { 3037 do { 3038 apic_next_bind_cpu += 2; 3039 bind_cpu = apic_next_bind_cpu / 2; 3040 if (bind_cpu >= apic_nproc) { 3041 apic_next_bind_cpu = 1; 3042 bind_cpu = 0; 3043 3044 } 3045 } while (apic_rebind_all(irq_ptr, bind_cpu, 1)); 3046 } 3047 } 3048 } 3049 if (hardbound) { 3050 cmn_err(CE_WARN, "Could not disable interrupts on %d" 3051 "due to user bound interrupts", cpun); 3052 return (PSM_FAILURE); 3053 } 3054 else 3055 return (PSM_SUCCESS); 3056 } 3057 3058 static void 3059 apic_enable_intr(processorid_t cpun) 3060 { 3061 int i, iflag; 3062 apic_irq_t *irq_ptr; 3063 3064 iflag = intr_clear(); 3065 lock_set(&apic_ioapic_lock); 3066 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE; 3067 lock_clear(&apic_ioapic_lock); 3068 intr_restore(iflag); 3069 3070 i = apic_min_device_irq; 3071 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) { 3072 if ((irq_ptr = apic_irq_table[i]) != NULL) { 3073 if ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) == cpun) { 3074 (void) apic_rebind_all(irq_ptr, 3075 irq_ptr->airq_cpu, 1); 3076 } 3077 } 3078 } 3079 } 3080 3081 /* 3082 * apic_introp_xlate() replaces apic_translate_irq() and is 3083 * called only from apic_intr_ops(). With the new ADII framework, 3084 * the priority can no longer be retrived through i_ddi_get_intrspec(). 3085 * It has to be passed in from the caller. 3086 */ 3087 int 3088 apic_introp_xlate(dev_info_t *dip, struct intrspec *ispec, int type) 3089 { 3090 char dev_type[16]; 3091 int dev_len, pci_irq, newirq, bustype, devid, busid, i; 3092 int irqno = ispec->intrspec_vec; 3093 ddi_acc_handle_t cfg_handle; 3094 uchar_t ipin; 3095 struct apic_io_intr *intrp; 3096 iflag_t intr_flag; 3097 APIC_HEADER *hp; 3098 MADT_INTERRUPT_OVERRIDE *isop; 3099 apic_irq_t *airqp; 3100 3101 DDI_INTR_IMPLDBG((CE_CONT, "apic_introp_xlate: dip=0x%p name=%s " 3102 "type=%d irqno=0x%x\n", (void *)dip, ddi_get_name(dip), type, 3103 irqno)); 3104 3105 if (DDI_INTR_IS_MSI_OR_MSIX(type)) { 3106 if ((airqp = apic_find_irq(dip, ispec, type)) != NULL) 3107 return (apic_vector_to_irq[airqp->airq_vector]); 3108 return (apic_setup_irq_table(dip, irqno, NULL, ispec, 3109 NULL, type)); 3110 } 3111 3112 bustype = 0; 3113 3114 /* check if we have already translated this irq */ 3115 mutex_enter(&airq_mutex); 3116 newirq = apic_min_device_irq; 3117 for (; newirq <= apic_max_device_irq; newirq++) { 3118 airqp = apic_irq_table[newirq]; 3119 while (airqp) { 3120 if ((airqp->airq_dip == dip) && 3121 (airqp->airq_origirq == irqno) && 3122 (airqp->airq_mps_intr_index != FREE_INDEX)) { 3123 3124 mutex_exit(&airq_mutex); 3125 return (VIRTIRQ(newirq, airqp->airq_share_id)); 3126 } 3127 airqp = airqp->airq_next; 3128 } 3129 } 3130 mutex_exit(&airq_mutex); 3131 3132 if (apic_defconf) 3133 goto defconf; 3134 3135 if ((dip == NULL) || (!apic_irq_translate && !apic_enable_acpi)) 3136 goto nonpci; 3137 3138 dev_len = sizeof (dev_type); 3139 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, ddi_get_parent(dip), 3140 DDI_PROP_DONTPASS, "device_type", (caddr_t)dev_type, 3141 &dev_len) != DDI_PROP_SUCCESS) { 3142 goto nonpci; 3143 } 3144 3145 if ((strcmp(dev_type, "pci") == 0) || 3146 (strcmp(dev_type, "pciex") == 0)) { 3147 /* pci device */ 3148 if (acpica_get_bdf(dip, &busid, &devid, NULL) != 0) 3149 goto nonpci; 3150 if (busid == 0 && apic_pci_bus_total == 1) 3151 busid = (int)apic_single_pci_busid; 3152 3153 if (pci_config_setup(dip, &cfg_handle) != DDI_SUCCESS) 3154 goto nonpci; 3155 ipin = pci_config_get8(cfg_handle, PCI_CONF_IPIN) - PCI_INTA; 3156 pci_config_teardown(&cfg_handle); 3157 if (apic_enable_acpi && !apic_use_acpi_madt_only) { 3158 if (apic_acpi_translate_pci_irq(dip, busid, devid, 3159 ipin, &pci_irq, &intr_flag) != ACPI_PSM_SUCCESS) 3160 goto nonpci; 3161 3162 intr_flag.bustype = BUS_PCI; 3163 if ((newirq = apic_setup_irq_table(dip, pci_irq, NULL, 3164 ispec, &intr_flag, type)) == -1) 3165 goto nonpci; 3166 return (newirq); 3167 } else { 3168 pci_irq = ((devid & 0x1f) << 2) | (ipin & 0x3); 3169 if ((intrp = apic_find_io_intr_w_busid(pci_irq, busid)) 3170 == NULL) { 3171 if ((pci_irq = apic_handle_pci_pci_bridge(dip, 3172 devid, ipin, &intrp)) == -1) 3173 goto nonpci; 3174 } 3175 if ((newirq = apic_setup_irq_table(dip, pci_irq, intrp, 3176 ispec, NULL, type)) == -1) 3177 goto nonpci; 3178 return (newirq); 3179 } 3180 } else if (strcmp(dev_type, "isa") == 0) 3181 bustype = BUS_ISA; 3182 else if (strcmp(dev_type, "eisa") == 0) 3183 bustype = BUS_EISA; 3184 3185 nonpci: 3186 if (apic_enable_acpi && !apic_use_acpi_madt_only) { 3187 /* search iso entries first */ 3188 if (acpi_iso_cnt != 0) { 3189 hp = (APIC_HEADER *)acpi_isop; 3190 i = 0; 3191 while (i < acpi_iso_cnt) { 3192 if (hp->Type == APIC_XRUPT_OVERRIDE) { 3193 isop = (MADT_INTERRUPT_OVERRIDE *)hp; 3194 if (isop->Bus == 0 && 3195 isop->Source == irqno) { 3196 newirq = isop->Interrupt; 3197 intr_flag.intr_po = 3198 isop->Polarity; 3199 intr_flag.intr_el = 3200 isop->TriggerMode; 3201 intr_flag.bustype = BUS_ISA; 3202 3203 return (apic_setup_irq_table( 3204 dip, newirq, NULL, ispec, 3205 &intr_flag, type)); 3206 3207 } 3208 i++; 3209 } 3210 hp = (APIC_HEADER *)(((char *)hp) + 3211 hp->Length); 3212 } 3213 } 3214 intr_flag.intr_po = INTR_PO_ACTIVE_HIGH; 3215 intr_flag.intr_el = INTR_EL_EDGE; 3216 intr_flag.bustype = BUS_ISA; 3217 return (apic_setup_irq_table(dip, irqno, NULL, ispec, 3218 &intr_flag, type)); 3219 } else { 3220 if (bustype == 0) 3221 bustype = eisa_level_intr_mask ? BUS_EISA : BUS_ISA; 3222 for (i = 0; i < 2; i++) { 3223 if (((busid = apic_find_bus_id(bustype)) != -1) && 3224 ((intrp = apic_find_io_intr_w_busid(irqno, busid)) 3225 != NULL)) { 3226 if ((newirq = apic_setup_irq_table(dip, irqno, 3227 intrp, ispec, NULL, type)) != -1) { 3228 return (newirq); 3229 } 3230 goto defconf; 3231 } 3232 bustype = (bustype == BUS_EISA) ? BUS_ISA : BUS_EISA; 3233 } 3234 } 3235 3236 /* MPS default configuration */ 3237 defconf: 3238 newirq = apic_setup_irq_table(dip, irqno, NULL, ispec, NULL, type); 3239 if (newirq == -1) 3240 return (newirq); 3241 ASSERT(IRQINDEX(newirq) == irqno); 3242 ASSERT(apic_irq_table[irqno]); 3243 return (newirq); 3244 } 3245 3246 3247 3248 3249 3250 3251 /* 3252 * On machines with PCI-PCI bridges, a device behind a PCI-PCI bridge 3253 * needs special handling. We may need to chase up the device tree, 3254 * using the PCI-PCI Bridge specification's "rotating IPIN assumptions", 3255 * to find the IPIN at the root bus that relates to the IPIN on the 3256 * subsidiary bus (for ACPI or MP). We may, however, have an entry 3257 * in the MP table or the ACPI namespace for this device itself. 3258 * We handle both cases in the search below. 3259 */ 3260 /* this is the non-acpi version */ 3261 static int 3262 apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, int child_ipin, 3263 struct apic_io_intr **intrp) 3264 { 3265 dev_info_t *dipp, *dip; 3266 int pci_irq; 3267 ddi_acc_handle_t cfg_handle; 3268 int bridge_devno, bridge_bus; 3269 int ipin; 3270 3271 dip = idip; 3272 3273 /*CONSTCOND*/ 3274 while (1) { 3275 if ((dipp = ddi_get_parent(dip)) == (dev_info_t *)NULL) 3276 return (-1); 3277 if ((pci_config_setup(dipp, &cfg_handle) == DDI_SUCCESS) && 3278 (pci_config_get8(cfg_handle, PCI_CONF_BASCLASS) == 3279 PCI_CLASS_BRIDGE) && (pci_config_get8(cfg_handle, 3280 PCI_CONF_SUBCLASS) == PCI_BRIDGE_PCI)) { 3281 pci_config_teardown(&cfg_handle); 3282 if (acpica_get_bdf(dipp, &bridge_bus, &bridge_devno, 3283 NULL) != 0) 3284 return (-1); 3285 /* 3286 * This is the rotating scheme that Compaq is using 3287 * and documented in the pci to pci spec. Also, if 3288 * the pci to pci bridge is behind another pci to 3289 * pci bridge, then it need to keep transversing 3290 * up until an interrupt entry is found or reach 3291 * the top of the tree 3292 */ 3293 ipin = (child_devno + child_ipin) % PCI_INTD; 3294 if (bridge_bus == 0 && apic_pci_bus_total == 1) 3295 bridge_bus = (int)apic_single_pci_busid; 3296 pci_irq = ((bridge_devno & 0x1f) << 2) | 3297 (ipin & 0x3); 3298 if ((*intrp = apic_find_io_intr_w_busid(pci_irq, 3299 bridge_bus)) != NULL) { 3300 return (pci_irq); 3301 } 3302 dip = dipp; 3303 child_devno = bridge_devno; 3304 child_ipin = ipin; 3305 } else 3306 return (-1); 3307 } 3308 /*LINTED: function will not fall off the bottom */ 3309 } 3310 3311 3312 3313 3314 static uchar_t 3315 acpi_find_ioapic(int irq) 3316 { 3317 int i; 3318 3319 for (i = 0; i < apic_io_max; i++) { 3320 if (irq >= apic_io_vectbase[i] && irq <= apic_io_vectend[i]) 3321 return (i); 3322 } 3323 return (0xFF); /* shouldn't happen */ 3324 } 3325 3326 /* 3327 * See if two irqs are compatible for sharing a vector. 3328 * Currently we only support sharing of PCI devices. 3329 */ 3330 static int 3331 acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2) 3332 { 3333 uint_t level1, po1; 3334 uint_t level2, po2; 3335 3336 /* Assume active high by default */ 3337 po1 = 0; 3338 po2 = 0; 3339 3340 if (iflag1.bustype != iflag2.bustype || iflag1.bustype != BUS_PCI) 3341 return (0); 3342 3343 if (iflag1.intr_el == INTR_EL_CONFORM) 3344 level1 = AV_LEVEL; 3345 else 3346 level1 = (iflag1.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0; 3347 3348 if (level1 && ((iflag1.intr_po == INTR_PO_ACTIVE_LOW) || 3349 (iflag1.intr_po == INTR_PO_CONFORM))) 3350 po1 = AV_ACTIVE_LOW; 3351 3352 if (iflag2.intr_el == INTR_EL_CONFORM) 3353 level2 = AV_LEVEL; 3354 else 3355 level2 = (iflag2.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0; 3356 3357 if (level2 && ((iflag2.intr_po == INTR_PO_ACTIVE_LOW) || 3358 (iflag2.intr_po == INTR_PO_CONFORM))) 3359 po2 = AV_ACTIVE_LOW; 3360 3361 if ((level1 == level2) && (po1 == po2)) 3362 return (1); 3363 3364 return (0); 3365 } 3366 3367 /* 3368 * Attempt to share vector with someone else 3369 */ 3370 static int 3371 apic_share_vector(int irqno, iflag_t *intr_flagp, short intr_index, int ipl, 3372 uchar_t ioapicindex, uchar_t ipin, apic_irq_t **irqptrp) 3373 { 3374 #ifdef DEBUG 3375 apic_irq_t *tmpirqp = NULL; 3376 #endif /* DEBUG */ 3377 apic_irq_t *irqptr, dummyirq; 3378 int newirq, chosen_irq = -1, share = 127; 3379 int lowest, highest, i; 3380 uchar_t share_id; 3381 3382 DDI_INTR_IMPLDBG((CE_CONT, "apic_share_vector: irqno=0x%x " 3383 "intr_index=0x%x ipl=0x%x\n", irqno, intr_index, ipl)); 3384 3385 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK; 3386 lowest = apic_ipltopri[ipl-1] + APIC_VECTOR_PER_IPL; 3387 3388 if (highest < lowest) /* Both ipl and ipl-1 map to same pri */ 3389 lowest -= APIC_VECTOR_PER_IPL; 3390 dummyirq.airq_mps_intr_index = intr_index; 3391 dummyirq.airq_ioapicindex = ioapicindex; 3392 dummyirq.airq_intin_no = ipin; 3393 if (intr_flagp) 3394 dummyirq.airq_iflag = *intr_flagp; 3395 apic_record_rdt_entry(&dummyirq, irqno); 3396 for (i = lowest; i <= highest; i++) { 3397 newirq = apic_vector_to_irq[i]; 3398 if (newirq == APIC_RESV_IRQ) 3399 continue; 3400 irqptr = apic_irq_table[newirq]; 3401 3402 if ((dummyirq.airq_rdt_entry & 0xFF00) != 3403 (irqptr->airq_rdt_entry & 0xFF00)) 3404 /* not compatible */ 3405 continue; 3406 3407 if (irqptr->airq_share < share) { 3408 share = irqptr->airq_share; 3409 chosen_irq = newirq; 3410 } 3411 } 3412 if (chosen_irq != -1) { 3413 /* 3414 * Assign a share id which is free or which is larger 3415 * than the largest one. 3416 */ 3417 share_id = 1; 3418 mutex_enter(&airq_mutex); 3419 irqptr = apic_irq_table[chosen_irq]; 3420 while (irqptr) { 3421 if (irqptr->airq_mps_intr_index == FREE_INDEX) { 3422 share_id = irqptr->airq_share_id; 3423 break; 3424 } 3425 if (share_id <= irqptr->airq_share_id) 3426 share_id = irqptr->airq_share_id + 1; 3427 #ifdef DEBUG 3428 tmpirqp = irqptr; 3429 #endif /* DEBUG */ 3430 irqptr = irqptr->airq_next; 3431 } 3432 if (!irqptr) { 3433 irqptr = kmem_zalloc(sizeof (apic_irq_t), KM_SLEEP); 3434 irqptr->airq_temp_cpu = IRQ_UNINIT; 3435 irqptr->airq_next = 3436 apic_irq_table[chosen_irq]->airq_next; 3437 apic_irq_table[chosen_irq]->airq_next = irqptr; 3438 #ifdef DEBUG 3439 tmpirqp = apic_irq_table[chosen_irq]; 3440 #endif /* DEBUG */ 3441 } 3442 irqptr->airq_mps_intr_index = intr_index; 3443 irqptr->airq_ioapicindex = ioapicindex; 3444 irqptr->airq_intin_no = ipin; 3445 if (intr_flagp) 3446 irqptr->airq_iflag = *intr_flagp; 3447 irqptr->airq_vector = apic_irq_table[chosen_irq]->airq_vector; 3448 irqptr->airq_share_id = share_id; 3449 apic_record_rdt_entry(irqptr, irqno); 3450 *irqptrp = irqptr; 3451 #ifdef DEBUG 3452 /* shuffle the pointers to test apic_delspl path */ 3453 if (tmpirqp) { 3454 tmpirqp->airq_next = irqptr->airq_next; 3455 irqptr->airq_next = apic_irq_table[chosen_irq]; 3456 apic_irq_table[chosen_irq] = irqptr; 3457 } 3458 #endif /* DEBUG */ 3459 mutex_exit(&airq_mutex); 3460 return (VIRTIRQ(chosen_irq, share_id)); 3461 } 3462 return (-1); 3463 } 3464 3465 /* 3466 * 3467 */ 3468 static int 3469 apic_setup_irq_table(dev_info_t *dip, int irqno, struct apic_io_intr *intrp, 3470 struct intrspec *ispec, iflag_t *intr_flagp, int type) 3471 { 3472 int origirq = ispec->intrspec_vec; 3473 uchar_t ipl = ispec->intrspec_pri; 3474 int newirq, intr_index; 3475 uchar_t ipin, ioapic, ioapicindex, vector; 3476 apic_irq_t *irqptr; 3477 major_t major; 3478 dev_info_t *sdip; 3479 3480 DDI_INTR_IMPLDBG((CE_CONT, "apic_setup_irq_table: dip=0x%p type=%d " 3481 "irqno=0x%x origirq=0x%x\n", (void *)dip, type, irqno, origirq)); 3482 3483 ASSERT(ispec != NULL); 3484 3485 major = (dip != NULL) ? ddi_name_to_major(ddi_get_name(dip)) : 0; 3486 3487 if (DDI_INTR_IS_MSI_OR_MSIX(type)) { 3488 /* MSI/X doesn't need to setup ioapic stuffs */ 3489 ioapicindex = 0xff; 3490 ioapic = 0xff; 3491 ipin = (uchar_t)0xff; 3492 intr_index = (type == DDI_INTR_TYPE_MSI) ? MSI_INDEX : 3493 MSIX_INDEX; 3494 mutex_enter(&airq_mutex); 3495 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) == -1) { 3496 mutex_exit(&airq_mutex); 3497 /* need an irq for MSI/X to index into autovect[] */ 3498 cmn_err(CE_WARN, "No interrupt irq: %s instance %d", 3499 ddi_get_name(dip), ddi_get_instance(dip)); 3500 return (-1); 3501 } 3502 mutex_exit(&airq_mutex); 3503 3504 } else if (intrp != NULL) { 3505 intr_index = (int)(intrp - apic_io_intrp); 3506 ioapic = intrp->intr_destid; 3507 ipin = intrp->intr_destintin; 3508 /* Find ioapicindex. If destid was ALL, we will exit with 0. */ 3509 for (ioapicindex = apic_io_max - 1; ioapicindex; ioapicindex--) 3510 if (apic_io_id[ioapicindex] == ioapic) 3511 break; 3512 ASSERT((ioapic == apic_io_id[ioapicindex]) || 3513 (ioapic == INTR_ALL_APIC)); 3514 3515 /* check whether this intin# has been used by another irqno */ 3516 if ((newirq = apic_find_intin(ioapicindex, ipin)) != -1) { 3517 return (newirq); 3518 } 3519 3520 } else if (intr_flagp != NULL) { 3521 /* ACPI case */ 3522 intr_index = ACPI_INDEX; 3523 ioapicindex = acpi_find_ioapic(irqno); 3524 ASSERT(ioapicindex != 0xFF); 3525 ioapic = apic_io_id[ioapicindex]; 3526 ipin = irqno - apic_io_vectbase[ioapicindex]; 3527 if (apic_irq_table[irqno] && 3528 apic_irq_table[irqno]->airq_mps_intr_index == ACPI_INDEX) { 3529 ASSERT(apic_irq_table[irqno]->airq_intin_no == ipin && 3530 apic_irq_table[irqno]->airq_ioapicindex == 3531 ioapicindex); 3532 return (irqno); 3533 } 3534 3535 } else { 3536 /* default configuration */ 3537 ioapicindex = 0; 3538 ioapic = apic_io_id[ioapicindex]; 3539 ipin = (uchar_t)irqno; 3540 intr_index = DEFAULT_INDEX; 3541 } 3542 3543 if (ispec == NULL) { 3544 APIC_VERBOSE_IOAPIC((CE_WARN, "No intrspec for irqno = %x\n", 3545 irqno)); 3546 } else if ((vector = apic_allocate_vector(ipl, irqno, 0)) == 0) { 3547 if ((newirq = apic_share_vector(irqno, intr_flagp, intr_index, 3548 ipl, ioapicindex, ipin, &irqptr)) != -1) { 3549 irqptr->airq_ipl = ipl; 3550 irqptr->airq_origirq = (uchar_t)origirq; 3551 irqptr->airq_dip = dip; 3552 irqptr->airq_major = major; 3553 sdip = apic_irq_table[IRQINDEX(newirq)]->airq_dip; 3554 /* This is OK to do really */ 3555 if (sdip == NULL) { 3556 cmn_err(CE_WARN, "Sharing vectors: %s" 3557 " instance %d and SCI", 3558 ddi_get_name(dip), ddi_get_instance(dip)); 3559 } else { 3560 cmn_err(CE_WARN, "Sharing vectors: %s" 3561 " instance %d and %s instance %d", 3562 ddi_get_name(sdip), ddi_get_instance(sdip), 3563 ddi_get_name(dip), ddi_get_instance(dip)); 3564 } 3565 return (newirq); 3566 } 3567 /* try high priority allocation now that share has failed */ 3568 if ((vector = apic_allocate_vector(ipl, irqno, 1)) == 0) { 3569 cmn_err(CE_WARN, "No interrupt vector: %s instance %d", 3570 ddi_get_name(dip), ddi_get_instance(dip)); 3571 return (-1); 3572 } 3573 } 3574 3575 mutex_enter(&airq_mutex); 3576 if (apic_irq_table[irqno] == NULL) { 3577 irqptr = kmem_zalloc(sizeof (apic_irq_t), KM_SLEEP); 3578 irqptr->airq_temp_cpu = IRQ_UNINIT; 3579 apic_irq_table[irqno] = irqptr; 3580 } else { 3581 irqptr = apic_irq_table[irqno]; 3582 if (irqptr->airq_mps_intr_index != FREE_INDEX) { 3583 /* 3584 * The slot is used by another irqno, so allocate 3585 * a free irqno for this interrupt 3586 */ 3587 newirq = apic_allocate_irq(apic_first_avail_irq); 3588 if (newirq == -1) { 3589 mutex_exit(&airq_mutex); 3590 return (-1); 3591 } 3592 irqno = newirq; 3593 irqptr = apic_irq_table[irqno]; 3594 if (irqptr == NULL) { 3595 irqptr = kmem_zalloc(sizeof (apic_irq_t), 3596 KM_SLEEP); 3597 irqptr->airq_temp_cpu = IRQ_UNINIT; 3598 apic_irq_table[irqno] = irqptr; 3599 } 3600 apic_modify_vector(vector, newirq); 3601 } 3602 } 3603 apic_max_device_irq = max(irqno, apic_max_device_irq); 3604 apic_min_device_irq = min(irqno, apic_min_device_irq); 3605 mutex_exit(&airq_mutex); 3606 irqptr->airq_ioapicindex = ioapicindex; 3607 irqptr->airq_intin_no = ipin; 3608 irqptr->airq_ipl = ipl; 3609 irqptr->airq_vector = vector; 3610 irqptr->airq_origirq = (uchar_t)origirq; 3611 irqptr->airq_share_id = 0; 3612 irqptr->airq_mps_intr_index = (short)intr_index; 3613 irqptr->airq_dip = dip; 3614 irqptr->airq_major = major; 3615 irqptr->airq_cpu = apic_bind_intr(dip, irqno, ioapic, ipin); 3616 if (intr_flagp) 3617 irqptr->airq_iflag = *intr_flagp; 3618 3619 if (!DDI_INTR_IS_MSI_OR_MSIX(type)) { 3620 /* setup I/O APIC entry for non-MSI/X interrupts */ 3621 apic_record_rdt_entry(irqptr, irqno); 3622 } 3623 return (irqno); 3624 } 3625 3626 /* 3627 * return the cpu to which this intr should be bound. 3628 * Check properties or any other mechanism to see if user wants it 3629 * bound to a specific CPU. If so, return the cpu id with high bit set. 3630 * If not, use the policy to choose a cpu and return the id. 3631 */ 3632 uchar_t 3633 apic_bind_intr(dev_info_t *dip, int irq, uchar_t ioapicid, uchar_t intin) 3634 { 3635 int instance, instno, prop_len, bind_cpu, count; 3636 uint_t i, rc; 3637 uchar_t cpu; 3638 major_t major; 3639 char *name, *drv_name, *prop_val, *cptr; 3640 char prop_name[32]; 3641 3642 3643 if (apic_intr_policy == INTR_LOWEST_PRIORITY) 3644 return (IRQ_UNBOUND); 3645 3646 drv_name = NULL; 3647 rc = DDI_PROP_NOT_FOUND; 3648 major = (major_t)-1; 3649 if (dip != NULL) { 3650 name = ddi_get_name(dip); 3651 major = ddi_name_to_major(name); 3652 drv_name = ddi_major_to_name(major); 3653 instance = ddi_get_instance(dip); 3654 if (apic_intr_policy == INTR_ROUND_ROBIN_WITH_AFFINITY) { 3655 i = apic_min_device_irq; 3656 for (; i <= apic_max_device_irq; i++) { 3657 3658 if ((i == irq) || (apic_irq_table[i] == NULL) || 3659 (apic_irq_table[i]->airq_mps_intr_index 3660 == FREE_INDEX)) 3661 continue; 3662 3663 if ((apic_irq_table[i]->airq_major == major) && 3664 (!(apic_irq_table[i]->airq_cpu & 3665 IRQ_USER_BOUND))) { 3666 3667 cpu = apic_irq_table[i]->airq_cpu; 3668 3669 cmn_err(CE_CONT, 3670 "!pcplusmp: %s (%s) instance #%d " 3671 "vector 0x%x ioapic 0x%x " 3672 "intin 0x%x is bound to cpu %d\n", 3673 name, drv_name, instance, irq, 3674 ioapicid, intin, cpu); 3675 return (cpu); 3676 } 3677 } 3678 } 3679 /* 3680 * search for "drvname"_intpt_bind_cpus property first, the 3681 * syntax of the property should be "a[,b,c,...]" where 3682 * instance 0 binds to cpu a, instance 1 binds to cpu b, 3683 * instance 3 binds to cpu c... 3684 * ddi_getlongprop() will search /option first, then / 3685 * if "drvname"_intpt_bind_cpus doesn't exist, then find 3686 * intpt_bind_cpus property. The syntax is the same, and 3687 * it applies to all the devices if its "drvname" specific 3688 * property doesn't exist 3689 */ 3690 (void) strcpy(prop_name, drv_name); 3691 (void) strcat(prop_name, "_intpt_bind_cpus"); 3692 rc = ddi_getlongprop(DDI_DEV_T_ANY, dip, 0, prop_name, 3693 (caddr_t)&prop_val, &prop_len); 3694 if (rc != DDI_PROP_SUCCESS) { 3695 rc = ddi_getlongprop(DDI_DEV_T_ANY, dip, 0, 3696 "intpt_bind_cpus", (caddr_t)&prop_val, &prop_len); 3697 } 3698 } 3699 if (rc == DDI_PROP_SUCCESS) { 3700 for (i = count = 0; i < (prop_len - 1); i++) 3701 if (prop_val[i] == ',') 3702 count++; 3703 if (prop_val[i-1] != ',') 3704 count++; 3705 /* 3706 * if somehow the binding instances defined in the 3707 * property are not enough for this instno., then 3708 * reuse the pattern for the next instance until 3709 * it reaches the requested instno 3710 */ 3711 instno = instance % count; 3712 i = 0; 3713 cptr = prop_val; 3714 while (i < instno) 3715 if (*cptr++ == ',') 3716 i++; 3717 bind_cpu = stoi(&cptr); 3718 kmem_free(prop_val, prop_len); 3719 /* if specific cpu is bogus, then default to cpu 0 */ 3720 if (bind_cpu >= apic_nproc) { 3721 cmn_err(CE_WARN, "pcplusmp: %s=%s: CPU %d not present", 3722 prop_name, prop_val, bind_cpu); 3723 bind_cpu = 0; 3724 } else { 3725 /* indicate that we are bound at user request */ 3726 bind_cpu |= IRQ_USER_BOUND; 3727 } 3728 /* 3729 * no need to check apic_cpus[].aci_status, if specific cpu is 3730 * not up, then post_cpu_start will handle it. 3731 */ 3732 } else { 3733 /* 3734 * We change bind_cpu only for every two calls 3735 * as most drivers still do 2 add_intrs for every 3736 * interrupt 3737 */ 3738 bind_cpu = (apic_next_bind_cpu++) / 2; 3739 if (bind_cpu >= apic_nproc) { 3740 apic_next_bind_cpu = 1; 3741 bind_cpu = 0; 3742 } 3743 } 3744 if (drv_name != NULL) 3745 cmn_err(CE_CONT, "!pcplusmp: %s (%s) instance %d " 3746 "vector 0x%x ioapic 0x%x intin 0x%x is bound to cpu %d\n", 3747 name, drv_name, instance, 3748 irq, ioapicid, intin, bind_cpu & ~IRQ_USER_BOUND); 3749 else 3750 cmn_err(CE_CONT, "!pcplusmp: " 3751 "vector 0x%x ioapic 0x%x intin 0x%x is bound to cpu %d\n", 3752 irq, ioapicid, intin, bind_cpu & ~IRQ_USER_BOUND); 3753 3754 return ((uchar_t)bind_cpu); 3755 } 3756 3757 static struct apic_io_intr * 3758 apic_find_io_intr_w_busid(int irqno, int busid) 3759 { 3760 struct apic_io_intr *intrp; 3761 3762 /* 3763 * It can have more than 1 entry with same source bus IRQ, 3764 * but unique with the source bus id 3765 */ 3766 intrp = apic_io_intrp; 3767 if (intrp != NULL) { 3768 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 3769 if (intrp->intr_irq == irqno && 3770 intrp->intr_busid == busid && 3771 intrp->intr_type == IO_INTR_INT) 3772 return (intrp); 3773 intrp++; 3774 } 3775 } 3776 APIC_VERBOSE_IOAPIC((CE_NOTE, "Did not find io intr for irqno:" 3777 "busid %x:%x\n", irqno, busid)); 3778 return ((struct apic_io_intr *)NULL); 3779 } 3780 3781 3782 struct mps_bus_info { 3783 char *bus_name; 3784 int bus_id; 3785 } bus_info_array[] = { 3786 "ISA ", BUS_ISA, 3787 "PCI ", BUS_PCI, 3788 "EISA ", BUS_EISA, 3789 "XPRESS", BUS_XPRESS, 3790 "PCMCIA", BUS_PCMCIA, 3791 "VL ", BUS_VL, 3792 "CBUS ", BUS_CBUS, 3793 "CBUSII", BUS_CBUSII, 3794 "FUTURE", BUS_FUTURE, 3795 "INTERN", BUS_INTERN, 3796 "MBI ", BUS_MBI, 3797 "MBII ", BUS_MBII, 3798 "MPI ", BUS_MPI, 3799 "MPSA ", BUS_MPSA, 3800 "NUBUS ", BUS_NUBUS, 3801 "TC ", BUS_TC, 3802 "VME ", BUS_VME 3803 }; 3804 3805 static int 3806 apic_find_bus_type(char *bus) 3807 { 3808 int i = 0; 3809 3810 for (; i < sizeof (bus_info_array)/sizeof (struct mps_bus_info); i++) 3811 if (strncmp(bus, bus_info_array[i].bus_name, 3812 strlen(bus_info_array[i].bus_name)) == 0) 3813 return (bus_info_array[i].bus_id); 3814 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus type for bus %s", bus)); 3815 return (0); 3816 } 3817 3818 static int 3819 apic_find_bus(int busid) 3820 { 3821 struct apic_bus *busp; 3822 3823 busp = apic_busp; 3824 while (busp->bus_entry == APIC_BUS_ENTRY) { 3825 if (busp->bus_id == busid) 3826 return (apic_find_bus_type((char *)&busp->bus_str1)); 3827 busp++; 3828 } 3829 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus for bus id %x", busid)); 3830 return (0); 3831 } 3832 3833 static int 3834 apic_find_bus_id(int bustype) 3835 { 3836 struct apic_bus *busp; 3837 3838 busp = apic_busp; 3839 while (busp->bus_entry == APIC_BUS_ENTRY) { 3840 if (apic_find_bus_type((char *)&busp->bus_str1) == bustype) 3841 return (busp->bus_id); 3842 busp++; 3843 } 3844 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus id for bustype %x", 3845 bustype)); 3846 return (-1); 3847 } 3848 3849 /* 3850 * Check if a particular irq need to be reserved for any io_intr 3851 */ 3852 static struct apic_io_intr * 3853 apic_find_io_intr(int irqno) 3854 { 3855 struct apic_io_intr *intrp; 3856 3857 intrp = apic_io_intrp; 3858 if (intrp != NULL) { 3859 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 3860 if (intrp->intr_irq == irqno && 3861 intrp->intr_type == IO_INTR_INT) 3862 return (intrp); 3863 intrp++; 3864 } 3865 } 3866 return ((struct apic_io_intr *)NULL); 3867 } 3868 3869 /* 3870 * Check if the given ioapicindex intin combination has already been assigned 3871 * an irq. If so return irqno. Else -1 3872 */ 3873 static int 3874 apic_find_intin(uchar_t ioapic, uchar_t intin) 3875 { 3876 apic_irq_t *irqptr; 3877 int i; 3878 3879 /* find ioapic and intin in the apic_irq_table[] and return the index */ 3880 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) { 3881 irqptr = apic_irq_table[i]; 3882 while (irqptr) { 3883 if ((irqptr->airq_mps_intr_index >= 0) && 3884 (irqptr->airq_intin_no == intin) && 3885 (irqptr->airq_ioapicindex == ioapic)) { 3886 APIC_VERBOSE_IOAPIC((CE_NOTE, "!Found irq " 3887 "entry for ioapic:intin %x:%x " 3888 "shared interrupts ?", ioapic, intin)); 3889 return (i); 3890 } 3891 irqptr = irqptr->airq_next; 3892 } 3893 } 3894 return (-1); 3895 } 3896 3897 int 3898 apic_allocate_irq(int irq) 3899 { 3900 int freeirq, i; 3901 3902 if ((freeirq = apic_find_free_irq(irq, (APIC_RESV_IRQ - 1))) == -1) 3903 if ((freeirq = apic_find_free_irq(APIC_FIRST_FREE_IRQ, 3904 (irq - 1))) == -1) { 3905 /* 3906 * if BIOS really defines every single irq in the mps 3907 * table, then don't worry about conflicting with 3908 * them, just use any free slot in apic_irq_table 3909 */ 3910 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) { 3911 if ((apic_irq_table[i] == NULL) || 3912 apic_irq_table[i]->airq_mps_intr_index == 3913 FREE_INDEX) { 3914 freeirq = i; 3915 break; 3916 } 3917 } 3918 if (freeirq == -1) { 3919 /* This shouldn't happen, but just in case */ 3920 cmn_err(CE_WARN, "pcplusmp: NO available IRQ"); 3921 return (-1); 3922 } 3923 } 3924 if (apic_irq_table[freeirq] == NULL) { 3925 apic_irq_table[freeirq] = 3926 kmem_zalloc(sizeof (apic_irq_t), KM_NOSLEEP); 3927 if (apic_irq_table[freeirq] == NULL) { 3928 cmn_err(CE_WARN, "pcplusmp: NO memory to allocate IRQ"); 3929 return (-1); 3930 } 3931 apic_irq_table[freeirq]->airq_mps_intr_index = FREE_INDEX; 3932 } 3933 return (freeirq); 3934 } 3935 3936 static int 3937 apic_find_free_irq(int start, int end) 3938 { 3939 int i; 3940 3941 for (i = start; i <= end; i++) 3942 /* Check if any I/O entry needs this IRQ */ 3943 if (apic_find_io_intr(i) == NULL) { 3944 /* Then see if it is free */ 3945 if ((apic_irq_table[i] == NULL) || 3946 (apic_irq_table[i]->airq_mps_intr_index == 3947 FREE_INDEX)) { 3948 return (i); 3949 } 3950 } 3951 return (-1); 3952 } 3953 3954 /* 3955 * Allocate a free vector for irq at ipl. Takes care of merging of multiple 3956 * IPLs into a single APIC level as well as stretching some IPLs onto multiple 3957 * levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority 3958 * requests and allocated only when pri is set. 3959 */ 3960 static uchar_t 3961 apic_allocate_vector(int ipl, int irq, int pri) 3962 { 3963 int lowest, highest, i; 3964 3965 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK; 3966 lowest = apic_ipltopri[ipl - 1] + APIC_VECTOR_PER_IPL; 3967 3968 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */ 3969 lowest -= APIC_VECTOR_PER_IPL; 3970 3971 #ifdef DEBUG 3972 if (apic_restrict_vector) /* for testing shared interrupt logic */ 3973 highest = lowest + apic_restrict_vector + APIC_HI_PRI_VECTS; 3974 #endif /* DEBUG */ 3975 if (pri == 0) 3976 highest -= APIC_HI_PRI_VECTS; 3977 3978 for (i = lowest; i < highest; i++) { 3979 if ((i == T_FASTTRAP) || (i == APIC_SPUR_INTR) || 3980 (i == T_SYSCALLINT) || (i == T_DTRACE_PROBE) || 3981 (i == T_DTRACE_RET)) 3982 continue; 3983 if (apic_vector_to_irq[i] == APIC_RESV_IRQ) { 3984 apic_vector_to_irq[i] = (uchar_t)irq; 3985 return (i); 3986 } 3987 } 3988 3989 return (0); 3990 } 3991 3992 static void 3993 apic_modify_vector(uchar_t vector, int irq) 3994 { 3995 apic_vector_to_irq[vector] = (uchar_t)irq; 3996 } 3997 3998 /* 3999 * Mark vector as being in the process of being deleted. Interrupts 4000 * may still come in on some CPU. The moment an interrupt comes with 4001 * the new vector, we know we can free the old one. Called only from 4002 * addspl and delspl with interrupts disabled. Because an interrupt 4003 * can be shared, but no interrupt from either device may come in, 4004 * we also use a timeout mechanism, which we arbitrarily set to 4005 * apic_revector_timeout microseconds. 4006 */ 4007 static void 4008 apic_mark_vector(uchar_t oldvector, uchar_t newvector) 4009 { 4010 int iflag = intr_clear(); 4011 lock_set(&apic_revector_lock); 4012 if (!apic_oldvec_to_newvec) { 4013 apic_oldvec_to_newvec = 4014 kmem_zalloc(sizeof (newvector) * APIC_MAX_VECTOR * 2, 4015 KM_NOSLEEP); 4016 4017 if (!apic_oldvec_to_newvec) { 4018 /* 4019 * This failure is not catastrophic. 4020 * But, the oldvec will never be freed. 4021 */ 4022 apic_error |= APIC_ERR_MARK_VECTOR_FAIL; 4023 lock_clear(&apic_revector_lock); 4024 intr_restore(iflag); 4025 return; 4026 } 4027 apic_newvec_to_oldvec = &apic_oldvec_to_newvec[APIC_MAX_VECTOR]; 4028 } 4029 4030 /* See if we already did this for drivers which do double addintrs */ 4031 if (apic_oldvec_to_newvec[oldvector] != newvector) { 4032 apic_oldvec_to_newvec[oldvector] = newvector; 4033 apic_newvec_to_oldvec[newvector] = oldvector; 4034 apic_revector_pending++; 4035 } 4036 lock_clear(&apic_revector_lock); 4037 intr_restore(iflag); 4038 (void) timeout(apic_xlate_vector_free_timeout_handler, 4039 (void *)(uintptr_t)oldvector, drv_usectohz(apic_revector_timeout)); 4040 } 4041 4042 /* 4043 * xlate_vector is called from intr_enter if revector_pending is set. 4044 * It will xlate it if needed and mark the old vector as free. 4045 */ 4046 static uchar_t 4047 apic_xlate_vector(uchar_t vector) 4048 { 4049 uchar_t newvector, oldvector = 0; 4050 4051 lock_set(&apic_revector_lock); 4052 /* Do we really need to do this ? */ 4053 if (!apic_revector_pending) { 4054 lock_clear(&apic_revector_lock); 4055 return (vector); 4056 } 4057 if ((newvector = apic_oldvec_to_newvec[vector]) != 0) 4058 oldvector = vector; 4059 else { 4060 /* 4061 * The incoming vector is new . See if a stale entry is 4062 * remaining 4063 */ 4064 if ((oldvector = apic_newvec_to_oldvec[vector]) != 0) 4065 newvector = vector; 4066 } 4067 4068 if (oldvector) { 4069 apic_revector_pending--; 4070 apic_oldvec_to_newvec[oldvector] = 0; 4071 apic_newvec_to_oldvec[newvector] = 0; 4072 apic_free_vector(oldvector); 4073 lock_clear(&apic_revector_lock); 4074 /* There could have been more than one reprogramming! */ 4075 return (apic_xlate_vector(newvector)); 4076 } 4077 lock_clear(&apic_revector_lock); 4078 return (vector); 4079 } 4080 4081 void 4082 apic_xlate_vector_free_timeout_handler(void *arg) 4083 { 4084 int iflag; 4085 uchar_t oldvector, newvector; 4086 4087 oldvector = (uchar_t)(uintptr_t)arg; 4088 iflag = intr_clear(); 4089 lock_set(&apic_revector_lock); 4090 if ((newvector = apic_oldvec_to_newvec[oldvector]) != 0) { 4091 apic_free_vector(oldvector); 4092 apic_oldvec_to_newvec[oldvector] = 0; 4093 apic_newvec_to_oldvec[newvector] = 0; 4094 apic_revector_pending--; 4095 } 4096 4097 lock_clear(&apic_revector_lock); 4098 intr_restore(iflag); 4099 } 4100 4101 4102 /* Mark vector as not being used by any irq */ 4103 static void 4104 apic_free_vector(uchar_t vector) 4105 { 4106 apic_vector_to_irq[vector] = APIC_RESV_IRQ; 4107 } 4108 4109 /* 4110 * compute the polarity, trigger mode and vector for programming into 4111 * the I/O apic and record in airq_rdt_entry. 4112 */ 4113 static void 4114 apic_record_rdt_entry(apic_irq_t *irqptr, int irq) 4115 { 4116 int ioapicindex, bus_type, vector; 4117 short intr_index; 4118 uint_t level, po, io_po; 4119 struct apic_io_intr *iointrp; 4120 4121 intr_index = irqptr->airq_mps_intr_index; 4122 DDI_INTR_IMPLDBG((CE_CONT, "apic_record_rdt_entry: intr_index=%d " 4123 "irq = 0x%x dip = 0x%p vector = 0x%x\n", intr_index, irq, 4124 (void *)irqptr->airq_dip, irqptr->airq_vector)); 4125 4126 if (intr_index == RESERVE_INDEX) { 4127 apic_error |= APIC_ERR_INVALID_INDEX; 4128 return; 4129 } else if (APIC_IS_MSI_OR_MSIX_INDEX(intr_index)) { 4130 return; 4131 } 4132 4133 vector = irqptr->airq_vector; 4134 ioapicindex = irqptr->airq_ioapicindex; 4135 /* Assume edge triggered by default */ 4136 level = 0; 4137 /* Assume active high by default */ 4138 po = 0; 4139 4140 if (intr_index == DEFAULT_INDEX || intr_index == FREE_INDEX) { 4141 ASSERT(irq < 16); 4142 if (eisa_level_intr_mask & (1 << irq)) 4143 level = AV_LEVEL; 4144 if (intr_index == FREE_INDEX && apic_defconf == 0) 4145 apic_error |= APIC_ERR_INVALID_INDEX; 4146 } else if (intr_index == ACPI_INDEX) { 4147 bus_type = irqptr->airq_iflag.bustype; 4148 if (irqptr->airq_iflag.intr_el == INTR_EL_CONFORM) { 4149 if (bus_type == BUS_PCI) 4150 level = AV_LEVEL; 4151 } else 4152 level = (irqptr->airq_iflag.intr_el == INTR_EL_LEVEL) ? 4153 AV_LEVEL : 0; 4154 if (level && 4155 ((irqptr->airq_iflag.intr_po == INTR_PO_ACTIVE_LOW) || 4156 (irqptr->airq_iflag.intr_po == INTR_PO_CONFORM && 4157 bus_type == BUS_PCI))) 4158 po = AV_ACTIVE_LOW; 4159 } else { 4160 iointrp = apic_io_intrp + intr_index; 4161 bus_type = apic_find_bus(iointrp->intr_busid); 4162 if (iointrp->intr_el == INTR_EL_CONFORM) { 4163 if ((irq < 16) && (eisa_level_intr_mask & (1 << irq))) 4164 level = AV_LEVEL; 4165 else if (bus_type == BUS_PCI) 4166 level = AV_LEVEL; 4167 } else 4168 level = (iointrp->intr_el == INTR_EL_LEVEL) ? 4169 AV_LEVEL : 0; 4170 if (level && ((iointrp->intr_po == INTR_PO_ACTIVE_LOW) || 4171 (iointrp->intr_po == INTR_PO_CONFORM && 4172 bus_type == BUS_PCI))) 4173 po = AV_ACTIVE_LOW; 4174 } 4175 if (level) 4176 apic_level_intr[irq] = 1; 4177 /* 4178 * The 82489DX External APIC cannot do active low polarity interrupts. 4179 */ 4180 if (po && (apic_io_ver[ioapicindex] != IOAPIC_VER_82489DX)) 4181 io_po = po; 4182 else 4183 io_po = 0; 4184 4185 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) 4186 printf("setio: ioapic=%x intin=%x level=%x po=%x vector=%x\n", 4187 ioapicindex, irqptr->airq_intin_no, level, io_po, vector); 4188 4189 irqptr->airq_rdt_entry = level|io_po|vector; 4190 } 4191 4192 /* 4193 * Call rebind to do the actual programming. 4194 */ 4195 static int 4196 apic_setup_io_intr(apic_irq_t *irqptr, int irq) 4197 { 4198 int rv; 4199 4200 if (rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, 1, 4201 IMMEDIATE)) 4202 /* CPU is not up or interrupt is disabled. Fall back to 0 */ 4203 rv = apic_rebind(irqptr, 0, 1, IMMEDIATE); 4204 4205 return (rv); 4206 } 4207 4208 /* 4209 * Deferred reprogramming: Call apic_rebind to do the real work. 4210 */ 4211 static int 4212 apic_setup_io_intr_deferred(apic_irq_t *irqptr, int irq) 4213 { 4214 int rv; 4215 4216 if (rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, 1, 4217 DEFERRED)) 4218 /* CPU is not up or interrupt is disabled. Fall back to 0 */ 4219 rv = apic_rebind(irqptr, 0, 1, DEFERRED); 4220 4221 return (rv); 4222 } 4223 4224 /* 4225 * Bind interrupt corresponding to irq_ptr to bind_cpu. acquire_lock 4226 * if false (0) means lock is already held (e.g: in rebind_all). 4227 */ 4228 static int 4229 apic_rebind(apic_irq_t *irq_ptr, int bind_cpu, int acquire_lock, int when) 4230 { 4231 int intin_no; 4232 volatile int32_t *ioapic; 4233 uchar_t airq_temp_cpu; 4234 apic_cpus_info_t *cpu_infop; 4235 int iflag; 4236 int which_irq = apic_vector_to_irq[irq_ptr->airq_vector]; 4237 4238 intin_no = irq_ptr->airq_intin_no; 4239 ioapic = apicioadr[irq_ptr->airq_ioapicindex]; 4240 airq_temp_cpu = irq_ptr->airq_temp_cpu; 4241 if (airq_temp_cpu != IRQ_UNINIT && airq_temp_cpu != IRQ_UNBOUND) { 4242 if (airq_temp_cpu & IRQ_USER_BOUND) 4243 /* Mask off high bit so it can be used as array index */ 4244 airq_temp_cpu &= ~IRQ_USER_BOUND; 4245 4246 ASSERT(airq_temp_cpu < apic_nproc); 4247 } 4248 4249 iflag = intr_clear(); 4250 4251 if (acquire_lock) 4252 lock_set(&apic_ioapic_lock); 4253 4254 /* 4255 * Can't bind to a CPU that's not online: 4256 */ 4257 cpu_infop = &apic_cpus[bind_cpu & ~IRQ_USER_BOUND]; 4258 if (!(cpu_infop->aci_status & APIC_CPU_INTR_ENABLE)) { 4259 4260 if (acquire_lock) 4261 lock_clear(&apic_ioapic_lock); 4262 4263 intr_restore(iflag); 4264 return (1); 4265 } 4266 4267 /* 4268 * If this is a deferred reprogramming attempt, ensure we have 4269 * not been passed stale data: 4270 */ 4271 if ((when == DEFERRED) && 4272 (apic_reprogram_info[which_irq].valid == 0)) { 4273 /* stale info, so just return */ 4274 if (acquire_lock) 4275 lock_clear(&apic_ioapic_lock); 4276 4277 intr_restore(iflag); 4278 return (0); 4279 } 4280 4281 /* 4282 * If this interrupt has been delivered to a CPU and that CPU 4283 * has not handled it yet, we cannot reprogram the IOAPIC now: 4284 */ 4285 if (!APIC_IS_MSI_OR_MSIX_INDEX(irq_ptr->airq_mps_intr_index) && 4286 apic_check_stuck_interrupt(irq_ptr, airq_temp_cpu, bind_cpu, 4287 ioapic, intin_no, which_irq) != 0) { 4288 4289 if (acquire_lock) 4290 lock_clear(&apic_ioapic_lock); 4291 4292 intr_restore(iflag); 4293 return (0); 4294 } 4295 4296 /* 4297 * NOTE: We do not unmask the RDT here, as an interrupt MAY still 4298 * come in before we have a chance to reprogram it below. The 4299 * reprogramming below will simultaneously change and unmask the 4300 * RDT entry. 4301 */ 4302 4303 if ((uchar_t)bind_cpu == IRQ_UNBOUND) { 4304 /* Write the RDT entry -- no specific CPU binding */ 4305 WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic, intin_no, AV_TOALL); 4306 4307 if (airq_temp_cpu != IRQ_UNINIT && airq_temp_cpu != IRQ_UNBOUND) 4308 apic_cpus[airq_temp_cpu].aci_temp_bound--; 4309 4310 /* Write the vector, trigger, and polarity portion of the RDT */ 4311 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic, intin_no, 4312 AV_LDEST | AV_LOPRI | irq_ptr->airq_rdt_entry); 4313 if (acquire_lock) 4314 lock_clear(&apic_ioapic_lock); 4315 irq_ptr->airq_temp_cpu = IRQ_UNBOUND; 4316 intr_restore(iflag); 4317 return (0); 4318 } 4319 4320 if (bind_cpu & IRQ_USER_BOUND) { 4321 cpu_infop->aci_bound++; 4322 } else { 4323 cpu_infop->aci_temp_bound++; 4324 } 4325 ASSERT((bind_cpu & ~IRQ_USER_BOUND) < apic_nproc); 4326 if (!APIC_IS_MSI_OR_MSIX_INDEX(irq_ptr->airq_mps_intr_index)) { 4327 /* Write the RDT entry -- bind to a specific CPU: */ 4328 WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic, intin_no, 4329 cpu_infop->aci_local_id << APIC_ID_BIT_OFFSET); 4330 } 4331 if ((airq_temp_cpu != IRQ_UNBOUND) && (airq_temp_cpu != IRQ_UNINIT)) { 4332 apic_cpus[airq_temp_cpu].aci_temp_bound--; 4333 } 4334 if (!APIC_IS_MSI_OR_MSIX_INDEX(irq_ptr->airq_mps_intr_index)) { 4335 /* Write the vector, trigger, and polarity portion of the RDT */ 4336 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic, intin_no, 4337 AV_PDEST | AV_FIXED | irq_ptr->airq_rdt_entry); 4338 } else { 4339 if (irq_ptr->airq_ioapicindex == irq_ptr->airq_origirq) { 4340 /* first one */ 4341 DDI_INTR_IMPLDBG((CE_CONT, "apic_rebind: call " 4342 "apic_pci_msi_enable_vector\n")); 4343 if (apic_pci_msi_enable_vector(irq_ptr->airq_dip, 4344 (irq_ptr->airq_mps_intr_index == MSI_INDEX) ? 4345 DDI_INTR_TYPE_MSI : DDI_INTR_TYPE_MSIX, which_irq, 4346 irq_ptr->airq_vector, irq_ptr->airq_intin_no, 4347 cpu_infop->aci_local_id) != PSM_SUCCESS) { 4348 cmn_err(CE_WARN, "pcplusmp: " 4349 "apic_pci_msi_enable_vector " 4350 "returned PSM_FAILURE"); 4351 } 4352 } 4353 if ((irq_ptr->airq_ioapicindex + irq_ptr->airq_intin_no - 1) == 4354 irq_ptr->airq_origirq) { /* last one */ 4355 DDI_INTR_IMPLDBG((CE_CONT, "apic_rebind: call " 4356 "pci_msi_enable_mode\n")); 4357 if (pci_msi_enable_mode(irq_ptr->airq_dip, 4358 (irq_ptr->airq_mps_intr_index == MSI_INDEX) ? 4359 DDI_INTR_TYPE_MSI : DDI_INTR_TYPE_MSIX, 4360 which_irq) != DDI_SUCCESS) { 4361 DDI_INTR_IMPLDBG((CE_CONT, "pcplusmp: " 4362 "pci_msi_enable failed\n")); 4363 (void) pci_msi_unconfigure(irq_ptr->airq_dip, 4364 (irq_ptr->airq_mps_intr_index == MSI_INDEX) ? 4365 DDI_INTR_TYPE_MSI : DDI_INTR_TYPE_MSIX, 4366 which_irq); 4367 } 4368 } 4369 } 4370 if (acquire_lock) 4371 lock_clear(&apic_ioapic_lock); 4372 irq_ptr->airq_temp_cpu = (uchar_t)bind_cpu; 4373 apic_redist_cpu_skip &= ~(1 << (bind_cpu & ~IRQ_USER_BOUND)); 4374 intr_restore(iflag); 4375 return (0); 4376 } 4377 4378 /* 4379 * Checks to see if the IOAPIC interrupt entry specified has its Remote IRR 4380 * bit set. Sets up a timeout to perform the reprogramming at a later time 4381 * if it cannot wait for the Remote IRR bit to clear (or if waiting did not 4382 * result in the bit's clearing). 4383 * 4384 * This function will mask the RDT entry if the Remote IRR bit is set. 4385 * 4386 * Returns non-zero if the caller should defer IOAPIC reprogramming. 4387 */ 4388 static int 4389 apic_check_stuck_interrupt(apic_irq_t *irq_ptr, int old_bind_cpu, 4390 int new_bind_cpu, volatile int32_t *ioapic, int intin_no, int which_irq) 4391 { 4392 int32_t rdt_entry; 4393 int waited; 4394 4395 /* Mask the RDT entry, but only if it's a level-triggered interrupt */ 4396 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic, intin_no); 4397 if ((rdt_entry & (AV_LEVEL|AV_MASK)) == AV_LEVEL) { 4398 4399 /* Mask it */ 4400 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic, intin_no, 4401 AV_MASK | rdt_entry); 4402 } 4403 4404 /* 4405 * Wait for the delivery pending bit to clear. 4406 */ 4407 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic, intin_no) & 4408 (AV_LEVEL|AV_PENDING)) == (AV_LEVEL|AV_PENDING)) { 4409 4410 /* 4411 * If we're still waiting on the delivery of this interrupt, 4412 * continue to wait here until it is delivered (this should be 4413 * a very small amount of time, but include a timeout just in 4414 * case). 4415 */ 4416 for (waited = 0; waited < apic_max_usecs_clear_pending; 4417 waited += APIC_USECS_PER_WAIT_INTERVAL) { 4418 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic, intin_no) 4419 & AV_PENDING) == 0) { 4420 break; 4421 } 4422 drv_usecwait(APIC_USECS_PER_WAIT_INTERVAL); 4423 } 4424 4425 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic, intin_no) & 4426 AV_PENDING) != 0) { 4427 cmn_err(CE_WARN, "!IOAPIC %d intin %d: Could not " 4428 "deliver interrupt to local APIC within " 4429 "%d usecs.", irq_ptr->airq_ioapicindex, 4430 irq_ptr->airq_intin_no, 4431 apic_max_usecs_clear_pending); 4432 } 4433 } 4434 4435 /* 4436 * If the remote IRR bit is set, then the interrupt has been sent 4437 * to a CPU for processing. We have no choice but to wait for 4438 * that CPU to process the interrupt, at which point the remote IRR 4439 * bit will be cleared. 4440 */ 4441 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic, intin_no) & 4442 (AV_LEVEL|AV_REMOTE_IRR)) == (AV_LEVEL|AV_REMOTE_IRR)) { 4443 4444 /* 4445 * If the CPU that this RDT is bound to is NOT the current 4446 * CPU, wait until that CPU handles the interrupt and ACKs 4447 * it. If this interrupt is not bound to any CPU (that is, 4448 * if it's bound to the logical destination of "anyone"), it 4449 * may have been delivered to the current CPU so handle that 4450 * case by deferring the reprogramming (below). 4451 */ 4452 kpreempt_disable(); 4453 if ((old_bind_cpu != IRQ_UNBOUND) && 4454 (old_bind_cpu != IRQ_UNINIT) && 4455 (old_bind_cpu != psm_get_cpu_id())) { 4456 for (waited = 0; waited < apic_max_usecs_clear_pending; 4457 waited += APIC_USECS_PER_WAIT_INTERVAL) { 4458 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic, 4459 intin_no) & AV_REMOTE_IRR) == 0) { 4460 4461 /* Clear the reprogramming state: */ 4462 lock_set(&apic_ioapic_reprogram_lock); 4463 4464 apic_reprogram_info[which_irq].valid 4465 = 0; 4466 apic_reprogram_info[which_irq].bindcpu 4467 = 0; 4468 apic_reprogram_info[which_irq].timeouts 4469 = 0; 4470 4471 lock_clear(&apic_ioapic_reprogram_lock); 4472 4473 /* Remote IRR has cleared! */ 4474 kpreempt_enable(); 4475 return (0); 4476 } 4477 drv_usecwait(APIC_USECS_PER_WAIT_INTERVAL); 4478 } 4479 } 4480 kpreempt_enable(); 4481 4482 /* 4483 * If we waited and the Remote IRR bit is still not cleared, 4484 * AND if we've invoked the timeout APIC_REPROGRAM_MAX_TIMEOUTS 4485 * times for this interrupt, try the last-ditch workarounds: 4486 */ 4487 if (apic_reprogram_info[which_irq].timeouts >= 4488 APIC_REPROGRAM_MAX_TIMEOUTS) { 4489 4490 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic, intin_no) 4491 & AV_REMOTE_IRR) != 0) { 4492 /* 4493 * Trying to clear the bit through normal 4494 * channels has failed. So as a last-ditch 4495 * effort, try to set the trigger mode to 4496 * edge, then to level. This has been 4497 * observed to work on many systems. 4498 */ 4499 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic, 4500 intin_no, 4501 READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic, 4502 intin_no) & ~AV_LEVEL); 4503 4504 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic, 4505 intin_no, 4506 READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic, 4507 intin_no) | AV_LEVEL); 4508 4509 /* 4510 * If the bit's STILL set, declare total and 4511 * utter failure 4512 */ 4513 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic, 4514 intin_no) & AV_REMOTE_IRR) != 0) { 4515 cmn_err(CE_WARN, "!IOAPIC %d intin %d: " 4516 "Remote IRR failed to reset " 4517 "within %d usecs. Interrupts to " 4518 "this pin may cease to function.", 4519 irq_ptr->airq_ioapicindex, 4520 irq_ptr->airq_intin_no, 4521 apic_max_usecs_clear_pending); 4522 } 4523 } 4524 /* Clear the reprogramming state: */ 4525 lock_set(&apic_ioapic_reprogram_lock); 4526 4527 apic_reprogram_info[which_irq].valid = 0; 4528 apic_reprogram_info[which_irq].bindcpu = 0; 4529 apic_reprogram_info[which_irq].timeouts = 0; 4530 4531 lock_clear(&apic_ioapic_reprogram_lock); 4532 } else { 4533 #ifdef DEBUG 4534 cmn_err(CE_WARN, "Deferring reprogramming of irq %d", 4535 which_irq); 4536 #endif /* DEBUG */ 4537 /* 4538 * If waiting for the Remote IRR bit (above) didn't 4539 * allow it to clear, defer the reprogramming: 4540 */ 4541 lock_set(&apic_ioapic_reprogram_lock); 4542 4543 apic_reprogram_info[which_irq].valid = 1; 4544 apic_reprogram_info[which_irq].bindcpu = new_bind_cpu; 4545 apic_reprogram_info[which_irq].timeouts++; 4546 4547 lock_clear(&apic_ioapic_reprogram_lock); 4548 4549 /* Fire up a timeout to handle this later */ 4550 (void) timeout(apic_reprogram_timeout_handler, 4551 (void *) 0, 4552 drv_usectohz(APIC_REPROGRAM_TIMEOUT_DELAY)); 4553 4554 /* Inform caller to defer IOAPIC programming: */ 4555 return (1); 4556 } 4557 } 4558 return (0); 4559 } 4560 4561 /* 4562 * Timeout handler that performs the APIC reprogramming 4563 */ 4564 /*ARGSUSED*/ 4565 static void 4566 apic_reprogram_timeout_handler(void *arg) 4567 { 4568 /*LINTED: set but not used in function*/ 4569 int i, result; 4570 4571 /* Serialize access to this function */ 4572 mutex_enter(&apic_reprogram_timeout_mutex); 4573 4574 /* 4575 * For each entry in the reprogramming state that's valid, 4576 * try the reprogramming again: 4577 */ 4578 for (i = 0; i < APIC_MAX_VECTOR; i++) { 4579 if (apic_reprogram_info[i].valid == 0) 4580 continue; 4581 /* 4582 * Though we can't really do anything about errors 4583 * at this point, keep track of them for reporting. 4584 * Note that it is very possible for apic_setup_io_intr 4585 * to re-register this very timeout if the Remote IRR bit 4586 * has not yet cleared. 4587 */ 4588 result = apic_setup_io_intr_deferred(apic_irq_table[i], i); 4589 4590 #ifdef DEBUG 4591 if (result) 4592 cmn_err(CE_WARN, "apic_reprogram_timeout: " 4593 "apic_setup_io_intr returned nonzero for " 4594 "irq=%d!", i); 4595 #endif /* DEBUG */ 4596 } 4597 4598 mutex_exit(&apic_reprogram_timeout_mutex); 4599 } 4600 4601 4602 /* 4603 * Called to migrate all interrupts at an irq to another cpu. safe 4604 * if true means we are not being called from an interrupt 4605 * context and hence it is safe to do a lock_set. If false 4606 * do only a lock_try and return failure ( non 0 ) if we cannot get it 4607 */ 4608 static int 4609 apic_rebind_all(apic_irq_t *irq_ptr, int bind_cpu, int safe) 4610 { 4611 apic_irq_t *irqptr = irq_ptr; 4612 int retval = 0; 4613 int iflag; 4614 4615 iflag = intr_clear(); 4616 if (!safe) { 4617 if (lock_try(&apic_ioapic_lock) == 0) { 4618 intr_restore(iflag); 4619 return (1); 4620 } 4621 } else 4622 lock_set(&apic_ioapic_lock); 4623 4624 while (irqptr) { 4625 if (irqptr->airq_temp_cpu != IRQ_UNINIT) 4626 retval |= apic_rebind(irqptr, bind_cpu, 0, IMMEDIATE); 4627 irqptr = irqptr->airq_next; 4628 } 4629 lock_clear(&apic_ioapic_lock); 4630 intr_restore(iflag); 4631 return (retval); 4632 } 4633 4634 /* 4635 * apic_intr_redistribute does all the messy computations for identifying 4636 * which interrupt to move to which CPU. Currently we do just one interrupt 4637 * at a time. This reduces the time we spent doing all this within clock 4638 * interrupt. When it is done in idle, we could do more than 1. 4639 * First we find the most busy and the most free CPU (time in ISR only) 4640 * skipping those CPUs that has been identified as being ineligible (cpu_skip) 4641 * Then we look for IRQs which are closest to the difference between the 4642 * most busy CPU and the average ISR load. We try to find one whose load 4643 * is less than difference.If none exists, then we chose one larger than the 4644 * difference, provided it does not make the most idle CPU worse than the 4645 * most busy one. In the end, we clear all the busy fields for CPUs. For 4646 * IRQs, they are cleared as they are scanned. 4647 */ 4648 static void 4649 apic_intr_redistribute() 4650 { 4651 int busiest_cpu, most_free_cpu; 4652 int cpu_free, cpu_busy, max_busy, min_busy; 4653 int min_free, diff; 4654 int average_busy, cpus_online; 4655 int i, busy; 4656 apic_cpus_info_t *cpu_infop; 4657 apic_irq_t *min_busy_irq = NULL; 4658 apic_irq_t *max_busy_irq = NULL; 4659 4660 busiest_cpu = most_free_cpu = -1; 4661 cpu_free = cpu_busy = max_busy = average_busy = 0; 4662 min_free = apic_sample_factor_redistribution; 4663 cpus_online = 0; 4664 /* 4665 * Below we will check for CPU_INTR_ENABLE, bound, temp_bound, temp_cpu 4666 * without ioapic_lock. That is OK as we are just doing statistical 4667 * sampling anyway and any inaccuracy now will get corrected next time 4668 * The call to rebind which actually changes things will make sure 4669 * we are consistent. 4670 */ 4671 for (i = 0; i < apic_nproc; i++) { 4672 if (!(apic_redist_cpu_skip & (1 << i)) && 4673 (apic_cpus[i].aci_status & APIC_CPU_INTR_ENABLE)) { 4674 4675 cpu_infop = &apic_cpus[i]; 4676 /* 4677 * If no unbound interrupts or only 1 total on this 4678 * CPU, skip 4679 */ 4680 if (!cpu_infop->aci_temp_bound || 4681 (cpu_infop->aci_bound + cpu_infop->aci_temp_bound) 4682 == 1) { 4683 apic_redist_cpu_skip |= 1 << i; 4684 continue; 4685 } 4686 4687 busy = cpu_infop->aci_busy; 4688 average_busy += busy; 4689 cpus_online++; 4690 if (max_busy < busy) { 4691 max_busy = busy; 4692 busiest_cpu = i; 4693 } 4694 if (min_free > busy) { 4695 min_free = busy; 4696 most_free_cpu = i; 4697 } 4698 if (busy > apic_int_busy_mark) { 4699 cpu_busy |= 1 << i; 4700 } else { 4701 if (busy < apic_int_free_mark) 4702 cpu_free |= 1 << i; 4703 } 4704 } 4705 } 4706 if ((cpu_busy && cpu_free) || 4707 (max_busy >= (min_free + apic_diff_for_redistribution))) { 4708 4709 apic_num_imbalance++; 4710 #ifdef DEBUG 4711 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) { 4712 prom_printf( 4713 "redistribute busy=%x free=%x max=%x min=%x", 4714 cpu_busy, cpu_free, max_busy, min_free); 4715 } 4716 #endif /* DEBUG */ 4717 4718 4719 average_busy /= cpus_online; 4720 4721 diff = max_busy - average_busy; 4722 min_busy = max_busy; /* start with the max possible value */ 4723 max_busy = 0; 4724 min_busy_irq = max_busy_irq = NULL; 4725 i = apic_min_device_irq; 4726 for (; i < apic_max_device_irq; i++) { 4727 apic_irq_t *irq_ptr; 4728 /* Change to linked list per CPU ? */ 4729 if ((irq_ptr = apic_irq_table[i]) == NULL) 4730 continue; 4731 /* Check for irq_busy & decide which one to move */ 4732 /* Also zero them for next round */ 4733 if ((irq_ptr->airq_temp_cpu == busiest_cpu) && 4734 irq_ptr->airq_busy) { 4735 if (irq_ptr->airq_busy < diff) { 4736 /* 4737 * Check for least busy CPU, 4738 * best fit or what ? 4739 */ 4740 if (max_busy < irq_ptr->airq_busy) { 4741 /* 4742 * Most busy within the 4743 * required differential 4744 */ 4745 max_busy = irq_ptr->airq_busy; 4746 max_busy_irq = irq_ptr; 4747 } 4748 } else { 4749 if (min_busy > irq_ptr->airq_busy) { 4750 /* 4751 * least busy, but more than 4752 * the reqd diff 4753 */ 4754 if (min_busy < 4755 (diff + average_busy - 4756 min_free)) { 4757 /* 4758 * Making sure new cpu 4759 * will not end up 4760 * worse 4761 */ 4762 min_busy = 4763 irq_ptr->airq_busy; 4764 4765 min_busy_irq = irq_ptr; 4766 } 4767 } 4768 } 4769 } 4770 irq_ptr->airq_busy = 0; 4771 } 4772 4773 if (max_busy_irq != NULL) { 4774 #ifdef DEBUG 4775 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) { 4776 prom_printf("rebinding %x to %x", 4777 max_busy_irq->airq_vector, most_free_cpu); 4778 } 4779 #endif /* DEBUG */ 4780 if (apic_rebind_all(max_busy_irq, most_free_cpu, 0) 4781 == 0) 4782 /* Make change permenant */ 4783 max_busy_irq->airq_cpu = (uchar_t)most_free_cpu; 4784 } else if (min_busy_irq != NULL) { 4785 #ifdef DEBUG 4786 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) { 4787 prom_printf("rebinding %x to %x", 4788 min_busy_irq->airq_vector, most_free_cpu); 4789 } 4790 #endif /* DEBUG */ 4791 4792 if (apic_rebind_all(min_busy_irq, most_free_cpu, 0) == 4793 0) 4794 /* Make change permenant */ 4795 min_busy_irq->airq_cpu = (uchar_t)most_free_cpu; 4796 } else { 4797 if (cpu_busy != (1 << busiest_cpu)) { 4798 apic_redist_cpu_skip |= 1 << busiest_cpu; 4799 /* 4800 * We leave cpu_skip set so that next time we 4801 * can choose another cpu 4802 */ 4803 } 4804 } 4805 apic_num_rebind++; 4806 } else { 4807 /* 4808 * found nothing. Could be that we skipped over valid CPUs 4809 * or we have balanced everything. If we had a variable 4810 * ticks_for_redistribution, it could be increased here. 4811 * apic_int_busy, int_free etc would also need to be 4812 * changed. 4813 */ 4814 if (apic_redist_cpu_skip) 4815 apic_redist_cpu_skip = 0; 4816 } 4817 for (i = 0; i < apic_nproc; i++) { 4818 apic_cpus[i].aci_busy = 0; 4819 } 4820 } 4821 4822 static void 4823 apic_cleanup_busy() 4824 { 4825 int i; 4826 apic_irq_t *irq_ptr; 4827 4828 for (i = 0; i < apic_nproc; i++) { 4829 apic_cpus[i].aci_busy = 0; 4830 } 4831 4832 for (i = apic_min_device_irq; i < apic_max_device_irq; i++) { 4833 if ((irq_ptr = apic_irq_table[i]) != NULL) 4834 irq_ptr->airq_busy = 0; 4835 } 4836 apic_skipped_redistribute = 0; 4837 } 4838 4839 4840 /* 4841 * This function will reprogram the timer. 4842 * 4843 * When in oneshot mode the argument is the absolute time in future to 4844 * generate the interrupt at. 4845 * 4846 * When in periodic mode, the argument is the interval at which the 4847 * interrupts should be generated. There is no need to support the periodic 4848 * mode timer change at this time. 4849 */ 4850 static void 4851 apic_timer_reprogram(hrtime_t time) 4852 { 4853 hrtime_t now; 4854 uint_t ticks; 4855 4856 /* 4857 * We should be called from high PIL context (CBE_HIGH_PIL), 4858 * so kpreempt is disabled. 4859 */ 4860 4861 if (!apic_oneshot) { 4862 /* time is the interval for periodic mode */ 4863 ticks = (uint_t)((time) / apic_nsec_per_tick); 4864 } else { 4865 /* one shot mode */ 4866 4867 now = gethrtime(); 4868 4869 if (time <= now) { 4870 /* 4871 * requested to generate an interrupt in the past 4872 * generate an interrupt as soon as possible 4873 */ 4874 ticks = apic_min_timer_ticks; 4875 } else if ((time - now) > apic_nsec_max) { 4876 /* 4877 * requested to generate an interrupt at a time 4878 * further than what we are capable of. Set to max 4879 * the hardware can handle 4880 */ 4881 4882 ticks = APIC_MAXVAL; 4883 #ifdef DEBUG 4884 cmn_err(CE_CONT, "apic_timer_reprogram, request at" 4885 " %lld too far in future, current time" 4886 " %lld \n", time, now); 4887 #endif /* DEBUG */ 4888 } else 4889 ticks = (uint_t)((time - now) / apic_nsec_per_tick); 4890 } 4891 4892 if (ticks < apic_min_timer_ticks) 4893 ticks = apic_min_timer_ticks; 4894 4895 apicadr[APIC_INIT_COUNT] = ticks; 4896 4897 } 4898 4899 /* 4900 * This function will enable timer interrupts. 4901 */ 4902 static void 4903 apic_timer_enable(void) 4904 { 4905 /* 4906 * We should be Called from high PIL context (CBE_HIGH_PIL), 4907 * so kpreempt is disabled. 4908 */ 4909 4910 if (!apic_oneshot) 4911 apicadr[APIC_LOCAL_TIMER] = 4912 (apic_clkvect + APIC_BASE_VECT) | AV_TIME; 4913 else { 4914 /* one shot */ 4915 apicadr[APIC_LOCAL_TIMER] = (apic_clkvect + APIC_BASE_VECT); 4916 } 4917 } 4918 4919 /* 4920 * This function will disable timer interrupts. 4921 */ 4922 static void 4923 apic_timer_disable(void) 4924 { 4925 /* 4926 * We should be Called from high PIL context (CBE_HIGH_PIL), 4927 * so kpreempt is disabled. 4928 */ 4929 4930 apicadr[APIC_LOCAL_TIMER] = (apic_clkvect + APIC_BASE_VECT) | AV_MASK; 4931 } 4932 4933 4934 cyclic_id_t apic_cyclic_id; 4935 4936 /* 4937 * If this module needs to be a consumer of cyclic subsystem, they 4938 * can be added here, since at this time kernel cyclic subsystem is initialized 4939 * argument is not currently used, and is reserved for future. 4940 */ 4941 static void 4942 apic_post_cyclic_setup(void *arg) 4943 { 4944 _NOTE(ARGUNUSED(arg)) 4945 cyc_handler_t hdlr; 4946 cyc_time_t when; 4947 4948 /* cpu_lock is held */ 4949 4950 /* set up cyclics for intr redistribution */ 4951 4952 /* 4953 * In peridoc mode intr redistribution processing is done in 4954 * apic_intr_enter during clk intr processing 4955 */ 4956 if (!apic_oneshot) 4957 return; 4958 4959 hdlr.cyh_level = CY_LOW_LEVEL; 4960 hdlr.cyh_func = (cyc_func_t)apic_redistribute_compute; 4961 hdlr.cyh_arg = NULL; 4962 4963 when.cyt_when = 0; 4964 when.cyt_interval = apic_redistribute_sample_interval; 4965 apic_cyclic_id = cyclic_add(&hdlr, &when); 4966 4967 4968 } 4969 4970 static void 4971 apic_redistribute_compute(void) 4972 { 4973 int i, j, max_busy; 4974 4975 if (apic_enable_dynamic_migration) { 4976 if (++apic_nticks == apic_sample_factor_redistribution) { 4977 /* 4978 * Time to call apic_intr_redistribute(). 4979 * reset apic_nticks. This will cause max_busy 4980 * to be calculated below and if it is more than 4981 * apic_int_busy, we will do the whole thing 4982 */ 4983 apic_nticks = 0; 4984 } 4985 max_busy = 0; 4986 for (i = 0; i < apic_nproc; i++) { 4987 4988 /* 4989 * Check if curipl is non zero & if ISR is in 4990 * progress 4991 */ 4992 if (((j = apic_cpus[i].aci_curipl) != 0) && 4993 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) { 4994 4995 int irq; 4996 apic_cpus[i].aci_busy++; 4997 irq = apic_cpus[i].aci_current[j]; 4998 apic_irq_table[irq]->airq_busy++; 4999 } 5000 5001 if (!apic_nticks && 5002 (apic_cpus[i].aci_busy > max_busy)) 5003 max_busy = apic_cpus[i].aci_busy; 5004 } 5005 if (!apic_nticks) { 5006 if (max_busy > apic_int_busy_mark) { 5007 /* 5008 * We could make the following check be 5009 * skipped > 1 in which case, we get a 5010 * redistribution at half the busy mark (due to 5011 * double interval). Need to be able to collect 5012 * more empirical data to decide if that is a 5013 * good strategy. Punt for now. 5014 */ 5015 if (apic_skipped_redistribute) 5016 apic_cleanup_busy(); 5017 else 5018 apic_intr_redistribute(); 5019 } else 5020 apic_skipped_redistribute++; 5021 } 5022 } 5023 } 5024 5025 5026 static int 5027 apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid, 5028 int ipin, int *pci_irqp, iflag_t *intr_flagp) 5029 { 5030 5031 int status; 5032 acpi_psm_lnk_t acpipsmlnk; 5033 5034 if ((status = acpi_get_irq_cache_ent(busid, devid, ipin, pci_irqp, 5035 intr_flagp)) == ACPI_PSM_SUCCESS) { 5036 APIC_VERBOSE_IRQ((CE_CONT, "!pcplusmp: Found irqno %d " 5037 "from cache for device %s, instance #%d\n", *pci_irqp, 5038 ddi_get_name(dip), ddi_get_instance(dip))); 5039 return (status); 5040 } 5041 5042 bzero(&acpipsmlnk, sizeof (acpi_psm_lnk_t)); 5043 5044 if ((status = acpi_translate_pci_irq(dip, ipin, pci_irqp, intr_flagp, 5045 &acpipsmlnk)) == ACPI_PSM_FAILURE) { 5046 APIC_VERBOSE_IRQ((CE_WARN, "pcplusmp: " 5047 " acpi_translate_pci_irq failed for device %s, instance" 5048 " #%d", ddi_get_name(dip), ddi_get_instance(dip))); 5049 return (status); 5050 } 5051 5052 if (status == ACPI_PSM_PARTIAL && acpipsmlnk.lnkobj != NULL) { 5053 status = apic_acpi_irq_configure(&acpipsmlnk, dip, pci_irqp, 5054 intr_flagp); 5055 if (status != ACPI_PSM_SUCCESS) { 5056 status = acpi_get_current_irq_resource(&acpipsmlnk, 5057 pci_irqp, intr_flagp); 5058 } 5059 } 5060 5061 if (status == ACPI_PSM_SUCCESS) { 5062 acpi_new_irq_cache_ent(busid, devid, ipin, *pci_irqp, 5063 intr_flagp, &acpipsmlnk); 5064 5065 APIC_VERBOSE_IRQ((CE_CONT, "pcplusmp: [ACPI] " 5066 "new irq %d for device %s, instance #%d\n", 5067 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip))); 5068 } 5069 5070 return (status); 5071 } 5072 5073 /* 5074 * Configures the irq for the interrupt link device identified by 5075 * acpipsmlnkp. 5076 * 5077 * Gets the current and the list of possible irq settings for the 5078 * device. If apic_unconditional_srs is not set, and the current 5079 * resource setting is in the list of possible irq settings, 5080 * current irq resource setting is passed to the caller. 5081 * 5082 * Otherwise, picks an irq number from the list of possible irq 5083 * settings, and sets the irq of the device to this value. 5084 * If prefer_crs is set, among a set of irq numbers in the list that have 5085 * the least number of devices sharing the interrupt, we pick current irq 5086 * resource setting if it is a member of this set. 5087 * 5088 * Passes the irq number in the value pointed to by pci_irqp, and 5089 * polarity and sensitivity in the structure pointed to by dipintrflagp 5090 * to the caller. 5091 * 5092 * Note that if setting the irq resource failed, but successfuly obtained 5093 * the current irq resource settings, passes the current irq resources 5094 * and considers it a success. 5095 * 5096 * Returns: 5097 * ACPI_PSM_SUCCESS on success. 5098 * 5099 * ACPI_PSM_FAILURE if an error occured during the configuration or 5100 * if a suitable irq was not found for this device, or if setting the 5101 * irq resource and obtaining the current resource fails. 5102 * 5103 */ 5104 static int 5105 apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip, 5106 int *pci_irqp, iflag_t *dipintr_flagp) 5107 { 5108 5109 int i, min_share, foundnow, done = 0; 5110 int32_t irq; 5111 int32_t share_irq = -1; 5112 int32_t chosen_irq = -1; 5113 int cur_irq = -1; 5114 acpi_irqlist_t *irqlistp; 5115 acpi_irqlist_t *irqlistent; 5116 5117 if ((acpi_get_possible_irq_resources(acpipsmlnkp, &irqlistp)) 5118 == ACPI_PSM_FAILURE) { 5119 APIC_VERBOSE_IRQ((CE_WARN, "!pcplusmp: Unable to determine " 5120 "or assign IRQ for device %s, instance #%d: The system was " 5121 "unable to get the list of potential IRQs from ACPI.", 5122 ddi_get_name(dip), ddi_get_instance(dip))); 5123 5124 return (ACPI_PSM_FAILURE); 5125 } 5126 5127 if ((acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq, 5128 dipintr_flagp) == ACPI_PSM_SUCCESS) && (!apic_unconditional_srs) && 5129 (cur_irq > 0)) { 5130 /* 5131 * If an IRQ is set in CRS and that IRQ exists in the set 5132 * returned from _PRS, return that IRQ, otherwise print 5133 * a warning 5134 */ 5135 5136 if (acpi_irqlist_find_irq(irqlistp, cur_irq, NULL) 5137 == ACPI_PSM_SUCCESS) { 5138 5139 acpi_free_irqlist(irqlistp); 5140 ASSERT(pci_irqp != NULL); 5141 *pci_irqp = cur_irq; 5142 return (ACPI_PSM_SUCCESS); 5143 } 5144 5145 APIC_VERBOSE_IRQ((CE_WARN, "!pcplusmp: Could not find the " 5146 "current irq %d for device %s, instance #%d in ACPI's " 5147 "list of possible irqs for this device. Picking one from " 5148 " the latter list.", cur_irq, ddi_get_name(dip), 5149 ddi_get_instance(dip))); 5150 } 5151 5152 irqlistent = irqlistp; 5153 min_share = 255; 5154 5155 while (irqlistent != NULL) { 5156 irqlistent->intr_flags.bustype = BUS_PCI; 5157 5158 for (foundnow = 0, i = 0; i < irqlistent->num_irqs; i++) { 5159 5160 irq = irqlistent->irqs[i]; 5161 5162 if ((irq < 16) && (apic_reserved_irqlist[irq])) 5163 continue; 5164 5165 if (irq == 0) { 5166 /* invalid irq number */ 5167 continue; 5168 } 5169 5170 if ((apic_irq_table[irq] == NULL) || 5171 (apic_irq_table[irq]->airq_dip == dip)) { 5172 chosen_irq = irq; 5173 foundnow = 1; 5174 /* 5175 * If we do not prefer current irq from crs 5176 * or if we do and this irq is the same as 5177 * current irq from crs, this is the one 5178 * to pick. 5179 */ 5180 if (!(apic_prefer_crs) || (irq == cur_irq)) { 5181 done = 1; 5182 break; 5183 } 5184 continue; 5185 } 5186 5187 if (irqlistent->intr_flags.intr_el == INTR_EL_EDGE) 5188 continue; 5189 5190 if (!acpi_intr_compatible(irqlistent->intr_flags, 5191 apic_irq_table[irq]->airq_iflag)) 5192 continue; 5193 5194 if ((apic_irq_table[irq]->airq_share < min_share) || 5195 ((apic_irq_table[irq]->airq_share == min_share) && 5196 (cur_irq == irq) && (apic_prefer_crs))) { 5197 min_share = apic_irq_table[irq]->airq_share; 5198 share_irq = irq; 5199 foundnow = 1; 5200 } 5201 } 5202 5203 /* 5204 * If we found an IRQ in the inner loop this time, save the 5205 * details from the irqlist for later use. 5206 */ 5207 if (foundnow && ((chosen_irq != -1) || (share_irq != -1))) { 5208 /* 5209 * Copy the acpi_prs_private_t and flags from this 5210 * irq list entry, since we found an irq from this 5211 * entry. 5212 */ 5213 acpipsmlnkp->acpi_prs_prv = irqlistent->acpi_prs_prv; 5214 *dipintr_flagp = irqlistent->intr_flags; 5215 } 5216 5217 if (done) 5218 break; 5219 5220 /* Go to the next irqlist entry */ 5221 irqlistent = irqlistent->next; 5222 } 5223 5224 5225 acpi_free_irqlist(irqlistp); 5226 if (chosen_irq != -1) 5227 irq = chosen_irq; 5228 else if (share_irq != -1) 5229 irq = share_irq; 5230 else { 5231 APIC_VERBOSE_IRQ((CE_WARN, "!pcplusmp: Could not find a " 5232 "suitable irq from the list of possible irqs for device " 5233 "%s, instance #%d in ACPI's list of possible irqs", 5234 ddi_get_name(dip), ddi_get_instance(dip))); 5235 return (ACPI_PSM_FAILURE); 5236 } 5237 5238 APIC_VERBOSE_IRQ((CE_CONT, "!pcplusmp: Setting irq %d for device %s " 5239 "instance #%d\n", irq, ddi_get_name(dip), ddi_get_instance(dip))); 5240 5241 if ((acpi_set_irq_resource(acpipsmlnkp, irq)) == ACPI_PSM_SUCCESS) { 5242 /* 5243 * setting irq was successful, check to make sure CRS 5244 * reflects that. If CRS does not agree with what we 5245 * set, return the irq that was set. 5246 */ 5247 5248 if (acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq, 5249 dipintr_flagp) == ACPI_PSM_SUCCESS) { 5250 5251 if (cur_irq != irq) 5252 APIC_VERBOSE_IRQ((CE_WARN, "!pcplusmp: " 5253 "IRQ resource set (irqno %d) for device %s " 5254 "instance #%d, differs from current " 5255 "setting irqno %d", 5256 irq, ddi_get_name(dip), 5257 ddi_get_instance(dip), cur_irq)); 5258 } 5259 5260 /* 5261 * return the irq that was set, and not what CRS reports, 5262 * since CRS has been seen to be bogus on some systems 5263 */ 5264 cur_irq = irq; 5265 } else { 5266 APIC_VERBOSE_IRQ((CE_WARN, "!pcplusmp: set resource irq %d " 5267 "failed for device %s instance #%d", 5268 irq, ddi_get_name(dip), ddi_get_instance(dip))); 5269 5270 if (cur_irq == -1) 5271 return (ACPI_PSM_FAILURE); 5272 } 5273 5274 ASSERT(pci_irqp != NULL); 5275 *pci_irqp = cur_irq; 5276 return (ACPI_PSM_SUCCESS); 5277 } 5278