1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright 2016 Nexenta Systems, Inc. 24 * Copyright (c) 2017 by Delphix. All rights reserved. 25 * Copyright 2017 Joyent, Inc. 26 */ 27 /* 28 * Copyright (c) 2010, Intel Corporation. 29 * All rights reserved. 30 */ 31 32 /* 33 * PSMI 1.1 extensions are supported only in 2.6 and later versions. 34 * PSMI 1.2 extensions are supported only in 2.7 and later versions. 35 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10. 36 * PSMI 1.5 extensions are supported in Solaris Nevada. 37 * PSMI 1.6 extensions are supported in Solaris Nevada. 38 * PSMI 1.7 extensions are supported in Solaris Nevada. 39 */ 40 #define PSMI_1_7 41 42 #include <sys/processor.h> 43 #include <sys/time.h> 44 #include <sys/psm.h> 45 #include <sys/smp_impldefs.h> 46 #include <sys/cram.h> 47 #include <sys/acpi/acpi.h> 48 #include <sys/acpica.h> 49 #include <sys/psm_common.h> 50 #include <sys/apic.h> 51 #include <sys/apic_timer.h> 52 #include <sys/pit.h> 53 #include <sys/ddi.h> 54 #include <sys/sunddi.h> 55 #include <sys/ddi_impldefs.h> 56 #include <sys/pci.h> 57 #include <sys/promif.h> 58 #include <sys/x86_archext.h> 59 #include <sys/cpc_impl.h> 60 #include <sys/uadmin.h> 61 #include <sys/panic.h> 62 #include <sys/debug.h> 63 #include <sys/archsystm.h> 64 #include <sys/trap.h> 65 #include <sys/machsystm.h> 66 #include <sys/cpuvar.h> 67 #include <sys/rm_platter.h> 68 #include <sys/privregs.h> 69 #include <sys/cyclic.h> 70 #include <sys/note.h> 71 #include <sys/pci_intr_lib.h> 72 #include <sys/sunndi.h> 73 #if !defined(__xpv) 74 #include <sys/hpet.h> 75 #include <sys/clock.h> 76 #endif 77 78 /* 79 * Local Function Prototypes 80 */ 81 static int apic_handle_defconf(); 82 static int apic_parse_mpct(caddr_t mpct, int bypass); 83 static struct apic_mpfps_hdr *apic_find_fps_sig(caddr_t fptr, int size); 84 static int apic_checksum(caddr_t bptr, int len); 85 static int apic_find_bus_type(char *bus); 86 static int apic_find_bus(int busid); 87 static struct apic_io_intr *apic_find_io_intr(int irqno); 88 static int apic_find_free_irq(int start, int end); 89 struct apic_io_intr *apic_find_io_intr_w_busid(int irqno, int busid); 90 static void apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp); 91 static void apic_free_apic_cpus(void); 92 static boolean_t apic_is_ioapic_AMD_813x(uint32_t physaddr); 93 static int apic_acpi_enter_apicmode(void); 94 95 int apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, 96 int child_ipin, struct apic_io_intr **intrp); 97 int apic_find_bus_id(int bustype); 98 int apic_find_intin(uchar_t ioapic, uchar_t intin); 99 void apic_record_rdt_entry(apic_irq_t *irqptr, int irq); 100 101 int apic_debug_mps_id = 0; /* 1 - print MPS ID strings */ 102 103 /* ACPI SCI interrupt configuration; -1 if SCI not used */ 104 int apic_sci_vect = -1; 105 iflag_t apic_sci_flags; 106 107 #if !defined(__xpv) 108 /* ACPI HPET interrupt configuration; -1 if HPET not used */ 109 int apic_hpet_vect = -1; 110 iflag_t apic_hpet_flags; 111 #endif 112 113 /* 114 * psm name pointer 115 */ 116 char *psm_name; 117 118 /* ACPI support routines */ 119 static int acpi_probe(char *); 120 static int apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip, 121 int *pci_irqp, iflag_t *intr_flagp); 122 123 int apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid, 124 int ipin, int *pci_irqp, iflag_t *intr_flagp); 125 uchar_t acpi_find_ioapic(int irq); 126 static int acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2); 127 128 /* Max wait time (in repetitions) for flags to clear in an RDT entry. */ 129 int apic_max_reps_clear_pending = 1000; 130 131 int apic_intr_policy = INTR_ROUND_ROBIN; 132 133 int apic_next_bind_cpu = 1; /* For round robin assignment */ 134 /* start with cpu 1 */ 135 136 /* 137 * If enabled, the distribution works as follows: 138 * On every interrupt entry, the current ipl for the CPU is set in cpu_info 139 * and the irq corresponding to the ipl is also set in the aci_current array. 140 * interrupt exit and setspl (due to soft interrupts) will cause the current 141 * ipl to be be changed. This is cache friendly as these frequently used 142 * paths write into a per cpu structure. 143 * 144 * Sampling is done by checking the structures for all CPUs and incrementing 145 * the busy field of the irq (if any) executing on each CPU and the busy field 146 * of the corresponding CPU. 147 * In periodic mode this is done on every clock interrupt. 148 * In one-shot mode, this is done thru a cyclic with an interval of 149 * apic_redistribute_sample_interval (default 10 milli sec). 150 * 151 * Every apic_sample_factor_redistribution times we sample, we do computations 152 * to decide which interrupt needs to be migrated (see comments 153 * before apic_intr_redistribute(). 154 */ 155 156 /* 157 * Following 3 variables start as % and can be patched or set using an 158 * API to be defined in future. They will be scaled to 159 * sample_factor_redistribution which is in turn set to hertz+1 (in periodic 160 * mode), or 101 in one-shot mode to stagger it away from one sec processing 161 */ 162 163 int apic_int_busy_mark = 60; 164 int apic_int_free_mark = 20; 165 int apic_diff_for_redistribution = 10; 166 167 /* sampling interval for interrupt redistribution for dynamic migration */ 168 int apic_redistribute_sample_interval = NANOSEC / 100; /* 10 millisec */ 169 170 /* 171 * number of times we sample before deciding to redistribute interrupts 172 * for dynamic migration 173 */ 174 int apic_sample_factor_redistribution = 101; 175 176 int apic_redist_cpu_skip = 0; 177 int apic_num_imbalance = 0; 178 int apic_num_rebind = 0; 179 180 /* 181 * Maximum number of APIC CPUs in the system, -1 indicates that dynamic 182 * allocation of CPU ids is disabled. 183 */ 184 int apic_max_nproc = -1; 185 int apic_nproc = 0; 186 size_t apic_cpus_size = 0; 187 int apic_defconf = 0; 188 int apic_irq_translate = 0; 189 int apic_spec_rev = 0; 190 int apic_imcrp = 0; 191 192 int apic_use_acpi = 1; /* 1 = use ACPI, 0 = don't use ACPI */ 193 int apic_use_acpi_madt_only = 0; /* 1=ONLY use MADT from ACPI */ 194 195 /* 196 * For interrupt link devices, if apic_unconditional_srs is set, an irq resource 197 * will be assigned (via _SRS). If it is not set, use the current 198 * irq setting (via _CRS), but only if that irq is in the set of possible 199 * irqs (returned by _PRS) for the device. 200 */ 201 int apic_unconditional_srs = 1; 202 203 /* 204 * For interrupt link devices, if apic_prefer_crs is set when we are 205 * assigning an IRQ resource to a device, prefer the current IRQ setting 206 * over other possible irq settings under same conditions. 207 */ 208 209 int apic_prefer_crs = 1; 210 211 uchar_t apic_io_id[MAX_IO_APIC]; 212 volatile uint32_t *apicioadr[MAX_IO_APIC]; 213 uchar_t apic_io_ver[MAX_IO_APIC]; 214 uchar_t apic_io_vectbase[MAX_IO_APIC]; 215 uchar_t apic_io_vectend[MAX_IO_APIC]; 216 uchar_t apic_reserved_irqlist[MAX_ISA_IRQ + 1]; 217 uint32_t apic_physaddr[MAX_IO_APIC]; 218 219 boolean_t ioapic_mask_workaround[MAX_IO_APIC]; 220 221 /* 222 * First available slot to be used as IRQ index into the apic_irq_table 223 * for those interrupts (like MSI/X) that don't have a physical IRQ. 224 */ 225 int apic_first_avail_irq = APIC_FIRST_FREE_IRQ; 226 227 /* 228 * apic_ioapic_lock protects the ioapics (reg select), the status, temp_bound 229 * and bound elements of cpus_info and the temp_cpu element of irq_struct 230 */ 231 lock_t apic_ioapic_lock; 232 233 int apic_io_max = 0; /* no. of i/o apics enabled */ 234 235 struct apic_io_intr *apic_io_intrp = NULL; 236 static struct apic_bus *apic_busp; 237 238 uchar_t apic_resv_vector[MAXIPL+1]; 239 240 char apic_level_intr[APIC_MAX_VECTOR+1]; 241 242 uint32_t eisa_level_intr_mask = 0; 243 /* At least MSB will be set if EISA bus */ 244 245 int apic_pci_bus_total = 0; 246 uchar_t apic_single_pci_busid = 0; 247 248 /* 249 * airq_mutex protects additions to the apic_irq_table - the first 250 * pointer and any airq_nexts off of that one. It also protects 251 * apic_max_device_irq & apic_min_device_irq. It also guarantees 252 * that share_id is unique as new ids are generated only when new 253 * irq_t structs are linked in. Once linked in the structs are never 254 * deleted. temp_cpu & mps_intr_index field indicate if it is programmed 255 * or allocated. Note that there is a slight gap between allocating in 256 * apic_introp_xlate and programming in addspl. 257 */ 258 kmutex_t airq_mutex; 259 apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1]; 260 int apic_max_device_irq = 0; 261 int apic_min_device_irq = APIC_MAX_VECTOR; 262 263 typedef struct prs_irq_list_ent { 264 int list_prio; 265 int32_t irq; 266 iflag_t intrflags; 267 acpi_prs_private_t prsprv; 268 struct prs_irq_list_ent *next; 269 } prs_irq_list_t; 270 271 272 /* 273 * ACPI variables 274 */ 275 /* 1 = acpi is enabled & working, 0 = acpi is not enabled or not there */ 276 int apic_enable_acpi = 0; 277 278 /* ACPI Multiple APIC Description Table ptr */ 279 static ACPI_TABLE_MADT *acpi_mapic_dtp = NULL; 280 281 /* ACPI Interrupt Source Override Structure ptr */ 282 ACPI_MADT_INTERRUPT_OVERRIDE *acpi_isop = NULL; 283 int acpi_iso_cnt = 0; 284 285 /* ACPI Non-maskable Interrupt Sources ptr */ 286 static ACPI_MADT_NMI_SOURCE *acpi_nmi_sp = NULL; 287 static int acpi_nmi_scnt = 0; 288 static ACPI_MADT_LOCAL_APIC_NMI *acpi_nmi_cp = NULL; 289 static int acpi_nmi_ccnt = 0; 290 291 static boolean_t acpi_found_smp_config = B_FALSE; 292 293 /* 294 * The following added to identify a software poweroff method if available. 295 */ 296 297 static struct { 298 int poweroff_method; 299 char oem_id[APIC_MPS_OEM_ID_LEN + 1]; /* MAX + 1 for NULL */ 300 char prod_id[APIC_MPS_PROD_ID_LEN + 1]; /* MAX + 1 for NULL */ 301 } apic_mps_ids[] = { 302 { APIC_POWEROFF_VIA_RTC, "INTEL", "ALDER" }, /* 4300 */ 303 { APIC_POWEROFF_VIA_RTC, "NCR", "AMC" }, /* 4300 */ 304 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "A450NX" }, /* 4400? */ 305 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AD450NX" }, /* 4400 */ 306 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AC450NX" }, /* 4400R */ 307 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "S450NX" }, /* S50 */ 308 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "SC450NX" } /* S50? */ 309 }; 310 311 int apic_poweroff_method = APIC_POWEROFF_NONE; 312 313 /* 314 * Auto-configuration routines 315 */ 316 317 /* 318 * Look at MPSpec 1.4 (Intel Order # 242016-005) for details of what we do here 319 * May work with 1.1 - but not guaranteed. 320 * According to the MP Spec, the MP floating pointer structure 321 * will be searched in the order described below: 322 * 1. In the first kilobyte of Extended BIOS Data Area (EBDA) 323 * 2. Within the last kilobyte of system base memory 324 * 3. In the BIOS ROM address space between 0F0000h and 0FFFFh 325 * Once we find the right signature with proper checksum, we call 326 * either handle_defconf or parse_mpct to get all info necessary for 327 * subsequent operations. 328 */ 329 int 330 apic_probe_common(char *modname) 331 { 332 uint32_t mpct_addr, ebda_start = 0, base_mem_end; 333 caddr_t biosdatap; 334 caddr_t mpct = NULL; 335 caddr_t fptr; 336 int i, mpct_size = 0, mapsize, retval = PSM_FAILURE; 337 ushort_t ebda_seg, base_mem_size; 338 struct apic_mpfps_hdr *fpsp; 339 struct apic_mp_cnf_hdr *hdrp; 340 int bypass_cpu_and_ioapics_in_mptables; 341 int acpi_user_options; 342 343 if (apic_forceload < 0) 344 return (retval); 345 346 /* 347 * Remember who we are 348 */ 349 psm_name = modname; 350 351 /* Allow override for MADT-only mode */ 352 acpi_user_options = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_root_node(), 0, 353 "acpi-user-options", 0); 354 apic_use_acpi_madt_only = ((acpi_user_options & ACPI_OUSER_MADT) != 0); 355 356 /* Allow apic_use_acpi to override MADT-only mode */ 357 if (!apic_use_acpi) 358 apic_use_acpi_madt_only = 0; 359 360 retval = acpi_probe(modname); 361 362 /* in UEFI system, there is no BIOS data */ 363 if (ddi_prop_exists(DDI_DEV_T_ANY, ddi_root_node(), 0, "efi-systab")) 364 goto apic_ret; 365 366 /* 367 * mapin the bios data area 40:0 368 * 40:13h - two-byte location reports the base memory size 369 * 40:0Eh - two-byte location for the exact starting address of 370 * the EBDA segment for EISA 371 */ 372 biosdatap = psm_map_phys(0x400, 0x20, PROT_READ); 373 if (!biosdatap) 374 goto apic_ret; 375 fpsp = (struct apic_mpfps_hdr *)NULL; 376 mapsize = MPFPS_RAM_WIN_LEN; 377 /*LINTED: pointer cast may result in improper alignment */ 378 ebda_seg = *((ushort_t *)(biosdatap+0xe)); 379 /* check the 1k of EBDA */ 380 if (ebda_seg) { 381 ebda_start = ((uint32_t)ebda_seg) << 4; 382 fptr = psm_map_phys(ebda_start, MPFPS_RAM_WIN_LEN, PROT_READ); 383 if (fptr) { 384 if (!(fpsp = 385 apic_find_fps_sig(fptr, MPFPS_RAM_WIN_LEN))) 386 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN); 387 } 388 } 389 /* If not in EBDA, check the last k of system base memory */ 390 if (!fpsp) { 391 /*LINTED: pointer cast may result in improper alignment */ 392 base_mem_size = *((ushort_t *)(biosdatap + 0x13)); 393 394 if (base_mem_size > 512) 395 base_mem_end = 639 * 1024; 396 else 397 base_mem_end = 511 * 1024; 398 /* if ebda == last k of base mem, skip to check BIOS ROM */ 399 if (base_mem_end != ebda_start) { 400 401 fptr = psm_map_phys(base_mem_end, MPFPS_RAM_WIN_LEN, 402 PROT_READ); 403 404 if (fptr) { 405 if (!(fpsp = apic_find_fps_sig(fptr, 406 MPFPS_RAM_WIN_LEN))) 407 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN); 408 } 409 } 410 } 411 psm_unmap_phys(biosdatap, 0x20); 412 413 /* If still cannot find it, check the BIOS ROM space */ 414 if (!fpsp) { 415 mapsize = MPFPS_ROM_WIN_LEN; 416 fptr = psm_map_phys(MPFPS_ROM_WIN_START, 417 MPFPS_ROM_WIN_LEN, PROT_READ); 418 if (fptr) { 419 if (!(fpsp = 420 apic_find_fps_sig(fptr, MPFPS_ROM_WIN_LEN))) { 421 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 422 goto apic_ret; 423 } 424 } 425 } 426 427 if (apic_checksum((caddr_t)fpsp, fpsp->mpfps_length * 16) != 0) { 428 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 429 goto apic_ret; 430 } 431 432 apic_spec_rev = fpsp->mpfps_spec_rev; 433 if ((apic_spec_rev != 04) && (apic_spec_rev != 01)) { 434 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 435 goto apic_ret; 436 } 437 438 /* check IMCR is present or not */ 439 apic_imcrp = fpsp->mpfps_featinfo2 & MPFPS_FEATINFO2_IMCRP; 440 441 /* check default configuration (dual CPUs) */ 442 if ((apic_defconf = fpsp->mpfps_featinfo1) != 0) { 443 psm_unmap_phys(fptr, mapsize); 444 if ((retval = apic_handle_defconf()) != PSM_SUCCESS) 445 return (retval); 446 447 goto apic_ret; 448 } 449 450 /* MP Configuration Table */ 451 mpct_addr = (uint32_t)(fpsp->mpfps_mpct_paddr); 452 453 psm_unmap_phys(fptr, mapsize); /* unmap floating ptr struct */ 454 455 /* 456 * Map in enough memory for the MP Configuration Table Header. 457 * Use this table to read the total length of the BIOS data and 458 * map in all the info 459 */ 460 /*LINTED: pointer cast may result in improper alignment */ 461 hdrp = (struct apic_mp_cnf_hdr *)psm_map_phys(mpct_addr, 462 sizeof (struct apic_mp_cnf_hdr), PROT_READ); 463 if (!hdrp) 464 goto apic_ret; 465 466 /* check mp configuration table signature PCMP */ 467 if (hdrp->mpcnf_sig != 0x504d4350) { 468 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr)); 469 goto apic_ret; 470 } 471 mpct_size = (int)hdrp->mpcnf_tbl_length; 472 473 apic_set_pwroff_method_from_mpcnfhdr(hdrp); 474 475 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr)); 476 477 if ((retval == PSM_SUCCESS) && !apic_use_acpi_madt_only) { 478 /* This is an ACPI machine No need for further checks */ 479 goto apic_ret; 480 } 481 482 /* 483 * Map in the entries for this machine, ie. Processor 484 * Entry Tables, Bus Entry Tables, etc. 485 * They are in fixed order following one another 486 */ 487 mpct = psm_map_phys(mpct_addr, mpct_size, PROT_READ); 488 if (!mpct) 489 goto apic_ret; 490 491 if (apic_checksum(mpct, mpct_size) != 0) 492 goto apic_fail1; 493 494 /*LINTED: pointer cast may result in improper alignment */ 495 hdrp = (struct apic_mp_cnf_hdr *)mpct; 496 apicadr = (uint32_t *)mapin_apic((uint32_t)hdrp->mpcnf_local_apic, 497 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE); 498 if (!apicadr) 499 goto apic_fail1; 500 501 /* Parse all information in the tables */ 502 bypass_cpu_and_ioapics_in_mptables = (retval == PSM_SUCCESS); 503 if (apic_parse_mpct(mpct, bypass_cpu_and_ioapics_in_mptables) == 504 PSM_SUCCESS) { 505 retval = PSM_SUCCESS; 506 goto apic_ret; 507 } 508 509 apic_fail1: 510 psm_unmap_phys(mpct, mpct_size); 511 mpct = NULL; 512 513 apic_ret: 514 if (retval == PSM_SUCCESS) { 515 extern int apic_ioapic_method_probe(); 516 517 if ((retval = apic_ioapic_method_probe()) == PSM_SUCCESS) 518 return (PSM_SUCCESS); 519 } 520 521 for (i = 0; i < apic_io_max; i++) 522 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN); 523 if (apic_cpus) { 524 kmem_free(apic_cpus, apic_cpus_size); 525 apic_cpus = NULL; 526 } 527 if (apicadr) { 528 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 529 apicadr = NULL; 530 } 531 if (mpct) 532 psm_unmap_phys(mpct, mpct_size); 533 534 return (retval); 535 } 536 537 static void 538 apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp) 539 { 540 int i; 541 542 for (i = 0; i < (sizeof (apic_mps_ids) / sizeof (apic_mps_ids[0])); 543 i++) { 544 if ((strncmp(hdrp->mpcnf_oem_str, apic_mps_ids[i].oem_id, 545 strlen(apic_mps_ids[i].oem_id)) == 0) && 546 (strncmp(hdrp->mpcnf_prod_str, apic_mps_ids[i].prod_id, 547 strlen(apic_mps_ids[i].prod_id)) == 0)) { 548 549 apic_poweroff_method = apic_mps_ids[i].poweroff_method; 550 break; 551 } 552 } 553 554 if (apic_debug_mps_id != 0) { 555 cmn_err(CE_CONT, "%s: MPS OEM ID = '%c%c%c%c%c%c%c%c'" 556 "Product ID = '%c%c%c%c%c%c%c%c%c%c%c%c'\n", 557 psm_name, 558 hdrp->mpcnf_oem_str[0], 559 hdrp->mpcnf_oem_str[1], 560 hdrp->mpcnf_oem_str[2], 561 hdrp->mpcnf_oem_str[3], 562 hdrp->mpcnf_oem_str[4], 563 hdrp->mpcnf_oem_str[5], 564 hdrp->mpcnf_oem_str[6], 565 hdrp->mpcnf_oem_str[7], 566 hdrp->mpcnf_prod_str[0], 567 hdrp->mpcnf_prod_str[1], 568 hdrp->mpcnf_prod_str[2], 569 hdrp->mpcnf_prod_str[3], 570 hdrp->mpcnf_prod_str[4], 571 hdrp->mpcnf_prod_str[5], 572 hdrp->mpcnf_prod_str[6], 573 hdrp->mpcnf_prod_str[7], 574 hdrp->mpcnf_prod_str[8], 575 hdrp->mpcnf_prod_str[9], 576 hdrp->mpcnf_prod_str[10], 577 hdrp->mpcnf_prod_str[11]); 578 } 579 } 580 581 static void 582 apic_free_apic_cpus(void) 583 { 584 if (apic_cpus != NULL) { 585 kmem_free(apic_cpus, apic_cpus_size); 586 apic_cpus = NULL; 587 apic_cpus_size = 0; 588 } 589 } 590 591 static int 592 acpi_probe(char *modname) 593 { 594 int i, intmax, index; 595 uint32_t id, ver; 596 int acpi_verboseflags = 0; 597 int madt_seen, madt_size; 598 ACPI_SUBTABLE_HEADER *ap; 599 ACPI_MADT_LOCAL_APIC *mpa; 600 ACPI_MADT_LOCAL_X2APIC *mpx2a; 601 ACPI_MADT_IO_APIC *mia; 602 ACPI_MADT_IO_SAPIC *misa; 603 ACPI_MADT_INTERRUPT_OVERRIDE *mio; 604 ACPI_MADT_NMI_SOURCE *mns; 605 ACPI_MADT_INTERRUPT_SOURCE *mis; 606 ACPI_MADT_LOCAL_APIC_NMI *mlan; 607 ACPI_MADT_LOCAL_X2APIC_NMI *mx2alan; 608 ACPI_MADT_LOCAL_APIC_OVERRIDE *mao; 609 int sci; 610 iflag_t sci_flags; 611 volatile uint32_t *ioapic; 612 int ioapic_ix; 613 uint32_t *local_ids; 614 uint32_t *proc_ids; 615 uchar_t hid; 616 int warned = 0; 617 618 if (!apic_use_acpi) 619 return (PSM_FAILURE); 620 621 if (AcpiGetTable(ACPI_SIG_MADT, 1, 622 (ACPI_TABLE_HEADER **) &acpi_mapic_dtp) != AE_OK) { 623 cmn_err(CE_WARN, "!acpi_probe: No MADT found!"); 624 return (PSM_FAILURE); 625 } 626 627 apicadr = mapin_apic((uint32_t)acpi_mapic_dtp->Address, 628 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE); 629 if (!apicadr) 630 return (PSM_FAILURE); 631 632 if ((local_ids = (uint32_t *)kmem_zalloc(NCPU * sizeof (uint32_t), 633 KM_NOSLEEP)) == NULL) 634 return (PSM_FAILURE); 635 636 if ((proc_ids = (uint32_t *)kmem_zalloc(NCPU * sizeof (uint32_t), 637 KM_NOSLEEP)) == NULL) { 638 kmem_free(local_ids, NCPU * sizeof (uint32_t)); 639 return (PSM_FAILURE); 640 } 641 642 id = apic_reg_ops->apic_read(APIC_LID_REG); 643 local_ids[0] = (uchar_t)(id >> 24); 644 apic_nproc = index = 1; 645 apic_io_max = 0; 646 647 ap = (ACPI_SUBTABLE_HEADER *) (acpi_mapic_dtp + 1); 648 madt_size = acpi_mapic_dtp->Header.Length; 649 madt_seen = sizeof (*acpi_mapic_dtp); 650 651 while (madt_seen < madt_size) { 652 switch (ap->Type) { 653 case ACPI_MADT_TYPE_LOCAL_APIC: 654 mpa = (ACPI_MADT_LOCAL_APIC *) ap; 655 if (mpa->LapicFlags & ACPI_MADT_ENABLED) { 656 if (mpa->Id == 255) { 657 cmn_err(CE_WARN, "!%s: encountered " 658 "invalid entry in MADT: CPU %d " 659 "has Local APIC Id equal to 255 ", 660 psm_name, mpa->ProcessorId); 661 } 662 if (mpa->Id == local_ids[0]) { 663 ASSERT(index == 1); 664 proc_ids[0] = mpa->ProcessorId; 665 } else if (apic_nproc < NCPU && use_mp && 666 apic_nproc < boot_ncpus) { 667 local_ids[index] = mpa->Id; 668 proc_ids[index] = mpa->ProcessorId; 669 index++; 670 apic_nproc++; 671 } else if (apic_nproc == NCPU && !warned) { 672 cmn_err(CE_WARN, "%s: CPU limit " 673 "exceeded" 674 #if !defined(__amd64) 675 " for 32-bit mode" 676 #endif 677 "; Solaris will use %d CPUs.", 678 psm_name, NCPU); 679 warned = 1; 680 } 681 } 682 break; 683 684 case ACPI_MADT_TYPE_IO_APIC: 685 mia = (ACPI_MADT_IO_APIC *) ap; 686 if (apic_io_max < MAX_IO_APIC) { 687 ioapic_ix = apic_io_max; 688 apic_io_id[apic_io_max] = mia->Id; 689 apic_io_vectbase[apic_io_max] = 690 mia->GlobalIrqBase; 691 apic_physaddr[apic_io_max] = 692 (uint32_t)mia->Address; 693 ioapic = apicioadr[apic_io_max] = 694 mapin_ioapic((uint32_t)mia->Address, 695 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 696 if (!ioapic) 697 goto cleanup; 698 ioapic_mask_workaround[apic_io_max] = 699 apic_is_ioapic_AMD_813x(mia->Address); 700 apic_io_max++; 701 } 702 break; 703 704 case ACPI_MADT_TYPE_INTERRUPT_OVERRIDE: 705 mio = (ACPI_MADT_INTERRUPT_OVERRIDE *) ap; 706 if (acpi_isop == NULL) 707 acpi_isop = mio; 708 acpi_iso_cnt++; 709 break; 710 711 case ACPI_MADT_TYPE_NMI_SOURCE: 712 /* UNIMPLEMENTED */ 713 mns = (ACPI_MADT_NMI_SOURCE *) ap; 714 if (acpi_nmi_sp == NULL) 715 acpi_nmi_sp = mns; 716 acpi_nmi_scnt++; 717 718 cmn_err(CE_NOTE, "!apic: nmi source: %d 0x%x\n", 719 mns->GlobalIrq, mns->IntiFlags); 720 break; 721 722 case ACPI_MADT_TYPE_LOCAL_APIC_NMI: 723 /* UNIMPLEMENTED */ 724 mlan = (ACPI_MADT_LOCAL_APIC_NMI *) ap; 725 if (acpi_nmi_cp == NULL) 726 acpi_nmi_cp = mlan; 727 acpi_nmi_ccnt++; 728 729 cmn_err(CE_NOTE, "!apic: local nmi: %d 0x%x %d\n", 730 mlan->ProcessorId, mlan->IntiFlags, 731 mlan->Lint); 732 break; 733 734 case ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE: 735 /* UNIMPLEMENTED */ 736 mao = (ACPI_MADT_LOCAL_APIC_OVERRIDE *) ap; 737 cmn_err(CE_NOTE, "!apic: address override: %lx\n", 738 (long)mao->Address); 739 break; 740 741 case ACPI_MADT_TYPE_IO_SAPIC: 742 /* UNIMPLEMENTED */ 743 misa = (ACPI_MADT_IO_SAPIC *) ap; 744 745 cmn_err(CE_NOTE, "!apic: io sapic: %d %d %lx\n", 746 misa->Id, misa->GlobalIrqBase, 747 (long)misa->Address); 748 break; 749 750 case ACPI_MADT_TYPE_INTERRUPT_SOURCE: 751 /* UNIMPLEMENTED */ 752 mis = (ACPI_MADT_INTERRUPT_SOURCE *) ap; 753 754 cmn_err(CE_NOTE, 755 "!apic: irq source: %d %d %d 0x%x %d %d\n", 756 mis->Id, mis->Eid, mis->GlobalIrq, 757 mis->IntiFlags, mis->Type, 758 mis->IoSapicVector); 759 break; 760 761 case ACPI_MADT_TYPE_LOCAL_X2APIC: 762 mpx2a = (ACPI_MADT_LOCAL_X2APIC *) ap; 763 764 /* 765 * All logical processors with APIC ID values 766 * of 255 and greater will have their APIC 767 * reported through Processor X2APIC structure. 768 * All logical processors with APIC ID less than 769 * 255 will have their APIC reported through 770 * Processor Local APIC. 771 * 772 * Some systems apparently don't care and report all 773 * processors through Processor X2APIC structures. We 774 * warn about that but don't ignore those CPUs. 775 */ 776 if (mpx2a->LocalApicId < 255) { 777 cmn_err(CE_WARN, "!%s: ignoring invalid entry " 778 "in MADT: CPU %d has X2APIC Id %d (< 255)", 779 psm_name, mpx2a->Uid, mpx2a->LocalApicId); 780 } 781 if (mpx2a->LapicFlags & ACPI_MADT_ENABLED) { 782 if (mpx2a->LocalApicId == local_ids[0]) { 783 ASSERT(index == 1); 784 proc_ids[0] = mpx2a->Uid; 785 } else if (apic_nproc < NCPU && use_mp && 786 apic_nproc < boot_ncpus) { 787 local_ids[index] = mpx2a->LocalApicId; 788 proc_ids[index] = mpx2a->Uid; 789 index++; 790 apic_nproc++; 791 } else if (apic_nproc == NCPU && !warned) { 792 cmn_err(CE_WARN, "%s: CPU limit " 793 "exceeded" 794 #if !defined(__amd64) 795 " for 32-bit mode" 796 #endif 797 "; Solaris will use %d CPUs.", 798 psm_name, NCPU); 799 warned = 1; 800 } 801 } 802 803 break; 804 805 case ACPI_MADT_TYPE_LOCAL_X2APIC_NMI: 806 /* UNIMPLEMENTED */ 807 mx2alan = (ACPI_MADT_LOCAL_X2APIC_NMI *) ap; 808 if (mx2alan->Uid >> 8) 809 acpi_nmi_ccnt++; 810 811 #ifdef DEBUG 812 cmn_err(CE_NOTE, 813 "!apic: local x2apic nmi: %d 0x%x %d\n", 814 mx2alan->Uid, mx2alan->IntiFlags, mx2alan->Lint); 815 #endif 816 817 break; 818 819 case ACPI_MADT_TYPE_RESERVED: 820 default: 821 break; 822 } 823 824 /* advance to next entry */ 825 madt_seen += ap->Length; 826 ap = (ACPI_SUBTABLE_HEADER *)(((char *)ap) + ap->Length); 827 } 828 829 /* We found multiple enabled cpus via MADT */ 830 if ((apic_nproc > 1) && (apic_io_max > 0)) { 831 acpi_found_smp_config = B_TRUE; 832 cmn_err(CE_NOTE, 833 "!apic: Using ACPI (MADT) for SMP configuration"); 834 } 835 836 /* 837 * allocate enough space for possible hot-adding of CPUs. 838 * max_ncpus may be less than apic_nproc if it's set by user. 839 */ 840 if (plat_dr_support_cpu()) { 841 apic_max_nproc = max_ncpus; 842 } 843 apic_cpus_size = max(apic_nproc, max_ncpus) * sizeof (*apic_cpus); 844 if ((apic_cpus = kmem_zalloc(apic_cpus_size, KM_NOSLEEP)) == NULL) 845 goto cleanup; 846 847 /* 848 * ACPI doesn't provide the local apic ver, get it directly from the 849 * local apic 850 */ 851 ver = apic_reg_ops->apic_read(APIC_VERS_REG); 852 for (i = 0; i < apic_nproc; i++) { 853 apic_cpus[i].aci_local_id = local_ids[i]; 854 apic_cpus[i].aci_local_ver = (uchar_t)(ver & 0xFF); 855 apic_cpus[i].aci_processor_id = proc_ids[i]; 856 /* Only build mapping info for CPUs present at boot. */ 857 if (i < boot_ncpus) 858 (void) acpica_map_cpu(i, proc_ids[i]); 859 } 860 861 /* 862 * To support CPU dynamic reconfiguration, the apic CPU info structure 863 * for each possible CPU will be pre-allocated at boot time. 864 * The state for each apic CPU info structure will be assigned according 865 * to the following rules: 866 * Rule 1: 867 * Slot index range: [0, min(apic_nproc, boot_ncpus)) 868 * State flags: 0 869 * Note: cpu exists and will be configured/enabled at boot time 870 * Rule 2: 871 * Slot index range: [boot_ncpus, apic_nproc) 872 * State flags: APIC_CPU_FREE | APIC_CPU_DIRTY 873 * Note: cpu exists but won't be configured/enabled at boot time 874 * Rule 3: 875 * Slot index range: [apic_nproc, boot_ncpus) 876 * State flags: APIC_CPU_FREE 877 * Note: cpu doesn't exist at boot time 878 * Rule 4: 879 * Slot index range: [max(apic_nproc, boot_ncpus), max_ncpus) 880 * State flags: APIC_CPU_FREE 881 * Note: cpu doesn't exist at boot time 882 */ 883 CPUSET_ZERO(apic_cpumask); 884 for (i = 0; i < min(boot_ncpus, apic_nproc); i++) { 885 CPUSET_ADD(apic_cpumask, i); 886 apic_cpus[i].aci_status = 0; 887 } 888 for (i = boot_ncpus; i < apic_nproc; i++) { 889 apic_cpus[i].aci_status = APIC_CPU_FREE | APIC_CPU_DIRTY; 890 } 891 for (i = apic_nproc; i < boot_ncpus; i++) { 892 apic_cpus[i].aci_status = APIC_CPU_FREE; 893 } 894 for (i = max(boot_ncpus, apic_nproc); i < max_ncpus; i++) { 895 apic_cpus[i].aci_status = APIC_CPU_FREE; 896 } 897 898 for (i = 0; i < apic_io_max; i++) { 899 ioapic_ix = i; 900 901 /* 902 * need to check Sitka on the following acpi problem 903 * On the Sitka, the ioapic's apic_id field isn't reporting 904 * the actual io apic id. We have reported this problem 905 * to Intel. Until they fix the problem, we will get the 906 * actual id directly from the ioapic. 907 */ 908 id = ioapic_read(ioapic_ix, APIC_ID_CMD); 909 hid = (uchar_t)(id >> 24); 910 911 if (hid != apic_io_id[i]) { 912 if (apic_io_id[i] == 0) 913 apic_io_id[i] = hid; 914 else { /* set ioapic id to whatever reported by ACPI */ 915 id = ((uint32_t)apic_io_id[i]) << 24; 916 ioapic_write(ioapic_ix, APIC_ID_CMD, id); 917 } 918 } 919 ver = ioapic_read(ioapic_ix, APIC_VERS_CMD); 920 apic_io_ver[i] = (uchar_t)(ver & 0xff); 921 intmax = (ver >> 16) & 0xff; 922 apic_io_vectend[i] = apic_io_vectbase[i] + intmax; 923 if (apic_first_avail_irq <= apic_io_vectend[i]) 924 apic_first_avail_irq = apic_io_vectend[i] + 1; 925 } 926 927 928 /* 929 * Process SCI configuration here 930 * An error may be returned here if 931 * acpi-user-options specifies legacy mode 932 * (no SCI, no ACPI mode) 933 */ 934 if (acpica_get_sci(&sci, &sci_flags) != AE_OK) 935 sci = -1; 936 937 /* 938 * Now call acpi_init() to generate namespaces 939 * If this fails, we don't attempt to use ACPI 940 * even if we were able to get a MADT above 941 */ 942 if (acpica_init() != AE_OK) { 943 cmn_err(CE_WARN, "!apic: Failed to initialize acpica!"); 944 goto cleanup; 945 } 946 947 /* 948 * Call acpica_build_processor_map() now that we have 949 * ACPI namesspace access 950 */ 951 (void) acpica_build_processor_map(); 952 953 /* 954 * Squirrel away the SCI and flags for later on 955 * in apic_picinit() when we're ready 956 */ 957 apic_sci_vect = sci; 958 apic_sci_flags = sci_flags; 959 960 if (apic_verbose & APIC_VERBOSE_IRQ_FLAG) 961 acpi_verboseflags |= PSM_VERBOSE_IRQ_FLAG; 962 963 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) 964 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_FLAG; 965 966 if (apic_verbose & APIC_VERBOSE_POWEROFF_PAUSE_FLAG) 967 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_PAUSE_FLAG; 968 969 if (acpi_psm_init(modname, acpi_verboseflags) == ACPI_PSM_FAILURE) 970 goto cleanup; 971 972 /* Enable ACPI APIC interrupt routing */ 973 if (apic_acpi_enter_apicmode() != PSM_FAILURE) { 974 cmn_err(CE_NOTE, "!apic: Using APIC interrupt routing mode"); 975 build_reserved_irqlist((uchar_t *)apic_reserved_irqlist); 976 apic_enable_acpi = 1; 977 if (apic_sci_vect > 0) { 978 acpica_set_core_feature(ACPI_FEATURE_SCI_EVENT); 979 } 980 if (apic_use_acpi_madt_only) { 981 cmn_err(CE_CONT, 982 "?Using ACPI for CPU/IOAPIC information ONLY\n"); 983 } 984 985 #if !defined(__xpv) 986 /* 987 * probe ACPI for hpet information here which is used later 988 * in apic_picinit(). 989 */ 990 if (hpet_acpi_init(&apic_hpet_vect, &apic_hpet_flags) < 0) { 991 cmn_err(CE_NOTE, "!ACPI HPET table query failed\n"); 992 } 993 #endif 994 995 kmem_free(local_ids, NCPU * sizeof (uint32_t)); 996 kmem_free(proc_ids, NCPU * sizeof (uint32_t)); 997 return (PSM_SUCCESS); 998 } 999 /* if setting APIC mode failed above, we fall through to cleanup */ 1000 1001 cleanup: 1002 cmn_err(CE_WARN, "!apic: Failed acpi_probe, SMP config was %s", 1003 acpi_found_smp_config ? "found" : "not found"); 1004 apic_free_apic_cpus(); 1005 if (apicadr != NULL) { 1006 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 1007 apicadr = NULL; 1008 } 1009 apic_max_nproc = -1; 1010 apic_nproc = 0; 1011 for (i = 0; i < apic_io_max; i++) { 1012 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN); 1013 apicioadr[i] = NULL; 1014 } 1015 apic_io_max = 0; 1016 acpi_isop = NULL; 1017 acpi_iso_cnt = 0; 1018 acpi_nmi_sp = NULL; 1019 acpi_nmi_scnt = 0; 1020 acpi_nmi_cp = NULL; 1021 acpi_nmi_ccnt = 0; 1022 acpi_found_smp_config = B_FALSE; 1023 kmem_free(local_ids, NCPU * sizeof (uint32_t)); 1024 kmem_free(proc_ids, NCPU * sizeof (uint32_t)); 1025 return (PSM_FAILURE); 1026 } 1027 1028 /* 1029 * Handle default configuration. Fill in reqd global variables & tables 1030 * Fill all details as MP table does not give any more info 1031 */ 1032 static int 1033 apic_handle_defconf() 1034 { 1035 uint_t lid; 1036 1037 /* Failed to probe ACPI MADT tables, disable CPU DR. */ 1038 apic_max_nproc = -1; 1039 apic_free_apic_cpus(); 1040 plat_dr_disable_cpu(); 1041 1042 apicioadr[0] = (void *)mapin_ioapic(APIC_IO_ADDR, 1043 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 1044 apicadr = (void *)psm_map_phys(APIC_LOCAL_ADDR, 1045 APIC_LOCAL_MEMLEN, PROT_READ); 1046 apic_cpus_size = 2 * sizeof (*apic_cpus); 1047 apic_cpus = (apic_cpus_info_t *) 1048 kmem_zalloc(apic_cpus_size, KM_NOSLEEP); 1049 if ((!apicadr) || (!apicioadr[0]) || (!apic_cpus)) 1050 goto apic_handle_defconf_fail; 1051 CPUSET_ONLY(apic_cpumask, 0); 1052 CPUSET_ADD(apic_cpumask, 1); 1053 apic_nproc = 2; 1054 lid = apic_reg_ops->apic_read(APIC_LID_REG); 1055 apic_cpus[0].aci_local_id = (uchar_t)(lid >> APIC_ID_BIT_OFFSET); 1056 /* 1057 * According to the PC+MP spec 1.1, the local ids 1058 * for the default configuration has to be 0 or 1 1059 */ 1060 if (apic_cpus[0].aci_local_id == 1) 1061 apic_cpus[1].aci_local_id = 0; 1062 else if (apic_cpus[0].aci_local_id == 0) 1063 apic_cpus[1].aci_local_id = 1; 1064 else 1065 goto apic_handle_defconf_fail; 1066 1067 apic_io_id[0] = 2; 1068 apic_io_max = 1; 1069 if (apic_defconf >= 5) { 1070 apic_cpus[0].aci_local_ver = APIC_INTEGRATED_VERS; 1071 apic_cpus[1].aci_local_ver = APIC_INTEGRATED_VERS; 1072 apic_io_ver[0] = APIC_INTEGRATED_VERS; 1073 } else { 1074 apic_cpus[0].aci_local_ver = 0; /* 82489 DX */ 1075 apic_cpus[1].aci_local_ver = 0; 1076 apic_io_ver[0] = 0; 1077 } 1078 if (apic_defconf == 2 || apic_defconf == 3 || apic_defconf == 6) 1079 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) | 1080 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1); 1081 return (PSM_SUCCESS); 1082 1083 apic_handle_defconf_fail: 1084 if (apicadr) 1085 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 1086 if (apicioadr[0]) 1087 mapout_ioapic((caddr_t)apicioadr[0], APIC_IO_MEMLEN); 1088 return (PSM_FAILURE); 1089 } 1090 1091 /* Parse the entries in MP configuration table and collect info that we need */ 1092 static int 1093 apic_parse_mpct(caddr_t mpct, int bypass_cpus_and_ioapics) 1094 { 1095 struct apic_procent *procp; 1096 struct apic_bus *busp; 1097 struct apic_io_entry *ioapicp; 1098 struct apic_io_intr *intrp; 1099 int ioapic_ix; 1100 uint_t lid; 1101 uint32_t id; 1102 uchar_t hid; 1103 int warned = 0; 1104 1105 /*LINTED: pointer cast may result in improper alignment */ 1106 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr)); 1107 1108 /* No need to count cpu entries if we won't use them */ 1109 if (!bypass_cpus_and_ioapics) { 1110 1111 /* Find max # of CPUS and allocate structure accordingly */ 1112 apic_nproc = 0; 1113 CPUSET_ZERO(apic_cpumask); 1114 while (procp->proc_entry == APIC_CPU_ENTRY) { 1115 if (procp->proc_cpuflags & CPUFLAGS_EN) { 1116 if (apic_nproc < NCPU && use_mp && 1117 apic_nproc < boot_ncpus) { 1118 CPUSET_ADD(apic_cpumask, apic_nproc); 1119 apic_nproc++; 1120 } else if (apic_nproc == NCPU && !warned) { 1121 cmn_err(CE_WARN, "%s: CPU limit " 1122 "exceeded" 1123 #if !defined(__amd64) 1124 " for 32-bit mode" 1125 #endif 1126 "; Solaris will use %d CPUs.", 1127 psm_name, NCPU); 1128 warned = 1; 1129 } 1130 1131 } 1132 procp++; 1133 } 1134 apic_cpus_size = apic_nproc * sizeof (*apic_cpus); 1135 if (!apic_nproc || !(apic_cpus = (apic_cpus_info_t *) 1136 kmem_zalloc(apic_cpus_size, KM_NOSLEEP))) 1137 return (PSM_FAILURE); 1138 } 1139 1140 /*LINTED: pointer cast may result in improper alignment */ 1141 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr)); 1142 1143 /* 1144 * start with index 1 as 0 needs to be filled in with Boot CPU, but 1145 * if we're bypassing this information, it has already been filled 1146 * in by acpi_probe(), so don't overwrite it. 1147 */ 1148 if (!bypass_cpus_and_ioapics) 1149 apic_nproc = 1; 1150 1151 while (procp->proc_entry == APIC_CPU_ENTRY) { 1152 /* check whether the cpu exists or not */ 1153 if (!bypass_cpus_and_ioapics && 1154 procp->proc_cpuflags & CPUFLAGS_EN) { 1155 if (procp->proc_cpuflags & CPUFLAGS_BP) { /* Boot CPU */ 1156 lid = apic_reg_ops->apic_read(APIC_LID_REG); 1157 apic_cpus[0].aci_local_id = procp->proc_apicid; 1158 if (apic_cpus[0].aci_local_id != 1159 (uchar_t)(lid >> APIC_ID_BIT_OFFSET)) { 1160 return (PSM_FAILURE); 1161 } 1162 apic_cpus[0].aci_local_ver = 1163 procp->proc_version; 1164 } else if (apic_nproc < NCPU && use_mp && 1165 apic_nproc < boot_ncpus) { 1166 apic_cpus[apic_nproc].aci_local_id = 1167 procp->proc_apicid; 1168 1169 apic_cpus[apic_nproc].aci_local_ver = 1170 procp->proc_version; 1171 apic_nproc++; 1172 1173 } 1174 } 1175 procp++; 1176 } 1177 1178 /* 1179 * Save start of bus entries for later use. 1180 * Get EISA level cntrl if EISA bus is present. 1181 * Also get the CPI bus id for single CPI bus case 1182 */ 1183 apic_busp = busp = (struct apic_bus *)procp; 1184 while (busp->bus_entry == APIC_BUS_ENTRY) { 1185 lid = apic_find_bus_type((char *)&busp->bus_str1); 1186 if (lid == BUS_EISA) { 1187 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) | 1188 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1); 1189 } else if (lid == BUS_PCI) { 1190 /* 1191 * apic_single_pci_busid will be used only if 1192 * apic_pic_bus_total is equal to 1 1193 */ 1194 apic_pci_bus_total++; 1195 apic_single_pci_busid = busp->bus_id; 1196 } 1197 busp++; 1198 } 1199 1200 ioapicp = (struct apic_io_entry *)busp; 1201 1202 if (!bypass_cpus_and_ioapics) 1203 apic_io_max = 0; 1204 do { 1205 if (!bypass_cpus_and_ioapics && apic_io_max < MAX_IO_APIC) { 1206 if (ioapicp->io_flags & IOAPIC_FLAGS_EN) { 1207 apic_io_id[apic_io_max] = ioapicp->io_apicid; 1208 apic_io_ver[apic_io_max] = ioapicp->io_version; 1209 apicioadr[apic_io_max] = 1210 (void *)mapin_ioapic( 1211 (uint32_t)ioapicp->io_apic_addr, 1212 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 1213 1214 if (!apicioadr[apic_io_max]) 1215 return (PSM_FAILURE); 1216 1217 ioapic_mask_workaround[apic_io_max] = 1218 apic_is_ioapic_AMD_813x( 1219 ioapicp->io_apic_addr); 1220 1221 ioapic_ix = apic_io_max; 1222 id = ioapic_read(ioapic_ix, APIC_ID_CMD); 1223 hid = (uchar_t)(id >> 24); 1224 1225 if (hid != apic_io_id[apic_io_max]) { 1226 if (apic_io_id[apic_io_max] == 0) 1227 apic_io_id[apic_io_max] = hid; 1228 else { 1229 /* 1230 * set ioapic id to whatever 1231 * reported by MPS 1232 * 1233 * may not need to set index 1234 * again ??? 1235 * take it out and try 1236 */ 1237 1238 id = ((uint32_t) 1239 apic_io_id[apic_io_max]) << 1240 24; 1241 1242 ioapic_write(ioapic_ix, 1243 APIC_ID_CMD, id); 1244 } 1245 } 1246 apic_io_max++; 1247 } 1248 } 1249 ioapicp++; 1250 } while (ioapicp->io_entry == APIC_IO_ENTRY); 1251 1252 apic_io_intrp = (struct apic_io_intr *)ioapicp; 1253 1254 intrp = apic_io_intrp; 1255 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 1256 if ((intrp->intr_irq > APIC_MAX_ISA_IRQ) || 1257 (apic_find_bus(intrp->intr_busid) == BUS_PCI)) { 1258 apic_irq_translate = 1; 1259 break; 1260 } 1261 intrp++; 1262 } 1263 1264 return (PSM_SUCCESS); 1265 } 1266 1267 boolean_t 1268 apic_cpu_in_range(int cpu) 1269 { 1270 cpu &= ~IRQ_USER_BOUND; 1271 /* Check whether cpu id is in valid range. */ 1272 if (cpu < 0 || cpu >= apic_nproc) { 1273 return (B_FALSE); 1274 } else if (apic_max_nproc != -1 && cpu >= apic_max_nproc) { 1275 /* 1276 * Check whether cpuid is in valid range if CPU DR is enabled. 1277 */ 1278 return (B_FALSE); 1279 } else if (!CPU_IN_SET(apic_cpumask, cpu)) { 1280 return (B_FALSE); 1281 } 1282 1283 return (B_TRUE); 1284 } 1285 1286 processorid_t 1287 apic_get_next_bind_cpu(void) 1288 { 1289 int i, count; 1290 processorid_t cpuid = 0; 1291 1292 for (count = 0; count < apic_nproc; count++) { 1293 if (apic_next_bind_cpu >= apic_nproc) { 1294 apic_next_bind_cpu = 0; 1295 } 1296 i = apic_next_bind_cpu++; 1297 if (apic_cpu_in_range(i)) { 1298 cpuid = i; 1299 break; 1300 } 1301 } 1302 1303 return (cpuid); 1304 } 1305 1306 uint16_t 1307 apic_get_apic_version() 1308 { 1309 int i; 1310 uchar_t min_io_apic_ver = 0; 1311 static uint16_t version; /* Cache as value is constant */ 1312 static boolean_t found = B_FALSE; /* Accomodate zero version */ 1313 1314 if (found == B_FALSE) { 1315 found = B_TRUE; 1316 1317 /* 1318 * Don't assume all IO APICs in the system are the same. 1319 * 1320 * Set to the minimum version. 1321 */ 1322 for (i = 0; i < apic_io_max; i++) { 1323 if ((apic_io_ver[i] != 0) && 1324 ((min_io_apic_ver == 0) || 1325 (min_io_apic_ver >= apic_io_ver[i]))) 1326 min_io_apic_ver = apic_io_ver[i]; 1327 } 1328 1329 /* Assume all local APICs are of the same version. */ 1330 version = (min_io_apic_ver << 8) | apic_cpus[0].aci_local_ver; 1331 } 1332 return (version); 1333 } 1334 1335 static struct apic_mpfps_hdr * 1336 apic_find_fps_sig(caddr_t cptr, int len) 1337 { 1338 int i; 1339 1340 /* Look for the pattern "_MP_" */ 1341 for (i = 0; i < len; i += 16) { 1342 if ((*(cptr+i) == '_') && 1343 (*(cptr+i+1) == 'M') && 1344 (*(cptr+i+2) == 'P') && 1345 (*(cptr+i+3) == '_')) 1346 /*LINTED: pointer cast may result in improper alignment */ 1347 return ((struct apic_mpfps_hdr *)(cptr + i)); 1348 } 1349 return (NULL); 1350 } 1351 1352 static int 1353 apic_checksum(caddr_t bptr, int len) 1354 { 1355 int i; 1356 uchar_t cksum; 1357 1358 cksum = 0; 1359 for (i = 0; i < len; i++) 1360 cksum += *bptr++; 1361 return ((int)cksum); 1362 } 1363 1364 /* 1365 * On machines with PCI-PCI bridges, a device behind a PCI-PCI bridge 1366 * needs special handling. We may need to chase up the device tree, 1367 * using the PCI-PCI Bridge specification's "rotating IPIN assumptions", 1368 * to find the IPIN at the root bus that relates to the IPIN on the 1369 * subsidiary bus (for ACPI or MP). We may, however, have an entry 1370 * in the MP table or the ACPI namespace for this device itself. 1371 * We handle both cases in the search below. 1372 */ 1373 /* this is the non-acpi version */ 1374 int 1375 apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, int child_ipin, 1376 struct apic_io_intr **intrp) 1377 { 1378 dev_info_t *dipp, *dip; 1379 int pci_irq; 1380 ddi_acc_handle_t cfg_handle; 1381 int bridge_devno, bridge_bus; 1382 int ipin; 1383 1384 dip = idip; 1385 1386 /*CONSTCOND*/ 1387 while (1) { 1388 if (((dipp = ddi_get_parent(dip)) == (dev_info_t *)NULL) || 1389 (pci_config_setup(dipp, &cfg_handle) != DDI_SUCCESS)) 1390 return (-1); 1391 if ((pci_config_get8(cfg_handle, PCI_CONF_BASCLASS) == 1392 PCI_CLASS_BRIDGE) && (pci_config_get8(cfg_handle, 1393 PCI_CONF_SUBCLASS) == PCI_BRIDGE_PCI)) { 1394 pci_config_teardown(&cfg_handle); 1395 if (acpica_get_bdf(dipp, &bridge_bus, &bridge_devno, 1396 NULL) != 0) 1397 return (-1); 1398 /* 1399 * This is the rotating scheme documented in the 1400 * PCI-to-PCI spec. If the PCI-to-PCI bridge is 1401 * behind another PCI-to-PCI bridge, then it needs 1402 * to keep ascending until an interrupt entry is 1403 * found or the root is reached. 1404 */ 1405 ipin = (child_devno + child_ipin) % PCI_INTD; 1406 if (bridge_bus == 0 && apic_pci_bus_total == 1) 1407 bridge_bus = (int)apic_single_pci_busid; 1408 pci_irq = ((bridge_devno & 0x1f) << 2) | 1409 (ipin & 0x3); 1410 if ((*intrp = apic_find_io_intr_w_busid(pci_irq, 1411 bridge_bus)) != NULL) { 1412 return (pci_irq); 1413 } 1414 dip = dipp; 1415 child_devno = bridge_devno; 1416 child_ipin = ipin; 1417 } else { 1418 pci_config_teardown(&cfg_handle); 1419 return (-1); 1420 } 1421 } 1422 /*LINTED: function will not fall off the bottom */ 1423 } 1424 1425 uchar_t 1426 acpi_find_ioapic(int irq) 1427 { 1428 int i; 1429 1430 for (i = 0; i < apic_io_max; i++) { 1431 if (irq >= apic_io_vectbase[i] && irq <= apic_io_vectend[i]) 1432 return ((uchar_t)i); 1433 } 1434 return (0xFF); /* shouldn't happen */ 1435 } 1436 1437 /* 1438 * See if two irqs are compatible for sharing a vector. 1439 * Currently we only support sharing of PCI devices. 1440 */ 1441 static int 1442 acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2) 1443 { 1444 uint_t level1, po1; 1445 uint_t level2, po2; 1446 1447 /* Assume active high by default */ 1448 po1 = 0; 1449 po2 = 0; 1450 1451 if (iflag1.bustype != iflag2.bustype || iflag1.bustype != BUS_PCI) 1452 return (0); 1453 1454 if (iflag1.intr_el == INTR_EL_CONFORM) 1455 level1 = AV_LEVEL; 1456 else 1457 level1 = (iflag1.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0; 1458 1459 if (level1 && ((iflag1.intr_po == INTR_PO_ACTIVE_LOW) || 1460 (iflag1.intr_po == INTR_PO_CONFORM))) 1461 po1 = AV_ACTIVE_LOW; 1462 1463 if (iflag2.intr_el == INTR_EL_CONFORM) 1464 level2 = AV_LEVEL; 1465 else 1466 level2 = (iflag2.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0; 1467 1468 if (level2 && ((iflag2.intr_po == INTR_PO_ACTIVE_LOW) || 1469 (iflag2.intr_po == INTR_PO_CONFORM))) 1470 po2 = AV_ACTIVE_LOW; 1471 1472 if ((level1 == level2) && (po1 == po2)) 1473 return (1); 1474 1475 return (0); 1476 } 1477 1478 struct apic_io_intr * 1479 apic_find_io_intr_w_busid(int irqno, int busid) 1480 { 1481 struct apic_io_intr *intrp; 1482 1483 /* 1484 * It can have more than 1 entry with same source bus IRQ, 1485 * but unique with the source bus id 1486 */ 1487 intrp = apic_io_intrp; 1488 if (intrp != NULL) { 1489 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 1490 if (intrp->intr_irq == irqno && 1491 intrp->intr_busid == busid && 1492 intrp->intr_type == IO_INTR_INT) 1493 return (intrp); 1494 intrp++; 1495 } 1496 } 1497 APIC_VERBOSE_IOAPIC((CE_NOTE, "Did not find io intr for irqno:" 1498 "busid %x:%x\n", irqno, busid)); 1499 return ((struct apic_io_intr *)NULL); 1500 } 1501 1502 1503 struct mps_bus_info { 1504 char *bus_name; 1505 int bus_id; 1506 } bus_info_array[] = { 1507 "ISA ", BUS_ISA, 1508 "PCI ", BUS_PCI, 1509 "EISA ", BUS_EISA, 1510 "XPRESS", BUS_XPRESS, 1511 "PCMCIA", BUS_PCMCIA, 1512 "VL ", BUS_VL, 1513 "CBUS ", BUS_CBUS, 1514 "CBUSII", BUS_CBUSII, 1515 "FUTURE", BUS_FUTURE, 1516 "INTERN", BUS_INTERN, 1517 "MBI ", BUS_MBI, 1518 "MBII ", BUS_MBII, 1519 "MPI ", BUS_MPI, 1520 "MPSA ", BUS_MPSA, 1521 "NUBUS ", BUS_NUBUS, 1522 "TC ", BUS_TC, 1523 "VME ", BUS_VME, 1524 "PCI-E ", BUS_PCIE 1525 }; 1526 1527 static int 1528 apic_find_bus_type(char *bus) 1529 { 1530 int i = 0; 1531 1532 for (; i < sizeof (bus_info_array)/sizeof (struct mps_bus_info); i++) 1533 if (strncmp(bus, bus_info_array[i].bus_name, 1534 strlen(bus_info_array[i].bus_name)) == 0) 1535 return (bus_info_array[i].bus_id); 1536 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus type for bus %s", bus)); 1537 return (0); 1538 } 1539 1540 static int 1541 apic_find_bus(int busid) 1542 { 1543 struct apic_bus *busp; 1544 1545 busp = apic_busp; 1546 while (busp->bus_entry == APIC_BUS_ENTRY) { 1547 if (busp->bus_id == busid) 1548 return (apic_find_bus_type((char *)&busp->bus_str1)); 1549 busp++; 1550 } 1551 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus for bus id %x", busid)); 1552 return (0); 1553 } 1554 1555 int 1556 apic_find_bus_id(int bustype) 1557 { 1558 struct apic_bus *busp; 1559 1560 busp = apic_busp; 1561 while (busp->bus_entry == APIC_BUS_ENTRY) { 1562 if (apic_find_bus_type((char *)&busp->bus_str1) == bustype) 1563 return (busp->bus_id); 1564 busp++; 1565 } 1566 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus id for bustype %x", 1567 bustype)); 1568 return (-1); 1569 } 1570 1571 /* 1572 * Check if a particular irq need to be reserved for any io_intr 1573 */ 1574 static struct apic_io_intr * 1575 apic_find_io_intr(int irqno) 1576 { 1577 struct apic_io_intr *intrp; 1578 1579 intrp = apic_io_intrp; 1580 if (intrp != NULL) { 1581 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 1582 if (intrp->intr_irq == irqno && 1583 intrp->intr_type == IO_INTR_INT) 1584 return (intrp); 1585 intrp++; 1586 } 1587 } 1588 return ((struct apic_io_intr *)NULL); 1589 } 1590 1591 /* 1592 * Check if the given ioapicindex intin combination has already been assigned 1593 * an irq. If so return irqno. Else -1 1594 */ 1595 int 1596 apic_find_intin(uchar_t ioapic, uchar_t intin) 1597 { 1598 apic_irq_t *irqptr; 1599 int i; 1600 1601 /* find ioapic and intin in the apic_irq_table[] and return the index */ 1602 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) { 1603 irqptr = apic_irq_table[i]; 1604 while (irqptr) { 1605 if ((irqptr->airq_mps_intr_index >= 0) && 1606 (irqptr->airq_intin_no == intin) && 1607 (irqptr->airq_ioapicindex == ioapic)) { 1608 APIC_VERBOSE_IOAPIC((CE_NOTE, "!Found irq " 1609 "entry for ioapic:intin %x:%x " 1610 "shared interrupts ?", ioapic, intin)); 1611 return (i); 1612 } 1613 irqptr = irqptr->airq_next; 1614 } 1615 } 1616 return (-1); 1617 } 1618 1619 int 1620 apic_allocate_irq(int irq) 1621 { 1622 int freeirq, i; 1623 1624 if ((freeirq = apic_find_free_irq(irq, (APIC_RESV_IRQ - 1))) == -1) 1625 if ((freeirq = apic_find_free_irq(APIC_FIRST_FREE_IRQ, 1626 (irq - 1))) == -1) { 1627 /* 1628 * if BIOS really defines every single irq in the mps 1629 * table, then don't worry about conflicting with 1630 * them, just use any free slot in apic_irq_table 1631 */ 1632 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) { 1633 if ((apic_irq_table[i] == NULL) || 1634 apic_irq_table[i]->airq_mps_intr_index == 1635 FREE_INDEX) { 1636 freeirq = i; 1637 break; 1638 } 1639 } 1640 if (freeirq == -1) { 1641 /* This shouldn't happen, but just in case */ 1642 cmn_err(CE_WARN, "%s: NO available IRQ", psm_name); 1643 return (-1); 1644 } 1645 } 1646 if (apic_irq_table[freeirq] == NULL) { 1647 apic_irq_table[freeirq] = 1648 kmem_zalloc(sizeof (apic_irq_t), KM_NOSLEEP); 1649 if (apic_irq_table[freeirq] == NULL) { 1650 cmn_err(CE_WARN, "%s: NO memory to allocate IRQ", 1651 psm_name); 1652 return (-1); 1653 } 1654 apic_irq_table[freeirq]->airq_temp_cpu = IRQ_UNINIT; 1655 apic_irq_table[freeirq]->airq_mps_intr_index = FREE_INDEX; 1656 } 1657 return (freeirq); 1658 } 1659 1660 static int 1661 apic_find_free_irq(int start, int end) 1662 { 1663 int i; 1664 1665 for (i = start; i <= end; i++) 1666 /* Check if any I/O entry needs this IRQ */ 1667 if (apic_find_io_intr(i) == NULL) { 1668 /* Then see if it is free */ 1669 if ((apic_irq_table[i] == NULL) || 1670 (apic_irq_table[i]->airq_mps_intr_index == 1671 FREE_INDEX)) { 1672 return (i); 1673 } 1674 } 1675 return (-1); 1676 } 1677 1678 /* 1679 * compute the polarity, trigger mode and vector for programming into 1680 * the I/O apic and record in airq_rdt_entry. 1681 */ 1682 void 1683 apic_record_rdt_entry(apic_irq_t *irqptr, int irq) 1684 { 1685 int ioapicindex, bus_type, vector; 1686 short intr_index; 1687 uint_t level, po, io_po; 1688 struct apic_io_intr *iointrp; 1689 1690 intr_index = irqptr->airq_mps_intr_index; 1691 DDI_INTR_IMPLDBG((CE_CONT, "apic_record_rdt_entry: intr_index=%d " 1692 "irq = 0x%x dip = 0x%p vector = 0x%x\n", intr_index, irq, 1693 (void *)irqptr->airq_dip, irqptr->airq_vector)); 1694 1695 if (intr_index == RESERVE_INDEX) { 1696 apic_error |= APIC_ERR_INVALID_INDEX; 1697 return; 1698 } else if (APIC_IS_MSI_OR_MSIX_INDEX(intr_index)) { 1699 return; 1700 } 1701 1702 vector = irqptr->airq_vector; 1703 ioapicindex = irqptr->airq_ioapicindex; 1704 /* Assume edge triggered by default */ 1705 level = 0; 1706 /* Assume active high by default */ 1707 po = 0; 1708 1709 if (intr_index == DEFAULT_INDEX || intr_index == FREE_INDEX) { 1710 ASSERT(irq < 16); 1711 if (eisa_level_intr_mask & (1 << irq)) 1712 level = AV_LEVEL; 1713 if (intr_index == FREE_INDEX && apic_defconf == 0) 1714 apic_error |= APIC_ERR_INVALID_INDEX; 1715 } else if (intr_index == ACPI_INDEX) { 1716 bus_type = irqptr->airq_iflag.bustype; 1717 if (irqptr->airq_iflag.intr_el == INTR_EL_CONFORM) { 1718 if (bus_type == BUS_PCI) 1719 level = AV_LEVEL; 1720 } else 1721 level = (irqptr->airq_iflag.intr_el == INTR_EL_LEVEL) ? 1722 AV_LEVEL : 0; 1723 if (level && 1724 ((irqptr->airq_iflag.intr_po == INTR_PO_ACTIVE_LOW) || 1725 (irqptr->airq_iflag.intr_po == INTR_PO_CONFORM && 1726 bus_type == BUS_PCI))) 1727 po = AV_ACTIVE_LOW; 1728 } else { 1729 iointrp = apic_io_intrp + intr_index; 1730 bus_type = apic_find_bus(iointrp->intr_busid); 1731 if (iointrp->intr_el == INTR_EL_CONFORM) { 1732 if ((irq < 16) && (eisa_level_intr_mask & (1 << irq))) 1733 level = AV_LEVEL; 1734 else if (bus_type == BUS_PCI) 1735 level = AV_LEVEL; 1736 } else 1737 level = (iointrp->intr_el == INTR_EL_LEVEL) ? 1738 AV_LEVEL : 0; 1739 if (level && ((iointrp->intr_po == INTR_PO_ACTIVE_LOW) || 1740 (iointrp->intr_po == INTR_PO_CONFORM && 1741 bus_type == BUS_PCI))) 1742 po = AV_ACTIVE_LOW; 1743 } 1744 if (level) 1745 apic_level_intr[irq] = 1; 1746 /* 1747 * The 82489DX External APIC cannot do active low polarity interrupts. 1748 */ 1749 if (po && (apic_io_ver[ioapicindex] != IOAPIC_VER_82489DX)) 1750 io_po = po; 1751 else 1752 io_po = 0; 1753 1754 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) 1755 prom_printf("setio: ioapic=0x%x intin=0x%x level=0x%x po=0x%x " 1756 "vector=0x%x cpu=0x%x\n\n", ioapicindex, 1757 irqptr->airq_intin_no, level, io_po, vector, 1758 irqptr->airq_cpu); 1759 1760 irqptr->airq_rdt_entry = level|io_po|vector; 1761 } 1762 1763 int 1764 apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid, 1765 int ipin, int *pci_irqp, iflag_t *intr_flagp) 1766 { 1767 1768 int status; 1769 acpi_psm_lnk_t acpipsmlnk; 1770 1771 if ((status = acpi_get_irq_cache_ent(busid, devid, ipin, pci_irqp, 1772 intr_flagp)) == ACPI_PSM_SUCCESS) { 1773 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Found irqno %d " 1774 "from cache for device %s, instance #%d\n", psm_name, 1775 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip))); 1776 return (status); 1777 } 1778 1779 bzero(&acpipsmlnk, sizeof (acpi_psm_lnk_t)); 1780 1781 if ((status = acpi_translate_pci_irq(dip, ipin, pci_irqp, intr_flagp, 1782 &acpipsmlnk)) == ACPI_PSM_FAILURE) { 1783 APIC_VERBOSE_IRQ((CE_WARN, "%s: " 1784 " acpi_translate_pci_irq failed for device %s, instance" 1785 " #%d", psm_name, ddi_get_name(dip), 1786 ddi_get_instance(dip))); 1787 return (status); 1788 } 1789 1790 if (status == ACPI_PSM_PARTIAL && acpipsmlnk.lnkobj != NULL) { 1791 status = apic_acpi_irq_configure(&acpipsmlnk, dip, pci_irqp, 1792 intr_flagp); 1793 if (status != ACPI_PSM_SUCCESS) { 1794 status = acpi_get_current_irq_resource(&acpipsmlnk, 1795 pci_irqp, intr_flagp); 1796 } 1797 } 1798 1799 if (status == ACPI_PSM_SUCCESS) { 1800 acpi_new_irq_cache_ent(busid, devid, ipin, *pci_irqp, 1801 intr_flagp, &acpipsmlnk); 1802 1803 APIC_VERBOSE_IRQ((CE_CONT, "%s: [ACPI] " 1804 "new irq %d for device %s, instance #%d\n", psm_name, 1805 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip))); 1806 } 1807 1808 return (status); 1809 } 1810 1811 /* 1812 * Adds an entry to the irq list passed in, and returns the new list. 1813 * Entries are added in priority order (lower numerical priorities are 1814 * placed closer to the head of the list) 1815 */ 1816 static prs_irq_list_t * 1817 acpi_insert_prs_irq_ent(prs_irq_list_t *listp, int priority, int irq, 1818 iflag_t *iflagp, acpi_prs_private_t *prsprvp) 1819 { 1820 struct prs_irq_list_ent *newent, *prevp = NULL, *origlistp; 1821 1822 newent = kmem_zalloc(sizeof (struct prs_irq_list_ent), KM_SLEEP); 1823 1824 newent->list_prio = priority; 1825 newent->irq = irq; 1826 newent->intrflags = *iflagp; 1827 newent->prsprv = *prsprvp; 1828 /* ->next is NULL from kmem_zalloc */ 1829 1830 /* 1831 * New list -- return the new entry as the list. 1832 */ 1833 if (listp == NULL) 1834 return (newent); 1835 1836 /* 1837 * Save original list pointer for return (since we're not modifying 1838 * the head) 1839 */ 1840 origlistp = listp; 1841 1842 /* 1843 * Insertion sort, with entries with identical keys stored AFTER 1844 * existing entries (the less-than-or-equal test of priority does 1845 * this for us). 1846 */ 1847 while (listp != NULL && listp->list_prio <= priority) { 1848 prevp = listp; 1849 listp = listp->next; 1850 } 1851 1852 newent->next = listp; 1853 1854 if (prevp == NULL) { /* Add at head of list (newent is the new head) */ 1855 return (newent); 1856 } else { 1857 prevp->next = newent; 1858 return (origlistp); 1859 } 1860 } 1861 1862 /* 1863 * Frees the list passed in, deallocating all memory and leaving *listpp 1864 * set to NULL. 1865 */ 1866 static void 1867 acpi_destroy_prs_irq_list(prs_irq_list_t **listpp) 1868 { 1869 struct prs_irq_list_ent *nextp; 1870 1871 ASSERT(listpp != NULL); 1872 1873 while (*listpp != NULL) { 1874 nextp = (*listpp)->next; 1875 kmem_free(*listpp, sizeof (struct prs_irq_list_ent)); 1876 *listpp = nextp; 1877 } 1878 } 1879 1880 /* 1881 * apic_choose_irqs_from_prs returns a list of irqs selected from the list of 1882 * irqs returned by the link device's _PRS method. The irqs are chosen 1883 * to minimize contention in situations where the interrupt link device 1884 * can be programmed to steer interrupts to different interrupt controller 1885 * inputs (some of which may already be in use). The list is sorted in order 1886 * of irqs to use, with the highest priority given to interrupt controller 1887 * inputs that are not shared. When an interrupt controller input 1888 * must be shared, apic_choose_irqs_from_prs adds the possible irqs to the 1889 * returned list in the order that minimizes sharing (thereby ensuring lowest 1890 * possible latency from interrupt trigger time to ISR execution time). 1891 */ 1892 static prs_irq_list_t * 1893 apic_choose_irqs_from_prs(acpi_irqlist_t *irqlistent, dev_info_t *dip, 1894 int crs_irq) 1895 { 1896 int32_t irq; 1897 int i; 1898 prs_irq_list_t *prsirqlistp = NULL; 1899 iflag_t iflags; 1900 1901 while (irqlistent != NULL) { 1902 irqlistent->intr_flags.bustype = BUS_PCI; 1903 1904 for (i = 0; i < irqlistent->num_irqs; i++) { 1905 1906 irq = irqlistent->irqs[i]; 1907 1908 if (irq <= 0) { 1909 /* invalid irq number */ 1910 continue; 1911 } 1912 1913 if ((irq < 16) && (apic_reserved_irqlist[irq])) 1914 continue; 1915 1916 if ((apic_irq_table[irq] == NULL) || 1917 (apic_irq_table[irq]->airq_dip == dip)) { 1918 1919 prsirqlistp = acpi_insert_prs_irq_ent( 1920 prsirqlistp, 0 /* Highest priority */, irq, 1921 &irqlistent->intr_flags, 1922 &irqlistent->acpi_prs_prv); 1923 1924 /* 1925 * If we do not prefer the current irq from _CRS 1926 * or if we do and this irq is the same as the 1927 * current irq from _CRS, this is the one 1928 * to pick. 1929 */ 1930 if (!(apic_prefer_crs) || (irq == crs_irq)) { 1931 return (prsirqlistp); 1932 } 1933 continue; 1934 } 1935 1936 /* 1937 * Edge-triggered interrupts cannot be shared 1938 */ 1939 if (irqlistent->intr_flags.intr_el == INTR_EL_EDGE) 1940 continue; 1941 1942 /* 1943 * To work around BIOSes that contain incorrect 1944 * interrupt polarity information in interrupt 1945 * descriptors returned by _PRS, we assume that 1946 * the polarity of the other device sharing this 1947 * interrupt controller input is compatible. 1948 * If it's not, the caller will catch it when 1949 * the caller invokes the link device's _CRS method 1950 * (after invoking its _SRS method). 1951 */ 1952 iflags = irqlistent->intr_flags; 1953 iflags.intr_po = 1954 apic_irq_table[irq]->airq_iflag.intr_po; 1955 1956 if (!acpi_intr_compatible(iflags, 1957 apic_irq_table[irq]->airq_iflag)) { 1958 APIC_VERBOSE_IRQ((CE_CONT, "!%s: irq %d " 1959 "not compatible [%x:%x:%x !~ %x:%x:%x]", 1960 psm_name, irq, 1961 iflags.intr_po, 1962 iflags.intr_el, 1963 iflags.bustype, 1964 apic_irq_table[irq]->airq_iflag.intr_po, 1965 apic_irq_table[irq]->airq_iflag.intr_el, 1966 apic_irq_table[irq]->airq_iflag.bustype)); 1967 continue; 1968 } 1969 1970 /* 1971 * If we prefer the irq from _CRS, no need 1972 * to search any further (and make sure 1973 * to add this irq with the highest priority 1974 * so it's tried first). 1975 */ 1976 if (crs_irq == irq && apic_prefer_crs) { 1977 1978 return (acpi_insert_prs_irq_ent( 1979 prsirqlistp, 1980 0 /* Highest priority */, 1981 irq, &iflags, 1982 &irqlistent->acpi_prs_prv)); 1983 } 1984 1985 /* 1986 * Priority is equal to the share count (lower 1987 * share count is higher priority). Note that 1988 * the intr flags passed in here are the ones we 1989 * changed above -- if incorrect, it will be 1990 * caught by the caller's _CRS flags comparison. 1991 */ 1992 prsirqlistp = acpi_insert_prs_irq_ent( 1993 prsirqlistp, 1994 apic_irq_table[irq]->airq_share, irq, 1995 &iflags, &irqlistent->acpi_prs_prv); 1996 } 1997 1998 /* Go to the next irqlist entry */ 1999 irqlistent = irqlistent->next; 2000 } 2001 2002 return (prsirqlistp); 2003 } 2004 2005 /* 2006 * Configures the irq for the interrupt link device identified by 2007 * acpipsmlnkp. 2008 * 2009 * Gets the current and the list of possible irq settings for the 2010 * device. If apic_unconditional_srs is not set, and the current 2011 * resource setting is in the list of possible irq settings, 2012 * current irq resource setting is passed to the caller. 2013 * 2014 * Otherwise, picks an irq number from the list of possible irq 2015 * settings, and sets the irq of the device to this value. 2016 * If prefer_crs is set, among a set of irq numbers in the list that have 2017 * the least number of devices sharing the interrupt, we pick current irq 2018 * resource setting if it is a member of this set. 2019 * 2020 * Passes the irq number in the value pointed to by pci_irqp, and 2021 * polarity and sensitivity in the structure pointed to by dipintrflagp 2022 * to the caller. 2023 * 2024 * Note that if setting the irq resource failed, but successfuly obtained 2025 * the current irq resource settings, passes the current irq resources 2026 * and considers it a success. 2027 * 2028 * Returns: 2029 * ACPI_PSM_SUCCESS on success. 2030 * 2031 * ACPI_PSM_FAILURE if an error occured during the configuration or 2032 * if a suitable irq was not found for this device, or if setting the 2033 * irq resource and obtaining the current resource fails. 2034 * 2035 */ 2036 static int 2037 apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip, 2038 int *pci_irqp, iflag_t *dipintr_flagp) 2039 { 2040 int32_t irq; 2041 int cur_irq = -1; 2042 acpi_irqlist_t *irqlistp; 2043 prs_irq_list_t *prs_irq_listp, *prs_irq_entp; 2044 boolean_t found_irq = B_FALSE; 2045 2046 dipintr_flagp->bustype = BUS_PCI; 2047 2048 if ((acpi_get_possible_irq_resources(acpipsmlnkp, &irqlistp)) 2049 == ACPI_PSM_FAILURE) { 2050 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Unable to determine " 2051 "or assign IRQ for device %s, instance #%d: The system was " 2052 "unable to get the list of potential IRQs from ACPI.", 2053 psm_name, ddi_get_name(dip), ddi_get_instance(dip))); 2054 2055 return (ACPI_PSM_FAILURE); 2056 } 2057 2058 if ((acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq, 2059 dipintr_flagp) == ACPI_PSM_SUCCESS) && (!apic_unconditional_srs) && 2060 (cur_irq > 0)) { 2061 /* 2062 * If an IRQ is set in CRS and that IRQ exists in the set 2063 * returned from _PRS, return that IRQ, otherwise print 2064 * a warning 2065 */ 2066 2067 if (acpi_irqlist_find_irq(irqlistp, cur_irq, NULL) 2068 == ACPI_PSM_SUCCESS) { 2069 2070 ASSERT(pci_irqp != NULL); 2071 *pci_irqp = cur_irq; 2072 acpi_free_irqlist(irqlistp); 2073 return (ACPI_PSM_SUCCESS); 2074 } 2075 2076 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find the " 2077 "current irq %d for device %s, instance #%d in ACPI's " 2078 "list of possible irqs for this device. Picking one from " 2079 " the latter list.", psm_name, cur_irq, ddi_get_name(dip), 2080 ddi_get_instance(dip))); 2081 } 2082 2083 if ((prs_irq_listp = apic_choose_irqs_from_prs(irqlistp, dip, 2084 cur_irq)) == NULL) { 2085 2086 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find a " 2087 "suitable irq from the list of possible irqs for device " 2088 "%s, instance #%d in ACPI's list of possible irqs", 2089 psm_name, ddi_get_name(dip), ddi_get_instance(dip))); 2090 2091 acpi_free_irqlist(irqlistp); 2092 return (ACPI_PSM_FAILURE); 2093 } 2094 2095 acpi_free_irqlist(irqlistp); 2096 2097 for (prs_irq_entp = prs_irq_listp; 2098 prs_irq_entp != NULL && found_irq == B_FALSE; 2099 prs_irq_entp = prs_irq_entp->next) { 2100 2101 acpipsmlnkp->acpi_prs_prv = prs_irq_entp->prsprv; 2102 irq = prs_irq_entp->irq; 2103 2104 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Setting irq %d for " 2105 "device %s instance #%d\n", psm_name, irq, 2106 ddi_get_name(dip), ddi_get_instance(dip))); 2107 2108 if ((acpi_set_irq_resource(acpipsmlnkp, irq)) 2109 == ACPI_PSM_SUCCESS) { 2110 /* 2111 * setting irq was successful, check to make sure CRS 2112 * reflects that. If CRS does not agree with what we 2113 * set, return the irq that was set. 2114 */ 2115 2116 if (acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq, 2117 dipintr_flagp) == ACPI_PSM_SUCCESS) { 2118 2119 if (cur_irq != irq) 2120 APIC_VERBOSE_IRQ((CE_WARN, 2121 "!%s: IRQ resource set " 2122 "(irqno %d) for device %s " 2123 "instance #%d, differs from " 2124 "current setting irqno %d", 2125 psm_name, irq, ddi_get_name(dip), 2126 ddi_get_instance(dip), cur_irq)); 2127 } else { 2128 /* 2129 * On at least one system, there was a bug in 2130 * a DSDT method called by _STA, causing _STA to 2131 * indicate that the link device was disabled 2132 * (when, in fact, it was enabled). Since _SRS 2133 * succeeded, assume that _CRS is lying and use 2134 * the iflags from this _PRS interrupt choice. 2135 * If we're wrong about the flags, the polarity 2136 * will be incorrect and we may get an interrupt 2137 * storm, but there's not much else we can do 2138 * at this point. 2139 */ 2140 *dipintr_flagp = prs_irq_entp->intrflags; 2141 } 2142 2143 /* 2144 * Return the irq that was set, and not what _CRS 2145 * reports, since _CRS has been seen to return 2146 * different IRQs than what was passed to _SRS on some 2147 * systems (and just not return successfully on others). 2148 */ 2149 cur_irq = irq; 2150 found_irq = B_TRUE; 2151 } else { 2152 APIC_VERBOSE_IRQ((CE_WARN, "!%s: set resource " 2153 "irq %d failed for device %s instance #%d", 2154 psm_name, irq, ddi_get_name(dip), 2155 ddi_get_instance(dip))); 2156 2157 if (cur_irq == -1) { 2158 acpi_destroy_prs_irq_list(&prs_irq_listp); 2159 return (ACPI_PSM_FAILURE); 2160 } 2161 } 2162 } 2163 2164 acpi_destroy_prs_irq_list(&prs_irq_listp); 2165 2166 if (!found_irq) 2167 return (ACPI_PSM_FAILURE); 2168 2169 ASSERT(pci_irqp != NULL); 2170 *pci_irqp = cur_irq; 2171 return (ACPI_PSM_SUCCESS); 2172 } 2173 2174 void 2175 ioapic_disable_redirection() 2176 { 2177 int ioapic_ix; 2178 int intin_max; 2179 int intin_ix; 2180 2181 /* Disable the I/O APIC redirection entries */ 2182 for (ioapic_ix = 0; ioapic_ix < apic_io_max; ioapic_ix++) { 2183 2184 /* Bits 23-16 define the maximum redirection entries */ 2185 intin_max = (ioapic_read(ioapic_ix, APIC_VERS_CMD) >> 16) 2186 & 0xff; 2187 2188 for (intin_ix = 0; intin_ix <= intin_max; intin_ix++) { 2189 /* 2190 * The assumption here is that this is safe, even for 2191 * systems with IOAPICs that suffer from the hardware 2192 * erratum because all devices have been quiesced before 2193 * this function is called from apic_shutdown() 2194 * (or equivalent). If that assumption turns out to be 2195 * false, this mask operation can induce the same 2196 * erratum result we're trying to avoid. 2197 */ 2198 ioapic_write(ioapic_ix, APIC_RDT_CMD + 2 * intin_ix, 2199 AV_MASK); 2200 } 2201 } 2202 } 2203 2204 /* 2205 * Looks for an IOAPIC with the specified physical address in the /ioapics 2206 * node in the device tree (created by the PCI enumerator). 2207 */ 2208 static boolean_t 2209 apic_is_ioapic_AMD_813x(uint32_t physaddr) 2210 { 2211 /* 2212 * Look in /ioapics, for the ioapic with 2213 * the physical address given 2214 */ 2215 dev_info_t *ioapicsnode = ddi_find_devinfo(IOAPICS_NODE_NAME, -1, 0); 2216 dev_info_t *ioapic_child; 2217 boolean_t rv = B_FALSE; 2218 int vid, did; 2219 uint64_t ioapic_paddr; 2220 boolean_t done = B_FALSE; 2221 2222 if (ioapicsnode == NULL) 2223 return (B_FALSE); 2224 2225 /* Load first child: */ 2226 ioapic_child = ddi_get_child(ioapicsnode); 2227 while (!done && ioapic_child != 0) { /* Iterate over children */ 2228 2229 if ((ioapic_paddr = (uint64_t)ddi_prop_get_int64(DDI_DEV_T_ANY, 2230 ioapic_child, DDI_PROP_DONTPASS, "reg", 0)) 2231 != 0 && physaddr == ioapic_paddr) { 2232 2233 vid = ddi_prop_get_int(DDI_DEV_T_ANY, ioapic_child, 2234 DDI_PROP_DONTPASS, IOAPICS_PROP_VENID, 0); 2235 2236 if (vid == VENID_AMD) { 2237 2238 did = ddi_prop_get_int(DDI_DEV_T_ANY, 2239 ioapic_child, DDI_PROP_DONTPASS, 2240 IOAPICS_PROP_DEVID, 0); 2241 2242 if (did == DEVID_8131_IOAPIC || 2243 did == DEVID_8132_IOAPIC) { 2244 rv = B_TRUE; 2245 done = B_TRUE; 2246 } 2247 } 2248 } 2249 2250 if (!done) 2251 ioapic_child = ddi_get_next_sibling(ioapic_child); 2252 } 2253 2254 /* The ioapics node was held by ddi_find_devinfo, so release it */ 2255 ndi_rele_devi(ioapicsnode); 2256 return (rv); 2257 } 2258 2259 struct apic_state { 2260 int32_t as_task_reg; 2261 int32_t as_dest_reg; 2262 int32_t as_format_reg; 2263 int32_t as_local_timer; 2264 int32_t as_pcint_vect; 2265 int32_t as_int_vect0; 2266 int32_t as_int_vect1; 2267 int32_t as_err_vect; 2268 int32_t as_init_count; 2269 int32_t as_divide_reg; 2270 int32_t as_spur_int_reg; 2271 uint32_t as_ioapic_ids[MAX_IO_APIC]; 2272 }; 2273 2274 2275 static int 2276 apic_acpi_enter_apicmode(void) 2277 { 2278 ACPI_OBJECT_LIST arglist; 2279 ACPI_OBJECT arg; 2280 ACPI_STATUS status; 2281 2282 /* Setup parameter object */ 2283 arglist.Count = 1; 2284 arglist.Pointer = &arg; 2285 arg.Type = ACPI_TYPE_INTEGER; 2286 arg.Integer.Value = ACPI_APIC_MODE; 2287 2288 status = AcpiEvaluateObject(NULL, "\\_PIC", &arglist, NULL); 2289 /* 2290 * Per ACPI spec - section 5.8.1 _PIC Method 2291 * calling the \_PIC control method is optional for the OS 2292 * and might not be found. It's ok to not fail in such cases. 2293 * This is the case on linux KVM and qemu (status AE_NOT_FOUND) 2294 */ 2295 if (ACPI_FAILURE(status) && (status != AE_NOT_FOUND)) { 2296 cmn_err(CE_NOTE, 2297 "!apic: Reporting APIC mode failed (via _PIC), err: 0x%x", 2298 ACPI_FAILURE(status)); 2299 return (PSM_FAILURE); 2300 } else { 2301 return (PSM_SUCCESS); 2302 } 2303 } 2304 2305 2306 static void 2307 apic_save_state(struct apic_state *sp) 2308 { 2309 int i, cpuid; 2310 ulong_t iflag; 2311 2312 PMD(PMD_SX, ("apic_save_state %p\n", (void *)sp)) 2313 /* 2314 * First the local APIC. 2315 */ 2316 sp->as_task_reg = apic_reg_ops->apic_get_pri(); 2317 sp->as_dest_reg = apic_reg_ops->apic_read(APIC_DEST_REG); 2318 if (apic_mode == LOCAL_APIC) 2319 sp->as_format_reg = apic_reg_ops->apic_read(APIC_FORMAT_REG); 2320 sp->as_local_timer = apic_reg_ops->apic_read(APIC_LOCAL_TIMER); 2321 sp->as_pcint_vect = apic_reg_ops->apic_read(APIC_PCINT_VECT); 2322 sp->as_int_vect0 = apic_reg_ops->apic_read(APIC_INT_VECT0); 2323 sp->as_int_vect1 = apic_reg_ops->apic_read(APIC_INT_VECT1); 2324 sp->as_err_vect = apic_reg_ops->apic_read(APIC_ERR_VECT); 2325 sp->as_init_count = apic_reg_ops->apic_read(APIC_INIT_COUNT); 2326 sp->as_divide_reg = apic_reg_ops->apic_read(APIC_DIVIDE_REG); 2327 sp->as_spur_int_reg = apic_reg_ops->apic_read(APIC_SPUR_INT_REG); 2328 2329 /* 2330 * If on the boot processor then save the IOAPICs' IDs 2331 */ 2332 if ((cpuid = psm_get_cpu_id()) == 0) { 2333 2334 iflag = intr_clear(); 2335 lock_set(&apic_ioapic_lock); 2336 2337 for (i = 0; i < apic_io_max; i++) 2338 sp->as_ioapic_ids[i] = ioapic_read(i, APIC_ID_CMD); 2339 2340 lock_clear(&apic_ioapic_lock); 2341 intr_restore(iflag); 2342 } 2343 2344 /* apic_state() is currently invoked only in Suspend/Resume */ 2345 apic_cpus[cpuid].aci_status |= APIC_CPU_SUSPEND; 2346 } 2347 2348 static void 2349 apic_restore_state(struct apic_state *sp) 2350 { 2351 int i; 2352 ulong_t iflag; 2353 2354 /* 2355 * First the local APIC. 2356 */ 2357 apic_reg_ops->apic_write_task_reg(sp->as_task_reg); 2358 if (apic_mode == LOCAL_APIC) { 2359 apic_reg_ops->apic_write(APIC_DEST_REG, sp->as_dest_reg); 2360 apic_reg_ops->apic_write(APIC_FORMAT_REG, sp->as_format_reg); 2361 } 2362 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, sp->as_local_timer); 2363 apic_reg_ops->apic_write(APIC_PCINT_VECT, sp->as_pcint_vect); 2364 apic_reg_ops->apic_write(APIC_INT_VECT0, sp->as_int_vect0); 2365 apic_reg_ops->apic_write(APIC_INT_VECT1, sp->as_int_vect1); 2366 apic_reg_ops->apic_write(APIC_ERR_VECT, sp->as_err_vect); 2367 apic_reg_ops->apic_write(APIC_INIT_COUNT, sp->as_init_count); 2368 apic_reg_ops->apic_write(APIC_DIVIDE_REG, sp->as_divide_reg); 2369 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, sp->as_spur_int_reg); 2370 2371 /* 2372 * the following only needs to be done once, so we do it on the 2373 * boot processor, since we know that we only have one of those 2374 */ 2375 if (psm_get_cpu_id() == 0) { 2376 2377 iflag = intr_clear(); 2378 lock_set(&apic_ioapic_lock); 2379 2380 /* Restore IOAPICs' APIC IDs */ 2381 for (i = 0; i < apic_io_max; i++) { 2382 ioapic_write(i, APIC_ID_CMD, sp->as_ioapic_ids[i]); 2383 } 2384 2385 lock_clear(&apic_ioapic_lock); 2386 intr_restore(iflag); 2387 2388 /* 2389 * Reenter APIC mode before restoring LNK devices 2390 */ 2391 (void) apic_acpi_enter_apicmode(); 2392 2393 /* 2394 * restore acpi link device mappings 2395 */ 2396 acpi_restore_link_devices(); 2397 } 2398 } 2399 2400 /* 2401 * Returns 0 on success 2402 */ 2403 int 2404 apic_state(psm_state_request_t *rp) 2405 { 2406 PMD(PMD_SX, ("apic_state ")) 2407 switch (rp->psr_cmd) { 2408 case PSM_STATE_ALLOC: 2409 rp->req.psm_state_req.psr_state = 2410 kmem_zalloc(sizeof (struct apic_state), KM_NOSLEEP); 2411 if (rp->req.psm_state_req.psr_state == NULL) 2412 return (ENOMEM); 2413 rp->req.psm_state_req.psr_state_size = 2414 sizeof (struct apic_state); 2415 PMD(PMD_SX, (":STATE_ALLOC: state %p, size %lx\n", 2416 rp->req.psm_state_req.psr_state, 2417 rp->req.psm_state_req.psr_state_size)) 2418 return (0); 2419 2420 case PSM_STATE_FREE: 2421 kmem_free(rp->req.psm_state_req.psr_state, 2422 rp->req.psm_state_req.psr_state_size); 2423 PMD(PMD_SX, (" STATE_FREE: state %p, size %lx\n", 2424 rp->req.psm_state_req.psr_state, 2425 rp->req.psm_state_req.psr_state_size)) 2426 return (0); 2427 2428 case PSM_STATE_SAVE: 2429 PMD(PMD_SX, (" STATE_SAVE: state %p, size %lx\n", 2430 rp->req.psm_state_req.psr_state, 2431 rp->req.psm_state_req.psr_state_size)) 2432 apic_save_state(rp->req.psm_state_req.psr_state); 2433 return (0); 2434 2435 case PSM_STATE_RESTORE: 2436 apic_restore_state(rp->req.psm_state_req.psr_state); 2437 PMD(PMD_SX, (" STATE_RESTORE: state %p, size %lx\n", 2438 rp->req.psm_state_req.psr_state, 2439 rp->req.psm_state_req.psr_state_size)) 2440 return (0); 2441 2442 default: 2443 return (EINVAL); 2444 } 2445 } 2446