1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * PSMI 1.1 extensions are supported only in 2.6 and later versions. 30 * PSMI 1.2 extensions are supported only in 2.7 and later versions. 31 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10. 32 * PSMI 1.5 extensions are supported in Solaris Nevada. 33 */ 34 #define PSMI_1_5 35 36 #include <sys/processor.h> 37 #include <sys/time.h> 38 #include <sys/psm.h> 39 #include <sys/smp_impldefs.h> 40 #include <sys/cram.h> 41 #include <sys/acpi/acpi.h> 42 #include <sys/acpica.h> 43 #include <sys/psm_common.h> 44 #include <sys/apic.h> 45 #include <sys/pit.h> 46 #include <sys/ddi.h> 47 #include <sys/sunddi.h> 48 #include <sys/ddi_impldefs.h> 49 #include <sys/pci.h> 50 #include <sys/promif.h> 51 #include <sys/x86_archext.h> 52 #include <sys/cpc_impl.h> 53 #include <sys/uadmin.h> 54 #include <sys/panic.h> 55 #include <sys/debug.h> 56 #include <sys/archsystm.h> 57 #include <sys/trap.h> 58 #include <sys/machsystm.h> 59 #include <sys/cpuvar.h> 60 #include <sys/rm_platter.h> 61 #include <sys/privregs.h> 62 #include <sys/cyclic.h> 63 #include <sys/note.h> 64 #include <sys/pci_intr_lib.h> 65 #include <sys/sunndi.h> 66 67 68 /* 69 * Local Function Prototypes 70 */ 71 static int apic_handle_defconf(); 72 static int apic_parse_mpct(caddr_t mpct, int bypass); 73 static struct apic_mpfps_hdr *apic_find_fps_sig(caddr_t fptr, int size); 74 static int apic_checksum(caddr_t bptr, int len); 75 static int apic_find_bus_type(char *bus); 76 static int apic_find_bus(int busid); 77 static int apic_find_bus_id(int bustype); 78 static struct apic_io_intr *apic_find_io_intr(int irqno); 79 static int apic_find_free_irq(int start, int end); 80 static void apic_mark_vector(uchar_t oldvector, uchar_t newvector); 81 static void apic_xlate_vector_free_timeout_handler(void *arg); 82 static int apic_check_stuck_interrupt(apic_irq_t *irq_ptr, int old_bind_cpu, 83 int new_bind_cpu, int apicindex, int intin_no, int which_irq, 84 struct ioapic_reprogram_data *drep); 85 static void apic_record_rdt_entry(apic_irq_t *irqptr, int irq); 86 static struct apic_io_intr *apic_find_io_intr_w_busid(int irqno, int busid); 87 static int apic_find_intin(uchar_t ioapic, uchar_t intin); 88 static int apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, 89 int child_ipin, struct apic_io_intr **intrp); 90 static int apic_setup_irq_table(dev_info_t *dip, int irqno, 91 struct apic_io_intr *intrp, struct intrspec *ispec, iflag_t *intr_flagp, 92 int type); 93 static void apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp); 94 static void apic_try_deferred_reprogram(int ipl, int vect); 95 static void delete_defer_repro_ent(int which_irq); 96 static void apic_ioapic_wait_pending_clear(int ioapicindex, 97 int intin_no); 98 static boolean_t apic_is_ioapic_AMD_813x(uint32_t physaddr); 99 100 int apic_debug_mps_id = 0; /* 1 - print MPS ID strings */ 101 102 /* ACPI SCI interrupt configuration; -1 if SCI not used */ 103 int apic_sci_vect = -1; 104 iflag_t apic_sci_flags; 105 106 /* 107 * psm name pointer 108 */ 109 static char *psm_name; 110 111 /* ACPI support routines */ 112 static int acpi_probe(char *); 113 static int apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip, 114 int *pci_irqp, iflag_t *intr_flagp); 115 116 static int apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid, 117 int ipin, int *pci_irqp, iflag_t *intr_flagp); 118 static uchar_t acpi_find_ioapic(int irq); 119 static int acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2); 120 121 122 /* 123 * number of bits per byte, from <sys/param.h> 124 */ 125 #define UCHAR_MAX ((1 << NBBY) - 1) 126 127 /* Max wait time (in repetitions) for flags to clear in an RDT entry. */ 128 int apic_max_reps_clear_pending = 1000; 129 130 /* The irq # is implicit in the array index: */ 131 struct ioapic_reprogram_data apic_reprogram_info[APIC_MAX_VECTOR+1]; 132 /* 133 * APIC_MAX_VECTOR + 1 is the maximum # of IRQs as well. ioapic_reprogram_info 134 * is indexed by IRQ number, NOT by vector number. 135 */ 136 137 int apic_intr_policy = INTR_ROUND_ROBIN_WITH_AFFINITY; 138 139 int apic_next_bind_cpu = 1; /* For round robin assignment */ 140 /* start with cpu 1 */ 141 142 /* 143 * If enabled, the distribution works as follows: 144 * On every interrupt entry, the current ipl for the CPU is set in cpu_info 145 * and the irq corresponding to the ipl is also set in the aci_current array. 146 * interrupt exit and setspl (due to soft interrupts) will cause the current 147 * ipl to be be changed. This is cache friendly as these frequently used 148 * paths write into a per cpu structure. 149 * 150 * Sampling is done by checking the structures for all CPUs and incrementing 151 * the busy field of the irq (if any) executing on each CPU and the busy field 152 * of the corresponding CPU. 153 * In periodic mode this is done on every clock interrupt. 154 * In one-shot mode, this is done thru a cyclic with an interval of 155 * apic_redistribute_sample_interval (default 10 milli sec). 156 * 157 * Every apic_sample_factor_redistribution times we sample, we do computations 158 * to decide which interrupt needs to be migrated (see comments 159 * before apic_intr_redistribute(). 160 */ 161 162 /* 163 * Following 3 variables start as % and can be patched or set using an 164 * API to be defined in future. They will be scaled to 165 * sample_factor_redistribution which is in turn set to hertz+1 (in periodic 166 * mode), or 101 in one-shot mode to stagger it away from one sec processing 167 */ 168 169 int apic_int_busy_mark = 60; 170 int apic_int_free_mark = 20; 171 int apic_diff_for_redistribution = 10; 172 173 /* sampling interval for interrupt redistribution for dynamic migration */ 174 int apic_redistribute_sample_interval = NANOSEC / 100; /* 10 millisec */ 175 176 /* 177 * number of times we sample before deciding to redistribute interrupts 178 * for dynamic migration 179 */ 180 int apic_sample_factor_redistribution = 101; 181 182 /* timeout for xlate_vector, mark_vector */ 183 int apic_revector_timeout = 16 * 10000; /* 160 millisec */ 184 185 int apic_redist_cpu_skip = 0; 186 int apic_num_imbalance = 0; 187 int apic_num_rebind = 0; 188 189 int apic_nproc = 0; 190 size_t apic_cpus_size = 0; 191 int apic_defconf = 0; 192 int apic_irq_translate = 0; 193 int apic_spec_rev = 0; 194 int apic_imcrp = 0; 195 196 int apic_use_acpi = 1; /* 1 = use ACPI, 0 = don't use ACPI */ 197 int apic_use_acpi_madt_only = 0; /* 1=ONLY use MADT from ACPI */ 198 199 /* 200 * For interrupt link devices, if apic_unconditional_srs is set, an irq resource 201 * will be assigned (via _SRS). If it is not set, use the current 202 * irq setting (via _CRS), but only if that irq is in the set of possible 203 * irqs (returned by _PRS) for the device. 204 */ 205 int apic_unconditional_srs = 1; 206 207 /* 208 * For interrupt link devices, if apic_prefer_crs is set when we are 209 * assigning an IRQ resource to a device, prefer the current IRQ setting 210 * over other possible irq settings under same conditions. 211 */ 212 213 int apic_prefer_crs = 1; 214 215 uchar_t apic_io_id[MAX_IO_APIC]; 216 volatile uint32_t *apicioadr[MAX_IO_APIC]; 217 static uchar_t apic_io_ver[MAX_IO_APIC]; 218 static uchar_t apic_io_vectbase[MAX_IO_APIC]; 219 static uchar_t apic_io_vectend[MAX_IO_APIC]; 220 uchar_t apic_reserved_irqlist[MAX_ISA_IRQ + 1]; 221 uint32_t apic_physaddr[MAX_IO_APIC]; 222 223 static boolean_t ioapic_mask_workaround[MAX_IO_APIC]; 224 225 /* 226 * First available slot to be used as IRQ index into the apic_irq_table 227 * for those interrupts (like MSI/X) that don't have a physical IRQ. 228 */ 229 int apic_first_avail_irq = APIC_FIRST_FREE_IRQ; 230 231 /* 232 * apic_ioapic_lock protects the ioapics (reg select), the status, temp_bound 233 * and bound elements of cpus_info and the temp_cpu element of irq_struct 234 */ 235 lock_t apic_ioapic_lock; 236 237 /* 238 * apic_defer_reprogram_lock ensures that only one processor is handling 239 * deferred interrupt programming at *_intr_exit time. 240 */ 241 static lock_t apic_defer_reprogram_lock; 242 243 /* 244 * The current number of deferred reprogrammings outstanding 245 */ 246 uint_t apic_reprogram_outstanding = 0; 247 248 #ifdef DEBUG 249 /* 250 * Counters that keep track of deferred reprogramming stats 251 */ 252 uint_t apic_intr_deferrals = 0; 253 uint_t apic_intr_deliver_timeouts = 0; 254 uint_t apic_last_ditch_reprogram_failures = 0; 255 uint_t apic_deferred_setup_failures = 0; 256 uint_t apic_defer_repro_total_retries = 0; 257 uint_t apic_defer_repro_successes = 0; 258 uint_t apic_deferred_spurious_enters = 0; 259 #endif 260 261 static int apic_io_max = 0; /* no. of i/o apics enabled */ 262 263 static struct apic_io_intr *apic_io_intrp = 0; 264 static struct apic_bus *apic_busp; 265 266 uchar_t apic_vector_to_irq[APIC_MAX_VECTOR+1]; 267 uchar_t apic_resv_vector[MAXIPL+1]; 268 269 char apic_level_intr[APIC_MAX_VECTOR+1]; 270 271 static uint32_t eisa_level_intr_mask = 0; 272 /* At least MSB will be set if EISA bus */ 273 274 static int apic_pci_bus_total = 0; 275 static uchar_t apic_single_pci_busid = 0; 276 277 /* 278 * airq_mutex protects additions to the apic_irq_table - the first 279 * pointer and any airq_nexts off of that one. It also protects 280 * apic_max_device_irq & apic_min_device_irq. It also guarantees 281 * that share_id is unique as new ids are generated only when new 282 * irq_t structs are linked in. Once linked in the structs are never 283 * deleted. temp_cpu & mps_intr_index field indicate if it is programmed 284 * or allocated. Note that there is a slight gap between allocating in 285 * apic_introp_xlate and programming in addspl. 286 */ 287 kmutex_t airq_mutex; 288 apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1]; 289 int apic_max_device_irq = 0; 290 int apic_min_device_irq = APIC_MAX_VECTOR; 291 292 /* 293 * Following declarations are for revectoring; used when ISRs at different 294 * IPLs share an irq. 295 */ 296 static lock_t apic_revector_lock; 297 int apic_revector_pending = 0; 298 static uchar_t *apic_oldvec_to_newvec; 299 static uchar_t *apic_newvec_to_oldvec; 300 301 typedef struct prs_irq_list_ent { 302 int list_prio; 303 int32_t irq; 304 iflag_t intrflags; 305 acpi_prs_private_t prsprv; 306 struct prs_irq_list_ent *next; 307 } prs_irq_list_t; 308 309 310 /* 311 * ACPI variables 312 */ 313 /* 1 = acpi is enabled & working, 0 = acpi is not enabled or not there */ 314 int apic_enable_acpi = 0; 315 316 /* ACPI Multiple APIC Description Table ptr */ 317 static MULTIPLE_APIC_TABLE *acpi_mapic_dtp = NULL; 318 319 /* ACPI Interrupt Source Override Structure ptr */ 320 static MADT_INTERRUPT_OVERRIDE *acpi_isop = NULL; 321 static int acpi_iso_cnt = 0; 322 323 /* ACPI Non-maskable Interrupt Sources ptr */ 324 static MADT_NMI_SOURCE *acpi_nmi_sp = NULL; 325 static int acpi_nmi_scnt = 0; 326 static MADT_LOCAL_APIC_NMI *acpi_nmi_cp = NULL; 327 static int acpi_nmi_ccnt = 0; 328 329 /* 330 * The following added to identify a software poweroff method if available. 331 */ 332 333 static struct { 334 int poweroff_method; 335 char oem_id[APIC_MPS_OEM_ID_LEN + 1]; /* MAX + 1 for NULL */ 336 char prod_id[APIC_MPS_PROD_ID_LEN + 1]; /* MAX + 1 for NULL */ 337 } apic_mps_ids[] = { 338 { APIC_POWEROFF_VIA_RTC, "INTEL", "ALDER" }, /* 4300 */ 339 { APIC_POWEROFF_VIA_RTC, "NCR", "AMC" }, /* 4300 */ 340 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "A450NX" }, /* 4400? */ 341 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AD450NX" }, /* 4400 */ 342 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AC450NX" }, /* 4400R */ 343 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "S450NX" }, /* S50 */ 344 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "SC450NX" } /* S50? */ 345 }; 346 347 int apic_poweroff_method = APIC_POWEROFF_NONE; 348 349 /* 350 * Auto-configuration routines 351 */ 352 353 /* 354 * Look at MPSpec 1.4 (Intel Order # 242016-005) for details of what we do here 355 * May work with 1.1 - but not guaranteed. 356 * According to the MP Spec, the MP floating pointer structure 357 * will be searched in the order described below: 358 * 1. In the first kilobyte of Extended BIOS Data Area (EBDA) 359 * 2. Within the last kilobyte of system base memory 360 * 3. In the BIOS ROM address space between 0F0000h and 0FFFFh 361 * Once we find the right signature with proper checksum, we call 362 * either handle_defconf or parse_mpct to get all info necessary for 363 * subsequent operations. 364 */ 365 int 366 apic_probe_common(char *modname) 367 { 368 uint32_t mpct_addr, ebda_start = 0, base_mem_end; 369 caddr_t biosdatap; 370 caddr_t mpct; 371 caddr_t fptr; 372 int i, mpct_size, mapsize, retval = PSM_FAILURE; 373 ushort_t ebda_seg, base_mem_size; 374 struct apic_mpfps_hdr *fpsp; 375 struct apic_mp_cnf_hdr *hdrp; 376 int bypass_cpu_and_ioapics_in_mptables; 377 int acpi_user_options; 378 379 if (apic_forceload < 0) 380 return (retval); 381 382 /* 383 * Remember who we are 384 */ 385 psm_name = modname; 386 387 /* Allow override for MADT-only mode */ 388 acpi_user_options = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_root_node(), 0, 389 "acpi-user-options", 0); 390 apic_use_acpi_madt_only = ((acpi_user_options & ACPI_OUSER_MADT) != 0); 391 392 /* Allow apic_use_acpi to override MADT-only mode */ 393 if (!apic_use_acpi) 394 apic_use_acpi_madt_only = 0; 395 396 retval = acpi_probe(modname); 397 398 /* 399 * mapin the bios data area 40:0 400 * 40:13h - two-byte location reports the base memory size 401 * 40:0Eh - two-byte location for the exact starting address of 402 * the EBDA segment for EISA 403 */ 404 biosdatap = psm_map_phys(0x400, 0x20, PROT_READ); 405 if (!biosdatap) 406 return (retval); 407 fpsp = (struct apic_mpfps_hdr *)NULL; 408 mapsize = MPFPS_RAM_WIN_LEN; 409 /*LINTED: pointer cast may result in improper alignment */ 410 ebda_seg = *((ushort_t *)(biosdatap+0xe)); 411 /* check the 1k of EBDA */ 412 if (ebda_seg) { 413 ebda_start = ((uint32_t)ebda_seg) << 4; 414 fptr = psm_map_phys(ebda_start, MPFPS_RAM_WIN_LEN, PROT_READ); 415 if (fptr) { 416 if (!(fpsp = 417 apic_find_fps_sig(fptr, MPFPS_RAM_WIN_LEN))) 418 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN); 419 } 420 } 421 /* If not in EBDA, check the last k of system base memory */ 422 if (!fpsp) { 423 /*LINTED: pointer cast may result in improper alignment */ 424 base_mem_size = *((ushort_t *)(biosdatap + 0x13)); 425 426 if (base_mem_size > 512) 427 base_mem_end = 639 * 1024; 428 else 429 base_mem_end = 511 * 1024; 430 /* if ebda == last k of base mem, skip to check BIOS ROM */ 431 if (base_mem_end != ebda_start) { 432 433 fptr = psm_map_phys(base_mem_end, MPFPS_RAM_WIN_LEN, 434 PROT_READ); 435 436 if (fptr) { 437 if (!(fpsp = apic_find_fps_sig(fptr, 438 MPFPS_RAM_WIN_LEN))) 439 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN); 440 } 441 } 442 } 443 psm_unmap_phys(biosdatap, 0x20); 444 445 /* If still cannot find it, check the BIOS ROM space */ 446 if (!fpsp) { 447 mapsize = MPFPS_ROM_WIN_LEN; 448 fptr = psm_map_phys(MPFPS_ROM_WIN_START, 449 MPFPS_ROM_WIN_LEN, PROT_READ); 450 if (fptr) { 451 if (!(fpsp = 452 apic_find_fps_sig(fptr, MPFPS_ROM_WIN_LEN))) { 453 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 454 return (retval); 455 } 456 } 457 } 458 459 if (apic_checksum((caddr_t)fpsp, fpsp->mpfps_length * 16) != 0) { 460 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 461 return (retval); 462 } 463 464 apic_spec_rev = fpsp->mpfps_spec_rev; 465 if ((apic_spec_rev != 04) && (apic_spec_rev != 01)) { 466 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 467 return (retval); 468 } 469 470 /* check IMCR is present or not */ 471 apic_imcrp = fpsp->mpfps_featinfo2 & MPFPS_FEATINFO2_IMCRP; 472 473 /* check default configuration (dual CPUs) */ 474 if ((apic_defconf = fpsp->mpfps_featinfo1) != 0) { 475 psm_unmap_phys(fptr, mapsize); 476 return (apic_handle_defconf()); 477 } 478 479 /* MP Configuration Table */ 480 mpct_addr = (uint32_t)(fpsp->mpfps_mpct_paddr); 481 482 psm_unmap_phys(fptr, mapsize); /* unmap floating ptr struct */ 483 484 /* 485 * Map in enough memory for the MP Configuration Table Header. 486 * Use this table to read the total length of the BIOS data and 487 * map in all the info 488 */ 489 /*LINTED: pointer cast may result in improper alignment */ 490 hdrp = (struct apic_mp_cnf_hdr *)psm_map_phys(mpct_addr, 491 sizeof (struct apic_mp_cnf_hdr), PROT_READ); 492 if (!hdrp) 493 return (retval); 494 495 /* check mp configuration table signature PCMP */ 496 if (hdrp->mpcnf_sig != 0x504d4350) { 497 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr)); 498 return (retval); 499 } 500 mpct_size = (int)hdrp->mpcnf_tbl_length; 501 502 apic_set_pwroff_method_from_mpcnfhdr(hdrp); 503 504 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr)); 505 506 if ((retval == PSM_SUCCESS) && !apic_use_acpi_madt_only) { 507 /* This is an ACPI machine No need for further checks */ 508 return (retval); 509 } 510 511 /* 512 * Map in the entries for this machine, ie. Processor 513 * Entry Tables, Bus Entry Tables, etc. 514 * They are in fixed order following one another 515 */ 516 mpct = psm_map_phys(mpct_addr, mpct_size, PROT_READ); 517 if (!mpct) 518 return (retval); 519 520 if (apic_checksum(mpct, mpct_size) != 0) 521 goto apic_fail1; 522 523 524 /*LINTED: pointer cast may result in improper alignment */ 525 hdrp = (struct apic_mp_cnf_hdr *)mpct; 526 apicadr = (uint32_t *)mapin_apic((uint32_t)hdrp->mpcnf_local_apic, 527 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE); 528 if (!apicadr) 529 goto apic_fail1; 530 531 /* Parse all information in the tables */ 532 bypass_cpu_and_ioapics_in_mptables = (retval == PSM_SUCCESS); 533 if (apic_parse_mpct(mpct, bypass_cpu_and_ioapics_in_mptables) == 534 PSM_SUCCESS) 535 return (PSM_SUCCESS); 536 537 for (i = 0; i < apic_io_max; i++) 538 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN); 539 if (apic_cpus) 540 kmem_free(apic_cpus, apic_cpus_size); 541 if (apicadr) 542 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 543 apic_fail1: 544 psm_unmap_phys(mpct, mpct_size); 545 return (retval); 546 } 547 548 static void 549 apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp) 550 { 551 int i; 552 553 for (i = 0; i < (sizeof (apic_mps_ids) / sizeof (apic_mps_ids[0])); 554 i++) { 555 if ((strncmp(hdrp->mpcnf_oem_str, apic_mps_ids[i].oem_id, 556 strlen(apic_mps_ids[i].oem_id)) == 0) && 557 (strncmp(hdrp->mpcnf_prod_str, apic_mps_ids[i].prod_id, 558 strlen(apic_mps_ids[i].prod_id)) == 0)) { 559 560 apic_poweroff_method = apic_mps_ids[i].poweroff_method; 561 break; 562 } 563 } 564 565 if (apic_debug_mps_id != 0) { 566 cmn_err(CE_CONT, "%s: MPS OEM ID = '%c%c%c%c%c%c%c%c'" 567 "Product ID = '%c%c%c%c%c%c%c%c%c%c%c%c'\n", 568 psm_name, 569 hdrp->mpcnf_oem_str[0], 570 hdrp->mpcnf_oem_str[1], 571 hdrp->mpcnf_oem_str[2], 572 hdrp->mpcnf_oem_str[3], 573 hdrp->mpcnf_oem_str[4], 574 hdrp->mpcnf_oem_str[5], 575 hdrp->mpcnf_oem_str[6], 576 hdrp->mpcnf_oem_str[7], 577 hdrp->mpcnf_prod_str[0], 578 hdrp->mpcnf_prod_str[1], 579 hdrp->mpcnf_prod_str[2], 580 hdrp->mpcnf_prod_str[3], 581 hdrp->mpcnf_prod_str[4], 582 hdrp->mpcnf_prod_str[5], 583 hdrp->mpcnf_prod_str[6], 584 hdrp->mpcnf_prod_str[7], 585 hdrp->mpcnf_prod_str[8], 586 hdrp->mpcnf_prod_str[9], 587 hdrp->mpcnf_prod_str[10], 588 hdrp->mpcnf_prod_str[11]); 589 } 590 } 591 592 static int 593 acpi_probe(char *modname) 594 { 595 int i, intmax, index, rv; 596 uint32_t id, ver; 597 int acpi_verboseflags = 0; 598 int madt_seen, madt_size; 599 APIC_HEADER *ap; 600 MADT_PROCESSOR_APIC *mpa; 601 MADT_IO_APIC *mia; 602 MADT_IO_SAPIC *misa; 603 MADT_INTERRUPT_OVERRIDE *mio; 604 MADT_NMI_SOURCE *mns; 605 MADT_INTERRUPT_SOURCE *mis; 606 MADT_LOCAL_APIC_NMI *mlan; 607 MADT_ADDRESS_OVERRIDE *mao; 608 ACPI_OBJECT_LIST arglist; 609 ACPI_OBJECT arg; 610 int sci; 611 iflag_t sci_flags; 612 volatile uint32_t *ioapic; 613 int apic_ix; 614 char local_ids[NCPU]; 615 char proc_ids[NCPU]; 616 uchar_t hid; 617 618 if (!apic_use_acpi) 619 return (PSM_FAILURE); 620 621 if (AcpiGetFirmwareTable(APIC_SIG, 1, ACPI_LOGICAL_ADDRESSING, 622 (ACPI_TABLE_HEADER **) &acpi_mapic_dtp) != AE_OK) 623 return (PSM_FAILURE); 624 625 apicadr = mapin_apic((uint32_t)acpi_mapic_dtp->LocalApicAddress, 626 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE); 627 if (!apicadr) 628 return (PSM_FAILURE); 629 630 id = apicadr[APIC_LID_REG]; 631 local_ids[0] = (uchar_t)(id >> 24); 632 apic_nproc = index = 1; 633 CPUSET_ONLY(apic_cpumask, 0); 634 apic_io_max = 0; 635 636 ap = (APIC_HEADER *) (acpi_mapic_dtp + 1); 637 madt_size = acpi_mapic_dtp->Length; 638 madt_seen = sizeof (*acpi_mapic_dtp); 639 640 while (madt_seen < madt_size) { 641 switch (ap->Type) { 642 case APIC_PROCESSOR: 643 mpa = (MADT_PROCESSOR_APIC *) ap; 644 if (mpa->ProcessorEnabled) { 645 if (mpa->LocalApicId == local_ids[0]) { 646 proc_ids[0] = mpa->ProcessorId; 647 acpica_map_cpu(0, mpa); 648 } else if (apic_nproc < NCPU) { 649 local_ids[index] = mpa->LocalApicId; 650 proc_ids[index] = mpa->ProcessorId; 651 CPUSET_ADD(apic_cpumask, index); 652 acpica_map_cpu(index, mpa); 653 index++; 654 apic_nproc++; 655 } else 656 cmn_err(CE_WARN, "%s: exceeded " 657 "maximum no. of CPUs (= %d)", 658 psm_name, NCPU); 659 } 660 break; 661 662 case APIC_IO: 663 mia = (MADT_IO_APIC *) ap; 664 if (apic_io_max < MAX_IO_APIC) { 665 apic_ix = apic_io_max; 666 apic_io_id[apic_io_max] = mia->IoApicId; 667 apic_io_vectbase[apic_io_max] = 668 mia->Interrupt; 669 apic_physaddr[apic_io_max] = 670 (uint32_t)mia->Address; 671 ioapic = apicioadr[apic_io_max] = 672 mapin_ioapic((uint32_t)mia->Address, 673 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 674 if (!ioapic) 675 goto cleanup; 676 ioapic_mask_workaround[apic_io_max] = 677 apic_is_ioapic_AMD_813x(mia->Address); 678 apic_io_max++; 679 } 680 break; 681 682 case APIC_XRUPT_OVERRIDE: 683 mio = (MADT_INTERRUPT_OVERRIDE *) ap; 684 if (acpi_isop == NULL) 685 acpi_isop = mio; 686 acpi_iso_cnt++; 687 break; 688 689 case APIC_NMI: 690 /* UNIMPLEMENTED */ 691 mns = (MADT_NMI_SOURCE *) ap; 692 if (acpi_nmi_sp == NULL) 693 acpi_nmi_sp = mns; 694 acpi_nmi_scnt++; 695 696 cmn_err(CE_NOTE, "!apic: nmi source: %d %d %d\n", 697 mns->Interrupt, mns->Polarity, 698 mns->TriggerMode); 699 break; 700 701 case APIC_LOCAL_NMI: 702 /* UNIMPLEMENTED */ 703 mlan = (MADT_LOCAL_APIC_NMI *) ap; 704 if (acpi_nmi_cp == NULL) 705 acpi_nmi_cp = mlan; 706 acpi_nmi_ccnt++; 707 708 cmn_err(CE_NOTE, "!apic: local nmi: %d %d %d %d\n", 709 mlan->ProcessorId, mlan->Polarity, 710 mlan->TriggerMode, mlan->Lint); 711 break; 712 713 case APIC_ADDRESS_OVERRIDE: 714 /* UNIMPLEMENTED */ 715 mao = (MADT_ADDRESS_OVERRIDE *) ap; 716 cmn_err(CE_NOTE, "!apic: address override: %lx\n", 717 (long)mao->Address); 718 break; 719 720 case APIC_IO_SAPIC: 721 /* UNIMPLEMENTED */ 722 misa = (MADT_IO_SAPIC *) ap; 723 724 cmn_err(CE_NOTE, "!apic: io sapic: %d %d %lx\n", 725 misa->IoSapicId, misa->InterruptBase, 726 (long)misa->Address); 727 break; 728 729 case APIC_XRUPT_SOURCE: 730 /* UNIMPLEMENTED */ 731 mis = (MADT_INTERRUPT_SOURCE *) ap; 732 733 cmn_err(CE_NOTE, 734 "!apic: irq source: %d %d %d %d %d %d %d\n", 735 mis->ProcessorId, mis->ProcessorEid, 736 mis->Interrupt, mis->Polarity, 737 mis->TriggerMode, mis->InterruptType, 738 mis->IoSapicVector); 739 break; 740 default: 741 break; 742 } 743 744 /* advance to next entry */ 745 madt_seen += ap->Length; 746 ap = (APIC_HEADER *)(((char *)ap) + ap->Length); 747 } 748 749 apic_cpus_size = apic_nproc * sizeof (*apic_cpus); 750 if ((apic_cpus = kmem_zalloc(apic_cpus_size, KM_NOSLEEP)) == NULL) 751 goto cleanup; 752 753 /* 754 * ACPI doesn't provide the local apic ver, get it directly from the 755 * local apic 756 */ 757 ver = apicadr[APIC_VERS_REG]; 758 for (i = 0; i < apic_nproc; i++) { 759 apic_cpus[i].aci_local_id = local_ids[i]; 760 apic_cpus[i].aci_local_ver = (uchar_t)(ver & 0xFF); 761 } 762 for (i = 0; i < apic_io_max; i++) { 763 apic_ix = i; 764 765 /* 766 * need to check Sitka on the following acpi problem 767 * On the Sitka, the ioapic's apic_id field isn't reporting 768 * the actual io apic id. We have reported this problem 769 * to Intel. Until they fix the problem, we will get the 770 * actual id directly from the ioapic. 771 */ 772 id = ioapic_read(apic_ix, APIC_ID_CMD); 773 hid = (uchar_t)(id >> 24); 774 775 if (hid != apic_io_id[i]) { 776 if (apic_io_id[i] == 0) 777 apic_io_id[i] = hid; 778 else { /* set ioapic id to whatever reported by ACPI */ 779 id = ((uint32_t)apic_io_id[i]) << 24; 780 ioapic_write(apic_ix, APIC_ID_CMD, id); 781 } 782 } 783 ver = ioapic_read(apic_ix, APIC_VERS_CMD); 784 apic_io_ver[i] = (uchar_t)(ver & 0xff); 785 intmax = (ver >> 16) & 0xff; 786 apic_io_vectend[i] = apic_io_vectbase[i] + intmax; 787 if (apic_first_avail_irq <= apic_io_vectend[i]) 788 apic_first_avail_irq = apic_io_vectend[i] + 1; 789 } 790 791 792 /* 793 * Process SCI configuration here 794 * An error may be returned here if 795 * acpi-user-options specifies legacy mode 796 * (no SCI, no ACPI mode) 797 */ 798 if (acpica_get_sci(&sci, &sci_flags) != AE_OK) 799 sci = -1; 800 801 /* 802 * Now call acpi_init() to generate namespaces 803 * If this fails, we don't attempt to use ACPI 804 * even if we were able to get a MADT above 805 */ 806 if (acpica_init() != AE_OK) 807 goto cleanup; 808 809 /* 810 * Call acpica_build_processor_map() now that we have 811 * ACPI namesspace access 812 */ 813 acpica_build_processor_map(); 814 815 /* 816 * Squirrel away the SCI and flags for later on 817 * in apic_picinit() when we're ready 818 */ 819 apic_sci_vect = sci; 820 apic_sci_flags = sci_flags; 821 822 if (apic_verbose & APIC_VERBOSE_IRQ_FLAG) 823 acpi_verboseflags |= PSM_VERBOSE_IRQ_FLAG; 824 825 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) 826 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_FLAG; 827 828 if (apic_verbose & APIC_VERBOSE_POWEROFF_PAUSE_FLAG) 829 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_PAUSE_FLAG; 830 831 if (acpi_psm_init(modname, acpi_verboseflags) == ACPI_PSM_FAILURE) 832 goto cleanup; 833 834 /* Enable ACPI APIC interrupt routing */ 835 arglist.Count = 1; 836 arglist.Pointer = &arg; 837 arg.Type = ACPI_TYPE_INTEGER; 838 arg.Integer.Value = ACPI_APIC_MODE; /* 1 */ 839 rv = AcpiEvaluateObject(NULL, "\\_PIC", &arglist, NULL); 840 if (rv == AE_OK) { 841 build_reserved_irqlist((uchar_t *)apic_reserved_irqlist); 842 apic_enable_acpi = 1; 843 if (apic_use_acpi_madt_only) { 844 cmn_err(CE_CONT, 845 "?Using ACPI for CPU/IOAPIC information ONLY\n"); 846 } 847 return (PSM_SUCCESS); 848 } 849 /* if setting APIC mode failed above, we fall through to cleanup */ 850 851 cleanup: 852 if (apicadr != NULL) { 853 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 854 apicadr = NULL; 855 } 856 apic_nproc = 0; 857 for (i = 0; i < apic_io_max; i++) { 858 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN); 859 apicioadr[i] = NULL; 860 } 861 apic_io_max = 0; 862 acpi_isop = NULL; 863 acpi_iso_cnt = 0; 864 acpi_nmi_sp = NULL; 865 acpi_nmi_scnt = 0; 866 acpi_nmi_cp = NULL; 867 acpi_nmi_ccnt = 0; 868 return (PSM_FAILURE); 869 } 870 871 /* 872 * Handle default configuration. Fill in reqd global variables & tables 873 * Fill all details as MP table does not give any more info 874 */ 875 static int 876 apic_handle_defconf() 877 { 878 uint_t lid; 879 880 /*LINTED: pointer cast may result in improper alignment */ 881 apicioadr[0] = mapin_ioapic(APIC_IO_ADDR, 882 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 883 /*LINTED: pointer cast may result in improper alignment */ 884 apicadr = (uint32_t *)psm_map_phys(APIC_LOCAL_ADDR, 885 APIC_LOCAL_MEMLEN, PROT_READ); 886 apic_cpus_size = 2 * sizeof (*apic_cpus); 887 apic_cpus = (apic_cpus_info_t *) 888 kmem_zalloc(apic_cpus_size, KM_NOSLEEP); 889 if ((!apicadr) || (!apicioadr[0]) || (!apic_cpus)) 890 goto apic_handle_defconf_fail; 891 CPUSET_ONLY(apic_cpumask, 0); 892 CPUSET_ADD(apic_cpumask, 1); 893 apic_nproc = 2; 894 lid = apicadr[APIC_LID_REG]; 895 apic_cpus[0].aci_local_id = (uchar_t)(lid >> APIC_ID_BIT_OFFSET); 896 /* 897 * According to the PC+MP spec 1.1, the local ids 898 * for the default configuration has to be 0 or 1 899 */ 900 if (apic_cpus[0].aci_local_id == 1) 901 apic_cpus[1].aci_local_id = 0; 902 else if (apic_cpus[0].aci_local_id == 0) 903 apic_cpus[1].aci_local_id = 1; 904 else 905 goto apic_handle_defconf_fail; 906 907 apic_io_id[0] = 2; 908 apic_io_max = 1; 909 if (apic_defconf >= 5) { 910 apic_cpus[0].aci_local_ver = APIC_INTEGRATED_VERS; 911 apic_cpus[1].aci_local_ver = APIC_INTEGRATED_VERS; 912 apic_io_ver[0] = APIC_INTEGRATED_VERS; 913 } else { 914 apic_cpus[0].aci_local_ver = 0; /* 82489 DX */ 915 apic_cpus[1].aci_local_ver = 0; 916 apic_io_ver[0] = 0; 917 } 918 if (apic_defconf == 2 || apic_defconf == 3 || apic_defconf == 6) 919 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) | 920 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1); 921 return (PSM_SUCCESS); 922 923 apic_handle_defconf_fail: 924 if (apic_cpus) 925 kmem_free(apic_cpus, apic_cpus_size); 926 if (apicadr) 927 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 928 if (apicioadr[0]) 929 mapout_ioapic((caddr_t)apicioadr[0], APIC_IO_MEMLEN); 930 return (PSM_FAILURE); 931 } 932 933 /* Parse the entries in MP configuration table and collect info that we need */ 934 static int 935 apic_parse_mpct(caddr_t mpct, int bypass_cpus_and_ioapics) 936 { 937 struct apic_procent *procp; 938 struct apic_bus *busp; 939 struct apic_io_entry *ioapicp; 940 struct apic_io_intr *intrp; 941 int apic_ix; 942 uint_t lid; 943 uint32_t id; 944 uchar_t hid; 945 946 /*LINTED: pointer cast may result in improper alignment */ 947 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr)); 948 949 /* No need to count cpu entries if we won't use them */ 950 if (!bypass_cpus_and_ioapics) { 951 952 /* Find max # of CPUS and allocate structure accordingly */ 953 apic_nproc = 0; 954 CPUSET_ZERO(apic_cpumask); 955 while (procp->proc_entry == APIC_CPU_ENTRY) { 956 if (procp->proc_cpuflags & CPUFLAGS_EN) { 957 if (apic_nproc < NCPU) 958 CPUSET_ADD(apic_cpumask, apic_nproc); 959 apic_nproc++; 960 } 961 procp++; 962 } 963 if (apic_nproc > NCPU) 964 cmn_err(CE_WARN, "%s: exceeded " 965 "maximum no. of CPUs (= %d)", psm_name, NCPU); 966 apic_cpus_size = apic_nproc * sizeof (*apic_cpus); 967 if (!apic_nproc || !(apic_cpus = (apic_cpus_info_t *) 968 kmem_zalloc(apic_cpus_size, KM_NOSLEEP))) 969 return (PSM_FAILURE); 970 } 971 972 /*LINTED: pointer cast may result in improper alignment */ 973 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr)); 974 975 /* 976 * start with index 1 as 0 needs to be filled in with Boot CPU, but 977 * if we're bypassing this information, it has already been filled 978 * in by acpi_probe(), so don't overwrite it. 979 */ 980 if (!bypass_cpus_and_ioapics) 981 apic_nproc = 1; 982 983 while (procp->proc_entry == APIC_CPU_ENTRY) { 984 /* check whether the cpu exists or not */ 985 if (!bypass_cpus_and_ioapics && 986 procp->proc_cpuflags & CPUFLAGS_EN) { 987 if (procp->proc_cpuflags & CPUFLAGS_BP) { /* Boot CPU */ 988 lid = apicadr[APIC_LID_REG]; 989 apic_cpus[0].aci_local_id = procp->proc_apicid; 990 if (apic_cpus[0].aci_local_id != 991 (uchar_t)(lid >> APIC_ID_BIT_OFFSET)) { 992 return (PSM_FAILURE); 993 } 994 apic_cpus[0].aci_local_ver = 995 procp->proc_version; 996 } else { 997 998 apic_cpus[apic_nproc].aci_local_id = 999 procp->proc_apicid; 1000 apic_cpus[apic_nproc].aci_local_ver = 1001 procp->proc_version; 1002 apic_nproc++; 1003 1004 } 1005 } 1006 procp++; 1007 } 1008 1009 /* 1010 * Save start of bus entries for later use. 1011 * Get EISA level cntrl if EISA bus is present. 1012 * Also get the CPI bus id for single CPI bus case 1013 */ 1014 apic_busp = busp = (struct apic_bus *)procp; 1015 while (busp->bus_entry == APIC_BUS_ENTRY) { 1016 lid = apic_find_bus_type((char *)&busp->bus_str1); 1017 if (lid == BUS_EISA) { 1018 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) | 1019 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1); 1020 } else if (lid == BUS_PCI) { 1021 /* 1022 * apic_single_pci_busid will be used only if 1023 * apic_pic_bus_total is equal to 1 1024 */ 1025 apic_pci_bus_total++; 1026 apic_single_pci_busid = busp->bus_id; 1027 } 1028 busp++; 1029 } 1030 1031 ioapicp = (struct apic_io_entry *)busp; 1032 1033 if (!bypass_cpus_and_ioapics) 1034 apic_io_max = 0; 1035 do { 1036 if (!bypass_cpus_and_ioapics && apic_io_max < MAX_IO_APIC) { 1037 if (ioapicp->io_flags & IOAPIC_FLAGS_EN) { 1038 apic_io_id[apic_io_max] = ioapicp->io_apicid; 1039 apic_io_ver[apic_io_max] = ioapicp->io_version; 1040 /*LINTED: pointer cast may result in improper alignment */ 1041 apicioadr[apic_io_max] = 1042 mapin_ioapic( 1043 (uint32_t)ioapicp->io_apic_addr, 1044 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 1045 1046 if (!apicioadr[apic_io_max]) 1047 return (PSM_FAILURE); 1048 1049 ioapic_mask_workaround[apic_io_max] = 1050 apic_is_ioapic_AMD_813x( 1051 ioapicp->io_apic_addr); 1052 1053 apic_ix = apic_io_max; 1054 id = ioapic_read(apic_ix, APIC_ID_CMD); 1055 hid = (uchar_t)(id >> 24); 1056 1057 if (hid != apic_io_id[apic_io_max]) { 1058 if (apic_io_id[apic_io_max] == 0) 1059 apic_io_id[apic_io_max] = hid; 1060 else { 1061 /* 1062 * set ioapic id to whatever 1063 * reported by MPS 1064 * 1065 * may not need to set index 1066 * again ??? 1067 * take it out and try 1068 */ 1069 1070 id = ((uint32_t) 1071 apic_io_id[apic_io_max]) << 1072 24; 1073 1074 ioapic_write(apic_ix, 1075 APIC_ID_CMD, id); 1076 } 1077 } 1078 apic_io_max++; 1079 } 1080 } 1081 ioapicp++; 1082 } while (ioapicp->io_entry == APIC_IO_ENTRY); 1083 1084 apic_io_intrp = (struct apic_io_intr *)ioapicp; 1085 1086 intrp = apic_io_intrp; 1087 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 1088 if ((intrp->intr_irq > APIC_MAX_ISA_IRQ) || 1089 (apic_find_bus(intrp->intr_busid) == BUS_PCI)) { 1090 apic_irq_translate = 1; 1091 break; 1092 } 1093 intrp++; 1094 } 1095 1096 return (PSM_SUCCESS); 1097 } 1098 1099 boolean_t 1100 apic_cpu_in_range(int cpu) 1101 { 1102 return ((cpu & ~IRQ_USER_BOUND) < apic_nproc); 1103 } 1104 1105 uint16_t 1106 apic_get_apic_version() 1107 { 1108 int i; 1109 uchar_t min_io_apic_ver = 0; 1110 static uint16_t version; /* Cache as value is constant */ 1111 static boolean_t found = B_FALSE; /* Accomodate zero version */ 1112 1113 if (found == B_FALSE) { 1114 found = B_TRUE; 1115 1116 /* 1117 * Don't assume all IO APICs in the system are the same. 1118 * 1119 * Set to the minimum version. 1120 */ 1121 for (i = 0; i < apic_io_max; i++) { 1122 if ((apic_io_ver[i] != 0) && 1123 ((min_io_apic_ver == 0) || 1124 (min_io_apic_ver >= apic_io_ver[i]))) 1125 min_io_apic_ver = apic_io_ver[i]; 1126 } 1127 1128 /* Assume all local APICs are of the same version. */ 1129 version = (min_io_apic_ver << 8) | apic_cpus[0].aci_local_ver; 1130 } 1131 return (version); 1132 } 1133 1134 static struct apic_mpfps_hdr * 1135 apic_find_fps_sig(caddr_t cptr, int len) 1136 { 1137 int i; 1138 1139 /* Look for the pattern "_MP_" */ 1140 for (i = 0; i < len; i += 16) { 1141 if ((*(cptr+i) == '_') && 1142 (*(cptr+i+1) == 'M') && 1143 (*(cptr+i+2) == 'P') && 1144 (*(cptr+i+3) == '_')) 1145 /*LINTED: pointer cast may result in improper alignment */ 1146 return ((struct apic_mpfps_hdr *)(cptr + i)); 1147 } 1148 return (NULL); 1149 } 1150 1151 static int 1152 apic_checksum(caddr_t bptr, int len) 1153 { 1154 int i; 1155 uchar_t cksum; 1156 1157 cksum = 0; 1158 for (i = 0; i < len; i++) 1159 cksum += *bptr++; 1160 return ((int)cksum); 1161 } 1162 1163 1164 /* 1165 * Initialise vector->ipl and ipl->pri arrays. level_intr and irqtable 1166 * are also set to NULL. vector->irq is set to a value which cannot map 1167 * to a real irq to show that it is free. 1168 */ 1169 void 1170 apic_init_common() 1171 { 1172 int i, j, indx; 1173 int *iptr; 1174 1175 /* 1176 * Initialize apic_ipls from apic_vectortoipl. This array is 1177 * used in apic_intr_enter to determine the IPL to use for the 1178 * corresponding vector. On some systems, due to hardware errata 1179 * and interrupt sharing, the IPL may not correspond to the IPL listed 1180 * in apic_vectortoipl (see apic_addspl and apic_delspl). 1181 */ 1182 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) { 1183 indx = i * APIC_VECTOR_PER_IPL; 1184 1185 for (j = 0; j < APIC_VECTOR_PER_IPL; j++, indx++) 1186 apic_ipls[indx] = apic_vectortoipl[i]; 1187 } 1188 1189 /* cpu 0 is always up (for now) */ 1190 apic_cpus[0].aci_status = APIC_CPU_ONLINE | APIC_CPU_INTR_ENABLE; 1191 1192 iptr = (int *)&apic_irq_table[0]; 1193 for (i = 0; i <= APIC_MAX_VECTOR; i++) { 1194 apic_level_intr[i] = 0; 1195 *iptr++ = NULL; 1196 apic_vector_to_irq[i] = APIC_RESV_IRQ; 1197 1198 /* These *must* be initted to B_TRUE! */ 1199 apic_reprogram_info[i].done = B_TRUE; 1200 apic_reprogram_info[i].irqp = NULL; 1201 apic_reprogram_info[i].tries = 0; 1202 apic_reprogram_info[i].bindcpu = 0; 1203 } 1204 1205 /* 1206 * Allocate a dummy irq table entry for the reserved entry. 1207 * This takes care of the race between removing an irq and 1208 * clock detecting a CPU in that irq during interrupt load 1209 * sampling. 1210 */ 1211 apic_irq_table[APIC_RESV_IRQ] = 1212 kmem_zalloc(sizeof (apic_irq_t), KM_NOSLEEP); 1213 1214 mutex_init(&airq_mutex, NULL, MUTEX_DEFAULT, NULL); 1215 } 1216 1217 void 1218 ioapic_init_intr(int mask_apic) 1219 { 1220 int apic_ix; 1221 struct intrspec ispec; 1222 apic_irq_t *irqptr; 1223 int i, j; 1224 ulong_t iflag; 1225 1226 LOCK_INIT_CLEAR(&apic_revector_lock); 1227 LOCK_INIT_CLEAR(&apic_defer_reprogram_lock); 1228 1229 /* mask interrupt vectors */ 1230 for (j = 0; j < apic_io_max && mask_apic; j++) { 1231 int intin_max; 1232 1233 apic_ix = j; 1234 /* Bits 23-16 define the maximum redirection entries */ 1235 intin_max = (ioapic_read(apic_ix, APIC_VERS_CMD) >> 16) & 0xff; 1236 for (i = 0; i < intin_max; i++) 1237 ioapic_write(apic_ix, APIC_RDT_CMD + 2 * i, AV_MASK); 1238 } 1239 1240 /* 1241 * Hack alert: deal with ACPI SCI interrupt chicken/egg here 1242 */ 1243 if (apic_sci_vect > 0) { 1244 /* 1245 * acpica has already done add_avintr(); we just 1246 * to finish the job by mimicing translate_irq() 1247 * 1248 * Fake up an intrspec and setup the tables 1249 */ 1250 ispec.intrspec_vec = apic_sci_vect; 1251 ispec.intrspec_pri = SCI_IPL; 1252 1253 if (apic_setup_irq_table(NULL, apic_sci_vect, NULL, 1254 &ispec, &apic_sci_flags, DDI_INTR_TYPE_FIXED) < 0) { 1255 cmn_err(CE_WARN, "!apic: SCI setup failed"); 1256 return; 1257 } 1258 irqptr = apic_irq_table[apic_sci_vect]; 1259 1260 iflag = intr_clear(); 1261 lock_set(&apic_ioapic_lock); 1262 1263 /* Program I/O APIC */ 1264 (void) apic_setup_io_intr(irqptr, apic_sci_vect, B_FALSE); 1265 1266 lock_clear(&apic_ioapic_lock); 1267 intr_restore(iflag); 1268 1269 irqptr->airq_share++; 1270 } 1271 } 1272 1273 /* 1274 * Add mask bits to disable interrupt vector from happening 1275 * at or above IPL. In addition, it should remove mask bits 1276 * to enable interrupt vectors below the given IPL. 1277 * 1278 * Both add and delspl are complicated by the fact that different interrupts 1279 * may share IRQs. This can happen in two ways. 1280 * 1. The same H/W line is shared by more than 1 device 1281 * 1a. with interrupts at different IPLs 1282 * 1b. with interrupts at same IPL 1283 * 2. We ran out of vectors at a given IPL and started sharing vectors. 1284 * 1b and 2 should be handled gracefully, except for the fact some ISRs 1285 * will get called often when no interrupt is pending for the device. 1286 * For 1a, we just hope that the machine blows up with the person who 1287 * set it up that way!. In the meantime, we handle it at the higher IPL. 1288 */ 1289 /*ARGSUSED*/ 1290 int 1291 apic_addspl_common(int irqno, int ipl, int min_ipl, int max_ipl) 1292 { 1293 uchar_t vector; 1294 ulong_t iflag; 1295 apic_irq_t *irqptr, *irqheadptr; 1296 int irqindex; 1297 1298 ASSERT(max_ipl <= UCHAR_MAX); 1299 irqindex = IRQINDEX(irqno); 1300 1301 if ((irqindex == -1) || (!apic_irq_table[irqindex])) 1302 return (PSM_FAILURE); 1303 1304 mutex_enter(&airq_mutex); 1305 irqptr = irqheadptr = apic_irq_table[irqindex]; 1306 1307 DDI_INTR_IMPLDBG((CE_CONT, "apic_addspl: dip=0x%p type=%d irqno=0x%x " 1308 "vector=0x%x\n", (void *)irqptr->airq_dip, 1309 irqptr->airq_mps_intr_index, irqno, irqptr->airq_vector)); 1310 1311 while (irqptr) { 1312 if (VIRTIRQ(irqindex, irqptr->airq_share_id) == irqno) 1313 break; 1314 irqptr = irqptr->airq_next; 1315 } 1316 irqptr->airq_share++; 1317 1318 mutex_exit(&airq_mutex); 1319 1320 /* return if it is not hardware interrupt */ 1321 if (irqptr->airq_mps_intr_index == RESERVE_INDEX) 1322 return (PSM_SUCCESS); 1323 1324 /* Or if there are more interupts at a higher IPL */ 1325 if (ipl != max_ipl) 1326 return (PSM_SUCCESS); 1327 1328 /* 1329 * if apic_picinit() has not been called yet, just return. 1330 * At the end of apic_picinit(), we will call setup_io_intr(). 1331 */ 1332 1333 if (!apic_picinit_called) 1334 return (PSM_SUCCESS); 1335 1336 /* 1337 * Upgrade vector if max_ipl is not earlier ipl. If we cannot allocate, 1338 * return failure. Not very elegant, but then we hope the 1339 * machine will blow up with ... 1340 */ 1341 if (irqptr->airq_ipl != max_ipl && 1342 !ioapic_mask_workaround[irqptr->airq_ioapicindex]) { 1343 1344 vector = apic_allocate_vector(max_ipl, irqindex, 1); 1345 if (vector == 0) { 1346 irqptr->airq_share--; 1347 return (PSM_FAILURE); 1348 } 1349 irqptr = irqheadptr; 1350 apic_mark_vector(irqptr->airq_vector, vector); 1351 while (irqptr) { 1352 irqptr->airq_vector = vector; 1353 irqptr->airq_ipl = (uchar_t)max_ipl; 1354 /* 1355 * reprogram irq being added and every one else 1356 * who is not in the UNINIT state 1357 */ 1358 if ((VIRTIRQ(irqindex, irqptr->airq_share_id) == 1359 irqno) || (irqptr->airq_temp_cpu != IRQ_UNINIT)) { 1360 apic_record_rdt_entry(irqptr, irqindex); 1361 1362 iflag = intr_clear(); 1363 lock_set(&apic_ioapic_lock); 1364 1365 (void) apic_setup_io_intr(irqptr, irqindex, 1366 B_FALSE); 1367 1368 lock_clear(&apic_ioapic_lock); 1369 intr_restore(iflag); 1370 } 1371 irqptr = irqptr->airq_next; 1372 } 1373 return (PSM_SUCCESS); 1374 1375 } else if (irqptr->airq_ipl != max_ipl && 1376 ioapic_mask_workaround[irqptr->airq_ioapicindex]) { 1377 /* 1378 * We cannot upgrade the vector, but we can change 1379 * the IPL that this vector induces. 1380 * 1381 * Note that we subtract APIC_BASE_VECT from the vector 1382 * here because this array is used in apic_intr_enter 1383 * (no need to add APIC_BASE_VECT in that hot code 1384 * path since we can do it in the rarely-executed path 1385 * here). 1386 */ 1387 apic_ipls[irqptr->airq_vector - APIC_BASE_VECT] = 1388 (uchar_t)max_ipl; 1389 1390 irqptr = irqheadptr; 1391 while (irqptr) { 1392 irqptr->airq_ipl = (uchar_t)max_ipl; 1393 irqptr = irqptr->airq_next; 1394 } 1395 1396 return (PSM_SUCCESS); 1397 } 1398 1399 ASSERT(irqptr); 1400 1401 iflag = intr_clear(); 1402 lock_set(&apic_ioapic_lock); 1403 1404 (void) apic_setup_io_intr(irqptr, irqindex, B_FALSE); 1405 1406 lock_clear(&apic_ioapic_lock); 1407 intr_restore(iflag); 1408 1409 return (PSM_SUCCESS); 1410 } 1411 1412 /* 1413 * Recompute mask bits for the given interrupt vector. 1414 * If there is no interrupt servicing routine for this 1415 * vector, this function should disable interrupt vector 1416 * from happening at all IPLs. If there are still 1417 * handlers using the given vector, this function should 1418 * disable the given vector from happening below the lowest 1419 * IPL of the remaining hadlers. 1420 */ 1421 /*ARGSUSED*/ 1422 int 1423 apic_delspl_common(int irqno, int ipl, int min_ipl, int max_ipl) 1424 { 1425 uchar_t vector, bind_cpu; 1426 int intin, irqindex; 1427 int apic_ix; 1428 apic_irq_t *irqptr, *irqheadptr, *irqp; 1429 ulong_t iflag; 1430 1431 mutex_enter(&airq_mutex); 1432 irqindex = IRQINDEX(irqno); 1433 irqptr = irqheadptr = apic_irq_table[irqindex]; 1434 1435 DDI_INTR_IMPLDBG((CE_CONT, "apic_delspl: dip=0x%p type=%d irqno=0x%x " 1436 "vector=0x%x\n", (void *)irqptr->airq_dip, 1437 irqptr->airq_mps_intr_index, irqno, irqptr->airq_vector)); 1438 1439 while (irqptr) { 1440 if (VIRTIRQ(irqindex, irqptr->airq_share_id) == irqno) 1441 break; 1442 irqptr = irqptr->airq_next; 1443 } 1444 ASSERT(irqptr); 1445 1446 irqptr->airq_share--; 1447 1448 mutex_exit(&airq_mutex); 1449 1450 if (ipl < max_ipl) 1451 return (PSM_SUCCESS); 1452 1453 /* return if it is not hardware interrupt */ 1454 if (irqptr->airq_mps_intr_index == RESERVE_INDEX) 1455 return (PSM_SUCCESS); 1456 1457 if (!apic_picinit_called) { 1458 /* 1459 * Clear irq_struct. If two devices shared an intpt 1460 * line & 1 unloaded before picinit, we are hosed. But, then 1461 * we hope the machine will ... 1462 */ 1463 irqptr->airq_mps_intr_index = FREE_INDEX; 1464 irqptr->airq_temp_cpu = IRQ_UNINIT; 1465 apic_free_vector(irqptr->airq_vector); 1466 return (PSM_SUCCESS); 1467 } 1468 /* 1469 * Downgrade vector to new max_ipl if needed.If we cannot allocate, 1470 * use old IPL. Not very elegant, but then we hope ... 1471 */ 1472 if ((irqptr->airq_ipl != max_ipl) && (max_ipl != PSM_INVALID_IPL) && 1473 !ioapic_mask_workaround[irqptr->airq_ioapicindex]) { 1474 apic_irq_t *irqp; 1475 if (vector = apic_allocate_vector(max_ipl, irqno, 1)) { 1476 apic_mark_vector(irqheadptr->airq_vector, vector); 1477 irqp = irqheadptr; 1478 while (irqp) { 1479 irqp->airq_vector = vector; 1480 irqp->airq_ipl = (uchar_t)max_ipl; 1481 if (irqp->airq_temp_cpu != IRQ_UNINIT) { 1482 apic_record_rdt_entry(irqp, irqindex); 1483 1484 iflag = intr_clear(); 1485 lock_set(&apic_ioapic_lock); 1486 1487 (void) apic_setup_io_intr(irqp, 1488 irqindex, B_FALSE); 1489 1490 lock_clear(&apic_ioapic_lock); 1491 intr_restore(iflag); 1492 } 1493 irqp = irqp->airq_next; 1494 } 1495 } 1496 1497 } else if (irqptr->airq_ipl != max_ipl && 1498 max_ipl != PSM_INVALID_IPL && 1499 ioapic_mask_workaround[irqptr->airq_ioapicindex]) { 1500 1501 /* 1502 * We cannot downgrade the IPL of the vector below the vector's 1503 * hardware priority. If we did, it would be possible for a 1504 * higher-priority hardware vector to interrupt a CPU running at an IPL 1505 * lower than the hardware priority of the interrupting vector (but 1506 * higher than the soft IPL of this IRQ). When this happens, we would 1507 * then try to drop the IPL BELOW what it was (effectively dropping 1508 * below base_spl) which would be potentially catastrophic. 1509 * 1510 * (e.g. Suppose the hardware vector associated with this IRQ is 0x40 1511 * (hardware IPL of 4). Further assume that the old IPL of this IRQ 1512 * was 4, but the new IPL is 1. If we forced vector 0x40 to result in 1513 * an IPL of 1, it would be possible for the processor to be executing 1514 * at IPL 3 and for an interrupt to come in on vector 0x40, interrupting 1515 * the currently-executing ISR. When apic_intr_enter consults 1516 * apic_irqs[], it will return 1, bringing the IPL of the CPU down to 1 1517 * so even though the processor was running at IPL 4, an IPL 1 1518 * interrupt will have interrupted it, which must not happen)). 1519 * 1520 * Effectively, this means that the hardware priority corresponding to 1521 * the IRQ's IPL (in apic_ipls[]) cannot be lower than the vector's 1522 * hardware priority. 1523 * 1524 * (In the above example, then, after removal of the IPL 4 device's 1525 * interrupt handler, the new IPL will continue to be 4 because the 1526 * hardware priority that IPL 1 implies is lower than the hardware 1527 * priority of the vector used.) 1528 */ 1529 /* apic_ipls is indexed by vector, starting at APIC_BASE_VECT */ 1530 const int apic_ipls_index = irqptr->airq_vector - 1531 APIC_BASE_VECT; 1532 const int vect_inherent_hwpri = irqptr->airq_vector >> 1533 APIC_IPL_SHIFT; 1534 1535 /* 1536 * If there are still devices using this IRQ, determine the 1537 * new ipl to use. 1538 */ 1539 if (irqptr->airq_share) { 1540 int vect_desired_hwpri, hwpri; 1541 1542 ASSERT(max_ipl < MAXIPL); 1543 vect_desired_hwpri = apic_ipltopri[max_ipl] >> 1544 APIC_IPL_SHIFT; 1545 1546 /* 1547 * If the desired IPL's hardware priority is lower 1548 * than that of the vector, use the hardware priority 1549 * of the vector to determine the new IPL. 1550 */ 1551 hwpri = (vect_desired_hwpri < vect_inherent_hwpri) ? 1552 vect_inherent_hwpri : vect_desired_hwpri; 1553 1554 /* 1555 * Now, to get the right index for apic_vectortoipl, 1556 * we need to subtract APIC_BASE_VECT from the 1557 * hardware-vector-equivalent (in hwpri). Since hwpri 1558 * is already shifted, we shift APIC_BASE_VECT before 1559 * doing the subtraction. 1560 */ 1561 hwpri -= (APIC_BASE_VECT >> APIC_IPL_SHIFT); 1562 1563 ASSERT(hwpri >= 0); 1564 ASSERT(hwpri < MAXIPL); 1565 max_ipl = apic_vectortoipl[hwpri]; 1566 apic_ipls[apic_ipls_index] = max_ipl; 1567 1568 irqp = irqheadptr; 1569 while (irqp) { 1570 irqp->airq_ipl = (uchar_t)max_ipl; 1571 irqp = irqp->airq_next; 1572 } 1573 } else { 1574 /* 1575 * No more devices on this IRQ, so reset this vector's 1576 * element in apic_ipls to the original IPL for this 1577 * vector 1578 */ 1579 apic_ipls[apic_ipls_index] = 1580 apic_vectortoipl[vect_inherent_hwpri]; 1581 } 1582 } 1583 1584 if (irqptr->airq_share) 1585 return (PSM_SUCCESS); 1586 1587 iflag = intr_clear(); 1588 lock_set(&apic_ioapic_lock); 1589 1590 if (irqptr->airq_mps_intr_index == MSI_INDEX) { 1591 /* 1592 * Disable the MSI vector 1593 * Make sure we only disable on the last 1594 * of the multi-MSI support 1595 */ 1596 if (i_ddi_intr_get_current_nintrs(irqptr->airq_dip) == 1) { 1597 apic_pci_msi_unconfigure(irqptr->airq_dip, 1598 DDI_INTR_TYPE_MSI, irqptr->airq_ioapicindex); 1599 1600 apic_pci_msi_disable_mode(irqptr->airq_dip, 1601 DDI_INTR_TYPE_MSI); 1602 } 1603 } else if (irqptr->airq_mps_intr_index == MSIX_INDEX) { 1604 /* 1605 * Disable the MSI-X vector 1606 * needs to clear its mask and addr/data for each MSI-X 1607 */ 1608 apic_pci_msi_unconfigure(irqptr->airq_dip, DDI_INTR_TYPE_MSIX, 1609 irqptr->airq_origirq); 1610 /* 1611 * Make sure we only disable on the last MSI-X 1612 */ 1613 if (i_ddi_intr_get_current_nintrs(irqptr->airq_dip) == 1) { 1614 apic_pci_msi_disable_mode(irqptr->airq_dip, 1615 DDI_INTR_TYPE_MSIX); 1616 } 1617 } else { 1618 /* 1619 * The assumption here is that this is safe, even for 1620 * systems with IOAPICs that suffer from the hardware 1621 * erratum because all devices have been quiesced before 1622 * they unregister their interrupt handlers. If that 1623 * assumption turns out to be false, this mask operation 1624 * can induce the same erratum result we're trying to 1625 * avoid. 1626 */ 1627 apic_ix = irqptr->airq_ioapicindex; 1628 intin = irqptr->airq_intin_no; 1629 ioapic_write(apic_ix, APIC_RDT_CMD + 2 * intin, AV_MASK); 1630 } 1631 1632 if (max_ipl == PSM_INVALID_IPL) { 1633 ASSERT(irqheadptr == irqptr); 1634 bind_cpu = irqptr->airq_temp_cpu; 1635 if (((uchar_t)bind_cpu != IRQ_UNBOUND) && 1636 ((uchar_t)bind_cpu != IRQ_UNINIT)) { 1637 ASSERT((bind_cpu & ~IRQ_USER_BOUND) < apic_nproc); 1638 if (bind_cpu & IRQ_USER_BOUND) { 1639 /* If hardbound, temp_cpu == cpu */ 1640 bind_cpu &= ~IRQ_USER_BOUND; 1641 apic_cpus[bind_cpu].aci_bound--; 1642 } else 1643 apic_cpus[bind_cpu].aci_temp_bound--; 1644 } 1645 irqptr->airq_temp_cpu = IRQ_UNINIT; 1646 irqptr->airq_mps_intr_index = FREE_INDEX; 1647 lock_clear(&apic_ioapic_lock); 1648 intr_restore(iflag); 1649 apic_free_vector(irqptr->airq_vector); 1650 return (PSM_SUCCESS); 1651 } 1652 lock_clear(&apic_ioapic_lock); 1653 intr_restore(iflag); 1654 1655 mutex_enter(&airq_mutex); 1656 if ((irqptr == apic_irq_table[irqindex])) { 1657 apic_irq_t *oldirqptr; 1658 /* Move valid irq entry to the head */ 1659 irqheadptr = oldirqptr = irqptr; 1660 irqptr = irqptr->airq_next; 1661 ASSERT(irqptr); 1662 while (irqptr) { 1663 if (irqptr->airq_mps_intr_index != FREE_INDEX) 1664 break; 1665 oldirqptr = irqptr; 1666 irqptr = irqptr->airq_next; 1667 } 1668 /* remove all invalid ones from the beginning */ 1669 apic_irq_table[irqindex] = irqptr; 1670 /* 1671 * and link them back after the head. The invalid ones 1672 * begin with irqheadptr and end at oldirqptr 1673 */ 1674 oldirqptr->airq_next = irqptr->airq_next; 1675 irqptr->airq_next = irqheadptr; 1676 } 1677 mutex_exit(&airq_mutex); 1678 1679 irqptr->airq_temp_cpu = IRQ_UNINIT; 1680 irqptr->airq_mps_intr_index = FREE_INDEX; 1681 1682 return (PSM_SUCCESS); 1683 } 1684 1685 /* 1686 * apic_introp_xlate() replaces apic_translate_irq() and is 1687 * called only from apic_intr_ops(). With the new ADII framework, 1688 * the priority can no longer be retrieved through i_ddi_get_intrspec(). 1689 * It has to be passed in from the caller. 1690 */ 1691 int 1692 apic_introp_xlate(dev_info_t *dip, struct intrspec *ispec, int type) 1693 { 1694 char dev_type[16]; 1695 int dev_len, pci_irq, newirq, bustype, devid, busid, i; 1696 int irqno = ispec->intrspec_vec; 1697 ddi_acc_handle_t cfg_handle; 1698 uchar_t ipin; 1699 struct apic_io_intr *intrp; 1700 iflag_t intr_flag; 1701 APIC_HEADER *hp; 1702 MADT_INTERRUPT_OVERRIDE *isop; 1703 apic_irq_t *airqp; 1704 int parent_is_pci_or_pciex = 0; 1705 int child_is_pciex = 0; 1706 1707 DDI_INTR_IMPLDBG((CE_CONT, "apic_introp_xlate: dip=0x%p name=%s " 1708 "type=%d irqno=0x%x\n", (void *)dip, ddi_get_name(dip), type, 1709 irqno)); 1710 1711 dev_len = sizeof (dev_type); 1712 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, ddi_get_parent(dip), 1713 DDI_PROP_DONTPASS, "device_type", (caddr_t)dev_type, 1714 &dev_len) == DDI_PROP_SUCCESS) { 1715 if ((strcmp(dev_type, "pci") == 0) || 1716 (strcmp(dev_type, "pciex") == 0)) 1717 parent_is_pci_or_pciex = 1; 1718 } 1719 1720 if (parent_is_pci_or_pciex && ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1721 DDI_PROP_DONTPASS, "pcie-capid-pointer", PCI_CAP_NEXT_PTR_NULL) != 1722 PCI_CAP_NEXT_PTR_NULL) { 1723 child_is_pciex = 1; 1724 } 1725 1726 if (DDI_INTR_IS_MSI_OR_MSIX(type)) { 1727 if ((airqp = apic_find_irq(dip, ispec, type)) != NULL) { 1728 airqp->airq_iflag.bustype = 1729 child_is_pciex ? BUS_PCIE : BUS_PCI; 1730 return (apic_vector_to_irq[airqp->airq_vector]); 1731 } 1732 return (apic_setup_irq_table(dip, irqno, NULL, ispec, 1733 NULL, type)); 1734 } 1735 1736 bustype = 0; 1737 1738 /* check if we have already translated this irq */ 1739 mutex_enter(&airq_mutex); 1740 newirq = apic_min_device_irq; 1741 for (; newirq <= apic_max_device_irq; newirq++) { 1742 airqp = apic_irq_table[newirq]; 1743 while (airqp) { 1744 if ((airqp->airq_dip == dip) && 1745 (airqp->airq_origirq == irqno) && 1746 (airqp->airq_mps_intr_index != FREE_INDEX)) { 1747 1748 mutex_exit(&airq_mutex); 1749 return (VIRTIRQ(newirq, airqp->airq_share_id)); 1750 } 1751 airqp = airqp->airq_next; 1752 } 1753 } 1754 mutex_exit(&airq_mutex); 1755 1756 if (apic_defconf) 1757 goto defconf; 1758 1759 if ((dip == NULL) || (!apic_irq_translate && !apic_enable_acpi)) 1760 goto nonpci; 1761 1762 if (parent_is_pci_or_pciex) { 1763 /* pci device */ 1764 if (acpica_get_bdf(dip, &busid, &devid, NULL) != 0) 1765 goto nonpci; 1766 if (busid == 0 && apic_pci_bus_total == 1) 1767 busid = (int)apic_single_pci_busid; 1768 1769 if (pci_config_setup(dip, &cfg_handle) != DDI_SUCCESS) 1770 goto nonpci; 1771 ipin = pci_config_get8(cfg_handle, PCI_CONF_IPIN) - PCI_INTA; 1772 pci_config_teardown(&cfg_handle); 1773 if (apic_enable_acpi && !apic_use_acpi_madt_only) { 1774 if (apic_acpi_translate_pci_irq(dip, busid, devid, 1775 ipin, &pci_irq, &intr_flag) != ACPI_PSM_SUCCESS) 1776 goto nonpci; 1777 1778 intr_flag.bustype = child_is_pciex ? BUS_PCIE : BUS_PCI; 1779 if ((newirq = apic_setup_irq_table(dip, pci_irq, NULL, 1780 ispec, &intr_flag, type)) == -1) 1781 goto nonpci; 1782 return (newirq); 1783 } else { 1784 pci_irq = ((devid & 0x1f) << 2) | (ipin & 0x3); 1785 if ((intrp = apic_find_io_intr_w_busid(pci_irq, busid)) 1786 == NULL) { 1787 if ((pci_irq = apic_handle_pci_pci_bridge(dip, 1788 devid, ipin, &intrp)) == -1) 1789 goto nonpci; 1790 } 1791 if ((newirq = apic_setup_irq_table(dip, pci_irq, intrp, 1792 ispec, NULL, type)) == -1) 1793 goto nonpci; 1794 return (newirq); 1795 } 1796 } else if (strcmp(dev_type, "isa") == 0) 1797 bustype = BUS_ISA; 1798 else if (strcmp(dev_type, "eisa") == 0) 1799 bustype = BUS_EISA; 1800 1801 nonpci: 1802 if (apic_enable_acpi && !apic_use_acpi_madt_only) { 1803 /* search iso entries first */ 1804 if (acpi_iso_cnt != 0) { 1805 hp = (APIC_HEADER *)acpi_isop; 1806 i = 0; 1807 while (i < acpi_iso_cnt) { 1808 if (hp->Type == APIC_XRUPT_OVERRIDE) { 1809 isop = (MADT_INTERRUPT_OVERRIDE *)hp; 1810 if (isop->Bus == 0 && 1811 isop->Source == irqno) { 1812 newirq = isop->Interrupt; 1813 intr_flag.intr_po = 1814 isop->Polarity; 1815 intr_flag.intr_el = 1816 isop->TriggerMode; 1817 intr_flag.bustype = BUS_ISA; 1818 1819 return (apic_setup_irq_table( 1820 dip, newirq, NULL, ispec, 1821 &intr_flag, type)); 1822 1823 } 1824 i++; 1825 } 1826 hp = (APIC_HEADER *)(((char *)hp) + 1827 hp->Length); 1828 } 1829 } 1830 intr_flag.intr_po = INTR_PO_ACTIVE_HIGH; 1831 intr_flag.intr_el = INTR_EL_EDGE; 1832 intr_flag.bustype = BUS_ISA; 1833 return (apic_setup_irq_table(dip, irqno, NULL, ispec, 1834 &intr_flag, type)); 1835 } else { 1836 if (bustype == 0) 1837 bustype = eisa_level_intr_mask ? BUS_EISA : BUS_ISA; 1838 for (i = 0; i < 2; i++) { 1839 if (((busid = apic_find_bus_id(bustype)) != -1) && 1840 ((intrp = apic_find_io_intr_w_busid(irqno, busid)) 1841 != NULL)) { 1842 if ((newirq = apic_setup_irq_table(dip, irqno, 1843 intrp, ispec, NULL, type)) != -1) { 1844 return (newirq); 1845 } 1846 goto defconf; 1847 } 1848 bustype = (bustype == BUS_EISA) ? BUS_ISA : BUS_EISA; 1849 } 1850 } 1851 1852 /* MPS default configuration */ 1853 defconf: 1854 newirq = apic_setup_irq_table(dip, irqno, NULL, ispec, NULL, type); 1855 if (newirq == -1) 1856 return (newirq); 1857 ASSERT(IRQINDEX(newirq) == irqno); 1858 ASSERT(apic_irq_table[irqno]); 1859 return (newirq); 1860 } 1861 1862 1863 1864 1865 1866 1867 /* 1868 * On machines with PCI-PCI bridges, a device behind a PCI-PCI bridge 1869 * needs special handling. We may need to chase up the device tree, 1870 * using the PCI-PCI Bridge specification's "rotating IPIN assumptions", 1871 * to find the IPIN at the root bus that relates to the IPIN on the 1872 * subsidiary bus (for ACPI or MP). We may, however, have an entry 1873 * in the MP table or the ACPI namespace for this device itself. 1874 * We handle both cases in the search below. 1875 */ 1876 /* this is the non-acpi version */ 1877 static int 1878 apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, int child_ipin, 1879 struct apic_io_intr **intrp) 1880 { 1881 dev_info_t *dipp, *dip; 1882 int pci_irq; 1883 ddi_acc_handle_t cfg_handle; 1884 int bridge_devno, bridge_bus; 1885 int ipin; 1886 1887 dip = idip; 1888 1889 /*CONSTCOND*/ 1890 while (1) { 1891 if (((dipp = ddi_get_parent(dip)) == (dev_info_t *)NULL) || 1892 (pci_config_setup(dipp, &cfg_handle) != DDI_SUCCESS)) 1893 return (-1); 1894 if ((pci_config_get8(cfg_handle, PCI_CONF_BASCLASS) == 1895 PCI_CLASS_BRIDGE) && (pci_config_get8(cfg_handle, 1896 PCI_CONF_SUBCLASS) == PCI_BRIDGE_PCI)) { 1897 pci_config_teardown(&cfg_handle); 1898 if (acpica_get_bdf(dipp, &bridge_bus, &bridge_devno, 1899 NULL) != 0) 1900 return (-1); 1901 /* 1902 * This is the rotating scheme documented in the 1903 * PCI-to-PCI spec. If the PCI-to-PCI bridge is 1904 * behind another PCI-to-PCI bridge, then it needs 1905 * to keep ascending until an interrupt entry is 1906 * found or the root is reached. 1907 */ 1908 ipin = (child_devno + child_ipin) % PCI_INTD; 1909 if (bridge_bus == 0 && apic_pci_bus_total == 1) 1910 bridge_bus = (int)apic_single_pci_busid; 1911 pci_irq = ((bridge_devno & 0x1f) << 2) | 1912 (ipin & 0x3); 1913 if ((*intrp = apic_find_io_intr_w_busid(pci_irq, 1914 bridge_bus)) != NULL) { 1915 return (pci_irq); 1916 } 1917 dip = dipp; 1918 child_devno = bridge_devno; 1919 child_ipin = ipin; 1920 } else { 1921 pci_config_teardown(&cfg_handle); 1922 return (-1); 1923 } 1924 } 1925 /*LINTED: function will not fall off the bottom */ 1926 } 1927 1928 1929 1930 1931 static uchar_t 1932 acpi_find_ioapic(int irq) 1933 { 1934 int i; 1935 1936 for (i = 0; i < apic_io_max; i++) { 1937 if (irq >= apic_io_vectbase[i] && irq <= apic_io_vectend[i]) 1938 return (i); 1939 } 1940 return (0xFF); /* shouldn't happen */ 1941 } 1942 1943 /* 1944 * See if two irqs are compatible for sharing a vector. 1945 * Currently we only support sharing of PCI devices. 1946 */ 1947 static int 1948 acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2) 1949 { 1950 uint_t level1, po1; 1951 uint_t level2, po2; 1952 1953 /* Assume active high by default */ 1954 po1 = 0; 1955 po2 = 0; 1956 1957 if (iflag1.bustype != iflag2.bustype || iflag1.bustype != BUS_PCI) 1958 return (0); 1959 1960 if (iflag1.intr_el == INTR_EL_CONFORM) 1961 level1 = AV_LEVEL; 1962 else 1963 level1 = (iflag1.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0; 1964 1965 if (level1 && ((iflag1.intr_po == INTR_PO_ACTIVE_LOW) || 1966 (iflag1.intr_po == INTR_PO_CONFORM))) 1967 po1 = AV_ACTIVE_LOW; 1968 1969 if (iflag2.intr_el == INTR_EL_CONFORM) 1970 level2 = AV_LEVEL; 1971 else 1972 level2 = (iflag2.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0; 1973 1974 if (level2 && ((iflag2.intr_po == INTR_PO_ACTIVE_LOW) || 1975 (iflag2.intr_po == INTR_PO_CONFORM))) 1976 po2 = AV_ACTIVE_LOW; 1977 1978 if ((level1 == level2) && (po1 == po2)) 1979 return (1); 1980 1981 return (0); 1982 } 1983 1984 /* 1985 * Attempt to share vector with someone else 1986 */ 1987 static int 1988 apic_share_vector(int irqno, iflag_t *intr_flagp, short intr_index, int ipl, 1989 uchar_t ioapicindex, uchar_t ipin, apic_irq_t **irqptrp) 1990 { 1991 #ifdef DEBUG 1992 apic_irq_t *tmpirqp = NULL; 1993 #endif /* DEBUG */ 1994 apic_irq_t *irqptr, dummyirq; 1995 int newirq, chosen_irq = -1, share = 127; 1996 int lowest, highest, i; 1997 uchar_t share_id; 1998 1999 DDI_INTR_IMPLDBG((CE_CONT, "apic_share_vector: irqno=0x%x " 2000 "intr_index=0x%x ipl=0x%x\n", irqno, intr_index, ipl)); 2001 2002 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK; 2003 lowest = apic_ipltopri[ipl-1] + APIC_VECTOR_PER_IPL; 2004 2005 if (highest < lowest) /* Both ipl and ipl-1 map to same pri */ 2006 lowest -= APIC_VECTOR_PER_IPL; 2007 dummyirq.airq_mps_intr_index = intr_index; 2008 dummyirq.airq_ioapicindex = ioapicindex; 2009 dummyirq.airq_intin_no = ipin; 2010 if (intr_flagp) 2011 dummyirq.airq_iflag = *intr_flagp; 2012 apic_record_rdt_entry(&dummyirq, irqno); 2013 for (i = lowest; i <= highest; i++) { 2014 newirq = apic_vector_to_irq[i]; 2015 if (newirq == APIC_RESV_IRQ) 2016 continue; 2017 irqptr = apic_irq_table[newirq]; 2018 2019 if ((dummyirq.airq_rdt_entry & 0xFF00) != 2020 (irqptr->airq_rdt_entry & 0xFF00)) 2021 /* not compatible */ 2022 continue; 2023 2024 if (irqptr->airq_share < share) { 2025 share = irqptr->airq_share; 2026 chosen_irq = newirq; 2027 } 2028 } 2029 if (chosen_irq != -1) { 2030 /* 2031 * Assign a share id which is free or which is larger 2032 * than the largest one. 2033 */ 2034 share_id = 1; 2035 mutex_enter(&airq_mutex); 2036 irqptr = apic_irq_table[chosen_irq]; 2037 while (irqptr) { 2038 if (irqptr->airq_mps_intr_index == FREE_INDEX) { 2039 share_id = irqptr->airq_share_id; 2040 break; 2041 } 2042 if (share_id <= irqptr->airq_share_id) 2043 share_id = irqptr->airq_share_id + 1; 2044 #ifdef DEBUG 2045 tmpirqp = irqptr; 2046 #endif /* DEBUG */ 2047 irqptr = irqptr->airq_next; 2048 } 2049 if (!irqptr) { 2050 irqptr = kmem_zalloc(sizeof (apic_irq_t), KM_SLEEP); 2051 irqptr->airq_temp_cpu = IRQ_UNINIT; 2052 irqptr->airq_next = 2053 apic_irq_table[chosen_irq]->airq_next; 2054 apic_irq_table[chosen_irq]->airq_next = irqptr; 2055 #ifdef DEBUG 2056 tmpirqp = apic_irq_table[chosen_irq]; 2057 #endif /* DEBUG */ 2058 } 2059 irqptr->airq_mps_intr_index = intr_index; 2060 irqptr->airq_ioapicindex = ioapicindex; 2061 irqptr->airq_intin_no = ipin; 2062 if (intr_flagp) 2063 irqptr->airq_iflag = *intr_flagp; 2064 irqptr->airq_vector = apic_irq_table[chosen_irq]->airq_vector; 2065 irqptr->airq_share_id = share_id; 2066 apic_record_rdt_entry(irqptr, irqno); 2067 *irqptrp = irqptr; 2068 #ifdef DEBUG 2069 /* shuffle the pointers to test apic_delspl path */ 2070 if (tmpirqp) { 2071 tmpirqp->airq_next = irqptr->airq_next; 2072 irqptr->airq_next = apic_irq_table[chosen_irq]; 2073 apic_irq_table[chosen_irq] = irqptr; 2074 } 2075 #endif /* DEBUG */ 2076 mutex_exit(&airq_mutex); 2077 return (VIRTIRQ(chosen_irq, share_id)); 2078 } 2079 return (-1); 2080 } 2081 2082 /* 2083 * 2084 */ 2085 static int 2086 apic_setup_irq_table(dev_info_t *dip, int irqno, struct apic_io_intr *intrp, 2087 struct intrspec *ispec, iflag_t *intr_flagp, int type) 2088 { 2089 int origirq = ispec->intrspec_vec; 2090 uchar_t ipl = ispec->intrspec_pri; 2091 int newirq, intr_index; 2092 uchar_t ipin, ioapic, ioapicindex, vector; 2093 apic_irq_t *irqptr; 2094 major_t major; 2095 dev_info_t *sdip; 2096 2097 DDI_INTR_IMPLDBG((CE_CONT, "apic_setup_irq_table: dip=0x%p type=%d " 2098 "irqno=0x%x origirq=0x%x\n", (void *)dip, type, irqno, origirq)); 2099 2100 ASSERT(ispec != NULL); 2101 2102 major = (dip != NULL) ? ddi_name_to_major(ddi_get_name(dip)) : 0; 2103 2104 if (DDI_INTR_IS_MSI_OR_MSIX(type)) { 2105 /* MSI/X doesn't need to setup ioapic stuffs */ 2106 ioapicindex = 0xff; 2107 ioapic = 0xff; 2108 ipin = (uchar_t)0xff; 2109 intr_index = (type == DDI_INTR_TYPE_MSI) ? MSI_INDEX : 2110 MSIX_INDEX; 2111 mutex_enter(&airq_mutex); 2112 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) == -1) { 2113 mutex_exit(&airq_mutex); 2114 /* need an irq for MSI/X to index into autovect[] */ 2115 cmn_err(CE_WARN, "No interrupt irq: %s instance %d", 2116 ddi_get_name(dip), ddi_get_instance(dip)); 2117 return (-1); 2118 } 2119 mutex_exit(&airq_mutex); 2120 2121 } else if (intrp != NULL) { 2122 intr_index = (int)(intrp - apic_io_intrp); 2123 ioapic = intrp->intr_destid; 2124 ipin = intrp->intr_destintin; 2125 /* Find ioapicindex. If destid was ALL, we will exit with 0. */ 2126 for (ioapicindex = apic_io_max - 1; ioapicindex; ioapicindex--) 2127 if (apic_io_id[ioapicindex] == ioapic) 2128 break; 2129 ASSERT((ioapic == apic_io_id[ioapicindex]) || 2130 (ioapic == INTR_ALL_APIC)); 2131 2132 /* check whether this intin# has been used by another irqno */ 2133 if ((newirq = apic_find_intin(ioapicindex, ipin)) != -1) { 2134 return (newirq); 2135 } 2136 2137 } else if (intr_flagp != NULL) { 2138 /* ACPI case */ 2139 intr_index = ACPI_INDEX; 2140 ioapicindex = acpi_find_ioapic(irqno); 2141 ASSERT(ioapicindex != 0xFF); 2142 ioapic = apic_io_id[ioapicindex]; 2143 ipin = irqno - apic_io_vectbase[ioapicindex]; 2144 if (apic_irq_table[irqno] && 2145 apic_irq_table[irqno]->airq_mps_intr_index == ACPI_INDEX) { 2146 ASSERT(apic_irq_table[irqno]->airq_intin_no == ipin && 2147 apic_irq_table[irqno]->airq_ioapicindex == 2148 ioapicindex); 2149 return (irqno); 2150 } 2151 2152 } else { 2153 /* default configuration */ 2154 ioapicindex = 0; 2155 ioapic = apic_io_id[ioapicindex]; 2156 ipin = (uchar_t)irqno; 2157 intr_index = DEFAULT_INDEX; 2158 } 2159 2160 if (ispec == NULL) { 2161 APIC_VERBOSE_IOAPIC((CE_WARN, "No intrspec for irqno = %x\n", 2162 irqno)); 2163 } else if ((vector = apic_allocate_vector(ipl, irqno, 0)) == 0) { 2164 if ((newirq = apic_share_vector(irqno, intr_flagp, intr_index, 2165 ipl, ioapicindex, ipin, &irqptr)) != -1) { 2166 irqptr->airq_ipl = ipl; 2167 irqptr->airq_origirq = (uchar_t)origirq; 2168 irqptr->airq_dip = dip; 2169 irqptr->airq_major = major; 2170 sdip = apic_irq_table[IRQINDEX(newirq)]->airq_dip; 2171 /* This is OK to do really */ 2172 if (sdip == NULL) { 2173 cmn_err(CE_WARN, "Sharing vectors: %s" 2174 " instance %d and SCI", 2175 ddi_get_name(dip), ddi_get_instance(dip)); 2176 } else { 2177 cmn_err(CE_WARN, "Sharing vectors: %s" 2178 " instance %d and %s instance %d", 2179 ddi_get_name(sdip), ddi_get_instance(sdip), 2180 ddi_get_name(dip), ddi_get_instance(dip)); 2181 } 2182 return (newirq); 2183 } 2184 /* try high priority allocation now that share has failed */ 2185 if ((vector = apic_allocate_vector(ipl, irqno, 1)) == 0) { 2186 cmn_err(CE_WARN, "No interrupt vector: %s instance %d", 2187 ddi_get_name(dip), ddi_get_instance(dip)); 2188 return (-1); 2189 } 2190 } 2191 2192 mutex_enter(&airq_mutex); 2193 if (apic_irq_table[irqno] == NULL) { 2194 irqptr = kmem_zalloc(sizeof (apic_irq_t), KM_SLEEP); 2195 irqptr->airq_temp_cpu = IRQ_UNINIT; 2196 apic_irq_table[irqno] = irqptr; 2197 } else { 2198 irqptr = apic_irq_table[irqno]; 2199 if (irqptr->airq_mps_intr_index != FREE_INDEX) { 2200 /* 2201 * The slot is used by another irqno, so allocate 2202 * a free irqno for this interrupt 2203 */ 2204 newirq = apic_allocate_irq(apic_first_avail_irq); 2205 if (newirq == -1) { 2206 mutex_exit(&airq_mutex); 2207 return (-1); 2208 } 2209 irqno = newirq; 2210 irqptr = apic_irq_table[irqno]; 2211 if (irqptr == NULL) { 2212 irqptr = kmem_zalloc(sizeof (apic_irq_t), 2213 KM_SLEEP); 2214 irqptr->airq_temp_cpu = IRQ_UNINIT; 2215 apic_irq_table[irqno] = irqptr; 2216 } 2217 vector = apic_modify_vector(vector, newirq); 2218 } 2219 } 2220 apic_max_device_irq = max(irqno, apic_max_device_irq); 2221 apic_min_device_irq = min(irqno, apic_min_device_irq); 2222 mutex_exit(&airq_mutex); 2223 irqptr->airq_ioapicindex = ioapicindex; 2224 irqptr->airq_intin_no = ipin; 2225 irqptr->airq_ipl = ipl; 2226 irqptr->airq_vector = vector; 2227 irqptr->airq_origirq = (uchar_t)origirq; 2228 irqptr->airq_share_id = 0; 2229 irqptr->airq_mps_intr_index = (short)intr_index; 2230 irqptr->airq_dip = dip; 2231 irqptr->airq_major = major; 2232 irqptr->airq_cpu = apic_bind_intr(dip, irqno, ioapic, ipin); 2233 if (intr_flagp) 2234 irqptr->airq_iflag = *intr_flagp; 2235 2236 if (!DDI_INTR_IS_MSI_OR_MSIX(type)) { 2237 /* setup I/O APIC entry for non-MSI/X interrupts */ 2238 apic_record_rdt_entry(irqptr, irqno); 2239 } 2240 return (irqno); 2241 } 2242 2243 /* 2244 * return the cpu to which this intr should be bound. 2245 * Check properties or any other mechanism to see if user wants it 2246 * bound to a specific CPU. If so, return the cpu id with high bit set. 2247 * If not, use the policy to choose a cpu and return the id. 2248 */ 2249 uchar_t 2250 apic_bind_intr(dev_info_t *dip, int irq, uchar_t ioapicid, uchar_t intin) 2251 { 2252 int instance, instno, prop_len, bind_cpu, count; 2253 uint_t i, rc; 2254 uchar_t cpu; 2255 major_t major; 2256 char *name, *drv_name, *prop_val, *cptr; 2257 char prop_name[32]; 2258 2259 2260 if (apic_intr_policy == INTR_LOWEST_PRIORITY) 2261 return (IRQ_UNBOUND); 2262 2263 drv_name = NULL; 2264 rc = DDI_PROP_NOT_FOUND; 2265 major = (major_t)-1; 2266 if (dip != NULL) { 2267 name = ddi_get_name(dip); 2268 major = ddi_name_to_major(name); 2269 drv_name = ddi_major_to_name(major); 2270 instance = ddi_get_instance(dip); 2271 if (apic_intr_policy == INTR_ROUND_ROBIN_WITH_AFFINITY) { 2272 i = apic_min_device_irq; 2273 for (; i <= apic_max_device_irq; i++) { 2274 2275 if ((i == irq) || (apic_irq_table[i] == NULL) || 2276 (apic_irq_table[i]->airq_mps_intr_index 2277 == FREE_INDEX)) 2278 continue; 2279 2280 if ((apic_irq_table[i]->airq_major == major) && 2281 (!(apic_irq_table[i]->airq_cpu & 2282 IRQ_USER_BOUND))) { 2283 2284 cpu = apic_irq_table[i]->airq_cpu; 2285 2286 cmn_err(CE_CONT, 2287 "!%s: %s (%s) instance #%d " 2288 "vector 0x%x ioapic 0x%x " 2289 "intin 0x%x is bound to cpu %d\n", 2290 psm_name, 2291 name, drv_name, instance, irq, 2292 ioapicid, intin, cpu); 2293 return (cpu); 2294 } 2295 } 2296 } 2297 /* 2298 * search for "drvname"_intpt_bind_cpus property first, the 2299 * syntax of the property should be "a[,b,c,...]" where 2300 * instance 0 binds to cpu a, instance 1 binds to cpu b, 2301 * instance 3 binds to cpu c... 2302 * ddi_getlongprop() will search /option first, then / 2303 * if "drvname"_intpt_bind_cpus doesn't exist, then find 2304 * intpt_bind_cpus property. The syntax is the same, and 2305 * it applies to all the devices if its "drvname" specific 2306 * property doesn't exist 2307 */ 2308 (void) strcpy(prop_name, drv_name); 2309 (void) strcat(prop_name, "_intpt_bind_cpus"); 2310 rc = ddi_getlongprop(DDI_DEV_T_ANY, dip, 0, prop_name, 2311 (caddr_t)&prop_val, &prop_len); 2312 if (rc != DDI_PROP_SUCCESS) { 2313 rc = ddi_getlongprop(DDI_DEV_T_ANY, dip, 0, 2314 "intpt_bind_cpus", (caddr_t)&prop_val, &prop_len); 2315 } 2316 } 2317 if (rc == DDI_PROP_SUCCESS) { 2318 for (i = count = 0; i < (prop_len - 1); i++) 2319 if (prop_val[i] == ',') 2320 count++; 2321 if (prop_val[i-1] != ',') 2322 count++; 2323 /* 2324 * if somehow the binding instances defined in the 2325 * property are not enough for this instno., then 2326 * reuse the pattern for the next instance until 2327 * it reaches the requested instno 2328 */ 2329 instno = instance % count; 2330 i = 0; 2331 cptr = prop_val; 2332 while (i < instno) 2333 if (*cptr++ == ',') 2334 i++; 2335 bind_cpu = stoi(&cptr); 2336 kmem_free(prop_val, prop_len); 2337 /* if specific cpu is bogus, then default to cpu 0 */ 2338 if (bind_cpu >= apic_nproc) { 2339 cmn_err(CE_WARN, "%s: %s=%s: CPU %d not present", 2340 psm_name, prop_name, prop_val, bind_cpu); 2341 bind_cpu = 0; 2342 } else { 2343 /* indicate that we are bound at user request */ 2344 bind_cpu |= IRQ_USER_BOUND; 2345 } 2346 /* 2347 * no need to check apic_cpus[].aci_status, if specific cpu is 2348 * not up, then post_cpu_start will handle it. 2349 */ 2350 } else { 2351 bind_cpu = apic_next_bind_cpu++; 2352 if (bind_cpu >= apic_nproc) { 2353 apic_next_bind_cpu = 1; 2354 bind_cpu = 0; 2355 } 2356 } 2357 if (drv_name != NULL) 2358 cmn_err(CE_CONT, "!%s: %s (%s) instance %d " 2359 "vector 0x%x ioapic 0x%x intin 0x%x is bound to cpu %d\n", 2360 psm_name, name, drv_name, instance, 2361 irq, ioapicid, intin, bind_cpu & ~IRQ_USER_BOUND); 2362 else 2363 cmn_err(CE_CONT, "!%s: " 2364 "vector 0x%x ioapic 0x%x intin 0x%x is bound to cpu %d\n", 2365 psm_name, irq, ioapicid, intin, bind_cpu & ~IRQ_USER_BOUND); 2366 2367 return ((uchar_t)bind_cpu); 2368 } 2369 2370 static struct apic_io_intr * 2371 apic_find_io_intr_w_busid(int irqno, int busid) 2372 { 2373 struct apic_io_intr *intrp; 2374 2375 /* 2376 * It can have more than 1 entry with same source bus IRQ, 2377 * but unique with the source bus id 2378 */ 2379 intrp = apic_io_intrp; 2380 if (intrp != NULL) { 2381 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 2382 if (intrp->intr_irq == irqno && 2383 intrp->intr_busid == busid && 2384 intrp->intr_type == IO_INTR_INT) 2385 return (intrp); 2386 intrp++; 2387 } 2388 } 2389 APIC_VERBOSE_IOAPIC((CE_NOTE, "Did not find io intr for irqno:" 2390 "busid %x:%x\n", irqno, busid)); 2391 return ((struct apic_io_intr *)NULL); 2392 } 2393 2394 2395 struct mps_bus_info { 2396 char *bus_name; 2397 int bus_id; 2398 } bus_info_array[] = { 2399 "ISA ", BUS_ISA, 2400 "PCI ", BUS_PCI, 2401 "EISA ", BUS_EISA, 2402 "XPRESS", BUS_XPRESS, 2403 "PCMCIA", BUS_PCMCIA, 2404 "VL ", BUS_VL, 2405 "CBUS ", BUS_CBUS, 2406 "CBUSII", BUS_CBUSII, 2407 "FUTURE", BUS_FUTURE, 2408 "INTERN", BUS_INTERN, 2409 "MBI ", BUS_MBI, 2410 "MBII ", BUS_MBII, 2411 "MPI ", BUS_MPI, 2412 "MPSA ", BUS_MPSA, 2413 "NUBUS ", BUS_NUBUS, 2414 "TC ", BUS_TC, 2415 "VME ", BUS_VME, 2416 "PCI-E ", BUS_PCIE 2417 }; 2418 2419 static int 2420 apic_find_bus_type(char *bus) 2421 { 2422 int i = 0; 2423 2424 for (; i < sizeof (bus_info_array)/sizeof (struct mps_bus_info); i++) 2425 if (strncmp(bus, bus_info_array[i].bus_name, 2426 strlen(bus_info_array[i].bus_name)) == 0) 2427 return (bus_info_array[i].bus_id); 2428 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus type for bus %s", bus)); 2429 return (0); 2430 } 2431 2432 static int 2433 apic_find_bus(int busid) 2434 { 2435 struct apic_bus *busp; 2436 2437 busp = apic_busp; 2438 while (busp->bus_entry == APIC_BUS_ENTRY) { 2439 if (busp->bus_id == busid) 2440 return (apic_find_bus_type((char *)&busp->bus_str1)); 2441 busp++; 2442 } 2443 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus for bus id %x", busid)); 2444 return (0); 2445 } 2446 2447 static int 2448 apic_find_bus_id(int bustype) 2449 { 2450 struct apic_bus *busp; 2451 2452 busp = apic_busp; 2453 while (busp->bus_entry == APIC_BUS_ENTRY) { 2454 if (apic_find_bus_type((char *)&busp->bus_str1) == bustype) 2455 return (busp->bus_id); 2456 busp++; 2457 } 2458 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus id for bustype %x", 2459 bustype)); 2460 return (-1); 2461 } 2462 2463 /* 2464 * Check if a particular irq need to be reserved for any io_intr 2465 */ 2466 static struct apic_io_intr * 2467 apic_find_io_intr(int irqno) 2468 { 2469 struct apic_io_intr *intrp; 2470 2471 intrp = apic_io_intrp; 2472 if (intrp != NULL) { 2473 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 2474 if (intrp->intr_irq == irqno && 2475 intrp->intr_type == IO_INTR_INT) 2476 return (intrp); 2477 intrp++; 2478 } 2479 } 2480 return ((struct apic_io_intr *)NULL); 2481 } 2482 2483 /* 2484 * Check if the given ioapicindex intin combination has already been assigned 2485 * an irq. If so return irqno. Else -1 2486 */ 2487 static int 2488 apic_find_intin(uchar_t ioapic, uchar_t intin) 2489 { 2490 apic_irq_t *irqptr; 2491 int i; 2492 2493 /* find ioapic and intin in the apic_irq_table[] and return the index */ 2494 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) { 2495 irqptr = apic_irq_table[i]; 2496 while (irqptr) { 2497 if ((irqptr->airq_mps_intr_index >= 0) && 2498 (irqptr->airq_intin_no == intin) && 2499 (irqptr->airq_ioapicindex == ioapic)) { 2500 APIC_VERBOSE_IOAPIC((CE_NOTE, "!Found irq " 2501 "entry for ioapic:intin %x:%x " 2502 "shared interrupts ?", ioapic, intin)); 2503 return (i); 2504 } 2505 irqptr = irqptr->airq_next; 2506 } 2507 } 2508 return (-1); 2509 } 2510 2511 int 2512 apic_allocate_irq(int irq) 2513 { 2514 int freeirq, i; 2515 2516 if ((freeirq = apic_find_free_irq(irq, (APIC_RESV_IRQ - 1))) == -1) 2517 if ((freeirq = apic_find_free_irq(APIC_FIRST_FREE_IRQ, 2518 (irq - 1))) == -1) { 2519 /* 2520 * if BIOS really defines every single irq in the mps 2521 * table, then don't worry about conflicting with 2522 * them, just use any free slot in apic_irq_table 2523 */ 2524 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) { 2525 if ((apic_irq_table[i] == NULL) || 2526 apic_irq_table[i]->airq_mps_intr_index == 2527 FREE_INDEX) { 2528 freeirq = i; 2529 break; 2530 } 2531 } 2532 if (freeirq == -1) { 2533 /* This shouldn't happen, but just in case */ 2534 cmn_err(CE_WARN, "%s: NO available IRQ", psm_name); 2535 return (-1); 2536 } 2537 } 2538 if (apic_irq_table[freeirq] == NULL) { 2539 apic_irq_table[freeirq] = 2540 kmem_zalloc(sizeof (apic_irq_t), KM_NOSLEEP); 2541 if (apic_irq_table[freeirq] == NULL) { 2542 cmn_err(CE_WARN, "%s: NO memory to allocate IRQ", 2543 psm_name); 2544 return (-1); 2545 } 2546 apic_irq_table[freeirq]->airq_mps_intr_index = FREE_INDEX; 2547 } 2548 return (freeirq); 2549 } 2550 2551 static int 2552 apic_find_free_irq(int start, int end) 2553 { 2554 int i; 2555 2556 for (i = start; i <= end; i++) 2557 /* Check if any I/O entry needs this IRQ */ 2558 if (apic_find_io_intr(i) == NULL) { 2559 /* Then see if it is free */ 2560 if ((apic_irq_table[i] == NULL) || 2561 (apic_irq_table[i]->airq_mps_intr_index == 2562 FREE_INDEX)) { 2563 return (i); 2564 } 2565 } 2566 return (-1); 2567 } 2568 2569 2570 /* 2571 * Mark vector as being in the process of being deleted. Interrupts 2572 * may still come in on some CPU. The moment an interrupt comes with 2573 * the new vector, we know we can free the old one. Called only from 2574 * addspl and delspl with interrupts disabled. Because an interrupt 2575 * can be shared, but no interrupt from either device may come in, 2576 * we also use a timeout mechanism, which we arbitrarily set to 2577 * apic_revector_timeout microseconds. 2578 */ 2579 static void 2580 apic_mark_vector(uchar_t oldvector, uchar_t newvector) 2581 { 2582 ulong_t iflag; 2583 2584 iflag = intr_clear(); 2585 lock_set(&apic_revector_lock); 2586 if (!apic_oldvec_to_newvec) { 2587 apic_oldvec_to_newvec = 2588 kmem_zalloc(sizeof (newvector) * APIC_MAX_VECTOR * 2, 2589 KM_NOSLEEP); 2590 2591 if (!apic_oldvec_to_newvec) { 2592 /* 2593 * This failure is not catastrophic. 2594 * But, the oldvec will never be freed. 2595 */ 2596 apic_error |= APIC_ERR_MARK_VECTOR_FAIL; 2597 lock_clear(&apic_revector_lock); 2598 intr_restore(iflag); 2599 return; 2600 } 2601 apic_newvec_to_oldvec = &apic_oldvec_to_newvec[APIC_MAX_VECTOR]; 2602 } 2603 2604 /* See if we already did this for drivers which do double addintrs */ 2605 if (apic_oldvec_to_newvec[oldvector] != newvector) { 2606 apic_oldvec_to_newvec[oldvector] = newvector; 2607 apic_newvec_to_oldvec[newvector] = oldvector; 2608 apic_revector_pending++; 2609 } 2610 lock_clear(&apic_revector_lock); 2611 intr_restore(iflag); 2612 (void) timeout(apic_xlate_vector_free_timeout_handler, 2613 (void *)(uintptr_t)oldvector, drv_usectohz(apic_revector_timeout)); 2614 } 2615 2616 /* 2617 * xlate_vector is called from intr_enter if revector_pending is set. 2618 * It will xlate it if needed and mark the old vector as free. 2619 */ 2620 uchar_t 2621 apic_xlate_vector(uchar_t vector) 2622 { 2623 uchar_t newvector, oldvector = 0; 2624 2625 lock_set(&apic_revector_lock); 2626 /* Do we really need to do this ? */ 2627 if (!apic_revector_pending) { 2628 lock_clear(&apic_revector_lock); 2629 return (vector); 2630 } 2631 if ((newvector = apic_oldvec_to_newvec[vector]) != 0) 2632 oldvector = vector; 2633 else { 2634 /* 2635 * The incoming vector is new . See if a stale entry is 2636 * remaining 2637 */ 2638 if ((oldvector = apic_newvec_to_oldvec[vector]) != 0) 2639 newvector = vector; 2640 } 2641 2642 if (oldvector) { 2643 apic_revector_pending--; 2644 apic_oldvec_to_newvec[oldvector] = 0; 2645 apic_newvec_to_oldvec[newvector] = 0; 2646 apic_free_vector(oldvector); 2647 lock_clear(&apic_revector_lock); 2648 /* There could have been more than one reprogramming! */ 2649 return (apic_xlate_vector(newvector)); 2650 } 2651 lock_clear(&apic_revector_lock); 2652 return (vector); 2653 } 2654 2655 void 2656 apic_xlate_vector_free_timeout_handler(void *arg) 2657 { 2658 ulong_t iflag; 2659 uchar_t oldvector, newvector; 2660 2661 oldvector = (uchar_t)(uintptr_t)arg; 2662 iflag = intr_clear(); 2663 lock_set(&apic_revector_lock); 2664 if ((newvector = apic_oldvec_to_newvec[oldvector]) != 0) { 2665 apic_free_vector(oldvector); 2666 apic_oldvec_to_newvec[oldvector] = 0; 2667 apic_newvec_to_oldvec[newvector] = 0; 2668 apic_revector_pending--; 2669 } 2670 2671 lock_clear(&apic_revector_lock); 2672 intr_restore(iflag); 2673 } 2674 2675 2676 /* 2677 * compute the polarity, trigger mode and vector for programming into 2678 * the I/O apic and record in airq_rdt_entry. 2679 */ 2680 static void 2681 apic_record_rdt_entry(apic_irq_t *irqptr, int irq) 2682 { 2683 int ioapicindex, bus_type, vector; 2684 short intr_index; 2685 uint_t level, po, io_po; 2686 struct apic_io_intr *iointrp; 2687 2688 intr_index = irqptr->airq_mps_intr_index; 2689 DDI_INTR_IMPLDBG((CE_CONT, "apic_record_rdt_entry: intr_index=%d " 2690 "irq = 0x%x dip = 0x%p vector = 0x%x\n", intr_index, irq, 2691 (void *)irqptr->airq_dip, irqptr->airq_vector)); 2692 2693 if (intr_index == RESERVE_INDEX) { 2694 apic_error |= APIC_ERR_INVALID_INDEX; 2695 return; 2696 } else if (APIC_IS_MSI_OR_MSIX_INDEX(intr_index)) { 2697 return; 2698 } 2699 2700 vector = irqptr->airq_vector; 2701 ioapicindex = irqptr->airq_ioapicindex; 2702 /* Assume edge triggered by default */ 2703 level = 0; 2704 /* Assume active high by default */ 2705 po = 0; 2706 2707 if (intr_index == DEFAULT_INDEX || intr_index == FREE_INDEX) { 2708 ASSERT(irq < 16); 2709 if (eisa_level_intr_mask & (1 << irq)) 2710 level = AV_LEVEL; 2711 if (intr_index == FREE_INDEX && apic_defconf == 0) 2712 apic_error |= APIC_ERR_INVALID_INDEX; 2713 } else if (intr_index == ACPI_INDEX) { 2714 bus_type = irqptr->airq_iflag.bustype; 2715 if (irqptr->airq_iflag.intr_el == INTR_EL_CONFORM) { 2716 if (bus_type == BUS_PCI) 2717 level = AV_LEVEL; 2718 } else 2719 level = (irqptr->airq_iflag.intr_el == INTR_EL_LEVEL) ? 2720 AV_LEVEL : 0; 2721 if (level && 2722 ((irqptr->airq_iflag.intr_po == INTR_PO_ACTIVE_LOW) || 2723 (irqptr->airq_iflag.intr_po == INTR_PO_CONFORM && 2724 bus_type == BUS_PCI))) 2725 po = AV_ACTIVE_LOW; 2726 } else { 2727 iointrp = apic_io_intrp + intr_index; 2728 bus_type = apic_find_bus(iointrp->intr_busid); 2729 if (iointrp->intr_el == INTR_EL_CONFORM) { 2730 if ((irq < 16) && (eisa_level_intr_mask & (1 << irq))) 2731 level = AV_LEVEL; 2732 else if (bus_type == BUS_PCI) 2733 level = AV_LEVEL; 2734 } else 2735 level = (iointrp->intr_el == INTR_EL_LEVEL) ? 2736 AV_LEVEL : 0; 2737 if (level && ((iointrp->intr_po == INTR_PO_ACTIVE_LOW) || 2738 (iointrp->intr_po == INTR_PO_CONFORM && 2739 bus_type == BUS_PCI))) 2740 po = AV_ACTIVE_LOW; 2741 } 2742 if (level) 2743 apic_level_intr[irq] = 1; 2744 /* 2745 * The 82489DX External APIC cannot do active low polarity interrupts. 2746 */ 2747 if (po && (apic_io_ver[ioapicindex] != IOAPIC_VER_82489DX)) 2748 io_po = po; 2749 else 2750 io_po = 0; 2751 2752 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) 2753 printf("setio: ioapic=%x intin=%x level=%x po=%x vector=%x\n", 2754 ioapicindex, irqptr->airq_intin_no, level, io_po, vector); 2755 2756 irqptr->airq_rdt_entry = level|io_po|vector; 2757 } 2758 2759 /* 2760 * Bind interrupt corresponding to irq_ptr to bind_cpu. 2761 * Must be called with interrupts disabled and apic_ioapic_lock held 2762 */ 2763 int 2764 apic_rebind(apic_irq_t *irq_ptr, int bind_cpu, 2765 struct ioapic_reprogram_data *drep) 2766 { 2767 int ioapicindex, intin_no; 2768 uchar_t airq_temp_cpu; 2769 apic_cpus_info_t *cpu_infop; 2770 uint32_t rdt_entry; 2771 int which_irq; 2772 2773 which_irq = apic_vector_to_irq[irq_ptr->airq_vector]; 2774 2775 intin_no = irq_ptr->airq_intin_no; 2776 ioapicindex = irq_ptr->airq_ioapicindex; 2777 airq_temp_cpu = irq_ptr->airq_temp_cpu; 2778 if (airq_temp_cpu != IRQ_UNINIT && airq_temp_cpu != IRQ_UNBOUND) { 2779 if (airq_temp_cpu & IRQ_USER_BOUND) 2780 /* Mask off high bit so it can be used as array index */ 2781 airq_temp_cpu &= ~IRQ_USER_BOUND; 2782 2783 ASSERT(airq_temp_cpu < apic_nproc); 2784 } 2785 2786 /* 2787 * Can't bind to a CPU that's not accepting interrupts: 2788 */ 2789 cpu_infop = &apic_cpus[bind_cpu & ~IRQ_USER_BOUND]; 2790 if (!(cpu_infop->aci_status & APIC_CPU_INTR_ENABLE)) 2791 return (1); 2792 2793 /* 2794 * If we are about to change the interrupt vector for this interrupt, 2795 * and this interrupt is level-triggered, attached to an IOAPIC, 2796 * has been delivered to a CPU and that CPU has not handled it 2797 * yet, we cannot reprogram the IOAPIC now. 2798 */ 2799 if (!APIC_IS_MSI_OR_MSIX_INDEX(irq_ptr->airq_mps_intr_index)) { 2800 2801 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, 2802 intin_no); 2803 2804 if ((irq_ptr->airq_vector != RDT_VECTOR(rdt_entry)) && 2805 apic_check_stuck_interrupt(irq_ptr, airq_temp_cpu, 2806 bind_cpu, ioapicindex, intin_no, which_irq, drep) != 0) { 2807 2808 return (0); 2809 } 2810 2811 /* 2812 * NOTE: We do not unmask the RDT here, as an interrupt MAY 2813 * still come in before we have a chance to reprogram it below. 2814 * The reprogramming below will simultaneously change and 2815 * unmask the RDT entry. 2816 */ 2817 2818 if ((uchar_t)bind_cpu == IRQ_UNBOUND) { 2819 rdt_entry = AV_LDEST | AV_LOPRI | 2820 irq_ptr->airq_rdt_entry; 2821 2822 /* Write the RDT entry -- no specific CPU binding */ 2823 WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapicindex, intin_no, 2824 AV_TOALL); 2825 2826 if (airq_temp_cpu != IRQ_UNINIT && airq_temp_cpu != 2827 IRQ_UNBOUND) 2828 apic_cpus[airq_temp_cpu].aci_temp_bound--; 2829 2830 /* 2831 * Write the vector, trigger, and polarity portion of 2832 * the RDT 2833 */ 2834 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, intin_no, 2835 rdt_entry); 2836 2837 irq_ptr->airq_temp_cpu = IRQ_UNBOUND; 2838 return (0); 2839 } 2840 } 2841 2842 if (bind_cpu & IRQ_USER_BOUND) { 2843 cpu_infop->aci_bound++; 2844 } else { 2845 cpu_infop->aci_temp_bound++; 2846 } 2847 ASSERT((bind_cpu & ~IRQ_USER_BOUND) < apic_nproc); 2848 if (!APIC_IS_MSI_OR_MSIX_INDEX(irq_ptr->airq_mps_intr_index)) { 2849 /* Write the RDT entry -- bind to a specific CPU: */ 2850 WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapicindex, intin_no, 2851 cpu_infop->aci_local_id << APIC_ID_BIT_OFFSET); 2852 } 2853 if ((airq_temp_cpu != IRQ_UNBOUND) && (airq_temp_cpu != IRQ_UNINIT)) { 2854 apic_cpus[airq_temp_cpu].aci_temp_bound--; 2855 } 2856 if (!APIC_IS_MSI_OR_MSIX_INDEX(irq_ptr->airq_mps_intr_index)) { 2857 2858 rdt_entry = AV_PDEST | AV_FIXED | irq_ptr->airq_rdt_entry; 2859 2860 /* Write the vector, trigger, and polarity portion of the RDT */ 2861 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, intin_no, 2862 rdt_entry); 2863 2864 } else { 2865 int type = (irq_ptr->airq_mps_intr_index == MSI_INDEX) ? 2866 DDI_INTR_TYPE_MSI : DDI_INTR_TYPE_MSIX; 2867 if (type == DDI_INTR_TYPE_MSI) { 2868 if (irq_ptr->airq_ioapicindex == 2869 irq_ptr->airq_origirq) { 2870 /* first one */ 2871 DDI_INTR_IMPLDBG((CE_CONT, "apic_rebind: call " 2872 "apic_pci_msi_enable_vector\n")); 2873 apic_pci_msi_enable_vector(irq_ptr->airq_dip, 2874 type, which_irq, irq_ptr->airq_vector, 2875 irq_ptr->airq_intin_no, 2876 cpu_infop->aci_local_id); 2877 } 2878 if ((irq_ptr->airq_ioapicindex + 2879 irq_ptr->airq_intin_no - 1) == 2880 irq_ptr->airq_origirq) { /* last one */ 2881 DDI_INTR_IMPLDBG((CE_CONT, "apic_rebind: call " 2882 "apic_pci_msi_enable_mode\n")); 2883 apic_pci_msi_enable_mode(irq_ptr->airq_dip, 2884 type, which_irq); 2885 } 2886 } else { /* MSI-X */ 2887 apic_pci_msi_enable_vector(irq_ptr->airq_dip, type, 2888 irq_ptr->airq_origirq, irq_ptr->airq_vector, 1, 2889 cpu_infop->aci_local_id); 2890 apic_pci_msi_enable_mode(irq_ptr->airq_dip, type, 2891 irq_ptr->airq_origirq); 2892 } 2893 } 2894 irq_ptr->airq_temp_cpu = (uchar_t)bind_cpu; 2895 apic_redist_cpu_skip &= ~(1 << (bind_cpu & ~IRQ_USER_BOUND)); 2896 return (0); 2897 } 2898 2899 static void 2900 apic_last_ditch_clear_remote_irr(int ioapic_ix, int intin_no) 2901 { 2902 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no) 2903 & AV_REMOTE_IRR) != 0) { 2904 /* 2905 * Trying to clear the bit through normal 2906 * channels has failed. So as a last-ditch 2907 * effort, try to set the trigger mode to 2908 * edge, then to level. This has been 2909 * observed to work on many systems. 2910 */ 2911 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 2912 intin_no, 2913 READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 2914 intin_no) & ~AV_LEVEL); 2915 2916 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 2917 intin_no, 2918 READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 2919 intin_no) | AV_LEVEL); 2920 2921 /* 2922 * If the bit's STILL set, this interrupt may 2923 * be hosed. 2924 */ 2925 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 2926 intin_no) & AV_REMOTE_IRR) != 0) { 2927 2928 prom_printf("%s: Remote IRR still " 2929 "not clear for IOAPIC %d intin %d.\n" 2930 "\tInterrupts to this pin may cease " 2931 "functioning.\n", psm_name, ioapic_ix, 2932 intin_no); 2933 #ifdef DEBUG 2934 apic_last_ditch_reprogram_failures++; 2935 #endif 2936 } 2937 } 2938 } 2939 2940 /* 2941 * This function is protected by apic_ioapic_lock coupled with the 2942 * fact that interrupts are disabled. 2943 */ 2944 static void 2945 delete_defer_repro_ent(int which_irq) 2946 { 2947 ASSERT(which_irq >= 0); 2948 ASSERT(which_irq <= 255); 2949 2950 if (apic_reprogram_info[which_irq].done) 2951 return; 2952 2953 apic_reprogram_info[which_irq].done = B_TRUE; 2954 2955 #ifdef DEBUG 2956 apic_defer_repro_total_retries += 2957 apic_reprogram_info[which_irq].tries; 2958 2959 apic_defer_repro_successes++; 2960 #endif 2961 2962 if (--apic_reprogram_outstanding == 0) { 2963 2964 setlvlx = psm_intr_exit_fn(); 2965 } 2966 } 2967 2968 2969 /* 2970 * Interrupts must be disabled during this function to prevent 2971 * self-deadlock. Interrupts are disabled because this function 2972 * is called from apic_check_stuck_interrupt(), which is called 2973 * from apic_rebind(), which requires its caller to disable interrupts. 2974 */ 2975 static void 2976 add_defer_repro_ent(apic_irq_t *irq_ptr, int which_irq, int new_bind_cpu) 2977 { 2978 ASSERT(which_irq >= 0); 2979 ASSERT(which_irq <= 255); 2980 2981 /* 2982 * On the off-chance that there's already a deferred 2983 * reprogramming on this irq, check, and if so, just update the 2984 * CPU and irq pointer to which the interrupt is targeted, then return. 2985 */ 2986 if (!apic_reprogram_info[which_irq].done) { 2987 apic_reprogram_info[which_irq].bindcpu = new_bind_cpu; 2988 apic_reprogram_info[which_irq].irqp = irq_ptr; 2989 return; 2990 } 2991 2992 apic_reprogram_info[which_irq].irqp = irq_ptr; 2993 apic_reprogram_info[which_irq].bindcpu = new_bind_cpu; 2994 apic_reprogram_info[which_irq].tries = 0; 2995 /* 2996 * This must be the last thing set, since we're not 2997 * grabbing any locks, apic_try_deferred_reprogram() will 2998 * make its decision about using this entry iff done 2999 * is false. 3000 */ 3001 apic_reprogram_info[which_irq].done = B_FALSE; 3002 3003 /* 3004 * If there were previously no deferred reprogrammings, change 3005 * setlvlx to call apic_try_deferred_reprogram() 3006 */ 3007 if (++apic_reprogram_outstanding == 1) { 3008 3009 setlvlx = apic_try_deferred_reprogram; 3010 } 3011 } 3012 3013 static void 3014 apic_try_deferred_reprogram(int prev_ipl, int irq) 3015 { 3016 int reproirq, iflag; 3017 struct ioapic_reprogram_data *drep; 3018 3019 (*psm_intr_exit_fn())(prev_ipl, irq); 3020 3021 if (!lock_try(&apic_defer_reprogram_lock)) { 3022 return; 3023 } 3024 3025 /* 3026 * Acquire the apic_ioapic_lock so that any other operations that 3027 * may affect the apic_reprogram_info state are serialized. 3028 * It's still possible for the last deferred reprogramming to clear 3029 * between the time we entered this function and the time we get to 3030 * the for loop below. In that case, *setlvlx will have been set 3031 * back to *_intr_exit and drep will be NULL. (There's no way to 3032 * stop that from happening -- we would need to grab a lock before 3033 * calling *setlvlx, which is neither realistic nor prudent). 3034 */ 3035 iflag = intr_clear(); 3036 lock_set(&apic_ioapic_lock); 3037 3038 /* 3039 * For each deferred RDT entry, try to reprogram it now. Note that 3040 * there is no lock acquisition to read apic_reprogram_info because 3041 * '.done' is set only after the other fields in the structure are set. 3042 */ 3043 3044 drep = NULL; 3045 for (reproirq = 0; reproirq <= APIC_MAX_VECTOR; reproirq++) { 3046 if (apic_reprogram_info[reproirq].done == B_FALSE) { 3047 drep = &apic_reprogram_info[reproirq]; 3048 break; 3049 } 3050 } 3051 3052 /* 3053 * Either we found a deferred action to perform, or 3054 * we entered this function spuriously, after *setlvlx 3055 * was restored to point to *_intr_exit. Any other 3056 * permutation is invalid. 3057 */ 3058 ASSERT(drep != NULL || *setlvlx == psm_intr_exit_fn()); 3059 3060 /* 3061 * Though we can't really do anything about errors 3062 * at this point, keep track of them for reporting. 3063 * Note that it is very possible for apic_setup_io_intr 3064 * to re-register this very timeout if the Remote IRR bit 3065 * has not yet cleared. 3066 */ 3067 3068 #ifdef DEBUG 3069 if (drep != NULL) { 3070 if (apic_setup_io_intr(drep, reproirq, B_TRUE) != 0) { 3071 apic_deferred_setup_failures++; 3072 } 3073 } else { 3074 apic_deferred_spurious_enters++; 3075 } 3076 #else 3077 if (drep != NULL) 3078 (void) apic_setup_io_intr(drep, reproirq, B_TRUE); 3079 #endif 3080 3081 lock_clear(&apic_ioapic_lock); 3082 intr_restore(iflag); 3083 3084 lock_clear(&apic_defer_reprogram_lock); 3085 } 3086 3087 static void 3088 apic_ioapic_wait_pending_clear(int ioapic_ix, int intin_no) 3089 { 3090 int waited; 3091 3092 /* 3093 * Wait for the delivery pending bit to clear. 3094 */ 3095 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no) & 3096 (AV_LEVEL|AV_PENDING)) == (AV_LEVEL|AV_PENDING)) { 3097 3098 /* 3099 * If we're still waiting on the delivery of this interrupt, 3100 * continue to wait here until it is delivered (this should be 3101 * a very small amount of time, but include a timeout just in 3102 * case). 3103 */ 3104 for (waited = 0; waited < apic_max_reps_clear_pending; 3105 waited++) { 3106 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 3107 intin_no) & AV_PENDING) == 0) { 3108 break; 3109 } 3110 } 3111 } 3112 } 3113 3114 3115 /* 3116 * Checks to see if the IOAPIC interrupt entry specified has its Remote IRR 3117 * bit set. Calls functions that modify the function that setlvlx points to, 3118 * so that the reprogramming can be retried very shortly. 3119 * 3120 * This function will mask the RDT entry if the interrupt is level-triggered. 3121 * (The caller is responsible for unmasking the RDT entry.) 3122 * 3123 * Returns non-zero if the caller should defer IOAPIC reprogramming. 3124 */ 3125 static int 3126 apic_check_stuck_interrupt(apic_irq_t *irq_ptr, int old_bind_cpu, 3127 int new_bind_cpu, int ioapic_ix, int intin_no, int which_irq, 3128 struct ioapic_reprogram_data *drep) 3129 { 3130 int32_t rdt_entry; 3131 int waited; 3132 int reps = 0; 3133 3134 /* 3135 * Wait for the delivery pending bit to clear. 3136 */ 3137 do { 3138 ++reps; 3139 3140 apic_ioapic_wait_pending_clear(ioapic_ix, intin_no); 3141 3142 /* 3143 * Mask the RDT entry, but only if it's a level-triggered 3144 * interrupt 3145 */ 3146 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 3147 intin_no); 3148 if ((rdt_entry & (AV_LEVEL|AV_MASK)) == AV_LEVEL) { 3149 3150 /* Mask it */ 3151 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no, 3152 AV_MASK | rdt_entry); 3153 } 3154 3155 if ((rdt_entry & AV_LEVEL) == AV_LEVEL) { 3156 /* 3157 * If there was a race and an interrupt was injected 3158 * just before we masked, check for that case here. 3159 * Then, unmask the RDT entry and try again. If we're 3160 * on our last try, don't unmask (because we want the 3161 * RDT entry to remain masked for the rest of the 3162 * function). 3163 */ 3164 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 3165 intin_no); 3166 if ((rdt_entry & AV_PENDING) && 3167 (reps < apic_max_reps_clear_pending)) { 3168 /* Unmask it */ 3169 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 3170 intin_no, rdt_entry & ~AV_MASK); 3171 } 3172 } 3173 3174 } while ((rdt_entry & AV_PENDING) && 3175 (reps < apic_max_reps_clear_pending)); 3176 3177 #ifdef DEBUG 3178 if (rdt_entry & AV_PENDING) 3179 apic_intr_deliver_timeouts++; 3180 #endif 3181 3182 /* 3183 * If the remote IRR bit is set, then the interrupt has been sent 3184 * to a CPU for processing. We have no choice but to wait for 3185 * that CPU to process the interrupt, at which point the remote IRR 3186 * bit will be cleared. 3187 */ 3188 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no) & 3189 (AV_LEVEL|AV_REMOTE_IRR)) == (AV_LEVEL|AV_REMOTE_IRR)) { 3190 3191 /* 3192 * If the CPU that this RDT is bound to is NOT the current 3193 * CPU, wait until that CPU handles the interrupt and ACKs 3194 * it. If this interrupt is not bound to any CPU (that is, 3195 * if it's bound to the logical destination of "anyone"), it 3196 * may have been delivered to the current CPU so handle that 3197 * case by deferring the reprogramming (below). 3198 */ 3199 if ((old_bind_cpu != IRQ_UNBOUND) && 3200 (old_bind_cpu != IRQ_UNINIT) && 3201 (old_bind_cpu != psm_get_cpu_id())) { 3202 for (waited = 0; waited < apic_max_reps_clear_pending; 3203 waited++) { 3204 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 3205 intin_no) & AV_REMOTE_IRR) == 0) { 3206 3207 delete_defer_repro_ent(which_irq); 3208 3209 /* Remote IRR has cleared! */ 3210 return (0); 3211 } 3212 } 3213 } 3214 3215 /* 3216 * If we waited and the Remote IRR bit is still not cleared, 3217 * AND if we've invoked the timeout APIC_REPROGRAM_MAX_TIMEOUTS 3218 * times for this interrupt, try the last-ditch workaround: 3219 */ 3220 if (drep && drep->tries >= APIC_REPROGRAM_MAX_TRIES) { 3221 3222 apic_last_ditch_clear_remote_irr(ioapic_ix, intin_no); 3223 3224 /* Mark this one as reprogrammed: */ 3225 delete_defer_repro_ent(which_irq); 3226 3227 return (0); 3228 } else { 3229 #ifdef DEBUG 3230 apic_intr_deferrals++; 3231 #endif 3232 3233 /* 3234 * If waiting for the Remote IRR bit (above) didn't 3235 * allow it to clear, defer the reprogramming. 3236 * Add a new deferred-programming entry if the 3237 * caller passed a NULL one (and update the existing one 3238 * in case anything changed). 3239 */ 3240 add_defer_repro_ent(irq_ptr, which_irq, new_bind_cpu); 3241 if (drep) 3242 drep->tries++; 3243 3244 /* Inform caller to defer IOAPIC programming: */ 3245 return (1); 3246 } 3247 3248 } 3249 3250 /* Remote IRR is clear */ 3251 delete_defer_repro_ent(which_irq); 3252 3253 return (0); 3254 } 3255 3256 /* 3257 * Called to migrate all interrupts at an irq to another cpu. 3258 * Must be called with interrupts disabled and apic_ioapic_lock held 3259 */ 3260 int 3261 apic_rebind_all(apic_irq_t *irq_ptr, int bind_cpu) 3262 { 3263 apic_irq_t *irqptr = irq_ptr; 3264 int retval = 0; 3265 3266 while (irqptr) { 3267 if (irqptr->airq_temp_cpu != IRQ_UNINIT) 3268 retval |= apic_rebind(irqptr, bind_cpu, NULL); 3269 irqptr = irqptr->airq_next; 3270 } 3271 3272 return (retval); 3273 } 3274 3275 /* 3276 * apic_intr_redistribute does all the messy computations for identifying 3277 * which interrupt to move to which CPU. Currently we do just one interrupt 3278 * at a time. This reduces the time we spent doing all this within clock 3279 * interrupt. When it is done in idle, we could do more than 1. 3280 * First we find the most busy and the most free CPU (time in ISR only) 3281 * skipping those CPUs that has been identified as being ineligible (cpu_skip) 3282 * Then we look for IRQs which are closest to the difference between the 3283 * most busy CPU and the average ISR load. We try to find one whose load 3284 * is less than difference.If none exists, then we chose one larger than the 3285 * difference, provided it does not make the most idle CPU worse than the 3286 * most busy one. In the end, we clear all the busy fields for CPUs. For 3287 * IRQs, they are cleared as they are scanned. 3288 */ 3289 void 3290 apic_intr_redistribute() 3291 { 3292 int busiest_cpu, most_free_cpu; 3293 int cpu_free, cpu_busy, max_busy, min_busy; 3294 int min_free, diff; 3295 int average_busy, cpus_online; 3296 int i, busy, iflag; 3297 apic_cpus_info_t *cpu_infop; 3298 apic_irq_t *min_busy_irq = NULL; 3299 apic_irq_t *max_busy_irq = NULL; 3300 3301 busiest_cpu = most_free_cpu = -1; 3302 cpu_free = cpu_busy = max_busy = average_busy = 0; 3303 min_free = apic_sample_factor_redistribution; 3304 cpus_online = 0; 3305 /* 3306 * Below we will check for CPU_INTR_ENABLE, bound, temp_bound, temp_cpu 3307 * without ioapic_lock. That is OK as we are just doing statistical 3308 * sampling anyway and any inaccuracy now will get corrected next time 3309 * The call to rebind which actually changes things will make sure 3310 * we are consistent. 3311 */ 3312 for (i = 0; i < apic_nproc; i++) { 3313 if (!(apic_redist_cpu_skip & (1 << i)) && 3314 (apic_cpus[i].aci_status & APIC_CPU_INTR_ENABLE)) { 3315 3316 cpu_infop = &apic_cpus[i]; 3317 /* 3318 * If no unbound interrupts or only 1 total on this 3319 * CPU, skip 3320 */ 3321 if (!cpu_infop->aci_temp_bound || 3322 (cpu_infop->aci_bound + cpu_infop->aci_temp_bound) 3323 == 1) { 3324 apic_redist_cpu_skip |= 1 << i; 3325 continue; 3326 } 3327 3328 busy = cpu_infop->aci_busy; 3329 average_busy += busy; 3330 cpus_online++; 3331 if (max_busy < busy) { 3332 max_busy = busy; 3333 busiest_cpu = i; 3334 } 3335 if (min_free > busy) { 3336 min_free = busy; 3337 most_free_cpu = i; 3338 } 3339 if (busy > apic_int_busy_mark) { 3340 cpu_busy |= 1 << i; 3341 } else { 3342 if (busy < apic_int_free_mark) 3343 cpu_free |= 1 << i; 3344 } 3345 } 3346 } 3347 if ((cpu_busy && cpu_free) || 3348 (max_busy >= (min_free + apic_diff_for_redistribution))) { 3349 3350 apic_num_imbalance++; 3351 #ifdef DEBUG 3352 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) { 3353 prom_printf( 3354 "redistribute busy=%x free=%x max=%x min=%x", 3355 cpu_busy, cpu_free, max_busy, min_free); 3356 } 3357 #endif /* DEBUG */ 3358 3359 3360 average_busy /= cpus_online; 3361 3362 diff = max_busy - average_busy; 3363 min_busy = max_busy; /* start with the max possible value */ 3364 max_busy = 0; 3365 min_busy_irq = max_busy_irq = NULL; 3366 i = apic_min_device_irq; 3367 for (; i < apic_max_device_irq; i++) { 3368 apic_irq_t *irq_ptr; 3369 /* Change to linked list per CPU ? */ 3370 if ((irq_ptr = apic_irq_table[i]) == NULL) 3371 continue; 3372 /* Check for irq_busy & decide which one to move */ 3373 /* Also zero them for next round */ 3374 if ((irq_ptr->airq_temp_cpu == busiest_cpu) && 3375 irq_ptr->airq_busy) { 3376 if (irq_ptr->airq_busy < diff) { 3377 /* 3378 * Check for least busy CPU, 3379 * best fit or what ? 3380 */ 3381 if (max_busy < irq_ptr->airq_busy) { 3382 /* 3383 * Most busy within the 3384 * required differential 3385 */ 3386 max_busy = irq_ptr->airq_busy; 3387 max_busy_irq = irq_ptr; 3388 } 3389 } else { 3390 if (min_busy > irq_ptr->airq_busy) { 3391 /* 3392 * least busy, but more than 3393 * the reqd diff 3394 */ 3395 if (min_busy < 3396 (diff + average_busy - 3397 min_free)) { 3398 /* 3399 * Making sure new cpu 3400 * will not end up 3401 * worse 3402 */ 3403 min_busy = 3404 irq_ptr->airq_busy; 3405 3406 min_busy_irq = irq_ptr; 3407 } 3408 } 3409 } 3410 } 3411 irq_ptr->airq_busy = 0; 3412 } 3413 3414 if (max_busy_irq != NULL) { 3415 #ifdef DEBUG 3416 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) { 3417 prom_printf("rebinding %x to %x", 3418 max_busy_irq->airq_vector, most_free_cpu); 3419 } 3420 #endif /* DEBUG */ 3421 iflag = intr_clear(); 3422 if (lock_try(&apic_ioapic_lock)) { 3423 if (apic_rebind_all(max_busy_irq, 3424 most_free_cpu) == 0) { 3425 /* Make change permenant */ 3426 max_busy_irq->airq_cpu = 3427 (uchar_t)most_free_cpu; 3428 } 3429 lock_clear(&apic_ioapic_lock); 3430 } 3431 intr_restore(iflag); 3432 3433 } else if (min_busy_irq != NULL) { 3434 #ifdef DEBUG 3435 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) { 3436 prom_printf("rebinding %x to %x", 3437 min_busy_irq->airq_vector, most_free_cpu); 3438 } 3439 #endif /* DEBUG */ 3440 3441 iflag = intr_clear(); 3442 if (lock_try(&apic_ioapic_lock)) { 3443 if (apic_rebind_all(min_busy_irq, 3444 most_free_cpu) == 0) { 3445 /* Make change permenant */ 3446 min_busy_irq->airq_cpu = 3447 (uchar_t)most_free_cpu; 3448 } 3449 lock_clear(&apic_ioapic_lock); 3450 } 3451 intr_restore(iflag); 3452 3453 } else { 3454 if (cpu_busy != (1 << busiest_cpu)) { 3455 apic_redist_cpu_skip |= 1 << busiest_cpu; 3456 /* 3457 * We leave cpu_skip set so that next time we 3458 * can choose another cpu 3459 */ 3460 } 3461 } 3462 apic_num_rebind++; 3463 } else { 3464 /* 3465 * found nothing. Could be that we skipped over valid CPUs 3466 * or we have balanced everything. If we had a variable 3467 * ticks_for_redistribution, it could be increased here. 3468 * apic_int_busy, int_free etc would also need to be 3469 * changed. 3470 */ 3471 if (apic_redist_cpu_skip) 3472 apic_redist_cpu_skip = 0; 3473 } 3474 for (i = 0; i < apic_nproc; i++) { 3475 apic_cpus[i].aci_busy = 0; 3476 } 3477 } 3478 3479 void 3480 apic_cleanup_busy() 3481 { 3482 int i; 3483 apic_irq_t *irq_ptr; 3484 3485 for (i = 0; i < apic_nproc; i++) { 3486 apic_cpus[i].aci_busy = 0; 3487 } 3488 3489 for (i = apic_min_device_irq; i < apic_max_device_irq; i++) { 3490 if ((irq_ptr = apic_irq_table[i]) != NULL) 3491 irq_ptr->airq_busy = 0; 3492 } 3493 } 3494 3495 3496 static int 3497 apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid, 3498 int ipin, int *pci_irqp, iflag_t *intr_flagp) 3499 { 3500 3501 int status; 3502 acpi_psm_lnk_t acpipsmlnk; 3503 3504 if ((status = acpi_get_irq_cache_ent(busid, devid, ipin, pci_irqp, 3505 intr_flagp)) == ACPI_PSM_SUCCESS) { 3506 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Found irqno %d " 3507 "from cache for device %s, instance #%d\n", psm_name, 3508 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip))); 3509 return (status); 3510 } 3511 3512 bzero(&acpipsmlnk, sizeof (acpi_psm_lnk_t)); 3513 3514 if ((status = acpi_translate_pci_irq(dip, ipin, pci_irqp, intr_flagp, 3515 &acpipsmlnk)) == ACPI_PSM_FAILURE) { 3516 APIC_VERBOSE_IRQ((CE_WARN, "%s: " 3517 " acpi_translate_pci_irq failed for device %s, instance" 3518 " #%d", psm_name, ddi_get_name(dip), 3519 ddi_get_instance(dip))); 3520 return (status); 3521 } 3522 3523 if (status == ACPI_PSM_PARTIAL && acpipsmlnk.lnkobj != NULL) { 3524 status = apic_acpi_irq_configure(&acpipsmlnk, dip, pci_irqp, 3525 intr_flagp); 3526 if (status != ACPI_PSM_SUCCESS) { 3527 status = acpi_get_current_irq_resource(&acpipsmlnk, 3528 pci_irqp, intr_flagp); 3529 } 3530 } 3531 3532 if (status == ACPI_PSM_SUCCESS) { 3533 acpi_new_irq_cache_ent(busid, devid, ipin, *pci_irqp, 3534 intr_flagp, &acpipsmlnk); 3535 3536 APIC_VERBOSE_IRQ((CE_CONT, "%s: [ACPI] " 3537 "new irq %d for device %s, instance #%d\n", psm_name, 3538 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip))); 3539 } 3540 3541 return (status); 3542 } 3543 3544 /* 3545 * Adds an entry to the irq list passed in, and returns the new list. 3546 * Entries are added in priority order (lower numerical priorities are 3547 * placed closer to the head of the list) 3548 */ 3549 static prs_irq_list_t * 3550 acpi_insert_prs_irq_ent(prs_irq_list_t *listp, int priority, int irq, 3551 iflag_t *iflagp, acpi_prs_private_t *prsprvp) 3552 { 3553 struct prs_irq_list_ent *newent, *prevp = NULL, *origlistp; 3554 3555 newent = kmem_zalloc(sizeof (struct prs_irq_list_ent), KM_SLEEP); 3556 3557 newent->list_prio = priority; 3558 newent->irq = irq; 3559 newent->intrflags = *iflagp; 3560 newent->prsprv = *prsprvp; 3561 /* ->next is NULL from kmem_zalloc */ 3562 3563 /* 3564 * New list -- return the new entry as the list. 3565 */ 3566 if (listp == NULL) 3567 return (newent); 3568 3569 /* 3570 * Save original list pointer for return (since we're not modifying 3571 * the head) 3572 */ 3573 origlistp = listp; 3574 3575 /* 3576 * Insertion sort, with entries with identical keys stored AFTER 3577 * existing entries (the less-than-or-equal test of priority does 3578 * this for us). 3579 */ 3580 while (listp != NULL && listp->list_prio <= priority) { 3581 prevp = listp; 3582 listp = listp->next; 3583 } 3584 3585 newent->next = listp; 3586 3587 if (prevp == NULL) { /* Add at head of list (newent is the new head) */ 3588 return (newent); 3589 } else { 3590 prevp->next = newent; 3591 return (origlistp); 3592 } 3593 } 3594 3595 /* 3596 * Frees the list passed in, deallocating all memory and leaving *listpp 3597 * set to NULL. 3598 */ 3599 static void 3600 acpi_destroy_prs_irq_list(prs_irq_list_t **listpp) 3601 { 3602 struct prs_irq_list_ent *nextp; 3603 3604 ASSERT(listpp != NULL); 3605 3606 while (*listpp != NULL) { 3607 nextp = (*listpp)->next; 3608 kmem_free(*listpp, sizeof (struct prs_irq_list_ent)); 3609 *listpp = nextp; 3610 } 3611 } 3612 3613 /* 3614 * apic_choose_irqs_from_prs returns a list of irqs selected from the list of 3615 * irqs returned by the link device's _PRS method. The irqs are chosen 3616 * to minimize contention in situations where the interrupt link device 3617 * can be programmed to steer interrupts to different interrupt controller 3618 * inputs (some of which may already be in use). The list is sorted in order 3619 * of irqs to use, with the highest priority given to interrupt controller 3620 * inputs that are not shared. When an interrupt controller input 3621 * must be shared, apic_choose_irqs_from_prs adds the possible irqs to the 3622 * returned list in the order that minimizes sharing (thereby ensuring lowest 3623 * possible latency from interrupt trigger time to ISR execution time). 3624 */ 3625 static prs_irq_list_t * 3626 apic_choose_irqs_from_prs(acpi_irqlist_t *irqlistent, dev_info_t *dip, 3627 int crs_irq) 3628 { 3629 int32_t irq; 3630 int i; 3631 prs_irq_list_t *prsirqlistp = NULL; 3632 iflag_t iflags; 3633 3634 while (irqlistent != NULL) { 3635 irqlistent->intr_flags.bustype = BUS_PCI; 3636 3637 for (i = 0; i < irqlistent->num_irqs; i++) { 3638 3639 irq = irqlistent->irqs[i]; 3640 3641 if (irq <= 0) { 3642 /* invalid irq number */ 3643 continue; 3644 } 3645 3646 if ((irq < 16) && (apic_reserved_irqlist[irq])) 3647 continue; 3648 3649 if ((apic_irq_table[irq] == NULL) || 3650 (apic_irq_table[irq]->airq_dip == dip)) { 3651 3652 prsirqlistp = acpi_insert_prs_irq_ent( 3653 prsirqlistp, 0 /* Highest priority */, irq, 3654 &irqlistent->intr_flags, 3655 &irqlistent->acpi_prs_prv); 3656 3657 /* 3658 * If we do not prefer the current irq from _CRS 3659 * or if we do and this irq is the same as the 3660 * current irq from _CRS, this is the one 3661 * to pick. 3662 */ 3663 if (!(apic_prefer_crs) || (irq == crs_irq)) { 3664 return (prsirqlistp); 3665 } 3666 continue; 3667 } 3668 3669 /* 3670 * Edge-triggered interrupts cannot be shared 3671 */ 3672 if (irqlistent->intr_flags.intr_el == INTR_EL_EDGE) 3673 continue; 3674 3675 /* 3676 * To work around BIOSes that contain incorrect 3677 * interrupt polarity information in interrupt 3678 * descriptors returned by _PRS, we assume that 3679 * the polarity of the other device sharing this 3680 * interrupt controller input is compatible. 3681 * If it's not, the caller will catch it when 3682 * the caller invokes the link device's _CRS method 3683 * (after invoking its _SRS method). 3684 */ 3685 iflags = irqlistent->intr_flags; 3686 iflags.intr_po = 3687 apic_irq_table[irq]->airq_iflag.intr_po; 3688 3689 if (!acpi_intr_compatible(iflags, 3690 apic_irq_table[irq]->airq_iflag)) { 3691 APIC_VERBOSE_IRQ((CE_CONT, "!%s: irq %d " 3692 "not compatible [%x:%x:%x !~ %x:%x:%x]", 3693 psm_name, irq, 3694 iflags.intr_po, 3695 iflags.intr_el, 3696 iflags.bustype, 3697 apic_irq_table[irq]->airq_iflag.intr_po, 3698 apic_irq_table[irq]->airq_iflag.intr_el, 3699 apic_irq_table[irq]->airq_iflag.bustype)); 3700 continue; 3701 } 3702 3703 /* 3704 * If we prefer the irq from _CRS, no need 3705 * to search any further (and make sure 3706 * to add this irq with the highest priority 3707 * so it's tried first). 3708 */ 3709 if (crs_irq == irq && apic_prefer_crs) { 3710 3711 return (acpi_insert_prs_irq_ent( 3712 prsirqlistp, 3713 0 /* Highest priority */, 3714 irq, &iflags, 3715 &irqlistent->acpi_prs_prv)); 3716 } 3717 3718 /* 3719 * Priority is equal to the share count (lower 3720 * share count is higher priority). Note that 3721 * the intr flags passed in here are the ones we 3722 * changed above -- if incorrect, it will be 3723 * caught by the caller's _CRS flags comparison. 3724 */ 3725 prsirqlistp = acpi_insert_prs_irq_ent( 3726 prsirqlistp, 3727 apic_irq_table[irq]->airq_share, irq, 3728 &iflags, &irqlistent->acpi_prs_prv); 3729 } 3730 3731 /* Go to the next irqlist entry */ 3732 irqlistent = irqlistent->next; 3733 } 3734 3735 return (prsirqlistp); 3736 } 3737 3738 /* 3739 * Configures the irq for the interrupt link device identified by 3740 * acpipsmlnkp. 3741 * 3742 * Gets the current and the list of possible irq settings for the 3743 * device. If apic_unconditional_srs is not set, and the current 3744 * resource setting is in the list of possible irq settings, 3745 * current irq resource setting is passed to the caller. 3746 * 3747 * Otherwise, picks an irq number from the list of possible irq 3748 * settings, and sets the irq of the device to this value. 3749 * If prefer_crs is set, among a set of irq numbers in the list that have 3750 * the least number of devices sharing the interrupt, we pick current irq 3751 * resource setting if it is a member of this set. 3752 * 3753 * Passes the irq number in the value pointed to by pci_irqp, and 3754 * polarity and sensitivity in the structure pointed to by dipintrflagp 3755 * to the caller. 3756 * 3757 * Note that if setting the irq resource failed, but successfuly obtained 3758 * the current irq resource settings, passes the current irq resources 3759 * and considers it a success. 3760 * 3761 * Returns: 3762 * ACPI_PSM_SUCCESS on success. 3763 * 3764 * ACPI_PSM_FAILURE if an error occured during the configuration or 3765 * if a suitable irq was not found for this device, or if setting the 3766 * irq resource and obtaining the current resource fails. 3767 * 3768 */ 3769 static int 3770 apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip, 3771 int *pci_irqp, iflag_t *dipintr_flagp) 3772 { 3773 int32_t irq; 3774 int cur_irq = -1; 3775 acpi_irqlist_t *irqlistp; 3776 prs_irq_list_t *prs_irq_listp, *prs_irq_entp; 3777 boolean_t found_irq = B_FALSE; 3778 3779 dipintr_flagp->bustype = BUS_PCI; 3780 3781 if ((acpi_get_possible_irq_resources(acpipsmlnkp, &irqlistp)) 3782 == ACPI_PSM_FAILURE) { 3783 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Unable to determine " 3784 "or assign IRQ for device %s, instance #%d: The system was " 3785 "unable to get the list of potential IRQs from ACPI.", 3786 psm_name, ddi_get_name(dip), ddi_get_instance(dip))); 3787 3788 return (ACPI_PSM_FAILURE); 3789 } 3790 3791 if ((acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq, 3792 dipintr_flagp) == ACPI_PSM_SUCCESS) && (!apic_unconditional_srs) && 3793 (cur_irq > 0)) { 3794 /* 3795 * If an IRQ is set in CRS and that IRQ exists in the set 3796 * returned from _PRS, return that IRQ, otherwise print 3797 * a warning 3798 */ 3799 3800 if (acpi_irqlist_find_irq(irqlistp, cur_irq, NULL) 3801 == ACPI_PSM_SUCCESS) { 3802 3803 ASSERT(pci_irqp != NULL); 3804 *pci_irqp = cur_irq; 3805 acpi_free_irqlist(irqlistp); 3806 return (ACPI_PSM_SUCCESS); 3807 } 3808 3809 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find the " 3810 "current irq %d for device %s, instance #%d in ACPI's " 3811 "list of possible irqs for this device. Picking one from " 3812 " the latter list.", psm_name, cur_irq, ddi_get_name(dip), 3813 ddi_get_instance(dip))); 3814 } 3815 3816 if ((prs_irq_listp = apic_choose_irqs_from_prs(irqlistp, dip, 3817 cur_irq)) == NULL) { 3818 3819 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find a " 3820 "suitable irq from the list of possible irqs for device " 3821 "%s, instance #%d in ACPI's list of possible irqs", 3822 psm_name, ddi_get_name(dip), ddi_get_instance(dip))); 3823 3824 acpi_free_irqlist(irqlistp); 3825 return (ACPI_PSM_FAILURE); 3826 } 3827 3828 acpi_free_irqlist(irqlistp); 3829 3830 for (prs_irq_entp = prs_irq_listp; 3831 prs_irq_entp != NULL && found_irq == B_FALSE; 3832 prs_irq_entp = prs_irq_entp->next) { 3833 3834 acpipsmlnkp->acpi_prs_prv = prs_irq_entp->prsprv; 3835 irq = prs_irq_entp->irq; 3836 3837 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Setting irq %d for " 3838 "device %s instance #%d\n", psm_name, irq, 3839 ddi_get_name(dip), ddi_get_instance(dip))); 3840 3841 if ((acpi_set_irq_resource(acpipsmlnkp, irq)) 3842 == ACPI_PSM_SUCCESS) { 3843 /* 3844 * setting irq was successful, check to make sure CRS 3845 * reflects that. If CRS does not agree with what we 3846 * set, return the irq that was set. 3847 */ 3848 3849 if (acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq, 3850 dipintr_flagp) == ACPI_PSM_SUCCESS) { 3851 3852 if (cur_irq != irq) 3853 APIC_VERBOSE_IRQ((CE_WARN, 3854 "!%s: IRQ resource set " 3855 "(irqno %d) for device %s " 3856 "instance #%d, differs from " 3857 "current setting irqno %d", 3858 psm_name, irq, ddi_get_name(dip), 3859 ddi_get_instance(dip), cur_irq)); 3860 } else { 3861 /* 3862 * On at least one system, there was a bug in 3863 * a DSDT method called by _STA, causing _STA to 3864 * indicate that the link device was disabled 3865 * (when, in fact, it was enabled). Since _SRS 3866 * succeeded, assume that _CRS is lying and use 3867 * the iflags from this _PRS interrupt choice. 3868 * If we're wrong about the flags, the polarity 3869 * will be incorrect and we may get an interrupt 3870 * storm, but there's not much else we can do 3871 * at this point. 3872 */ 3873 *dipintr_flagp = prs_irq_entp->intrflags; 3874 } 3875 3876 /* 3877 * Return the irq that was set, and not what _CRS 3878 * reports, since _CRS has been seen to return 3879 * different IRQs than what was passed to _SRS on some 3880 * systems (and just not return successfully on others). 3881 */ 3882 cur_irq = irq; 3883 found_irq = B_TRUE; 3884 } else { 3885 APIC_VERBOSE_IRQ((CE_WARN, "!%s: set resource " 3886 "irq %d failed for device %s instance #%d", 3887 psm_name, irq, ddi_get_name(dip), 3888 ddi_get_instance(dip))); 3889 3890 if (cur_irq == -1) { 3891 acpi_destroy_prs_irq_list(&prs_irq_listp); 3892 return (ACPI_PSM_FAILURE); 3893 } 3894 } 3895 } 3896 3897 acpi_destroy_prs_irq_list(&prs_irq_listp); 3898 3899 if (!found_irq) 3900 return (ACPI_PSM_FAILURE); 3901 3902 ASSERT(pci_irqp != NULL); 3903 *pci_irqp = cur_irq; 3904 return (ACPI_PSM_SUCCESS); 3905 } 3906 3907 void 3908 ioapic_disable_redirection() 3909 { 3910 int ioapic_ix; 3911 int intin_max; 3912 int intin_ix; 3913 3914 /* Disable the I/O APIC redirection entries */ 3915 for (ioapic_ix = 0; ioapic_ix < apic_io_max; ioapic_ix++) { 3916 3917 /* Bits 23-16 define the maximum redirection entries */ 3918 intin_max = (ioapic_read(ioapic_ix, APIC_VERS_CMD) >> 16) 3919 & 0xff; 3920 3921 for (intin_ix = 0; intin_ix < intin_max; intin_ix++) { 3922 /* 3923 * The assumption here is that this is safe, even for 3924 * systems with IOAPICs that suffer from the hardware 3925 * erratum because all devices have been quiesced before 3926 * this function is called from apic_shutdown() 3927 * (or equivalent). If that assumption turns out to be 3928 * false, this mask operation can induce the same 3929 * erratum result we're trying to avoid. 3930 */ 3931 ioapic_write(ioapic_ix, APIC_RDT_CMD + 2 * intin_ix, 3932 AV_MASK); 3933 } 3934 } 3935 } 3936 3937 /* 3938 * Looks for an IOAPIC with the specified physical address in the /ioapics 3939 * node in the device tree (created by the PCI enumerator). 3940 */ 3941 static boolean_t 3942 apic_is_ioapic_AMD_813x(uint32_t physaddr) 3943 { 3944 /* 3945 * Look in /ioapics, for the ioapic with 3946 * the physical address given 3947 */ 3948 dev_info_t *ioapicsnode = ddi_find_devinfo(IOAPICS_NODE_NAME, -1, 0); 3949 dev_info_t *ioapic_child; 3950 boolean_t rv = B_FALSE; 3951 int vid, did; 3952 uint64_t ioapic_paddr; 3953 boolean_t done = B_FALSE; 3954 3955 if (ioapicsnode == NULL) 3956 return (B_FALSE); 3957 3958 /* Load first child: */ 3959 ioapic_child = ddi_get_child(ioapicsnode); 3960 while (!done && ioapic_child != 0) { /* Iterate over children */ 3961 3962 if ((ioapic_paddr = (uint64_t)ddi_prop_get_int64(DDI_DEV_T_ANY, 3963 ioapic_child, DDI_PROP_DONTPASS, "reg", 0)) 3964 != 0 && physaddr == ioapic_paddr) { 3965 3966 vid = ddi_prop_get_int(DDI_DEV_T_ANY, ioapic_child, 3967 DDI_PROP_DONTPASS, IOAPICS_PROP_VENID, 0); 3968 3969 if (vid == VENID_AMD) { 3970 3971 did = ddi_prop_get_int(DDI_DEV_T_ANY, 3972 ioapic_child, DDI_PROP_DONTPASS, 3973 IOAPICS_PROP_DEVID, 0); 3974 3975 if (did == DEVID_8131_IOAPIC || 3976 did == DEVID_8132_IOAPIC) { 3977 3978 rv = B_TRUE; 3979 done = B_TRUE; 3980 } 3981 } 3982 } 3983 3984 if (!done) 3985 ioapic_child = ddi_get_next_sibling(ioapic_child); 3986 } 3987 3988 /* The ioapics node was held by ddi_find_devinfo, so release it */ 3989 ndi_rele_devi(ioapicsnode); 3990 return (rv); 3991 } 3992