1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * PSMI 1.1 extensions are supported only in 2.6 and later versions. 30 * PSMI 1.2 extensions are supported only in 2.7 and later versions. 31 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10. 32 * PSMI 1.5 extensions are supported in Solaris Nevada. 33 */ 34 #define PSMI_1_5 35 36 #include <sys/processor.h> 37 #include <sys/time.h> 38 #include <sys/psm.h> 39 #include <sys/smp_impldefs.h> 40 #include <sys/cram.h> 41 #include <sys/acpi/acpi.h> 42 #include <sys/acpica.h> 43 #include <sys/psm_common.h> 44 #include <sys/apic.h> 45 #include <sys/pit.h> 46 #include <sys/ddi.h> 47 #include <sys/sunddi.h> 48 #include <sys/ddi_impldefs.h> 49 #include <sys/pci.h> 50 #include <sys/promif.h> 51 #include <sys/x86_archext.h> 52 #include <sys/cpc_impl.h> 53 #include <sys/uadmin.h> 54 #include <sys/panic.h> 55 #include <sys/debug.h> 56 #include <sys/archsystm.h> 57 #include <sys/trap.h> 58 #include <sys/machsystm.h> 59 #include <sys/cpuvar.h> 60 #include <sys/rm_platter.h> 61 #include <sys/privregs.h> 62 #include <sys/cyclic.h> 63 #include <sys/note.h> 64 #include <sys/pci_intr_lib.h> 65 #include <sys/sunndi.h> 66 67 68 /* 69 * Local Function Prototypes 70 */ 71 static int apic_handle_defconf(); 72 static int apic_parse_mpct(caddr_t mpct, int bypass); 73 static struct apic_mpfps_hdr *apic_find_fps_sig(caddr_t fptr, int size); 74 static int apic_checksum(caddr_t bptr, int len); 75 static int apic_find_bus_type(char *bus); 76 static int apic_find_bus(int busid); 77 static int apic_find_bus_id(int bustype); 78 static struct apic_io_intr *apic_find_io_intr(int irqno); 79 static int apic_find_free_irq(int start, int end); 80 static void apic_mark_vector(uchar_t oldvector, uchar_t newvector); 81 static void apic_xlate_vector_free_timeout_handler(void *arg); 82 static void apic_reprogram_timeout_handler(void *arg); 83 static int apic_check_stuck_interrupt(apic_irq_t *irq_ptr, int old_bind_cpu, 84 int new_bind_cpu, int apicindex, int intin_no, int which_irq, 85 struct ioapic_reprogram_data *drep); 86 static void apic_record_rdt_entry(apic_irq_t *irqptr, int irq); 87 static struct apic_io_intr *apic_find_io_intr_w_busid(int irqno, int busid); 88 static int apic_find_intin(uchar_t ioapic, uchar_t intin); 89 static int apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, 90 int child_ipin, struct apic_io_intr **intrp); 91 static int apic_setup_irq_table(dev_info_t *dip, int irqno, 92 struct apic_io_intr *intrp, struct intrspec *ispec, iflag_t *intr_flagp, 93 int type); 94 static int apic_setup_sci_irq_table(int irqno, uchar_t ipl, 95 iflag_t *intr_flagp); 96 static void apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp); 97 static void apic_try_deferred_reprogram(int ipl, int vect); 98 static void delete_defer_repro_ent(int which_irq); 99 static void apic_ioapic_wait_pending_clear(int ioapicindex, 100 int intin_no); 101 static boolean_t apic_is_ioapic_AMD_813x(uint32_t physaddr); 102 103 int apic_debug_mps_id = 0; /* 1 - print MPS ID strings */ 104 105 /* ACPI SCI interrupt configuration; -1 if SCI not used */ 106 int apic_sci_vect = -1; 107 iflag_t apic_sci_flags; 108 109 /* 110 * psm name pointer 111 */ 112 static char *psm_name; 113 114 /* ACPI support routines */ 115 static int acpi_probe(char *); 116 static int apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip, 117 int *pci_irqp, iflag_t *intr_flagp); 118 119 static int apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid, 120 int ipin, int *pci_irqp, iflag_t *intr_flagp); 121 static uchar_t acpi_find_ioapic(int irq); 122 static int acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2); 123 124 125 /* 126 * number of bits per byte, from <sys/param.h> 127 */ 128 #define UCHAR_MAX ((1 << NBBY) - 1) 129 130 /* Max wait time (in repetitions) for flags to clear in an RDT entry. */ 131 int apic_max_reps_clear_pending = 1000; 132 133 /* The irq # is implicit in the array index: */ 134 struct ioapic_reprogram_data apic_reprogram_info[APIC_MAX_VECTOR+1]; 135 /* 136 * APIC_MAX_VECTOR + 1 is the maximum # of IRQs as well. ioapic_reprogram_info 137 * is indexed by IRQ number, NOT by vector number. 138 */ 139 140 int apic_intr_policy = INTR_ROUND_ROBIN_WITH_AFFINITY; 141 142 int apic_next_bind_cpu = 1; /* For round robin assignment */ 143 /* start with cpu 1 */ 144 145 /* 146 * If enabled, the distribution works as follows: 147 * On every interrupt entry, the current ipl for the CPU is set in cpu_info 148 * and the irq corresponding to the ipl is also set in the aci_current array. 149 * interrupt exit and setspl (due to soft interrupts) will cause the current 150 * ipl to be be changed. This is cache friendly as these frequently used 151 * paths write into a per cpu structure. 152 * 153 * Sampling is done by checking the structures for all CPUs and incrementing 154 * the busy field of the irq (if any) executing on each CPU and the busy field 155 * of the corresponding CPU. 156 * In periodic mode this is done on every clock interrupt. 157 * In one-shot mode, this is done thru a cyclic with an interval of 158 * apic_redistribute_sample_interval (default 10 milli sec). 159 * 160 * Every apic_sample_factor_redistribution times we sample, we do computations 161 * to decide which interrupt needs to be migrated (see comments 162 * before apic_intr_redistribute(). 163 */ 164 165 /* 166 * Following 3 variables start as % and can be patched or set using an 167 * API to be defined in future. They will be scaled to 168 * sample_factor_redistribution which is in turn set to hertz+1 (in periodic 169 * mode), or 101 in one-shot mode to stagger it away from one sec processing 170 */ 171 172 int apic_int_busy_mark = 60; 173 int apic_int_free_mark = 20; 174 int apic_diff_for_redistribution = 10; 175 176 /* sampling interval for interrupt redistribution for dynamic migration */ 177 int apic_redistribute_sample_interval = NANOSEC / 100; /* 10 millisec */ 178 179 /* 180 * number of times we sample before deciding to redistribute interrupts 181 * for dynamic migration 182 */ 183 int apic_sample_factor_redistribution = 101; 184 185 /* timeout for xlate_vector, mark_vector */ 186 int apic_revector_timeout = 16 * 10000; /* 160 millisec */ 187 188 int apic_redist_cpu_skip = 0; 189 int apic_num_imbalance = 0; 190 int apic_num_rebind = 0; 191 192 int apic_nproc = 0; 193 size_t apic_cpus_size = 0; 194 int apic_defconf = 0; 195 int apic_irq_translate = 0; 196 int apic_spec_rev = 0; 197 int apic_imcrp = 0; 198 199 int apic_use_acpi = 1; /* 1 = use ACPI, 0 = don't use ACPI */ 200 int apic_use_acpi_madt_only = 0; /* 1=ONLY use MADT from ACPI */ 201 202 /* 203 * For interrupt link devices, if apic_unconditional_srs is set, an irq resource 204 * will be assigned (via _SRS). If it is not set, use the current 205 * irq setting (via _CRS), but only if that irq is in the set of possible 206 * irqs (returned by _PRS) for the device. 207 */ 208 int apic_unconditional_srs = 1; 209 210 /* 211 * For interrupt link devices, if apic_prefer_crs is set when we are 212 * assigning an IRQ resource to a device, prefer the current IRQ setting 213 * over other possible irq settings under same conditions. 214 */ 215 216 int apic_prefer_crs = 1; 217 218 uchar_t apic_io_id[MAX_IO_APIC]; 219 volatile uint32_t *apicioadr[MAX_IO_APIC]; 220 static uchar_t apic_io_ver[MAX_IO_APIC]; 221 static uchar_t apic_io_vectbase[MAX_IO_APIC]; 222 static uchar_t apic_io_vectend[MAX_IO_APIC]; 223 uchar_t apic_reserved_irqlist[MAX_ISA_IRQ + 1]; 224 uint32_t apic_physaddr[MAX_IO_APIC]; 225 226 static boolean_t ioapic_mask_workaround[MAX_IO_APIC]; 227 228 /* 229 * First available slot to be used as IRQ index into the apic_irq_table 230 * for those interrupts (like MSI/X) that don't have a physical IRQ. 231 */ 232 int apic_first_avail_irq = APIC_FIRST_FREE_IRQ; 233 234 /* 235 * apic_ioapic_lock protects the ioapics (reg select), the status, temp_bound 236 * and bound elements of cpus_info and the temp_cpu element of irq_struct 237 */ 238 lock_t apic_ioapic_lock; 239 240 /* 241 * apic_defer_reprogram_lock ensures that only one processor is handling 242 * deferred interrupt programming at apic_intr_exit time. 243 */ 244 static lock_t apic_defer_reprogram_lock; 245 246 /* 247 * The current number of deferred reprogrammings outstanding 248 */ 249 uint_t apic_reprogram_outstanding = 0; 250 251 #ifdef DEBUG 252 /* 253 * Counters that keep track of deferred reprogramming stats 254 */ 255 uint_t apic_intr_deferrals = 0; 256 uint_t apic_intr_deliver_timeouts = 0; 257 uint_t apic_last_ditch_reprogram_failures = 0; 258 uint_t apic_deferred_setup_failures = 0; 259 uint_t apic_defer_repro_total_retries = 0; 260 uint_t apic_defer_repro_successes = 0; 261 uint_t apic_deferred_spurious_enters = 0; 262 #endif 263 264 static int apic_io_max = 0; /* no. of i/o apics enabled */ 265 266 static struct apic_io_intr *apic_io_intrp = 0; 267 static struct apic_bus *apic_busp; 268 269 uchar_t apic_vector_to_irq[APIC_MAX_VECTOR+1]; 270 uchar_t apic_resv_vector[MAXIPL+1]; 271 272 char apic_level_intr[APIC_MAX_VECTOR+1]; 273 274 static uint32_t eisa_level_intr_mask = 0; 275 /* At least MSB will be set if EISA bus */ 276 277 static int apic_pci_bus_total = 0; 278 static uchar_t apic_single_pci_busid = 0; 279 280 /* 281 * airq_mutex protects additions to the apic_irq_table - the first 282 * pointer and any airq_nexts off of that one. It also protects 283 * apic_max_device_irq & apic_min_device_irq. It also guarantees 284 * that share_id is unique as new ids are generated only when new 285 * irq_t structs are linked in. Once linked in the structs are never 286 * deleted. temp_cpu & mps_intr_index field indicate if it is programmed 287 * or allocated. Note that there is a slight gap between allocating in 288 * apic_introp_xlate and programming in addspl. 289 */ 290 kmutex_t airq_mutex; 291 apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1]; 292 int apic_max_device_irq = 0; 293 int apic_min_device_irq = APIC_MAX_VECTOR; 294 295 /* 296 * Following declarations are for revectoring; used when ISRs at different 297 * IPLs share an irq. 298 */ 299 static lock_t apic_revector_lock; 300 int apic_revector_pending = 0; 301 static uchar_t *apic_oldvec_to_newvec; 302 static uchar_t *apic_newvec_to_oldvec; 303 304 typedef struct prs_irq_list_ent { 305 int list_prio; 306 int32_t irq; 307 iflag_t intrflags; 308 acpi_prs_private_t prsprv; 309 struct prs_irq_list_ent *next; 310 } prs_irq_list_t; 311 312 313 /* 314 * ACPI variables 315 */ 316 /* 1 = acpi is enabled & working, 0 = acpi is not enabled or not there */ 317 int apic_enable_acpi = 0; 318 319 /* ACPI Multiple APIC Description Table ptr */ 320 static MULTIPLE_APIC_TABLE *acpi_mapic_dtp = NULL; 321 322 /* ACPI Interrupt Source Override Structure ptr */ 323 static MADT_INTERRUPT_OVERRIDE *acpi_isop = NULL; 324 static int acpi_iso_cnt = 0; 325 326 /* ACPI Non-maskable Interrupt Sources ptr */ 327 static MADT_NMI_SOURCE *acpi_nmi_sp = NULL; 328 static int acpi_nmi_scnt = 0; 329 static MADT_LOCAL_APIC_NMI *acpi_nmi_cp = NULL; 330 static int acpi_nmi_ccnt = 0; 331 332 extern int apic_pci_msi_enable_vector(dev_info_t *, int, int, 333 int, int, int); 334 extern apic_irq_t *apic_find_irq(dev_info_t *, struct intrspec *, int); 335 336 /* 337 * The following added to identify a software poweroff method if available. 338 */ 339 340 static struct { 341 int poweroff_method; 342 char oem_id[APIC_MPS_OEM_ID_LEN + 1]; /* MAX + 1 for NULL */ 343 char prod_id[APIC_MPS_PROD_ID_LEN + 1]; /* MAX + 1 for NULL */ 344 } apic_mps_ids[] = { 345 { APIC_POWEROFF_VIA_RTC, "INTEL", "ALDER" }, /* 4300 */ 346 { APIC_POWEROFF_VIA_RTC, "NCR", "AMC" }, /* 4300 */ 347 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "A450NX" }, /* 4400? */ 348 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AD450NX" }, /* 4400 */ 349 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AC450NX" }, /* 4400R */ 350 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "S450NX" }, /* S50 */ 351 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "SC450NX" } /* S50? */ 352 }; 353 354 int apic_poweroff_method = APIC_POWEROFF_NONE; 355 356 /* 357 * Auto-configuration routines 358 */ 359 360 /* 361 * Look at MPSpec 1.4 (Intel Order # 242016-005) for details of what we do here 362 * May work with 1.1 - but not guaranteed. 363 * According to the MP Spec, the MP floating pointer structure 364 * will be searched in the order described below: 365 * 1. In the first kilobyte of Extended BIOS Data Area (EBDA) 366 * 2. Within the last kilobyte of system base memory 367 * 3. In the BIOS ROM address space between 0F0000h and 0FFFFh 368 * Once we find the right signature with proper checksum, we call 369 * either handle_defconf or parse_mpct to get all info necessary for 370 * subsequent operations. 371 */ 372 int 373 apic_probe_common(char *modname) 374 { 375 uint32_t mpct_addr, ebda_start = 0, base_mem_end; 376 caddr_t biosdatap; 377 caddr_t mpct; 378 caddr_t fptr; 379 int i, mpct_size, mapsize, retval = PSM_FAILURE; 380 ushort_t ebda_seg, base_mem_size; 381 struct apic_mpfps_hdr *fpsp; 382 struct apic_mp_cnf_hdr *hdrp; 383 int bypass_cpu_and_ioapics_in_mptables; 384 int acpi_user_options; 385 386 if (apic_forceload < 0) 387 return (retval); 388 389 /* 390 * Remember who we are 391 */ 392 psm_name = modname; 393 394 /* Allow override for MADT-only mode */ 395 acpi_user_options = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_root_node(), 0, 396 "acpi-user-options", 0); 397 apic_use_acpi_madt_only = ((acpi_user_options & ACPI_OUSER_MADT) != 0); 398 399 /* Allow apic_use_acpi to override MADT-only mode */ 400 if (!apic_use_acpi) 401 apic_use_acpi_madt_only = 0; 402 403 retval = acpi_probe(modname); 404 405 /* 406 * mapin the bios data area 40:0 407 * 40:13h - two-byte location reports the base memory size 408 * 40:0Eh - two-byte location for the exact starting address of 409 * the EBDA segment for EISA 410 */ 411 biosdatap = psm_map_phys(0x400, 0x20, PROT_READ); 412 if (!biosdatap) 413 return (retval); 414 fpsp = (struct apic_mpfps_hdr *)NULL; 415 mapsize = MPFPS_RAM_WIN_LEN; 416 /*LINTED: pointer cast may result in improper alignment */ 417 ebda_seg = *((ushort_t *)(biosdatap+0xe)); 418 /* check the 1k of EBDA */ 419 if (ebda_seg) { 420 ebda_start = ((uint32_t)ebda_seg) << 4; 421 fptr = psm_map_phys(ebda_start, MPFPS_RAM_WIN_LEN, PROT_READ); 422 if (fptr) { 423 if (!(fpsp = 424 apic_find_fps_sig(fptr, MPFPS_RAM_WIN_LEN))) 425 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN); 426 } 427 } 428 /* If not in EBDA, check the last k of system base memory */ 429 if (!fpsp) { 430 /*LINTED: pointer cast may result in improper alignment */ 431 base_mem_size = *((ushort_t *)(biosdatap + 0x13)); 432 433 if (base_mem_size > 512) 434 base_mem_end = 639 * 1024; 435 else 436 base_mem_end = 511 * 1024; 437 /* if ebda == last k of base mem, skip to check BIOS ROM */ 438 if (base_mem_end != ebda_start) { 439 440 fptr = psm_map_phys(base_mem_end, MPFPS_RAM_WIN_LEN, 441 PROT_READ); 442 443 if (fptr) { 444 if (!(fpsp = apic_find_fps_sig(fptr, 445 MPFPS_RAM_WIN_LEN))) 446 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN); 447 } 448 } 449 } 450 psm_unmap_phys(biosdatap, 0x20); 451 452 /* If still cannot find it, check the BIOS ROM space */ 453 if (!fpsp) { 454 mapsize = MPFPS_ROM_WIN_LEN; 455 fptr = psm_map_phys(MPFPS_ROM_WIN_START, 456 MPFPS_ROM_WIN_LEN, PROT_READ); 457 if (fptr) { 458 if (!(fpsp = 459 apic_find_fps_sig(fptr, MPFPS_ROM_WIN_LEN))) { 460 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 461 return (retval); 462 } 463 } 464 } 465 466 if (apic_checksum((caddr_t)fpsp, fpsp->mpfps_length * 16) != 0) { 467 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 468 return (retval); 469 } 470 471 apic_spec_rev = fpsp->mpfps_spec_rev; 472 if ((apic_spec_rev != 04) && (apic_spec_rev != 01)) { 473 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 474 return (retval); 475 } 476 477 /* check IMCR is present or not */ 478 apic_imcrp = fpsp->mpfps_featinfo2 & MPFPS_FEATINFO2_IMCRP; 479 480 /* check default configuration (dual CPUs) */ 481 if ((apic_defconf = fpsp->mpfps_featinfo1) != 0) { 482 psm_unmap_phys(fptr, mapsize); 483 return (apic_handle_defconf()); 484 } 485 486 /* MP Configuration Table */ 487 mpct_addr = (uint32_t)(fpsp->mpfps_mpct_paddr); 488 489 psm_unmap_phys(fptr, mapsize); /* unmap floating ptr struct */ 490 491 /* 492 * Map in enough memory for the MP Configuration Table Header. 493 * Use this table to read the total length of the BIOS data and 494 * map in all the info 495 */ 496 /*LINTED: pointer cast may result in improper alignment */ 497 hdrp = (struct apic_mp_cnf_hdr *)psm_map_phys(mpct_addr, 498 sizeof (struct apic_mp_cnf_hdr), PROT_READ); 499 if (!hdrp) 500 return (retval); 501 502 /* check mp configuration table signature PCMP */ 503 if (hdrp->mpcnf_sig != 0x504d4350) { 504 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr)); 505 return (retval); 506 } 507 mpct_size = (int)hdrp->mpcnf_tbl_length; 508 509 apic_set_pwroff_method_from_mpcnfhdr(hdrp); 510 511 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr)); 512 513 if ((retval == PSM_SUCCESS) && !apic_use_acpi_madt_only) { 514 /* This is an ACPI machine No need for further checks */ 515 return (retval); 516 } 517 518 /* 519 * Map in the entries for this machine, ie. Processor 520 * Entry Tables, Bus Entry Tables, etc. 521 * They are in fixed order following one another 522 */ 523 mpct = psm_map_phys(mpct_addr, mpct_size, PROT_READ); 524 if (!mpct) 525 return (retval); 526 527 if (apic_checksum(mpct, mpct_size) != 0) 528 goto apic_fail1; 529 530 531 /*LINTED: pointer cast may result in improper alignment */ 532 hdrp = (struct apic_mp_cnf_hdr *)mpct; 533 apicadr = (uint32_t *)mapin_apic((uint32_t)hdrp->mpcnf_local_apic, 534 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE); 535 if (!apicadr) 536 goto apic_fail1; 537 538 /* Parse all information in the tables */ 539 bypass_cpu_and_ioapics_in_mptables = (retval == PSM_SUCCESS); 540 if (apic_parse_mpct(mpct, bypass_cpu_and_ioapics_in_mptables) == 541 PSM_SUCCESS) 542 return (PSM_SUCCESS); 543 544 for (i = 0; i < apic_io_max; i++) 545 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN); 546 if (apic_cpus) 547 kmem_free(apic_cpus, apic_cpus_size); 548 if (apicadr) 549 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 550 apic_fail1: 551 psm_unmap_phys(mpct, mpct_size); 552 return (retval); 553 } 554 555 static void 556 apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp) 557 { 558 int i; 559 560 for (i = 0; i < (sizeof (apic_mps_ids) / sizeof (apic_mps_ids[0])); 561 i++) { 562 if ((strncmp(hdrp->mpcnf_oem_str, apic_mps_ids[i].oem_id, 563 strlen(apic_mps_ids[i].oem_id)) == 0) && 564 (strncmp(hdrp->mpcnf_prod_str, apic_mps_ids[i].prod_id, 565 strlen(apic_mps_ids[i].prod_id)) == 0)) { 566 567 apic_poweroff_method = apic_mps_ids[i].poweroff_method; 568 break; 569 } 570 } 571 572 if (apic_debug_mps_id != 0) { 573 cmn_err(CE_CONT, "%s: MPS OEM ID = '%c%c%c%c%c%c%c%c'" 574 "Product ID = '%c%c%c%c%c%c%c%c%c%c%c%c'\n", 575 psm_name, 576 hdrp->mpcnf_oem_str[0], 577 hdrp->mpcnf_oem_str[1], 578 hdrp->mpcnf_oem_str[2], 579 hdrp->mpcnf_oem_str[3], 580 hdrp->mpcnf_oem_str[4], 581 hdrp->mpcnf_oem_str[5], 582 hdrp->mpcnf_oem_str[6], 583 hdrp->mpcnf_oem_str[7], 584 hdrp->mpcnf_prod_str[0], 585 hdrp->mpcnf_prod_str[1], 586 hdrp->mpcnf_prod_str[2], 587 hdrp->mpcnf_prod_str[3], 588 hdrp->mpcnf_prod_str[4], 589 hdrp->mpcnf_prod_str[5], 590 hdrp->mpcnf_prod_str[6], 591 hdrp->mpcnf_prod_str[7], 592 hdrp->mpcnf_prod_str[8], 593 hdrp->mpcnf_prod_str[9], 594 hdrp->mpcnf_prod_str[10], 595 hdrp->mpcnf_prod_str[11]); 596 } 597 } 598 599 static int 600 acpi_probe(char *modname) 601 { 602 int i, intmax, index, rv; 603 uint32_t id, ver; 604 int acpi_verboseflags = 0; 605 int madt_seen, madt_size; 606 APIC_HEADER *ap; 607 MADT_PROCESSOR_APIC *mpa; 608 MADT_IO_APIC *mia; 609 MADT_IO_SAPIC *misa; 610 MADT_INTERRUPT_OVERRIDE *mio; 611 MADT_NMI_SOURCE *mns; 612 MADT_INTERRUPT_SOURCE *mis; 613 MADT_LOCAL_APIC_NMI *mlan; 614 MADT_ADDRESS_OVERRIDE *mao; 615 ACPI_OBJECT_LIST arglist; 616 ACPI_OBJECT arg; 617 int sci; 618 iflag_t sci_flags; 619 volatile uint32_t *ioapic; 620 int apic_ix; 621 char local_ids[NCPU]; 622 char proc_ids[NCPU]; 623 uchar_t hid; 624 625 if (!apic_use_acpi) 626 return (PSM_FAILURE); 627 628 if (AcpiGetFirmwareTable(APIC_SIG, 1, ACPI_LOGICAL_ADDRESSING, 629 (ACPI_TABLE_HEADER **) &acpi_mapic_dtp) != AE_OK) 630 return (PSM_FAILURE); 631 632 apicadr = mapin_apic((uint32_t)acpi_mapic_dtp->LocalApicAddress, 633 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE); 634 if (!apicadr) 635 return (PSM_FAILURE); 636 637 id = apicadr[APIC_LID_REG]; 638 local_ids[0] = (uchar_t)(id >> 24); 639 apic_nproc = index = 1; 640 CPUSET_ONLY(apic_cpumask, 0); 641 apic_io_max = 0; 642 643 ap = (APIC_HEADER *) (acpi_mapic_dtp + 1); 644 madt_size = acpi_mapic_dtp->Length; 645 madt_seen = sizeof (*acpi_mapic_dtp); 646 647 while (madt_seen < madt_size) { 648 switch (ap->Type) { 649 case APIC_PROCESSOR: 650 mpa = (MADT_PROCESSOR_APIC *) ap; 651 if (mpa->ProcessorEnabled) { 652 if (mpa->LocalApicId == local_ids[0]) { 653 proc_ids[0] = mpa->ProcessorId; 654 acpica_map_cpu(0, mpa); 655 } else if (apic_nproc < NCPU) { 656 local_ids[index] = mpa->LocalApicId; 657 proc_ids[index] = mpa->ProcessorId; 658 CPUSET_ADD(apic_cpumask, index); 659 acpica_map_cpu(index, mpa); 660 index++; 661 apic_nproc++; 662 } else 663 cmn_err(CE_WARN, "%s: exceeded " 664 "maximum no. of CPUs (= %d)", 665 psm_name, NCPU); 666 } 667 break; 668 669 case APIC_IO: 670 mia = (MADT_IO_APIC *) ap; 671 if (apic_io_max < MAX_IO_APIC) { 672 apic_ix = apic_io_max; 673 apic_io_id[apic_io_max] = mia->IoApicId; 674 apic_io_vectbase[apic_io_max] = 675 mia->Interrupt; 676 apic_physaddr[apic_io_max] = 677 (uint32_t)mia->Address; 678 ioapic = apicioadr[apic_io_max] = 679 mapin_ioapic((uint32_t)mia->Address, 680 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 681 if (!ioapic) 682 goto cleanup; 683 ioapic_mask_workaround[apic_io_max] = 684 apic_is_ioapic_AMD_813x(mia->Address); 685 apic_io_max++; 686 } 687 break; 688 689 case APIC_XRUPT_OVERRIDE: 690 mio = (MADT_INTERRUPT_OVERRIDE *) ap; 691 if (acpi_isop == NULL) 692 acpi_isop = mio; 693 acpi_iso_cnt++; 694 break; 695 696 case APIC_NMI: 697 /* UNIMPLEMENTED */ 698 mns = (MADT_NMI_SOURCE *) ap; 699 if (acpi_nmi_sp == NULL) 700 acpi_nmi_sp = mns; 701 acpi_nmi_scnt++; 702 703 cmn_err(CE_NOTE, "!apic: nmi source: %d %d %d\n", 704 mns->Interrupt, mns->Polarity, 705 mns->TriggerMode); 706 break; 707 708 case APIC_LOCAL_NMI: 709 /* UNIMPLEMENTED */ 710 mlan = (MADT_LOCAL_APIC_NMI *) ap; 711 if (acpi_nmi_cp == NULL) 712 acpi_nmi_cp = mlan; 713 acpi_nmi_ccnt++; 714 715 cmn_err(CE_NOTE, "!apic: local nmi: %d %d %d %d\n", 716 mlan->ProcessorId, mlan->Polarity, 717 mlan->TriggerMode, mlan->Lint); 718 break; 719 720 case APIC_ADDRESS_OVERRIDE: 721 /* UNIMPLEMENTED */ 722 mao = (MADT_ADDRESS_OVERRIDE *) ap; 723 cmn_err(CE_NOTE, "!apic: address override: %lx\n", 724 (long)mao->Address); 725 break; 726 727 case APIC_IO_SAPIC: 728 /* UNIMPLEMENTED */ 729 misa = (MADT_IO_SAPIC *) ap; 730 731 cmn_err(CE_NOTE, "!apic: io sapic: %d %d %lx\n", 732 misa->IoSapicId, misa->InterruptBase, 733 (long)misa->Address); 734 break; 735 736 case APIC_XRUPT_SOURCE: 737 /* UNIMPLEMENTED */ 738 mis = (MADT_INTERRUPT_SOURCE *) ap; 739 740 cmn_err(CE_NOTE, 741 "!apic: irq source: %d %d %d %d %d %d %d\n", 742 mis->ProcessorId, mis->ProcessorEid, 743 mis->Interrupt, mis->Polarity, 744 mis->TriggerMode, mis->InterruptType, 745 mis->IoSapicVector); 746 break; 747 default: 748 break; 749 } 750 751 /* advance to next entry */ 752 madt_seen += ap->Length; 753 ap = (APIC_HEADER *)(((char *)ap) + ap->Length); 754 } 755 756 apic_cpus_size = apic_nproc * sizeof (*apic_cpus); 757 if ((apic_cpus = kmem_zalloc(apic_cpus_size, KM_NOSLEEP)) == NULL) 758 goto cleanup; 759 760 /* 761 * ACPI doesn't provide the local apic ver, get it directly from the 762 * local apic 763 */ 764 ver = apicadr[APIC_VERS_REG]; 765 for (i = 0; i < apic_nproc; i++) { 766 apic_cpus[i].aci_local_id = local_ids[i]; 767 apic_cpus[i].aci_local_ver = (uchar_t)(ver & 0xFF); 768 } 769 for (i = 0; i < apic_io_max; i++) { 770 apic_ix = i; 771 772 /* 773 * need to check Sitka on the following acpi problem 774 * On the Sitka, the ioapic's apic_id field isn't reporting 775 * the actual io apic id. We have reported this problem 776 * to Intel. Until they fix the problem, we will get the 777 * actual id directly from the ioapic. 778 */ 779 id = ioapic_read(apic_ix, APIC_ID_CMD); 780 hid = (uchar_t)(id >> 24); 781 782 if (hid != apic_io_id[i]) { 783 if (apic_io_id[i] == 0) 784 apic_io_id[i] = hid; 785 else { /* set ioapic id to whatever reported by ACPI */ 786 id = ((uint32_t)apic_io_id[i]) << 24; 787 ioapic_write(apic_ix, APIC_ID_CMD, id); 788 } 789 } 790 ver = ioapic_read(apic_ix, APIC_VERS_CMD); 791 apic_io_ver[i] = (uchar_t)(ver & 0xff); 792 intmax = (ver >> 16) & 0xff; 793 apic_io_vectend[i] = apic_io_vectbase[i] + intmax; 794 if (apic_first_avail_irq <= apic_io_vectend[i]) 795 apic_first_avail_irq = apic_io_vectend[i] + 1; 796 } 797 798 799 /* 800 * Process SCI configuration here 801 * An error may be returned here if 802 * acpi-user-options specifies legacy mode 803 * (no SCI, no ACPI mode) 804 */ 805 if (acpica_get_sci(&sci, &sci_flags) != AE_OK) 806 sci = -1; 807 808 /* 809 * Now call acpi_init() to generate namespaces 810 * If this fails, we don't attempt to use ACPI 811 * even if we were able to get a MADT above 812 */ 813 if (acpica_init() != AE_OK) 814 goto cleanup; 815 816 /* 817 * Call acpica_build_processor_map() now that we have 818 * ACPI namesspace access 819 */ 820 acpica_build_processor_map(); 821 822 /* 823 * Squirrel away the SCI and flags for later on 824 * in apic_picinit() when we're ready 825 */ 826 apic_sci_vect = sci; 827 apic_sci_flags = sci_flags; 828 829 if (apic_verbose & APIC_VERBOSE_IRQ_FLAG) 830 acpi_verboseflags |= PSM_VERBOSE_IRQ_FLAG; 831 832 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) 833 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_FLAG; 834 835 if (apic_verbose & APIC_VERBOSE_POWEROFF_PAUSE_FLAG) 836 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_PAUSE_FLAG; 837 838 if (acpi_psm_init(modname, acpi_verboseflags) == ACPI_PSM_FAILURE) 839 goto cleanup; 840 841 /* Enable ACPI APIC interrupt routing */ 842 arglist.Count = 1; 843 arglist.Pointer = &arg; 844 arg.Type = ACPI_TYPE_INTEGER; 845 arg.Integer.Value = ACPI_APIC_MODE; /* 1 */ 846 rv = AcpiEvaluateObject(NULL, "\\_PIC", &arglist, NULL); 847 if (rv == AE_OK) { 848 build_reserved_irqlist((uchar_t *)apic_reserved_irqlist); 849 apic_enable_acpi = 1; 850 if (apic_use_acpi_madt_only) { 851 cmn_err(CE_CONT, 852 "?Using ACPI for CPU/IOAPIC information ONLY\n"); 853 } 854 return (PSM_SUCCESS); 855 } 856 /* if setting APIC mode failed above, we fall through to cleanup */ 857 858 cleanup: 859 if (apicadr != NULL) { 860 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 861 apicadr = NULL; 862 } 863 apic_nproc = 0; 864 for (i = 0; i < apic_io_max; i++) { 865 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN); 866 apicioadr[i] = NULL; 867 } 868 apic_io_max = 0; 869 acpi_isop = NULL; 870 acpi_iso_cnt = 0; 871 acpi_nmi_sp = NULL; 872 acpi_nmi_scnt = 0; 873 acpi_nmi_cp = NULL; 874 acpi_nmi_ccnt = 0; 875 return (PSM_FAILURE); 876 } 877 878 /* 879 * Handle default configuration. Fill in reqd global variables & tables 880 * Fill all details as MP table does not give any more info 881 */ 882 static int 883 apic_handle_defconf() 884 { 885 uint_t lid; 886 887 /*LINTED: pointer cast may result in improper alignment */ 888 apicioadr[0] = mapin_ioapic(APIC_IO_ADDR, 889 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 890 /*LINTED: pointer cast may result in improper alignment */ 891 apicadr = (uint32_t *)psm_map_phys(APIC_LOCAL_ADDR, 892 APIC_LOCAL_MEMLEN, PROT_READ); 893 apic_cpus_size = 2 * sizeof (*apic_cpus); 894 apic_cpus = (apic_cpus_info_t *) 895 kmem_zalloc(apic_cpus_size, KM_NOSLEEP); 896 if ((!apicadr) || (!apicioadr[0]) || (!apic_cpus)) 897 goto apic_handle_defconf_fail; 898 CPUSET_ONLY(apic_cpumask, 0); 899 CPUSET_ADD(apic_cpumask, 1); 900 apic_nproc = 2; 901 lid = apicadr[APIC_LID_REG]; 902 apic_cpus[0].aci_local_id = (uchar_t)(lid >> APIC_ID_BIT_OFFSET); 903 /* 904 * According to the PC+MP spec 1.1, the local ids 905 * for the default configuration has to be 0 or 1 906 */ 907 if (apic_cpus[0].aci_local_id == 1) 908 apic_cpus[1].aci_local_id = 0; 909 else if (apic_cpus[0].aci_local_id == 0) 910 apic_cpus[1].aci_local_id = 1; 911 else 912 goto apic_handle_defconf_fail; 913 914 apic_io_id[0] = 2; 915 apic_io_max = 1; 916 if (apic_defconf >= 5) { 917 apic_cpus[0].aci_local_ver = APIC_INTEGRATED_VERS; 918 apic_cpus[1].aci_local_ver = APIC_INTEGRATED_VERS; 919 apic_io_ver[0] = APIC_INTEGRATED_VERS; 920 } else { 921 apic_cpus[0].aci_local_ver = 0; /* 82489 DX */ 922 apic_cpus[1].aci_local_ver = 0; 923 apic_io_ver[0] = 0; 924 } 925 if (apic_defconf == 2 || apic_defconf == 3 || apic_defconf == 6) 926 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) | 927 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1); 928 return (PSM_SUCCESS); 929 930 apic_handle_defconf_fail: 931 if (apic_cpus) 932 kmem_free(apic_cpus, apic_cpus_size); 933 if (apicadr) 934 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 935 if (apicioadr[0]) 936 mapout_ioapic((caddr_t)apicioadr[0], APIC_IO_MEMLEN); 937 return (PSM_FAILURE); 938 } 939 940 /* Parse the entries in MP configuration table and collect info that we need */ 941 static int 942 apic_parse_mpct(caddr_t mpct, int bypass_cpus_and_ioapics) 943 { 944 struct apic_procent *procp; 945 struct apic_bus *busp; 946 struct apic_io_entry *ioapicp; 947 struct apic_io_intr *intrp; 948 int apic_ix; 949 uint_t lid; 950 uint32_t id; 951 uchar_t hid; 952 953 /*LINTED: pointer cast may result in improper alignment */ 954 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr)); 955 956 /* No need to count cpu entries if we won't use them */ 957 if (!bypass_cpus_and_ioapics) { 958 959 /* Find max # of CPUS and allocate structure accordingly */ 960 apic_nproc = 0; 961 CPUSET_ZERO(apic_cpumask); 962 while (procp->proc_entry == APIC_CPU_ENTRY) { 963 if (procp->proc_cpuflags & CPUFLAGS_EN) { 964 if (apic_nproc < NCPU) 965 CPUSET_ADD(apic_cpumask, apic_nproc); 966 apic_nproc++; 967 } 968 procp++; 969 } 970 if (apic_nproc > NCPU) 971 cmn_err(CE_WARN, "%s: exceeded " 972 "maximum no. of CPUs (= %d)", psm_name, NCPU); 973 apic_cpus_size = apic_nproc * sizeof (*apic_cpus); 974 if (!apic_nproc || !(apic_cpus = (apic_cpus_info_t *) 975 kmem_zalloc(apic_cpus_size, KM_NOSLEEP))) 976 return (PSM_FAILURE); 977 } 978 979 /*LINTED: pointer cast may result in improper alignment */ 980 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr)); 981 982 /* 983 * start with index 1 as 0 needs to be filled in with Boot CPU, but 984 * if we're bypassing this information, it has already been filled 985 * in by acpi_probe(), so don't overwrite it. 986 */ 987 if (!bypass_cpus_and_ioapics) 988 apic_nproc = 1; 989 990 while (procp->proc_entry == APIC_CPU_ENTRY) { 991 /* check whether the cpu exists or not */ 992 if (!bypass_cpus_and_ioapics && 993 procp->proc_cpuflags & CPUFLAGS_EN) { 994 if (procp->proc_cpuflags & CPUFLAGS_BP) { /* Boot CPU */ 995 lid = apicadr[APIC_LID_REG]; 996 apic_cpus[0].aci_local_id = procp->proc_apicid; 997 if (apic_cpus[0].aci_local_id != 998 (uchar_t)(lid >> APIC_ID_BIT_OFFSET)) { 999 return (PSM_FAILURE); 1000 } 1001 apic_cpus[0].aci_local_ver = 1002 procp->proc_version; 1003 } else { 1004 1005 apic_cpus[apic_nproc].aci_local_id = 1006 procp->proc_apicid; 1007 apic_cpus[apic_nproc].aci_local_ver = 1008 procp->proc_version; 1009 apic_nproc++; 1010 1011 } 1012 } 1013 procp++; 1014 } 1015 1016 /* 1017 * Save start of bus entries for later use. 1018 * Get EISA level cntrl if EISA bus is present. 1019 * Also get the CPI bus id for single CPI bus case 1020 */ 1021 apic_busp = busp = (struct apic_bus *)procp; 1022 while (busp->bus_entry == APIC_BUS_ENTRY) { 1023 lid = apic_find_bus_type((char *)&busp->bus_str1); 1024 if (lid == BUS_EISA) { 1025 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) | 1026 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1); 1027 } else if (lid == BUS_PCI) { 1028 /* 1029 * apic_single_pci_busid will be used only if 1030 * apic_pic_bus_total is equal to 1 1031 */ 1032 apic_pci_bus_total++; 1033 apic_single_pci_busid = busp->bus_id; 1034 } 1035 busp++; 1036 } 1037 1038 ioapicp = (struct apic_io_entry *)busp; 1039 1040 if (!bypass_cpus_and_ioapics) 1041 apic_io_max = 0; 1042 do { 1043 if (!bypass_cpus_and_ioapics && apic_io_max < MAX_IO_APIC) { 1044 if (ioapicp->io_flags & IOAPIC_FLAGS_EN) { 1045 apic_io_id[apic_io_max] = ioapicp->io_apicid; 1046 apic_io_ver[apic_io_max] = ioapicp->io_version; 1047 /*LINTED: pointer cast may result in improper alignment */ 1048 apicioadr[apic_io_max] = 1049 mapin_ioapic( 1050 (uint32_t)ioapicp->io_apic_addr, 1051 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 1052 1053 if (!apicioadr[apic_io_max]) 1054 return (PSM_FAILURE); 1055 1056 ioapic_mask_workaround[apic_io_max] = 1057 apic_is_ioapic_AMD_813x( 1058 ioapicp->io_apic_addr); 1059 1060 apic_ix = apic_io_max; 1061 id = ioapic_read(apic_ix, APIC_ID_CMD); 1062 hid = (uchar_t)(id >> 24); 1063 1064 if (hid != apic_io_id[apic_io_max]) { 1065 if (apic_io_id[apic_io_max] == 0) 1066 apic_io_id[apic_io_max] = hid; 1067 else { 1068 /* 1069 * set ioapic id to whatever 1070 * reported by MPS 1071 * 1072 * may not need to set index 1073 * again ??? 1074 * take it out and try 1075 */ 1076 1077 id = ((uint32_t) 1078 apic_io_id[apic_io_max]) << 1079 24; 1080 1081 ioapic_write(apic_ix, 1082 APIC_ID_CMD, id); 1083 } 1084 } 1085 apic_io_max++; 1086 } 1087 } 1088 ioapicp++; 1089 } while (ioapicp->io_entry == APIC_IO_ENTRY); 1090 1091 apic_io_intrp = (struct apic_io_intr *)ioapicp; 1092 1093 intrp = apic_io_intrp; 1094 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 1095 if ((intrp->intr_irq > APIC_MAX_ISA_IRQ) || 1096 (apic_find_bus(intrp->intr_busid) == BUS_PCI)) { 1097 apic_irq_translate = 1; 1098 break; 1099 } 1100 intrp++; 1101 } 1102 1103 return (PSM_SUCCESS); 1104 } 1105 1106 boolean_t 1107 apic_cpu_in_range(int cpu) 1108 { 1109 return ((cpu & ~IRQ_USER_BOUND) < apic_nproc); 1110 } 1111 1112 uint16_t 1113 apic_get_apic_version() 1114 { 1115 int i; 1116 uchar_t min_io_apic_ver = 0; 1117 static uint16_t version; /* Cache as value is constant */ 1118 static boolean_t found = B_FALSE; /* Accomodate zero version */ 1119 1120 if (found == B_FALSE) { 1121 found = B_TRUE; 1122 1123 /* 1124 * Don't assume all IO APICs in the system are the same. 1125 * 1126 * Set to the minimum version. 1127 */ 1128 for (i = 0; i < apic_io_max; i++) { 1129 if ((apic_io_ver[i] != 0) && 1130 ((min_io_apic_ver == 0) || 1131 (min_io_apic_ver >= apic_io_ver[i]))) 1132 min_io_apic_ver = apic_io_ver[i]; 1133 } 1134 1135 /* Assume all local APICs are of the same version. */ 1136 version = (min_io_apic_ver << 8) | apic_cpus[0].aci_local_ver; 1137 } 1138 return (version); 1139 } 1140 1141 static struct apic_mpfps_hdr * 1142 apic_find_fps_sig(caddr_t cptr, int len) 1143 { 1144 int i; 1145 1146 /* Look for the pattern "_MP_" */ 1147 for (i = 0; i < len; i += 16) { 1148 if ((*(cptr+i) == '_') && 1149 (*(cptr+i+1) == 'M') && 1150 (*(cptr+i+2) == 'P') && 1151 (*(cptr+i+3) == '_')) 1152 /*LINTED: pointer cast may result in improper alignment */ 1153 return ((struct apic_mpfps_hdr *)(cptr + i)); 1154 } 1155 return (NULL); 1156 } 1157 1158 static int 1159 apic_checksum(caddr_t bptr, int len) 1160 { 1161 int i; 1162 uchar_t cksum; 1163 1164 cksum = 0; 1165 for (i = 0; i < len; i++) 1166 cksum += *bptr++; 1167 return ((int)cksum); 1168 } 1169 1170 1171 /* 1172 * Initialise vector->ipl and ipl->pri arrays. level_intr and irqtable 1173 * are also set to NULL. vector->irq is set to a value which cannot map 1174 * to a real irq to show that it is free. 1175 */ 1176 void 1177 apic_init_common() 1178 { 1179 int i, j, indx; 1180 int *iptr; 1181 1182 /* 1183 * Initialize apic_ipls from apic_vectortoipl. This array is 1184 * used in apic_intr_enter to determine the IPL to use for the 1185 * corresponding vector. On some systems, due to hardware errata 1186 * and interrupt sharing, the IPL may not correspond to the IPL listed 1187 * in apic_vectortoipl (see apic_addspl and apic_delspl). 1188 */ 1189 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) { 1190 indx = i * APIC_VECTOR_PER_IPL; 1191 1192 for (j = 0; j < APIC_VECTOR_PER_IPL; j++, indx++) 1193 apic_ipls[indx] = apic_vectortoipl[i]; 1194 } 1195 1196 /* cpu 0 is always up (for now) */ 1197 apic_cpus[0].aci_status = APIC_CPU_ONLINE | APIC_CPU_INTR_ENABLE; 1198 1199 iptr = (int *)&apic_irq_table[0]; 1200 for (i = 0; i <= APIC_MAX_VECTOR; i++) { 1201 apic_level_intr[i] = 0; 1202 *iptr++ = NULL; 1203 apic_vector_to_irq[i] = APIC_RESV_IRQ; 1204 1205 /* These *must* be initted to B_TRUE! */ 1206 apic_reprogram_info[i].done = B_TRUE; 1207 apic_reprogram_info[i].irqp = NULL; 1208 apic_reprogram_info[i].tries = 0; 1209 apic_reprogram_info[i].bindcpu = 0; 1210 } 1211 1212 /* 1213 * Allocate a dummy irq table entry for the reserved entry. 1214 * This takes care of the race between removing an irq and 1215 * clock detecting a CPU in that irq during interrupt load 1216 * sampling. 1217 */ 1218 apic_irq_table[APIC_RESV_IRQ] = 1219 kmem_zalloc(sizeof (apic_irq_t), KM_NOSLEEP); 1220 1221 mutex_init(&airq_mutex, NULL, MUTEX_DEFAULT, NULL); 1222 } 1223 1224 void 1225 ioapic_init_intr(int mask_apic) 1226 { 1227 int apic_ix; 1228 struct intrspec ispec; 1229 apic_irq_t *irqptr; 1230 int i, j; 1231 ulong_t iflag; 1232 1233 LOCK_INIT_CLEAR(&apic_revector_lock); 1234 LOCK_INIT_CLEAR(&apic_defer_reprogram_lock); 1235 1236 /* mask interrupt vectors */ 1237 for (j = 0; j < apic_io_max && mask_apic; j++) { 1238 int intin_max; 1239 1240 apic_ix = j; 1241 /* Bits 23-16 define the maximum redirection entries */ 1242 intin_max = (ioapic_read(apic_ix, APIC_VERS_CMD) >> 16) & 0xff; 1243 for (i = 0; i < intin_max; i++) 1244 ioapic_write(apic_ix, APIC_RDT_CMD + 2 * i, AV_MASK); 1245 } 1246 1247 /* 1248 * Hack alert: deal with ACPI SCI interrupt chicken/egg here 1249 */ 1250 if (apic_sci_vect > 0) { 1251 /* 1252 * acpica has already done add_avintr(); we just 1253 * to finish the job by mimicing translate_irq() 1254 * 1255 * Fake up an intrspec and setup the tables 1256 */ 1257 ispec.intrspec_vec = apic_sci_vect; 1258 ispec.intrspec_pri = SCI_IPL; 1259 1260 if (apic_setup_irq_table(NULL, apic_sci_vect, NULL, 1261 &ispec, &apic_sci_flags, DDI_INTR_TYPE_FIXED) < 0) { 1262 cmn_err(CE_WARN, "!apic: SCI setup failed"); 1263 return; 1264 } 1265 irqptr = apic_irq_table[apic_sci_vect]; 1266 1267 iflag = intr_clear(); 1268 lock_set(&apic_ioapic_lock); 1269 1270 /* Program I/O APIC */ 1271 (void) apic_setup_io_intr(irqptr, apic_sci_vect, B_FALSE); 1272 1273 lock_clear(&apic_ioapic_lock); 1274 intr_restore(iflag); 1275 1276 irqptr->airq_share++; 1277 } 1278 } 1279 1280 /* 1281 * Add mask bits to disable interrupt vector from happening 1282 * at or above IPL. In addition, it should remove mask bits 1283 * to enable interrupt vectors below the given IPL. 1284 * 1285 * Both add and delspl are complicated by the fact that different interrupts 1286 * may share IRQs. This can happen in two ways. 1287 * 1. The same H/W line is shared by more than 1 device 1288 * 1a. with interrupts at different IPLs 1289 * 1b. with interrupts at same IPL 1290 * 2. We ran out of vectors at a given IPL and started sharing vectors. 1291 * 1b and 2 should be handled gracefully, except for the fact some ISRs 1292 * will get called often when no interrupt is pending for the device. 1293 * For 1a, we just hope that the machine blows up with the person who 1294 * set it up that way!. In the meantime, we handle it at the higher IPL. 1295 */ 1296 /*ARGSUSED*/ 1297 int 1298 apic_addspl_common(int irqno, int ipl, int min_ipl, int max_ipl) 1299 { 1300 uchar_t vector; 1301 ulong_t iflag; 1302 apic_irq_t *irqptr, *irqheadptr; 1303 int irqindex; 1304 1305 ASSERT(max_ipl <= UCHAR_MAX); 1306 irqindex = IRQINDEX(irqno); 1307 1308 if ((irqindex == -1) || (!apic_irq_table[irqindex])) 1309 return (PSM_FAILURE); 1310 1311 mutex_enter(&airq_mutex); 1312 irqptr = irqheadptr = apic_irq_table[irqindex]; 1313 1314 DDI_INTR_IMPLDBG((CE_CONT, "apic_addspl: dip=0x%p type=%d irqno=0x%x " 1315 "vector=0x%x\n", (void *)irqptr->airq_dip, 1316 irqptr->airq_mps_intr_index, irqno, irqptr->airq_vector)); 1317 1318 while (irqptr) { 1319 if (VIRTIRQ(irqindex, irqptr->airq_share_id) == irqno) 1320 break; 1321 irqptr = irqptr->airq_next; 1322 } 1323 irqptr->airq_share++; 1324 1325 mutex_exit(&airq_mutex); 1326 1327 /* return if it is not hardware interrupt */ 1328 if (irqptr->airq_mps_intr_index == RESERVE_INDEX) 1329 return (PSM_SUCCESS); 1330 1331 /* Or if there are more interupts at a higher IPL */ 1332 if (ipl != max_ipl) 1333 return (PSM_SUCCESS); 1334 1335 /* 1336 * if apic_picinit() has not been called yet, just return. 1337 * At the end of apic_picinit(), we will call setup_io_intr(). 1338 */ 1339 1340 if (!apic_flag) 1341 return (PSM_SUCCESS); 1342 1343 /* 1344 * Upgrade vector if max_ipl is not earlier ipl. If we cannot allocate, 1345 * return failure. Not very elegant, but then we hope the 1346 * machine will blow up with ... 1347 */ 1348 if (irqptr->airq_ipl != max_ipl && 1349 !ioapic_mask_workaround[irqptr->airq_ioapicindex]) { 1350 1351 vector = apic_allocate_vector(max_ipl, irqindex, 1); 1352 if (vector == 0) { 1353 irqptr->airq_share--; 1354 return (PSM_FAILURE); 1355 } 1356 irqptr = irqheadptr; 1357 apic_mark_vector(irqptr->airq_vector, vector); 1358 while (irqptr) { 1359 irqptr->airq_vector = vector; 1360 irqptr->airq_ipl = (uchar_t)max_ipl; 1361 /* 1362 * reprogram irq being added and every one else 1363 * who is not in the UNINIT state 1364 */ 1365 if ((VIRTIRQ(irqindex, irqptr->airq_share_id) == 1366 irqno) || (irqptr->airq_temp_cpu != IRQ_UNINIT)) { 1367 apic_record_rdt_entry(irqptr, irqindex); 1368 1369 iflag = intr_clear(); 1370 lock_set(&apic_ioapic_lock); 1371 1372 (void) apic_setup_io_intr(irqptr, irqindex, 1373 B_FALSE); 1374 1375 lock_clear(&apic_ioapic_lock); 1376 intr_restore(iflag); 1377 } 1378 irqptr = irqptr->airq_next; 1379 } 1380 return (PSM_SUCCESS); 1381 1382 } else if (irqptr->airq_ipl != max_ipl && 1383 ioapic_mask_workaround[irqptr->airq_ioapicindex]) { 1384 /* 1385 * We cannot upgrade the vector, but we can change 1386 * the IPL that this vector induces. 1387 * 1388 * Note that we subtract APIC_BASE_VECT from the vector 1389 * here because this array is used in apic_intr_enter 1390 * (no need to add APIC_BASE_VECT in that hot code 1391 * path since we can do it in the rarely-executed path 1392 * here). 1393 */ 1394 apic_ipls[irqptr->airq_vector - APIC_BASE_VECT] = 1395 (uchar_t)max_ipl; 1396 1397 irqptr = irqheadptr; 1398 while (irqptr) { 1399 irqptr->airq_ipl = (uchar_t)max_ipl; 1400 irqptr = irqptr->airq_next; 1401 } 1402 1403 return (PSM_SUCCESS); 1404 } 1405 1406 ASSERT(irqptr); 1407 1408 iflag = intr_clear(); 1409 lock_set(&apic_ioapic_lock); 1410 1411 (void) apic_setup_io_intr(irqptr, irqindex, B_FALSE); 1412 1413 lock_clear(&apic_ioapic_lock); 1414 intr_restore(iflag); 1415 1416 return (PSM_SUCCESS); 1417 } 1418 1419 /* 1420 * Recompute mask bits for the given interrupt vector. 1421 * If there is no interrupt servicing routine for this 1422 * vector, this function should disable interrupt vector 1423 * from happening at all IPLs. If there are still 1424 * handlers using the given vector, this function should 1425 * disable the given vector from happening below the lowest 1426 * IPL of the remaining hadlers. 1427 */ 1428 /*ARGSUSED*/ 1429 int 1430 apic_delspl_common(int irqno, int ipl, int min_ipl, int max_ipl) 1431 { 1432 uchar_t vector, bind_cpu; 1433 int intin, irqindex; 1434 int apic_ix; 1435 apic_irq_t *irqptr, *irqheadptr, *irqp; 1436 ulong_t iflag; 1437 1438 mutex_enter(&airq_mutex); 1439 irqindex = IRQINDEX(irqno); 1440 irqptr = irqheadptr = apic_irq_table[irqindex]; 1441 1442 DDI_INTR_IMPLDBG((CE_CONT, "apic_delspl: dip=0x%p type=%d irqno=0x%x " 1443 "vector=0x%x\n", (void *)irqptr->airq_dip, 1444 irqptr->airq_mps_intr_index, irqno, irqptr->airq_vector)); 1445 1446 while (irqptr) { 1447 if (VIRTIRQ(irqindex, irqptr->airq_share_id) == irqno) 1448 break; 1449 irqptr = irqptr->airq_next; 1450 } 1451 ASSERT(irqptr); 1452 1453 irqptr->airq_share--; 1454 1455 mutex_exit(&airq_mutex); 1456 1457 if (ipl < max_ipl) 1458 return (PSM_SUCCESS); 1459 1460 /* return if it is not hardware interrupt */ 1461 if (irqptr->airq_mps_intr_index == RESERVE_INDEX) 1462 return (PSM_SUCCESS); 1463 1464 if (!apic_flag) { 1465 /* 1466 * Clear irq_struct. If two devices shared an intpt 1467 * line & 1 unloaded before picinit, we are hosed. But, then 1468 * we hope the machine will ... 1469 */ 1470 irqptr->airq_mps_intr_index = FREE_INDEX; 1471 irqptr->airq_temp_cpu = IRQ_UNINIT; 1472 apic_free_vector(irqptr->airq_vector); 1473 return (PSM_SUCCESS); 1474 } 1475 /* 1476 * Downgrade vector to new max_ipl if needed.If we cannot allocate, 1477 * use old IPL. Not very elegant, but then we hope ... 1478 */ 1479 if ((irqptr->airq_ipl != max_ipl) && (max_ipl != PSM_INVALID_IPL) && 1480 !ioapic_mask_workaround[irqptr->airq_ioapicindex]) { 1481 apic_irq_t *irqp; 1482 if (vector = apic_allocate_vector(max_ipl, irqno, 1)) { 1483 apic_mark_vector(irqheadptr->airq_vector, vector); 1484 irqp = irqheadptr; 1485 while (irqp) { 1486 irqp->airq_vector = vector; 1487 irqp->airq_ipl = (uchar_t)max_ipl; 1488 if (irqp->airq_temp_cpu != IRQ_UNINIT) { 1489 apic_record_rdt_entry(irqp, irqindex); 1490 1491 iflag = intr_clear(); 1492 lock_set(&apic_ioapic_lock); 1493 1494 (void) apic_setup_io_intr(irqp, 1495 irqindex, B_FALSE); 1496 1497 lock_clear(&apic_ioapic_lock); 1498 intr_restore(iflag); 1499 } 1500 irqp = irqp->airq_next; 1501 } 1502 } 1503 1504 } else if (irqptr->airq_ipl != max_ipl && 1505 max_ipl != PSM_INVALID_IPL && 1506 ioapic_mask_workaround[irqptr->airq_ioapicindex]) { 1507 1508 /* 1509 * We cannot downgrade the IPL of the vector below the vector's 1510 * hardware priority. If we did, it would be possible for a 1511 * higher-priority hardware vector to interrupt a CPU running at an IPL 1512 * lower than the hardware priority of the interrupting vector (but 1513 * higher than the soft IPL of this IRQ). When this happens, we would 1514 * then try to drop the IPL BELOW what it was (effectively dropping 1515 * below base_spl) which would be potentially catastrophic. 1516 * 1517 * (e.g. Suppose the hardware vector associated with this IRQ is 0x40 1518 * (hardware IPL of 4). Further assume that the old IPL of this IRQ 1519 * was 4, but the new IPL is 1. If we forced vector 0x40 to result in 1520 * an IPL of 1, it would be possible for the processor to be executing 1521 * at IPL 3 and for an interrupt to come in on vector 0x40, interrupting 1522 * the currently-executing ISR. When apic_intr_enter consults 1523 * apic_irqs[], it will return 1, bringing the IPL of the CPU down to 1 1524 * so even though the processor was running at IPL 4, an IPL 1 1525 * interrupt will have interrupted it, which must not happen)). 1526 * 1527 * Effectively, this means that the hardware priority corresponding to 1528 * the IRQ's IPL (in apic_ipls[]) cannot be lower than the vector's 1529 * hardware priority. 1530 * 1531 * (In the above example, then, after removal of the IPL 4 device's 1532 * interrupt handler, the new IPL will continue to be 4 because the 1533 * hardware priority that IPL 1 implies is lower than the hardware 1534 * priority of the vector used.) 1535 */ 1536 /* apic_ipls is indexed by vector, starting at APIC_BASE_VECT */ 1537 const int apic_ipls_index = irqptr->airq_vector - 1538 APIC_BASE_VECT; 1539 const int vect_inherent_hwpri = irqptr->airq_vector >> 1540 APIC_IPL_SHIFT; 1541 1542 /* 1543 * If there are still devices using this IRQ, determine the 1544 * new ipl to use. 1545 */ 1546 if (irqptr->airq_share) { 1547 int vect_desired_hwpri, hwpri; 1548 1549 ASSERT(max_ipl < MAXIPL); 1550 vect_desired_hwpri = apic_ipltopri[max_ipl] >> 1551 APIC_IPL_SHIFT; 1552 1553 /* 1554 * If the desired IPL's hardware priority is lower 1555 * than that of the vector, use the hardware priority 1556 * of the vector to determine the new IPL. 1557 */ 1558 hwpri = (vect_desired_hwpri < vect_inherent_hwpri) ? 1559 vect_inherent_hwpri : vect_desired_hwpri; 1560 1561 /* 1562 * Now, to get the right index for apic_vectortoipl, 1563 * we need to subtract APIC_BASE_VECT from the 1564 * hardware-vector-equivalent (in hwpri). Since hwpri 1565 * is already shifted, we shift APIC_BASE_VECT before 1566 * doing the subtraction. 1567 */ 1568 hwpri -= (APIC_BASE_VECT >> APIC_IPL_SHIFT); 1569 1570 ASSERT(hwpri >= 0); 1571 ASSERT(hwpri < MAXIPL); 1572 max_ipl = apic_vectortoipl[hwpri]; 1573 apic_ipls[apic_ipls_index] = max_ipl; 1574 1575 irqp = irqheadptr; 1576 while (irqp) { 1577 irqp->airq_ipl = (uchar_t)max_ipl; 1578 irqp = irqp->airq_next; 1579 } 1580 } else { 1581 /* 1582 * No more devices on this IRQ, so reset this vector's 1583 * element in apic_ipls to the original IPL for this 1584 * vector 1585 */ 1586 apic_ipls[apic_ipls_index] = 1587 apic_vectortoipl[vect_inherent_hwpri]; 1588 } 1589 } 1590 1591 if (irqptr->airq_share) 1592 return (PSM_SUCCESS); 1593 1594 iflag = intr_clear(); 1595 lock_set(&apic_ioapic_lock); 1596 1597 /* Disable the MSI/X vector */ 1598 if (APIC_IS_MSI_OR_MSIX_INDEX(irqptr->airq_mps_intr_index)) { 1599 int type = (irqptr->airq_mps_intr_index == MSI_INDEX) ? 1600 DDI_INTR_TYPE_MSI : DDI_INTR_TYPE_MSIX; 1601 1602 /* 1603 * Make sure we only disable on the last 1604 * of the multi-MSI support 1605 */ 1606 if (i_ddi_intr_get_current_nintrs(irqptr->airq_dip) == 1) { 1607 (void) apic_pci_msi_unconfigure(irqptr->airq_dip, 1608 type, irqptr->airq_ioapicindex); 1609 1610 (void) apic_pci_msi_disable_mode(irqptr->airq_dip, 1611 type, irqptr->airq_ioapicindex); 1612 } 1613 } else { 1614 /* 1615 * The assumption here is that this is safe, even for 1616 * systems with IOAPICs that suffer from the hardware 1617 * erratum because all devices have been quiesced before 1618 * they unregister their interrupt handlers. If that 1619 * assumption turns out to be false, this mask operation 1620 * can induce the same erratum result we're trying to 1621 * avoid. 1622 */ 1623 apic_ix = irqptr->airq_ioapicindex; 1624 intin = irqptr->airq_intin_no; 1625 ioapic_write(apic_ix, APIC_RDT_CMD + 2 * intin, AV_MASK); 1626 } 1627 1628 if (max_ipl == PSM_INVALID_IPL) { 1629 ASSERT(irqheadptr == irqptr); 1630 bind_cpu = irqptr->airq_temp_cpu; 1631 if (((uchar_t)bind_cpu != IRQ_UNBOUND) && 1632 ((uchar_t)bind_cpu != IRQ_UNINIT)) { 1633 ASSERT((bind_cpu & ~IRQ_USER_BOUND) < apic_nproc); 1634 if (bind_cpu & IRQ_USER_BOUND) { 1635 /* If hardbound, temp_cpu == cpu */ 1636 bind_cpu &= ~IRQ_USER_BOUND; 1637 apic_cpus[bind_cpu].aci_bound--; 1638 } else 1639 apic_cpus[bind_cpu].aci_temp_bound--; 1640 } 1641 irqptr->airq_temp_cpu = IRQ_UNINIT; 1642 irqptr->airq_mps_intr_index = FREE_INDEX; 1643 lock_clear(&apic_ioapic_lock); 1644 intr_restore(iflag); 1645 apic_free_vector(irqptr->airq_vector); 1646 return (PSM_SUCCESS); 1647 } 1648 lock_clear(&apic_ioapic_lock); 1649 intr_restore(iflag); 1650 1651 mutex_enter(&airq_mutex); 1652 if ((irqptr == apic_irq_table[irqindex])) { 1653 apic_irq_t *oldirqptr; 1654 /* Move valid irq entry to the head */ 1655 irqheadptr = oldirqptr = irqptr; 1656 irqptr = irqptr->airq_next; 1657 ASSERT(irqptr); 1658 while (irqptr) { 1659 if (irqptr->airq_mps_intr_index != FREE_INDEX) 1660 break; 1661 oldirqptr = irqptr; 1662 irqptr = irqptr->airq_next; 1663 } 1664 /* remove all invalid ones from the beginning */ 1665 apic_irq_table[irqindex] = irqptr; 1666 /* 1667 * and link them back after the head. The invalid ones 1668 * begin with irqheadptr and end at oldirqptr 1669 */ 1670 oldirqptr->airq_next = irqptr->airq_next; 1671 irqptr->airq_next = irqheadptr; 1672 } 1673 mutex_exit(&airq_mutex); 1674 1675 irqptr->airq_temp_cpu = IRQ_UNINIT; 1676 irqptr->airq_mps_intr_index = FREE_INDEX; 1677 1678 return (PSM_SUCCESS); 1679 } 1680 1681 /* 1682 * apic_introp_xlate() replaces apic_translate_irq() and is 1683 * called only from apic_intr_ops(). With the new ADII framework, 1684 * the priority can no longer be retrieved through i_ddi_get_intrspec(). 1685 * It has to be passed in from the caller. 1686 */ 1687 int 1688 apic_introp_xlate(dev_info_t *dip, struct intrspec *ispec, int type) 1689 { 1690 char dev_type[16]; 1691 int dev_len, pci_irq, newirq, bustype, devid, busid, i; 1692 int irqno = ispec->intrspec_vec; 1693 ddi_acc_handle_t cfg_handle; 1694 uchar_t ipin; 1695 struct apic_io_intr *intrp; 1696 iflag_t intr_flag; 1697 APIC_HEADER *hp; 1698 MADT_INTERRUPT_OVERRIDE *isop; 1699 apic_irq_t *airqp; 1700 int parent_is_pci_or_pciex = 0; 1701 int child_is_pciex = 0; 1702 1703 DDI_INTR_IMPLDBG((CE_CONT, "apic_introp_xlate: dip=0x%p name=%s " 1704 "type=%d irqno=0x%x\n", (void *)dip, ddi_get_name(dip), type, 1705 irqno)); 1706 1707 dev_len = sizeof (dev_type); 1708 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, ddi_get_parent(dip), 1709 DDI_PROP_DONTPASS, "device_type", (caddr_t)dev_type, 1710 &dev_len) == DDI_PROP_SUCCESS) { 1711 if ((strcmp(dev_type, "pci") == 0) || 1712 (strcmp(dev_type, "pciex") == 0)) 1713 parent_is_pci_or_pciex = 1; 1714 } 1715 1716 if (parent_is_pci_or_pciex && ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1717 DDI_PROP_DONTPASS, "pcie-capid-pointer", PCI_CAP_NEXT_PTR_NULL) != 1718 PCI_CAP_NEXT_PTR_NULL) { 1719 child_is_pciex = 1; 1720 } 1721 1722 if (DDI_INTR_IS_MSI_OR_MSIX(type)) { 1723 if ((airqp = apic_find_irq(dip, ispec, type)) != NULL) { 1724 airqp->airq_iflag.bustype = 1725 child_is_pciex ? BUS_PCIE : BUS_PCI; 1726 return (apic_vector_to_irq[airqp->airq_vector]); 1727 } 1728 return (apic_setup_irq_table(dip, irqno, NULL, ispec, 1729 NULL, type)); 1730 } 1731 1732 bustype = 0; 1733 1734 /* check if we have already translated this irq */ 1735 mutex_enter(&airq_mutex); 1736 newirq = apic_min_device_irq; 1737 for (; newirq <= apic_max_device_irq; newirq++) { 1738 airqp = apic_irq_table[newirq]; 1739 while (airqp) { 1740 if ((airqp->airq_dip == dip) && 1741 (airqp->airq_origirq == irqno) && 1742 (airqp->airq_mps_intr_index != FREE_INDEX)) { 1743 1744 mutex_exit(&airq_mutex); 1745 return (VIRTIRQ(newirq, airqp->airq_share_id)); 1746 } 1747 airqp = airqp->airq_next; 1748 } 1749 } 1750 mutex_exit(&airq_mutex); 1751 1752 if (apic_defconf) 1753 goto defconf; 1754 1755 if ((dip == NULL) || (!apic_irq_translate && !apic_enable_acpi)) 1756 goto nonpci; 1757 1758 if (parent_is_pci_or_pciex) { 1759 /* pci device */ 1760 if (acpica_get_bdf(dip, &busid, &devid, NULL) != 0) 1761 goto nonpci; 1762 if (busid == 0 && apic_pci_bus_total == 1) 1763 busid = (int)apic_single_pci_busid; 1764 1765 if (pci_config_setup(dip, &cfg_handle) != DDI_SUCCESS) 1766 goto nonpci; 1767 ipin = pci_config_get8(cfg_handle, PCI_CONF_IPIN) - PCI_INTA; 1768 pci_config_teardown(&cfg_handle); 1769 if (apic_enable_acpi && !apic_use_acpi_madt_only) { 1770 if (apic_acpi_translate_pci_irq(dip, busid, devid, 1771 ipin, &pci_irq, &intr_flag) != ACPI_PSM_SUCCESS) 1772 goto nonpci; 1773 1774 intr_flag.bustype = child_is_pciex ? BUS_PCIE : BUS_PCI; 1775 if ((newirq = apic_setup_irq_table(dip, pci_irq, NULL, 1776 ispec, &intr_flag, type)) == -1) 1777 goto nonpci; 1778 return (newirq); 1779 } else { 1780 pci_irq = ((devid & 0x1f) << 2) | (ipin & 0x3); 1781 if ((intrp = apic_find_io_intr_w_busid(pci_irq, busid)) 1782 == NULL) { 1783 if ((pci_irq = apic_handle_pci_pci_bridge(dip, 1784 devid, ipin, &intrp)) == -1) 1785 goto nonpci; 1786 } 1787 if ((newirq = apic_setup_irq_table(dip, pci_irq, intrp, 1788 ispec, NULL, type)) == -1) 1789 goto nonpci; 1790 return (newirq); 1791 } 1792 } else if (strcmp(dev_type, "isa") == 0) 1793 bustype = BUS_ISA; 1794 else if (strcmp(dev_type, "eisa") == 0) 1795 bustype = BUS_EISA; 1796 1797 nonpci: 1798 if (apic_enable_acpi && !apic_use_acpi_madt_only) { 1799 /* search iso entries first */ 1800 if (acpi_iso_cnt != 0) { 1801 hp = (APIC_HEADER *)acpi_isop; 1802 i = 0; 1803 while (i < acpi_iso_cnt) { 1804 if (hp->Type == APIC_XRUPT_OVERRIDE) { 1805 isop = (MADT_INTERRUPT_OVERRIDE *)hp; 1806 if (isop->Bus == 0 && 1807 isop->Source == irqno) { 1808 newirq = isop->Interrupt; 1809 intr_flag.intr_po = 1810 isop->Polarity; 1811 intr_flag.intr_el = 1812 isop->TriggerMode; 1813 intr_flag.bustype = BUS_ISA; 1814 1815 return (apic_setup_irq_table( 1816 dip, newirq, NULL, ispec, 1817 &intr_flag, type)); 1818 1819 } 1820 i++; 1821 } 1822 hp = (APIC_HEADER *)(((char *)hp) + 1823 hp->Length); 1824 } 1825 } 1826 intr_flag.intr_po = INTR_PO_ACTIVE_HIGH; 1827 intr_flag.intr_el = INTR_EL_EDGE; 1828 intr_flag.bustype = BUS_ISA; 1829 return (apic_setup_irq_table(dip, irqno, NULL, ispec, 1830 &intr_flag, type)); 1831 } else { 1832 if (bustype == 0) 1833 bustype = eisa_level_intr_mask ? BUS_EISA : BUS_ISA; 1834 for (i = 0; i < 2; i++) { 1835 if (((busid = apic_find_bus_id(bustype)) != -1) && 1836 ((intrp = apic_find_io_intr_w_busid(irqno, busid)) 1837 != NULL)) { 1838 if ((newirq = apic_setup_irq_table(dip, irqno, 1839 intrp, ispec, NULL, type)) != -1) { 1840 return (newirq); 1841 } 1842 goto defconf; 1843 } 1844 bustype = (bustype == BUS_EISA) ? BUS_ISA : BUS_EISA; 1845 } 1846 } 1847 1848 /* MPS default configuration */ 1849 defconf: 1850 newirq = apic_setup_irq_table(dip, irqno, NULL, ispec, NULL, type); 1851 if (newirq == -1) 1852 return (newirq); 1853 ASSERT(IRQINDEX(newirq) == irqno); 1854 ASSERT(apic_irq_table[irqno]); 1855 return (newirq); 1856 } 1857 1858 1859 1860 1861 1862 1863 /* 1864 * On machines with PCI-PCI bridges, a device behind a PCI-PCI bridge 1865 * needs special handling. We may need to chase up the device tree, 1866 * using the PCI-PCI Bridge specification's "rotating IPIN assumptions", 1867 * to find the IPIN at the root bus that relates to the IPIN on the 1868 * subsidiary bus (for ACPI or MP). We may, however, have an entry 1869 * in the MP table or the ACPI namespace for this device itself. 1870 * We handle both cases in the search below. 1871 */ 1872 /* this is the non-acpi version */ 1873 static int 1874 apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, int child_ipin, 1875 struct apic_io_intr **intrp) 1876 { 1877 dev_info_t *dipp, *dip; 1878 int pci_irq; 1879 ddi_acc_handle_t cfg_handle; 1880 int bridge_devno, bridge_bus; 1881 int ipin; 1882 1883 dip = idip; 1884 1885 /*CONSTCOND*/ 1886 while (1) { 1887 if (((dipp = ddi_get_parent(dip)) == (dev_info_t *)NULL) || 1888 (pci_config_setup(dipp, &cfg_handle) != DDI_SUCCESS)) 1889 return (-1); 1890 if ((pci_config_get8(cfg_handle, PCI_CONF_BASCLASS) == 1891 PCI_CLASS_BRIDGE) && (pci_config_get8(cfg_handle, 1892 PCI_CONF_SUBCLASS) == PCI_BRIDGE_PCI)) { 1893 pci_config_teardown(&cfg_handle); 1894 if (acpica_get_bdf(dipp, &bridge_bus, &bridge_devno, 1895 NULL) != 0) 1896 return (-1); 1897 /* 1898 * This is the rotating scheme documented in the 1899 * PCI-to-PCI spec. If the PCI-to-PCI bridge is 1900 * behind another PCI-to-PCI bridge, then it needs 1901 * to keep ascending until an interrupt entry is 1902 * found or the root is reached. 1903 */ 1904 ipin = (child_devno + child_ipin) % PCI_INTD; 1905 if (bridge_bus == 0 && apic_pci_bus_total == 1) 1906 bridge_bus = (int)apic_single_pci_busid; 1907 pci_irq = ((bridge_devno & 0x1f) << 2) | 1908 (ipin & 0x3); 1909 if ((*intrp = apic_find_io_intr_w_busid(pci_irq, 1910 bridge_bus)) != NULL) { 1911 return (pci_irq); 1912 } 1913 dip = dipp; 1914 child_devno = bridge_devno; 1915 child_ipin = ipin; 1916 } else { 1917 pci_config_teardown(&cfg_handle); 1918 return (-1); 1919 } 1920 } 1921 /*LINTED: function will not fall off the bottom */ 1922 } 1923 1924 1925 1926 1927 static uchar_t 1928 acpi_find_ioapic(int irq) 1929 { 1930 int i; 1931 1932 for (i = 0; i < apic_io_max; i++) { 1933 if (irq >= apic_io_vectbase[i] && irq <= apic_io_vectend[i]) 1934 return (i); 1935 } 1936 return (0xFF); /* shouldn't happen */ 1937 } 1938 1939 /* 1940 * See if two irqs are compatible for sharing a vector. 1941 * Currently we only support sharing of PCI devices. 1942 */ 1943 static int 1944 acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2) 1945 { 1946 uint_t level1, po1; 1947 uint_t level2, po2; 1948 1949 /* Assume active high by default */ 1950 po1 = 0; 1951 po2 = 0; 1952 1953 if (iflag1.bustype != iflag2.bustype || iflag1.bustype != BUS_PCI) 1954 return (0); 1955 1956 if (iflag1.intr_el == INTR_EL_CONFORM) 1957 level1 = AV_LEVEL; 1958 else 1959 level1 = (iflag1.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0; 1960 1961 if (level1 && ((iflag1.intr_po == INTR_PO_ACTIVE_LOW) || 1962 (iflag1.intr_po == INTR_PO_CONFORM))) 1963 po1 = AV_ACTIVE_LOW; 1964 1965 if (iflag2.intr_el == INTR_EL_CONFORM) 1966 level2 = AV_LEVEL; 1967 else 1968 level2 = (iflag2.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0; 1969 1970 if (level2 && ((iflag2.intr_po == INTR_PO_ACTIVE_LOW) || 1971 (iflag2.intr_po == INTR_PO_CONFORM))) 1972 po2 = AV_ACTIVE_LOW; 1973 1974 if ((level1 == level2) && (po1 == po2)) 1975 return (1); 1976 1977 return (0); 1978 } 1979 1980 /* 1981 * Attempt to share vector with someone else 1982 */ 1983 static int 1984 apic_share_vector(int irqno, iflag_t *intr_flagp, short intr_index, int ipl, 1985 uchar_t ioapicindex, uchar_t ipin, apic_irq_t **irqptrp) 1986 { 1987 #ifdef DEBUG 1988 apic_irq_t *tmpirqp = NULL; 1989 #endif /* DEBUG */ 1990 apic_irq_t *irqptr, dummyirq; 1991 int newirq, chosen_irq = -1, share = 127; 1992 int lowest, highest, i; 1993 uchar_t share_id; 1994 1995 DDI_INTR_IMPLDBG((CE_CONT, "apic_share_vector: irqno=0x%x " 1996 "intr_index=0x%x ipl=0x%x\n", irqno, intr_index, ipl)); 1997 1998 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK; 1999 lowest = apic_ipltopri[ipl-1] + APIC_VECTOR_PER_IPL; 2000 2001 if (highest < lowest) /* Both ipl and ipl-1 map to same pri */ 2002 lowest -= APIC_VECTOR_PER_IPL; 2003 dummyirq.airq_mps_intr_index = intr_index; 2004 dummyirq.airq_ioapicindex = ioapicindex; 2005 dummyirq.airq_intin_no = ipin; 2006 if (intr_flagp) 2007 dummyirq.airq_iflag = *intr_flagp; 2008 apic_record_rdt_entry(&dummyirq, irqno); 2009 for (i = lowest; i <= highest; i++) { 2010 newirq = apic_vector_to_irq[i]; 2011 if (newirq == APIC_RESV_IRQ) 2012 continue; 2013 irqptr = apic_irq_table[newirq]; 2014 2015 if ((dummyirq.airq_rdt_entry & 0xFF00) != 2016 (irqptr->airq_rdt_entry & 0xFF00)) 2017 /* not compatible */ 2018 continue; 2019 2020 if (irqptr->airq_share < share) { 2021 share = irqptr->airq_share; 2022 chosen_irq = newirq; 2023 } 2024 } 2025 if (chosen_irq != -1) { 2026 /* 2027 * Assign a share id which is free or which is larger 2028 * than the largest one. 2029 */ 2030 share_id = 1; 2031 mutex_enter(&airq_mutex); 2032 irqptr = apic_irq_table[chosen_irq]; 2033 while (irqptr) { 2034 if (irqptr->airq_mps_intr_index == FREE_INDEX) { 2035 share_id = irqptr->airq_share_id; 2036 break; 2037 } 2038 if (share_id <= irqptr->airq_share_id) 2039 share_id = irqptr->airq_share_id + 1; 2040 #ifdef DEBUG 2041 tmpirqp = irqptr; 2042 #endif /* DEBUG */ 2043 irqptr = irqptr->airq_next; 2044 } 2045 if (!irqptr) { 2046 irqptr = kmem_zalloc(sizeof (apic_irq_t), KM_SLEEP); 2047 irqptr->airq_temp_cpu = IRQ_UNINIT; 2048 irqptr->airq_next = 2049 apic_irq_table[chosen_irq]->airq_next; 2050 apic_irq_table[chosen_irq]->airq_next = irqptr; 2051 #ifdef DEBUG 2052 tmpirqp = apic_irq_table[chosen_irq]; 2053 #endif /* DEBUG */ 2054 } 2055 irqptr->airq_mps_intr_index = intr_index; 2056 irqptr->airq_ioapicindex = ioapicindex; 2057 irqptr->airq_intin_no = ipin; 2058 if (intr_flagp) 2059 irqptr->airq_iflag = *intr_flagp; 2060 irqptr->airq_vector = apic_irq_table[chosen_irq]->airq_vector; 2061 irqptr->airq_share_id = share_id; 2062 apic_record_rdt_entry(irqptr, irqno); 2063 *irqptrp = irqptr; 2064 #ifdef DEBUG 2065 /* shuffle the pointers to test apic_delspl path */ 2066 if (tmpirqp) { 2067 tmpirqp->airq_next = irqptr->airq_next; 2068 irqptr->airq_next = apic_irq_table[chosen_irq]; 2069 apic_irq_table[chosen_irq] = irqptr; 2070 } 2071 #endif /* DEBUG */ 2072 mutex_exit(&airq_mutex); 2073 return (VIRTIRQ(chosen_irq, share_id)); 2074 } 2075 return (-1); 2076 } 2077 2078 /* 2079 * 2080 */ 2081 static int 2082 apic_setup_irq_table(dev_info_t *dip, int irqno, struct apic_io_intr *intrp, 2083 struct intrspec *ispec, iflag_t *intr_flagp, int type) 2084 { 2085 int origirq = ispec->intrspec_vec; 2086 uchar_t ipl = ispec->intrspec_pri; 2087 int newirq, intr_index; 2088 uchar_t ipin, ioapic, ioapicindex, vector; 2089 apic_irq_t *irqptr; 2090 major_t major; 2091 dev_info_t *sdip; 2092 2093 DDI_INTR_IMPLDBG((CE_CONT, "apic_setup_irq_table: dip=0x%p type=%d " 2094 "irqno=0x%x origirq=0x%x\n", (void *)dip, type, irqno, origirq)); 2095 2096 ASSERT(ispec != NULL); 2097 2098 major = (dip != NULL) ? ddi_name_to_major(ddi_get_name(dip)) : 0; 2099 2100 if (DDI_INTR_IS_MSI_OR_MSIX(type)) { 2101 /* MSI/X doesn't need to setup ioapic stuffs */ 2102 ioapicindex = 0xff; 2103 ioapic = 0xff; 2104 ipin = (uchar_t)0xff; 2105 intr_index = (type == DDI_INTR_TYPE_MSI) ? MSI_INDEX : 2106 MSIX_INDEX; 2107 mutex_enter(&airq_mutex); 2108 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) == -1) { 2109 mutex_exit(&airq_mutex); 2110 /* need an irq for MSI/X to index into autovect[] */ 2111 cmn_err(CE_WARN, "No interrupt irq: %s instance %d", 2112 ddi_get_name(dip), ddi_get_instance(dip)); 2113 return (-1); 2114 } 2115 mutex_exit(&airq_mutex); 2116 2117 } else if (intrp != NULL) { 2118 intr_index = (int)(intrp - apic_io_intrp); 2119 ioapic = intrp->intr_destid; 2120 ipin = intrp->intr_destintin; 2121 /* Find ioapicindex. If destid was ALL, we will exit with 0. */ 2122 for (ioapicindex = apic_io_max - 1; ioapicindex; ioapicindex--) 2123 if (apic_io_id[ioapicindex] == ioapic) 2124 break; 2125 ASSERT((ioapic == apic_io_id[ioapicindex]) || 2126 (ioapic == INTR_ALL_APIC)); 2127 2128 /* check whether this intin# has been used by another irqno */ 2129 if ((newirq = apic_find_intin(ioapicindex, ipin)) != -1) { 2130 return (newirq); 2131 } 2132 2133 } else if (intr_flagp != NULL) { 2134 /* ACPI case */ 2135 intr_index = ACPI_INDEX; 2136 ioapicindex = acpi_find_ioapic(irqno); 2137 ASSERT(ioapicindex != 0xFF); 2138 ioapic = apic_io_id[ioapicindex]; 2139 ipin = irqno - apic_io_vectbase[ioapicindex]; 2140 if (apic_irq_table[irqno] && 2141 apic_irq_table[irqno]->airq_mps_intr_index == ACPI_INDEX) { 2142 ASSERT(apic_irq_table[irqno]->airq_intin_no == ipin && 2143 apic_irq_table[irqno]->airq_ioapicindex == 2144 ioapicindex); 2145 return (irqno); 2146 } 2147 2148 } else { 2149 /* default configuration */ 2150 ioapicindex = 0; 2151 ioapic = apic_io_id[ioapicindex]; 2152 ipin = (uchar_t)irqno; 2153 intr_index = DEFAULT_INDEX; 2154 } 2155 2156 if (ispec == NULL) { 2157 APIC_VERBOSE_IOAPIC((CE_WARN, "No intrspec for irqno = %x\n", 2158 irqno)); 2159 } else if ((vector = apic_allocate_vector(ipl, irqno, 0)) == 0) { 2160 if ((newirq = apic_share_vector(irqno, intr_flagp, intr_index, 2161 ipl, ioapicindex, ipin, &irqptr)) != -1) { 2162 irqptr->airq_ipl = ipl; 2163 irqptr->airq_origirq = (uchar_t)origirq; 2164 irqptr->airq_dip = dip; 2165 irqptr->airq_major = major; 2166 sdip = apic_irq_table[IRQINDEX(newirq)]->airq_dip; 2167 /* This is OK to do really */ 2168 if (sdip == NULL) { 2169 cmn_err(CE_WARN, "Sharing vectors: %s" 2170 " instance %d and SCI", 2171 ddi_get_name(dip), ddi_get_instance(dip)); 2172 } else { 2173 cmn_err(CE_WARN, "Sharing vectors: %s" 2174 " instance %d and %s instance %d", 2175 ddi_get_name(sdip), ddi_get_instance(sdip), 2176 ddi_get_name(dip), ddi_get_instance(dip)); 2177 } 2178 return (newirq); 2179 } 2180 /* try high priority allocation now that share has failed */ 2181 if ((vector = apic_allocate_vector(ipl, irqno, 1)) == 0) { 2182 cmn_err(CE_WARN, "No interrupt vector: %s instance %d", 2183 ddi_get_name(dip), ddi_get_instance(dip)); 2184 return (-1); 2185 } 2186 } 2187 2188 mutex_enter(&airq_mutex); 2189 if (apic_irq_table[irqno] == NULL) { 2190 irqptr = kmem_zalloc(sizeof (apic_irq_t), KM_SLEEP); 2191 irqptr->airq_temp_cpu = IRQ_UNINIT; 2192 apic_irq_table[irqno] = irqptr; 2193 } else { 2194 irqptr = apic_irq_table[irqno]; 2195 if (irqptr->airq_mps_intr_index != FREE_INDEX) { 2196 /* 2197 * The slot is used by another irqno, so allocate 2198 * a free irqno for this interrupt 2199 */ 2200 newirq = apic_allocate_irq(apic_first_avail_irq); 2201 if (newirq == -1) { 2202 mutex_exit(&airq_mutex); 2203 return (-1); 2204 } 2205 irqno = newirq; 2206 irqptr = apic_irq_table[irqno]; 2207 if (irqptr == NULL) { 2208 irqptr = kmem_zalloc(sizeof (apic_irq_t), 2209 KM_SLEEP); 2210 irqptr->airq_temp_cpu = IRQ_UNINIT; 2211 apic_irq_table[irqno] = irqptr; 2212 } 2213 vector = apic_modify_vector(vector, newirq); 2214 } 2215 } 2216 apic_max_device_irq = max(irqno, apic_max_device_irq); 2217 apic_min_device_irq = min(irqno, apic_min_device_irq); 2218 mutex_exit(&airq_mutex); 2219 irqptr->airq_ioapicindex = ioapicindex; 2220 irqptr->airq_intin_no = ipin; 2221 irqptr->airq_ipl = ipl; 2222 irqptr->airq_vector = vector; 2223 irqptr->airq_origirq = (uchar_t)origirq; 2224 irqptr->airq_share_id = 0; 2225 irqptr->airq_mps_intr_index = (short)intr_index; 2226 irqptr->airq_dip = dip; 2227 irqptr->airq_major = major; 2228 irqptr->airq_cpu = apic_bind_intr(dip, irqno, ioapic, ipin); 2229 if (intr_flagp) 2230 irqptr->airq_iflag = *intr_flagp; 2231 2232 if (!DDI_INTR_IS_MSI_OR_MSIX(type)) { 2233 /* setup I/O APIC entry for non-MSI/X interrupts */ 2234 apic_record_rdt_entry(irqptr, irqno); 2235 } 2236 return (irqno); 2237 } 2238 2239 /* 2240 * return the cpu to which this intr should be bound. 2241 * Check properties or any other mechanism to see if user wants it 2242 * bound to a specific CPU. If so, return the cpu id with high bit set. 2243 * If not, use the policy to choose a cpu and return the id. 2244 */ 2245 uchar_t 2246 apic_bind_intr(dev_info_t *dip, int irq, uchar_t ioapicid, uchar_t intin) 2247 { 2248 int instance, instno, prop_len, bind_cpu, count; 2249 uint_t i, rc; 2250 uchar_t cpu; 2251 major_t major; 2252 char *name, *drv_name, *prop_val, *cptr; 2253 char prop_name[32]; 2254 2255 2256 if (apic_intr_policy == INTR_LOWEST_PRIORITY) 2257 return (IRQ_UNBOUND); 2258 2259 drv_name = NULL; 2260 rc = DDI_PROP_NOT_FOUND; 2261 major = (major_t)-1; 2262 if (dip != NULL) { 2263 name = ddi_get_name(dip); 2264 major = ddi_name_to_major(name); 2265 drv_name = ddi_major_to_name(major); 2266 instance = ddi_get_instance(dip); 2267 if (apic_intr_policy == INTR_ROUND_ROBIN_WITH_AFFINITY) { 2268 i = apic_min_device_irq; 2269 for (; i <= apic_max_device_irq; i++) { 2270 2271 if ((i == irq) || (apic_irq_table[i] == NULL) || 2272 (apic_irq_table[i]->airq_mps_intr_index 2273 == FREE_INDEX)) 2274 continue; 2275 2276 if ((apic_irq_table[i]->airq_major == major) && 2277 (!(apic_irq_table[i]->airq_cpu & 2278 IRQ_USER_BOUND))) { 2279 2280 cpu = apic_irq_table[i]->airq_cpu; 2281 2282 cmn_err(CE_CONT, 2283 "!%s: %s (%s) instance #%d " 2284 "vector 0x%x ioapic 0x%x " 2285 "intin 0x%x is bound to cpu %d\n", 2286 psm_name, 2287 name, drv_name, instance, irq, 2288 ioapicid, intin, cpu); 2289 return (cpu); 2290 } 2291 } 2292 } 2293 /* 2294 * search for "drvname"_intpt_bind_cpus property first, the 2295 * syntax of the property should be "a[,b,c,...]" where 2296 * instance 0 binds to cpu a, instance 1 binds to cpu b, 2297 * instance 3 binds to cpu c... 2298 * ddi_getlongprop() will search /option first, then / 2299 * if "drvname"_intpt_bind_cpus doesn't exist, then find 2300 * intpt_bind_cpus property. The syntax is the same, and 2301 * it applies to all the devices if its "drvname" specific 2302 * property doesn't exist 2303 */ 2304 (void) strcpy(prop_name, drv_name); 2305 (void) strcat(prop_name, "_intpt_bind_cpus"); 2306 rc = ddi_getlongprop(DDI_DEV_T_ANY, dip, 0, prop_name, 2307 (caddr_t)&prop_val, &prop_len); 2308 if (rc != DDI_PROP_SUCCESS) { 2309 rc = ddi_getlongprop(DDI_DEV_T_ANY, dip, 0, 2310 "intpt_bind_cpus", (caddr_t)&prop_val, &prop_len); 2311 } 2312 } 2313 if (rc == DDI_PROP_SUCCESS) { 2314 for (i = count = 0; i < (prop_len - 1); i++) 2315 if (prop_val[i] == ',') 2316 count++; 2317 if (prop_val[i-1] != ',') 2318 count++; 2319 /* 2320 * if somehow the binding instances defined in the 2321 * property are not enough for this instno., then 2322 * reuse the pattern for the next instance until 2323 * it reaches the requested instno 2324 */ 2325 instno = instance % count; 2326 i = 0; 2327 cptr = prop_val; 2328 while (i < instno) 2329 if (*cptr++ == ',') 2330 i++; 2331 bind_cpu = stoi(&cptr); 2332 kmem_free(prop_val, prop_len); 2333 /* if specific cpu is bogus, then default to cpu 0 */ 2334 if (bind_cpu >= apic_nproc) { 2335 cmn_err(CE_WARN, "%s: %s=%s: CPU %d not present", 2336 psm_name, prop_name, prop_val, bind_cpu); 2337 bind_cpu = 0; 2338 } else { 2339 /* indicate that we are bound at user request */ 2340 bind_cpu |= IRQ_USER_BOUND; 2341 } 2342 /* 2343 * no need to check apic_cpus[].aci_status, if specific cpu is 2344 * not up, then post_cpu_start will handle it. 2345 */ 2346 } else { 2347 bind_cpu = apic_next_bind_cpu++; 2348 if (bind_cpu >= apic_nproc) { 2349 apic_next_bind_cpu = 1; 2350 bind_cpu = 0; 2351 } 2352 } 2353 if (drv_name != NULL) 2354 cmn_err(CE_CONT, "!%s: %s (%s) instance %d " 2355 "vector 0x%x ioapic 0x%x intin 0x%x is bound to cpu %d\n", 2356 psm_name, name, drv_name, instance, 2357 irq, ioapicid, intin, bind_cpu & ~IRQ_USER_BOUND); 2358 else 2359 cmn_err(CE_CONT, "!%s: " 2360 "vector 0x%x ioapic 0x%x intin 0x%x is bound to cpu %d\n", 2361 psm_name, irq, ioapicid, intin, bind_cpu & ~IRQ_USER_BOUND); 2362 2363 return ((uchar_t)bind_cpu); 2364 } 2365 2366 static struct apic_io_intr * 2367 apic_find_io_intr_w_busid(int irqno, int busid) 2368 { 2369 struct apic_io_intr *intrp; 2370 2371 /* 2372 * It can have more than 1 entry with same source bus IRQ, 2373 * but unique with the source bus id 2374 */ 2375 intrp = apic_io_intrp; 2376 if (intrp != NULL) { 2377 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 2378 if (intrp->intr_irq == irqno && 2379 intrp->intr_busid == busid && 2380 intrp->intr_type == IO_INTR_INT) 2381 return (intrp); 2382 intrp++; 2383 } 2384 } 2385 APIC_VERBOSE_IOAPIC((CE_NOTE, "Did not find io intr for irqno:" 2386 "busid %x:%x\n", irqno, busid)); 2387 return ((struct apic_io_intr *)NULL); 2388 } 2389 2390 2391 struct mps_bus_info { 2392 char *bus_name; 2393 int bus_id; 2394 } bus_info_array[] = { 2395 "ISA ", BUS_ISA, 2396 "PCI ", BUS_PCI, 2397 "EISA ", BUS_EISA, 2398 "XPRESS", BUS_XPRESS, 2399 "PCMCIA", BUS_PCMCIA, 2400 "VL ", BUS_VL, 2401 "CBUS ", BUS_CBUS, 2402 "CBUSII", BUS_CBUSII, 2403 "FUTURE", BUS_FUTURE, 2404 "INTERN", BUS_INTERN, 2405 "MBI ", BUS_MBI, 2406 "MBII ", BUS_MBII, 2407 "MPI ", BUS_MPI, 2408 "MPSA ", BUS_MPSA, 2409 "NUBUS ", BUS_NUBUS, 2410 "TC ", BUS_TC, 2411 "VME ", BUS_VME, 2412 "PCI-E ", BUS_PCIE 2413 }; 2414 2415 static int 2416 apic_find_bus_type(char *bus) 2417 { 2418 int i = 0; 2419 2420 for (; i < sizeof (bus_info_array)/sizeof (struct mps_bus_info); i++) 2421 if (strncmp(bus, bus_info_array[i].bus_name, 2422 strlen(bus_info_array[i].bus_name)) == 0) 2423 return (bus_info_array[i].bus_id); 2424 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus type for bus %s", bus)); 2425 return (0); 2426 } 2427 2428 static int 2429 apic_find_bus(int busid) 2430 { 2431 struct apic_bus *busp; 2432 2433 busp = apic_busp; 2434 while (busp->bus_entry == APIC_BUS_ENTRY) { 2435 if (busp->bus_id == busid) 2436 return (apic_find_bus_type((char *)&busp->bus_str1)); 2437 busp++; 2438 } 2439 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus for bus id %x", busid)); 2440 return (0); 2441 } 2442 2443 static int 2444 apic_find_bus_id(int bustype) 2445 { 2446 struct apic_bus *busp; 2447 2448 busp = apic_busp; 2449 while (busp->bus_entry == APIC_BUS_ENTRY) { 2450 if (apic_find_bus_type((char *)&busp->bus_str1) == bustype) 2451 return (busp->bus_id); 2452 busp++; 2453 } 2454 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus id for bustype %x", 2455 bustype)); 2456 return (-1); 2457 } 2458 2459 /* 2460 * Check if a particular irq need to be reserved for any io_intr 2461 */ 2462 static struct apic_io_intr * 2463 apic_find_io_intr(int irqno) 2464 { 2465 struct apic_io_intr *intrp; 2466 2467 intrp = apic_io_intrp; 2468 if (intrp != NULL) { 2469 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 2470 if (intrp->intr_irq == irqno && 2471 intrp->intr_type == IO_INTR_INT) 2472 return (intrp); 2473 intrp++; 2474 } 2475 } 2476 return ((struct apic_io_intr *)NULL); 2477 } 2478 2479 /* 2480 * Check if the given ioapicindex intin combination has already been assigned 2481 * an irq. If so return irqno. Else -1 2482 */ 2483 static int 2484 apic_find_intin(uchar_t ioapic, uchar_t intin) 2485 { 2486 apic_irq_t *irqptr; 2487 int i; 2488 2489 /* find ioapic and intin in the apic_irq_table[] and return the index */ 2490 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) { 2491 irqptr = apic_irq_table[i]; 2492 while (irqptr) { 2493 if ((irqptr->airq_mps_intr_index >= 0) && 2494 (irqptr->airq_intin_no == intin) && 2495 (irqptr->airq_ioapicindex == ioapic)) { 2496 APIC_VERBOSE_IOAPIC((CE_NOTE, "!Found irq " 2497 "entry for ioapic:intin %x:%x " 2498 "shared interrupts ?", ioapic, intin)); 2499 return (i); 2500 } 2501 irqptr = irqptr->airq_next; 2502 } 2503 } 2504 return (-1); 2505 } 2506 2507 int 2508 apic_allocate_irq(int irq) 2509 { 2510 int freeirq, i; 2511 2512 if ((freeirq = apic_find_free_irq(irq, (APIC_RESV_IRQ - 1))) == -1) 2513 if ((freeirq = apic_find_free_irq(APIC_FIRST_FREE_IRQ, 2514 (irq - 1))) == -1) { 2515 /* 2516 * if BIOS really defines every single irq in the mps 2517 * table, then don't worry about conflicting with 2518 * them, just use any free slot in apic_irq_table 2519 */ 2520 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) { 2521 if ((apic_irq_table[i] == NULL) || 2522 apic_irq_table[i]->airq_mps_intr_index == 2523 FREE_INDEX) { 2524 freeirq = i; 2525 break; 2526 } 2527 } 2528 if (freeirq == -1) { 2529 /* This shouldn't happen, but just in case */ 2530 cmn_err(CE_WARN, "%s: NO available IRQ", psm_name); 2531 return (-1); 2532 } 2533 } 2534 if (apic_irq_table[freeirq] == NULL) { 2535 apic_irq_table[freeirq] = 2536 kmem_zalloc(sizeof (apic_irq_t), KM_NOSLEEP); 2537 if (apic_irq_table[freeirq] == NULL) { 2538 cmn_err(CE_WARN, "%s: NO memory to allocate IRQ", 2539 psm_name); 2540 return (-1); 2541 } 2542 apic_irq_table[freeirq]->airq_mps_intr_index = FREE_INDEX; 2543 } 2544 return (freeirq); 2545 } 2546 2547 static int 2548 apic_find_free_irq(int start, int end) 2549 { 2550 int i; 2551 2552 for (i = start; i <= end; i++) 2553 /* Check if any I/O entry needs this IRQ */ 2554 if (apic_find_io_intr(i) == NULL) { 2555 /* Then see if it is free */ 2556 if ((apic_irq_table[i] == NULL) || 2557 (apic_irq_table[i]->airq_mps_intr_index == 2558 FREE_INDEX)) { 2559 return (i); 2560 } 2561 } 2562 return (-1); 2563 } 2564 2565 2566 /* 2567 * Mark vector as being in the process of being deleted. Interrupts 2568 * may still come in on some CPU. The moment an interrupt comes with 2569 * the new vector, we know we can free the old one. Called only from 2570 * addspl and delspl with interrupts disabled. Because an interrupt 2571 * can be shared, but no interrupt from either device may come in, 2572 * we also use a timeout mechanism, which we arbitrarily set to 2573 * apic_revector_timeout microseconds. 2574 */ 2575 static void 2576 apic_mark_vector(uchar_t oldvector, uchar_t newvector) 2577 { 2578 ulong_t iflag; 2579 2580 iflag = intr_clear(); 2581 lock_set(&apic_revector_lock); 2582 if (!apic_oldvec_to_newvec) { 2583 apic_oldvec_to_newvec = 2584 kmem_zalloc(sizeof (newvector) * APIC_MAX_VECTOR * 2, 2585 KM_NOSLEEP); 2586 2587 if (!apic_oldvec_to_newvec) { 2588 /* 2589 * This failure is not catastrophic. 2590 * But, the oldvec will never be freed. 2591 */ 2592 apic_error |= APIC_ERR_MARK_VECTOR_FAIL; 2593 lock_clear(&apic_revector_lock); 2594 intr_restore(iflag); 2595 return; 2596 } 2597 apic_newvec_to_oldvec = &apic_oldvec_to_newvec[APIC_MAX_VECTOR]; 2598 } 2599 2600 /* See if we already did this for drivers which do double addintrs */ 2601 if (apic_oldvec_to_newvec[oldvector] != newvector) { 2602 apic_oldvec_to_newvec[oldvector] = newvector; 2603 apic_newvec_to_oldvec[newvector] = oldvector; 2604 apic_revector_pending++; 2605 } 2606 lock_clear(&apic_revector_lock); 2607 intr_restore(iflag); 2608 (void) timeout(apic_xlate_vector_free_timeout_handler, 2609 (void *)(uintptr_t)oldvector, drv_usectohz(apic_revector_timeout)); 2610 } 2611 2612 /* 2613 * xlate_vector is called from intr_enter if revector_pending is set. 2614 * It will xlate it if needed and mark the old vector as free. 2615 */ 2616 uchar_t 2617 apic_xlate_vector(uchar_t vector) 2618 { 2619 uchar_t newvector, oldvector = 0; 2620 2621 lock_set(&apic_revector_lock); 2622 /* Do we really need to do this ? */ 2623 if (!apic_revector_pending) { 2624 lock_clear(&apic_revector_lock); 2625 return (vector); 2626 } 2627 if ((newvector = apic_oldvec_to_newvec[vector]) != 0) 2628 oldvector = vector; 2629 else { 2630 /* 2631 * The incoming vector is new . See if a stale entry is 2632 * remaining 2633 */ 2634 if ((oldvector = apic_newvec_to_oldvec[vector]) != 0) 2635 newvector = vector; 2636 } 2637 2638 if (oldvector) { 2639 apic_revector_pending--; 2640 apic_oldvec_to_newvec[oldvector] = 0; 2641 apic_newvec_to_oldvec[newvector] = 0; 2642 apic_free_vector(oldvector); 2643 lock_clear(&apic_revector_lock); 2644 /* There could have been more than one reprogramming! */ 2645 return (apic_xlate_vector(newvector)); 2646 } 2647 lock_clear(&apic_revector_lock); 2648 return (vector); 2649 } 2650 2651 void 2652 apic_xlate_vector_free_timeout_handler(void *arg) 2653 { 2654 ulong_t iflag; 2655 uchar_t oldvector, newvector; 2656 2657 oldvector = (uchar_t)(uintptr_t)arg; 2658 iflag = intr_clear(); 2659 lock_set(&apic_revector_lock); 2660 if ((newvector = apic_oldvec_to_newvec[oldvector]) != 0) { 2661 apic_free_vector(oldvector); 2662 apic_oldvec_to_newvec[oldvector] = 0; 2663 apic_newvec_to_oldvec[newvector] = 0; 2664 apic_revector_pending--; 2665 } 2666 2667 lock_clear(&apic_revector_lock); 2668 intr_restore(iflag); 2669 } 2670 2671 2672 /* 2673 * compute the polarity, trigger mode and vector for programming into 2674 * the I/O apic and record in airq_rdt_entry. 2675 */ 2676 static void 2677 apic_record_rdt_entry(apic_irq_t *irqptr, int irq) 2678 { 2679 int ioapicindex, bus_type, vector; 2680 short intr_index; 2681 uint_t level, po, io_po; 2682 struct apic_io_intr *iointrp; 2683 2684 intr_index = irqptr->airq_mps_intr_index; 2685 DDI_INTR_IMPLDBG((CE_CONT, "apic_record_rdt_entry: intr_index=%d " 2686 "irq = 0x%x dip = 0x%p vector = 0x%x\n", intr_index, irq, 2687 (void *)irqptr->airq_dip, irqptr->airq_vector)); 2688 2689 if (intr_index == RESERVE_INDEX) { 2690 apic_error |= APIC_ERR_INVALID_INDEX; 2691 return; 2692 } else if (APIC_IS_MSI_OR_MSIX_INDEX(intr_index)) { 2693 return; 2694 } 2695 2696 vector = irqptr->airq_vector; 2697 ioapicindex = irqptr->airq_ioapicindex; 2698 /* Assume edge triggered by default */ 2699 level = 0; 2700 /* Assume active high by default */ 2701 po = 0; 2702 2703 if (intr_index == DEFAULT_INDEX || intr_index == FREE_INDEX) { 2704 ASSERT(irq < 16); 2705 if (eisa_level_intr_mask & (1 << irq)) 2706 level = AV_LEVEL; 2707 if (intr_index == FREE_INDEX && apic_defconf == 0) 2708 apic_error |= APIC_ERR_INVALID_INDEX; 2709 } else if (intr_index == ACPI_INDEX) { 2710 bus_type = irqptr->airq_iflag.bustype; 2711 if (irqptr->airq_iflag.intr_el == INTR_EL_CONFORM) { 2712 if (bus_type == BUS_PCI) 2713 level = AV_LEVEL; 2714 } else 2715 level = (irqptr->airq_iflag.intr_el == INTR_EL_LEVEL) ? 2716 AV_LEVEL : 0; 2717 if (level && 2718 ((irqptr->airq_iflag.intr_po == INTR_PO_ACTIVE_LOW) || 2719 (irqptr->airq_iflag.intr_po == INTR_PO_CONFORM && 2720 bus_type == BUS_PCI))) 2721 po = AV_ACTIVE_LOW; 2722 } else { 2723 iointrp = apic_io_intrp + intr_index; 2724 bus_type = apic_find_bus(iointrp->intr_busid); 2725 if (iointrp->intr_el == INTR_EL_CONFORM) { 2726 if ((irq < 16) && (eisa_level_intr_mask & (1 << irq))) 2727 level = AV_LEVEL; 2728 else if (bus_type == BUS_PCI) 2729 level = AV_LEVEL; 2730 } else 2731 level = (iointrp->intr_el == INTR_EL_LEVEL) ? 2732 AV_LEVEL : 0; 2733 if (level && ((iointrp->intr_po == INTR_PO_ACTIVE_LOW) || 2734 (iointrp->intr_po == INTR_PO_CONFORM && 2735 bus_type == BUS_PCI))) 2736 po = AV_ACTIVE_LOW; 2737 } 2738 if (level) 2739 apic_level_intr[irq] = 1; 2740 /* 2741 * The 82489DX External APIC cannot do active low polarity interrupts. 2742 */ 2743 if (po && (apic_io_ver[ioapicindex] != IOAPIC_VER_82489DX)) 2744 io_po = po; 2745 else 2746 io_po = 0; 2747 2748 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) 2749 printf("setio: ioapic=%x intin=%x level=%x po=%x vector=%x\n", 2750 ioapicindex, irqptr->airq_intin_no, level, io_po, vector); 2751 2752 irqptr->airq_rdt_entry = level|io_po|vector; 2753 } 2754 2755 /* 2756 * Bind interrupt corresponding to irq_ptr to bind_cpu. 2757 * Must be called with interrupts disabled and apic_ioapic_lock held 2758 */ 2759 int 2760 apic_rebind(apic_irq_t *irq_ptr, int bind_cpu, 2761 struct ioapic_reprogram_data *drep) 2762 { 2763 int ioapicindex, intin_no; 2764 uchar_t airq_temp_cpu; 2765 apic_cpus_info_t *cpu_infop; 2766 uint32_t rdt_entry; 2767 int which_irq; 2768 2769 which_irq = apic_vector_to_irq[irq_ptr->airq_vector]; 2770 2771 intin_no = irq_ptr->airq_intin_no; 2772 ioapicindex = irq_ptr->airq_ioapicindex; 2773 airq_temp_cpu = irq_ptr->airq_temp_cpu; 2774 if (airq_temp_cpu != IRQ_UNINIT && airq_temp_cpu != IRQ_UNBOUND) { 2775 if (airq_temp_cpu & IRQ_USER_BOUND) 2776 /* Mask off high bit so it can be used as array index */ 2777 airq_temp_cpu &= ~IRQ_USER_BOUND; 2778 2779 ASSERT(airq_temp_cpu < apic_nproc); 2780 } 2781 2782 /* 2783 * Can't bind to a CPU that's not accepting interrupts: 2784 */ 2785 cpu_infop = &apic_cpus[bind_cpu & ~IRQ_USER_BOUND]; 2786 if (!(cpu_infop->aci_status & APIC_CPU_INTR_ENABLE)) 2787 return (1); 2788 2789 /* 2790 * If we are about to change the interrupt vector for this interrupt, 2791 * and this interrupt is level-triggered, attached to an IOAPIC, 2792 * has been delivered to a CPU and that CPU has not handled it 2793 * yet, we cannot reprogram the IOAPIC now. 2794 */ 2795 if (!APIC_IS_MSI_OR_MSIX_INDEX(irq_ptr->airq_mps_intr_index)) { 2796 2797 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, 2798 intin_no); 2799 2800 if ((irq_ptr->airq_vector != RDT_VECTOR(rdt_entry)) && 2801 apic_check_stuck_interrupt(irq_ptr, airq_temp_cpu, 2802 bind_cpu, ioapicindex, intin_no, which_irq, drep) != 0) { 2803 2804 return (0); 2805 } 2806 2807 /* 2808 * NOTE: We do not unmask the RDT here, as an interrupt MAY 2809 * still come in before we have a chance to reprogram it below. 2810 * The reprogramming below will simultaneously change and 2811 * unmask the RDT entry. 2812 */ 2813 2814 if ((uchar_t)bind_cpu == IRQ_UNBOUND) { 2815 rdt_entry = AV_LDEST | AV_LOPRI | 2816 irq_ptr->airq_rdt_entry; 2817 2818 /* Write the RDT entry -- no specific CPU binding */ 2819 WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapicindex, intin_no, 2820 AV_TOALL); 2821 2822 if (airq_temp_cpu != IRQ_UNINIT && airq_temp_cpu != 2823 IRQ_UNBOUND) 2824 apic_cpus[airq_temp_cpu].aci_temp_bound--; 2825 2826 /* 2827 * Write the vector, trigger, and polarity portion of 2828 * the RDT 2829 */ 2830 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, intin_no, 2831 rdt_entry); 2832 2833 irq_ptr->airq_temp_cpu = IRQ_UNBOUND; 2834 return (0); 2835 } 2836 } 2837 2838 if (bind_cpu & IRQ_USER_BOUND) { 2839 cpu_infop->aci_bound++; 2840 } else { 2841 cpu_infop->aci_temp_bound++; 2842 } 2843 ASSERT((bind_cpu & ~IRQ_USER_BOUND) < apic_nproc); 2844 if (!APIC_IS_MSI_OR_MSIX_INDEX(irq_ptr->airq_mps_intr_index)) { 2845 /* Write the RDT entry -- bind to a specific CPU: */ 2846 WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapicindex, intin_no, 2847 cpu_infop->aci_local_id << APIC_ID_BIT_OFFSET); 2848 } 2849 if ((airq_temp_cpu != IRQ_UNBOUND) && (airq_temp_cpu != IRQ_UNINIT)) { 2850 apic_cpus[airq_temp_cpu].aci_temp_bound--; 2851 } 2852 if (!APIC_IS_MSI_OR_MSIX_INDEX(irq_ptr->airq_mps_intr_index)) { 2853 2854 rdt_entry = AV_PDEST | AV_FIXED | irq_ptr->airq_rdt_entry; 2855 2856 /* Write the vector, trigger, and polarity portion of the RDT */ 2857 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, intin_no, 2858 rdt_entry); 2859 2860 } else { 2861 int type = (irq_ptr->airq_mps_intr_index == MSI_INDEX) ? 2862 DDI_INTR_TYPE_MSI : DDI_INTR_TYPE_MSIX; 2863 if (ioapicindex == irq_ptr->airq_origirq) { 2864 /* first one */ 2865 DDI_INTR_IMPLDBG((CE_CONT, "apic_rebind: call " 2866 "apic_pci_msi_enable_vector\n")); 2867 if (apic_pci_msi_enable_vector(irq_ptr->airq_dip, type, 2868 which_irq, irq_ptr->airq_vector, 2869 irq_ptr->airq_intin_no, 2870 cpu_infop->aci_local_id) != PSM_SUCCESS) { 2871 cmn_err(CE_WARN, "pcplusmp: " 2872 "apic_pci_msi_enable_vector " 2873 "returned PSM_FAILURE"); 2874 } 2875 } 2876 if ((ioapicindex + irq_ptr->airq_intin_no - 1) == 2877 irq_ptr->airq_origirq) { /* last one */ 2878 DDI_INTR_IMPLDBG((CE_CONT, "apic_rebind: call " 2879 "pci_msi_enable_mode\n")); 2880 if (apic_pci_msi_enable_mode(irq_ptr->airq_dip, 2881 type, which_irq) != PSM_SUCCESS) { 2882 DDI_INTR_IMPLDBG((CE_CONT, "pcplusmp: " 2883 "pci_msi_enable failed\n")); 2884 (void) apic_pci_msi_unconfigure( 2885 irq_ptr->airq_dip, type, which_irq); 2886 } 2887 } 2888 } 2889 irq_ptr->airq_temp_cpu = (uchar_t)bind_cpu; 2890 apic_redist_cpu_skip &= ~(1 << (bind_cpu & ~IRQ_USER_BOUND)); 2891 return (0); 2892 } 2893 2894 static void 2895 apic_last_ditch_clear_remote_irr(int ioapic_ix, int intin_no) 2896 { 2897 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no) 2898 & AV_REMOTE_IRR) != 0) { 2899 /* 2900 * Trying to clear the bit through normal 2901 * channels has failed. So as a last-ditch 2902 * effort, try to set the trigger mode to 2903 * edge, then to level. This has been 2904 * observed to work on many systems. 2905 */ 2906 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 2907 intin_no, 2908 READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 2909 intin_no) & ~AV_LEVEL); 2910 2911 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 2912 intin_no, 2913 READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 2914 intin_no) | AV_LEVEL); 2915 2916 /* 2917 * If the bit's STILL set, this interrupt may 2918 * be hosed. 2919 */ 2920 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 2921 intin_no) & AV_REMOTE_IRR) != 0) { 2922 2923 prom_printf("%s: Remote IRR still " 2924 "not clear for IOAPIC %d intin %d.\n" 2925 "\tInterrupts to this pin may cease " 2926 "functioning.\n", psm_name, ioapic_ix, 2927 intin_no); 2928 #ifdef DEBUG 2929 apic_last_ditch_reprogram_failures++; 2930 #endif 2931 } 2932 } 2933 } 2934 2935 /* 2936 * This function is protected by apic_ioapic_lock coupled with the 2937 * fact that interrupts are disabled. 2938 */ 2939 static void 2940 delete_defer_repro_ent(int which_irq) 2941 { 2942 ASSERT(which_irq >= 0); 2943 ASSERT(which_irq <= 255); 2944 2945 if (apic_reprogram_info[which_irq].done) 2946 return; 2947 2948 apic_reprogram_info[which_irq].done = B_TRUE; 2949 2950 #ifdef DEBUG 2951 apic_defer_repro_total_retries += 2952 apic_reprogram_info[which_irq].tries; 2953 2954 apic_defer_repro_successes++; 2955 #endif 2956 2957 if (--apic_reprogram_outstanding == 0) { 2958 2959 setlvlx = apic_intr_exit; 2960 } 2961 } 2962 2963 2964 /* 2965 * Interrupts must be disabled during this function to prevent 2966 * self-deadlock. Interrupts are disabled because this function 2967 * is called from apic_check_stuck_interrupt(), which is called 2968 * from apic_rebind(), which requires its caller to disable interrupts. 2969 */ 2970 static void 2971 add_defer_repro_ent(apic_irq_t *irq_ptr, int which_irq, int new_bind_cpu) 2972 { 2973 ASSERT(which_irq >= 0); 2974 ASSERT(which_irq <= 255); 2975 2976 /* 2977 * On the off-chance that there's already a deferred 2978 * reprogramming on this irq, check, and if so, just update the 2979 * CPU and irq pointer to which the interrupt is targeted, then return. 2980 */ 2981 if (!apic_reprogram_info[which_irq].done) { 2982 apic_reprogram_info[which_irq].bindcpu = new_bind_cpu; 2983 apic_reprogram_info[which_irq].irqp = irq_ptr; 2984 return; 2985 } 2986 2987 apic_reprogram_info[which_irq].irqp = irq_ptr; 2988 apic_reprogram_info[which_irq].bindcpu = new_bind_cpu; 2989 apic_reprogram_info[which_irq].tries = 0; 2990 /* 2991 * This must be the last thing set, since we're not 2992 * grabbing any locks, apic_try_deferred_reprogram() will 2993 * make its decision about using this entry iff done 2994 * is false. 2995 */ 2996 apic_reprogram_info[which_irq].done = B_FALSE; 2997 2998 /* 2999 * If there were previously no deferred reprogrammings, change 3000 * setlvlx to call apic_try_deferred_reprogram() 3001 */ 3002 if (++apic_reprogram_outstanding == 1) { 3003 3004 setlvlx = apic_try_deferred_reprogram; 3005 } 3006 } 3007 3008 static void 3009 apic_try_deferred_reprogram(int prev_ipl, int irq) 3010 { 3011 int reproirq, iflag; 3012 struct ioapic_reprogram_data *drep; 3013 3014 apic_intr_exit(prev_ipl, irq); 3015 3016 if (!lock_try(&apic_defer_reprogram_lock)) { 3017 return; 3018 } 3019 3020 /* 3021 * Acquire the apic_ioapic_lock so that any other operations that 3022 * may affect the apic_reprogram_info state are serialized. 3023 * It's still possible for the last deferred reprogramming to clear 3024 * between the time we entered this function and the time we get to 3025 * the for loop below. In that case, *setlvlx will have been set 3026 * back to apic_intr_exit and drep will be NULL. (There's no way to 3027 * stop that from happening -- we would need to grab a lock before 3028 * calling *setlvlx, which is neither realistic nor prudent). 3029 */ 3030 iflag = intr_clear(); 3031 lock_set(&apic_ioapic_lock); 3032 3033 /* 3034 * For each deferred RDT entry, try to reprogram it now. Note that 3035 * there is no lock acquisition to read apic_reprogram_info because 3036 * '.done' is set only after the other fields in the structure are set. 3037 */ 3038 3039 drep = NULL; 3040 for (reproirq = 0; reproirq <= APIC_MAX_VECTOR; reproirq++) { 3041 if (apic_reprogram_info[reproirq].done == B_FALSE) { 3042 drep = &apic_reprogram_info[reproirq]; 3043 break; 3044 } 3045 } 3046 3047 /* 3048 * Either we found a deferred action to perform, or 3049 * we entered this function spuriously, after *setlvlx 3050 * was restored to point to apic_intr_enter. Any other 3051 * permutation is invalid. 3052 */ 3053 ASSERT(drep != NULL || *setlvlx == apic_intr_exit); 3054 3055 /* 3056 * Though we can't really do anything about errors 3057 * at this point, keep track of them for reporting. 3058 * Note that it is very possible for apic_setup_io_intr 3059 * to re-register this very timeout if the Remote IRR bit 3060 * has not yet cleared. 3061 */ 3062 3063 #ifdef DEBUG 3064 if (drep != NULL) { 3065 if (apic_setup_io_intr(drep, reproirq, B_TRUE) != 0) { 3066 apic_deferred_setup_failures++; 3067 } 3068 } else { 3069 apic_deferred_spurious_enters++; 3070 } 3071 #else 3072 if (drep != NULL) 3073 (void) apic_setup_io_intr(drep, reproirq, B_TRUE); 3074 #endif 3075 3076 lock_clear(&apic_ioapic_lock); 3077 intr_restore(iflag); 3078 3079 lock_clear(&apic_defer_reprogram_lock); 3080 } 3081 3082 static void 3083 apic_ioapic_wait_pending_clear(int ioapic_ix, int intin_no) 3084 { 3085 int waited; 3086 3087 /* 3088 * Wait for the delivery pending bit to clear. 3089 */ 3090 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no) & 3091 (AV_LEVEL|AV_PENDING)) == (AV_LEVEL|AV_PENDING)) { 3092 3093 /* 3094 * If we're still waiting on the delivery of this interrupt, 3095 * continue to wait here until it is delivered (this should be 3096 * a very small amount of time, but include a timeout just in 3097 * case). 3098 */ 3099 for (waited = 0; waited < apic_max_reps_clear_pending; 3100 waited++) { 3101 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 3102 intin_no) & AV_PENDING) == 0) { 3103 break; 3104 } 3105 } 3106 } 3107 } 3108 3109 3110 /* 3111 * Checks to see if the IOAPIC interrupt entry specified has its Remote IRR 3112 * bit set. Calls functions that modify the function that setlvlx points to, 3113 * so that the reprogramming can be retried very shortly. 3114 * 3115 * This function will mask the RDT entry if the interrupt is level-triggered. 3116 * (The caller is responsible for unmasking the RDT entry.) 3117 * 3118 * Returns non-zero if the caller should defer IOAPIC reprogramming. 3119 */ 3120 static int 3121 apic_check_stuck_interrupt(apic_irq_t *irq_ptr, int old_bind_cpu, 3122 int new_bind_cpu, int ioapic_ix, int intin_no, int which_irq, 3123 struct ioapic_reprogram_data *drep) 3124 { 3125 int32_t rdt_entry; 3126 int waited; 3127 int reps = 0; 3128 3129 /* 3130 * Wait for the delivery pending bit to clear. 3131 */ 3132 do { 3133 ++reps; 3134 3135 apic_ioapic_wait_pending_clear(ioapic_ix, intin_no); 3136 3137 /* 3138 * Mask the RDT entry, but only if it's a level-triggered 3139 * interrupt 3140 */ 3141 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 3142 intin_no); 3143 if ((rdt_entry & (AV_LEVEL|AV_MASK)) == AV_LEVEL) { 3144 3145 /* Mask it */ 3146 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no, 3147 AV_MASK | rdt_entry); 3148 } 3149 3150 if ((rdt_entry & AV_LEVEL) == AV_LEVEL) { 3151 /* 3152 * If there was a race and an interrupt was injected 3153 * just before we masked, check for that case here. 3154 * Then, unmask the RDT entry and try again. If we're 3155 * on our last try, don't unmask (because we want the 3156 * RDT entry to remain masked for the rest of the 3157 * function). 3158 */ 3159 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 3160 intin_no); 3161 if ((rdt_entry & AV_PENDING) && 3162 (reps < apic_max_reps_clear_pending)) { 3163 /* Unmask it */ 3164 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 3165 intin_no, rdt_entry & ~AV_MASK); 3166 } 3167 } 3168 3169 } while ((rdt_entry & AV_PENDING) && 3170 (reps < apic_max_reps_clear_pending)); 3171 3172 #ifdef DEBUG 3173 if (rdt_entry & AV_PENDING) 3174 apic_intr_deliver_timeouts++; 3175 #endif 3176 3177 /* 3178 * If the remote IRR bit is set, then the interrupt has been sent 3179 * to a CPU for processing. We have no choice but to wait for 3180 * that CPU to process the interrupt, at which point the remote IRR 3181 * bit will be cleared. 3182 */ 3183 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no) & 3184 (AV_LEVEL|AV_REMOTE_IRR)) == (AV_LEVEL|AV_REMOTE_IRR)) { 3185 3186 /* 3187 * If the CPU that this RDT is bound to is NOT the current 3188 * CPU, wait until that CPU handles the interrupt and ACKs 3189 * it. If this interrupt is not bound to any CPU (that is, 3190 * if it's bound to the logical destination of "anyone"), it 3191 * may have been delivered to the current CPU so handle that 3192 * case by deferring the reprogramming (below). 3193 */ 3194 if ((old_bind_cpu != IRQ_UNBOUND) && 3195 (old_bind_cpu != IRQ_UNINIT) && 3196 (old_bind_cpu != psm_get_cpu_id())) { 3197 for (waited = 0; waited < apic_max_reps_clear_pending; 3198 waited++) { 3199 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 3200 intin_no) & AV_REMOTE_IRR) == 0) { 3201 3202 delete_defer_repro_ent(which_irq); 3203 3204 /* Remote IRR has cleared! */ 3205 return (0); 3206 } 3207 } 3208 } 3209 3210 /* 3211 * If we waited and the Remote IRR bit is still not cleared, 3212 * AND if we've invoked the timeout APIC_REPROGRAM_MAX_TIMEOUTS 3213 * times for this interrupt, try the last-ditch workaround: 3214 */ 3215 if (drep && drep->tries >= APIC_REPROGRAM_MAX_TRIES) { 3216 3217 apic_last_ditch_clear_remote_irr(ioapic_ix, intin_no); 3218 3219 /* Mark this one as reprogrammed: */ 3220 delete_defer_repro_ent(which_irq); 3221 3222 return (0); 3223 } else { 3224 #ifdef DEBUG 3225 apic_intr_deferrals++; 3226 #endif 3227 3228 /* 3229 * If waiting for the Remote IRR bit (above) didn't 3230 * allow it to clear, defer the reprogramming. 3231 * Add a new deferred-programming entry if the 3232 * caller passed a NULL one (and update the existing one 3233 * in case anything changed). 3234 */ 3235 add_defer_repro_ent(irq_ptr, which_irq, new_bind_cpu); 3236 if (drep) 3237 drep->tries++; 3238 3239 /* Inform caller to defer IOAPIC programming: */ 3240 return (1); 3241 } 3242 3243 } 3244 3245 /* Remote IRR is clear */ 3246 delete_defer_repro_ent(which_irq); 3247 3248 return (0); 3249 } 3250 3251 /* 3252 * Called to migrate all interrupts at an irq to another cpu. 3253 * Must be called with interrupts disabled and apic_ioapic_lock held 3254 */ 3255 int 3256 apic_rebind_all(apic_irq_t *irq_ptr, int bind_cpu) 3257 { 3258 apic_irq_t *irqptr = irq_ptr; 3259 int retval = 0; 3260 3261 while (irqptr) { 3262 if (irqptr->airq_temp_cpu != IRQ_UNINIT) 3263 retval |= apic_rebind(irqptr, bind_cpu, NULL); 3264 irqptr = irqptr->airq_next; 3265 } 3266 3267 return (retval); 3268 } 3269 3270 /* 3271 * apic_intr_redistribute does all the messy computations for identifying 3272 * which interrupt to move to which CPU. Currently we do just one interrupt 3273 * at a time. This reduces the time we spent doing all this within clock 3274 * interrupt. When it is done in idle, we could do more than 1. 3275 * First we find the most busy and the most free CPU (time in ISR only) 3276 * skipping those CPUs that has been identified as being ineligible (cpu_skip) 3277 * Then we look for IRQs which are closest to the difference between the 3278 * most busy CPU and the average ISR load. We try to find one whose load 3279 * is less than difference.If none exists, then we chose one larger than the 3280 * difference, provided it does not make the most idle CPU worse than the 3281 * most busy one. In the end, we clear all the busy fields for CPUs. For 3282 * IRQs, they are cleared as they are scanned. 3283 */ 3284 void 3285 apic_intr_redistribute() 3286 { 3287 int busiest_cpu, most_free_cpu; 3288 int cpu_free, cpu_busy, max_busy, min_busy; 3289 int min_free, diff; 3290 int average_busy, cpus_online; 3291 int i, busy, iflag; 3292 apic_cpus_info_t *cpu_infop; 3293 apic_irq_t *min_busy_irq = NULL; 3294 apic_irq_t *max_busy_irq = NULL; 3295 3296 busiest_cpu = most_free_cpu = -1; 3297 cpu_free = cpu_busy = max_busy = average_busy = 0; 3298 min_free = apic_sample_factor_redistribution; 3299 cpus_online = 0; 3300 /* 3301 * Below we will check for CPU_INTR_ENABLE, bound, temp_bound, temp_cpu 3302 * without ioapic_lock. That is OK as we are just doing statistical 3303 * sampling anyway and any inaccuracy now will get corrected next time 3304 * The call to rebind which actually changes things will make sure 3305 * we are consistent. 3306 */ 3307 for (i = 0; i < apic_nproc; i++) { 3308 if (!(apic_redist_cpu_skip & (1 << i)) && 3309 (apic_cpus[i].aci_status & APIC_CPU_INTR_ENABLE)) { 3310 3311 cpu_infop = &apic_cpus[i]; 3312 /* 3313 * If no unbound interrupts or only 1 total on this 3314 * CPU, skip 3315 */ 3316 if (!cpu_infop->aci_temp_bound || 3317 (cpu_infop->aci_bound + cpu_infop->aci_temp_bound) 3318 == 1) { 3319 apic_redist_cpu_skip |= 1 << i; 3320 continue; 3321 } 3322 3323 busy = cpu_infop->aci_busy; 3324 average_busy += busy; 3325 cpus_online++; 3326 if (max_busy < busy) { 3327 max_busy = busy; 3328 busiest_cpu = i; 3329 } 3330 if (min_free > busy) { 3331 min_free = busy; 3332 most_free_cpu = i; 3333 } 3334 if (busy > apic_int_busy_mark) { 3335 cpu_busy |= 1 << i; 3336 } else { 3337 if (busy < apic_int_free_mark) 3338 cpu_free |= 1 << i; 3339 } 3340 } 3341 } 3342 if ((cpu_busy && cpu_free) || 3343 (max_busy >= (min_free + apic_diff_for_redistribution))) { 3344 3345 apic_num_imbalance++; 3346 #ifdef DEBUG 3347 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) { 3348 prom_printf( 3349 "redistribute busy=%x free=%x max=%x min=%x", 3350 cpu_busy, cpu_free, max_busy, min_free); 3351 } 3352 #endif /* DEBUG */ 3353 3354 3355 average_busy /= cpus_online; 3356 3357 diff = max_busy - average_busy; 3358 min_busy = max_busy; /* start with the max possible value */ 3359 max_busy = 0; 3360 min_busy_irq = max_busy_irq = NULL; 3361 i = apic_min_device_irq; 3362 for (; i < apic_max_device_irq; i++) { 3363 apic_irq_t *irq_ptr; 3364 /* Change to linked list per CPU ? */ 3365 if ((irq_ptr = apic_irq_table[i]) == NULL) 3366 continue; 3367 /* Check for irq_busy & decide which one to move */ 3368 /* Also zero them for next round */ 3369 if ((irq_ptr->airq_temp_cpu == busiest_cpu) && 3370 irq_ptr->airq_busy) { 3371 if (irq_ptr->airq_busy < diff) { 3372 /* 3373 * Check for least busy CPU, 3374 * best fit or what ? 3375 */ 3376 if (max_busy < irq_ptr->airq_busy) { 3377 /* 3378 * Most busy within the 3379 * required differential 3380 */ 3381 max_busy = irq_ptr->airq_busy; 3382 max_busy_irq = irq_ptr; 3383 } 3384 } else { 3385 if (min_busy > irq_ptr->airq_busy) { 3386 /* 3387 * least busy, but more than 3388 * the reqd diff 3389 */ 3390 if (min_busy < 3391 (diff + average_busy - 3392 min_free)) { 3393 /* 3394 * Making sure new cpu 3395 * will not end up 3396 * worse 3397 */ 3398 min_busy = 3399 irq_ptr->airq_busy; 3400 3401 min_busy_irq = irq_ptr; 3402 } 3403 } 3404 } 3405 } 3406 irq_ptr->airq_busy = 0; 3407 } 3408 3409 if (max_busy_irq != NULL) { 3410 #ifdef DEBUG 3411 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) { 3412 prom_printf("rebinding %x to %x", 3413 max_busy_irq->airq_vector, most_free_cpu); 3414 } 3415 #endif /* DEBUG */ 3416 iflag = intr_clear(); 3417 if (lock_try(&apic_ioapic_lock)) { 3418 if (apic_rebind_all(max_busy_irq, 3419 most_free_cpu) == 0) { 3420 /* Make change permenant */ 3421 max_busy_irq->airq_cpu = 3422 (uchar_t)most_free_cpu; 3423 } 3424 lock_clear(&apic_ioapic_lock); 3425 } 3426 intr_restore(iflag); 3427 3428 } else if (min_busy_irq != NULL) { 3429 #ifdef DEBUG 3430 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) { 3431 prom_printf("rebinding %x to %x", 3432 min_busy_irq->airq_vector, most_free_cpu); 3433 } 3434 #endif /* DEBUG */ 3435 3436 iflag = intr_clear(); 3437 if (lock_try(&apic_ioapic_lock)) { 3438 if (apic_rebind_all(min_busy_irq, 3439 most_free_cpu) == 0) { 3440 /* Make change permenant */ 3441 min_busy_irq->airq_cpu = 3442 (uchar_t)most_free_cpu; 3443 } 3444 lock_clear(&apic_ioapic_lock); 3445 } 3446 intr_restore(iflag); 3447 3448 } else { 3449 if (cpu_busy != (1 << busiest_cpu)) { 3450 apic_redist_cpu_skip |= 1 << busiest_cpu; 3451 /* 3452 * We leave cpu_skip set so that next time we 3453 * can choose another cpu 3454 */ 3455 } 3456 } 3457 apic_num_rebind++; 3458 } else { 3459 /* 3460 * found nothing. Could be that we skipped over valid CPUs 3461 * or we have balanced everything. If we had a variable 3462 * ticks_for_redistribution, it could be increased here. 3463 * apic_int_busy, int_free etc would also need to be 3464 * changed. 3465 */ 3466 if (apic_redist_cpu_skip) 3467 apic_redist_cpu_skip = 0; 3468 } 3469 for (i = 0; i < apic_nproc; i++) { 3470 apic_cpus[i].aci_busy = 0; 3471 } 3472 } 3473 3474 void 3475 apic_cleanup_busy() 3476 { 3477 int i; 3478 apic_irq_t *irq_ptr; 3479 3480 for (i = 0; i < apic_nproc; i++) { 3481 apic_cpus[i].aci_busy = 0; 3482 } 3483 3484 for (i = apic_min_device_irq; i < apic_max_device_irq; i++) { 3485 if ((irq_ptr = apic_irq_table[i]) != NULL) 3486 irq_ptr->airq_busy = 0; 3487 } 3488 } 3489 3490 3491 static int 3492 apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid, 3493 int ipin, int *pci_irqp, iflag_t *intr_flagp) 3494 { 3495 3496 int status; 3497 acpi_psm_lnk_t acpipsmlnk; 3498 3499 if ((status = acpi_get_irq_cache_ent(busid, devid, ipin, pci_irqp, 3500 intr_flagp)) == ACPI_PSM_SUCCESS) { 3501 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Found irqno %d " 3502 "from cache for device %s, instance #%d\n", psm_name, 3503 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip))); 3504 return (status); 3505 } 3506 3507 bzero(&acpipsmlnk, sizeof (acpi_psm_lnk_t)); 3508 3509 if ((status = acpi_translate_pci_irq(dip, ipin, pci_irqp, intr_flagp, 3510 &acpipsmlnk)) == ACPI_PSM_FAILURE) { 3511 APIC_VERBOSE_IRQ((CE_WARN, "%s: " 3512 " acpi_translate_pci_irq failed for device %s, instance" 3513 " #%d", psm_name, ddi_get_name(dip), 3514 ddi_get_instance(dip))); 3515 return (status); 3516 } 3517 3518 if (status == ACPI_PSM_PARTIAL && acpipsmlnk.lnkobj != NULL) { 3519 status = apic_acpi_irq_configure(&acpipsmlnk, dip, pci_irqp, 3520 intr_flagp); 3521 if (status != ACPI_PSM_SUCCESS) { 3522 status = acpi_get_current_irq_resource(&acpipsmlnk, 3523 pci_irqp, intr_flagp); 3524 } 3525 } 3526 3527 if (status == ACPI_PSM_SUCCESS) { 3528 acpi_new_irq_cache_ent(busid, devid, ipin, *pci_irqp, 3529 intr_flagp, &acpipsmlnk); 3530 3531 APIC_VERBOSE_IRQ((CE_CONT, "%s: [ACPI] " 3532 "new irq %d for device %s, instance #%d\n", psm_name, 3533 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip))); 3534 } 3535 3536 return (status); 3537 } 3538 3539 /* 3540 * Adds an entry to the irq list passed in, and returns the new list. 3541 * Entries are added in priority order (lower numerical priorities are 3542 * placed closer to the head of the list) 3543 */ 3544 static prs_irq_list_t * 3545 acpi_insert_prs_irq_ent(prs_irq_list_t *listp, int priority, int irq, 3546 iflag_t *iflagp, acpi_prs_private_t *prsprvp) 3547 { 3548 struct prs_irq_list_ent *newent, *prevp = NULL, *origlistp; 3549 3550 newent = kmem_zalloc(sizeof (struct prs_irq_list_ent), KM_SLEEP); 3551 3552 newent->list_prio = priority; 3553 newent->irq = irq; 3554 newent->intrflags = *iflagp; 3555 newent->prsprv = *prsprvp; 3556 /* ->next is NULL from kmem_zalloc */ 3557 3558 /* 3559 * New list -- return the new entry as the list. 3560 */ 3561 if (listp == NULL) 3562 return (newent); 3563 3564 /* 3565 * Save original list pointer for return (since we're not modifying 3566 * the head) 3567 */ 3568 origlistp = listp; 3569 3570 /* 3571 * Insertion sort, with entries with identical keys stored AFTER 3572 * existing entries (the less-than-or-equal test of priority does 3573 * this for us). 3574 */ 3575 while (listp != NULL && listp->list_prio <= priority) { 3576 prevp = listp; 3577 listp = listp->next; 3578 } 3579 3580 newent->next = listp; 3581 3582 if (prevp == NULL) { /* Add at head of list (newent is the new head) */ 3583 return (newent); 3584 } else { 3585 prevp->next = newent; 3586 return (origlistp); 3587 } 3588 } 3589 3590 /* 3591 * Frees the list passed in, deallocating all memory and leaving *listpp 3592 * set to NULL. 3593 */ 3594 static void 3595 acpi_destroy_prs_irq_list(prs_irq_list_t **listpp) 3596 { 3597 struct prs_irq_list_ent *nextp; 3598 3599 ASSERT(listpp != NULL); 3600 3601 while (*listpp != NULL) { 3602 nextp = (*listpp)->next; 3603 kmem_free(*listpp, sizeof (struct prs_irq_list_ent)); 3604 *listpp = nextp; 3605 } 3606 } 3607 3608 /* 3609 * apic_choose_irqs_from_prs returns a list of irqs selected from the list of 3610 * irqs returned by the link device's _PRS method. The irqs are chosen 3611 * to minimize contention in situations where the interrupt link device 3612 * can be programmed to steer interrupts to different interrupt controller 3613 * inputs (some of which may already be in use). The list is sorted in order 3614 * of irqs to use, with the highest priority given to interrupt controller 3615 * inputs that are not shared. When an interrupt controller input 3616 * must be shared, apic_choose_irqs_from_prs adds the possible irqs to the 3617 * returned list in the order that minimizes sharing (thereby ensuring lowest 3618 * possible latency from interrupt trigger time to ISR execution time). 3619 */ 3620 static prs_irq_list_t * 3621 apic_choose_irqs_from_prs(acpi_irqlist_t *irqlistent, dev_info_t *dip, 3622 int crs_irq) 3623 { 3624 int32_t irq; 3625 int i; 3626 prs_irq_list_t *prsirqlistp = NULL; 3627 iflag_t iflags; 3628 3629 while (irqlistent != NULL) { 3630 irqlistent->intr_flags.bustype = BUS_PCI; 3631 3632 for (i = 0; i < irqlistent->num_irqs; i++) { 3633 3634 irq = irqlistent->irqs[i]; 3635 3636 if (irq <= 0) { 3637 /* invalid irq number */ 3638 continue; 3639 } 3640 3641 if ((irq < 16) && (apic_reserved_irqlist[irq])) 3642 continue; 3643 3644 if ((apic_irq_table[irq] == NULL) || 3645 (apic_irq_table[irq]->airq_dip == dip)) { 3646 3647 prsirqlistp = acpi_insert_prs_irq_ent( 3648 prsirqlistp, 0 /* Highest priority */, irq, 3649 &irqlistent->intr_flags, 3650 &irqlistent->acpi_prs_prv); 3651 3652 /* 3653 * If we do not prefer the current irq from _CRS 3654 * or if we do and this irq is the same as the 3655 * current irq from _CRS, this is the one 3656 * to pick. 3657 */ 3658 if (!(apic_prefer_crs) || (irq == crs_irq)) { 3659 return (prsirqlistp); 3660 } 3661 continue; 3662 } 3663 3664 /* 3665 * Edge-triggered interrupts cannot be shared 3666 */ 3667 if (irqlistent->intr_flags.intr_el == INTR_EL_EDGE) 3668 continue; 3669 3670 /* 3671 * To work around BIOSes that contain incorrect 3672 * interrupt polarity information in interrupt 3673 * descriptors returned by _PRS, we assume that 3674 * the polarity of the other device sharing this 3675 * interrupt controller input is compatible. 3676 * If it's not, the caller will catch it when 3677 * the caller invokes the link device's _CRS method 3678 * (after invoking its _SRS method). 3679 */ 3680 iflags = irqlistent->intr_flags; 3681 iflags.intr_po = 3682 apic_irq_table[irq]->airq_iflag.intr_po; 3683 3684 if (!acpi_intr_compatible(iflags, 3685 apic_irq_table[irq]->airq_iflag)) { 3686 APIC_VERBOSE_IRQ((CE_CONT, "!%s: irq %d " 3687 "not compatible [%x:%x:%x !~ %x:%x:%x]", 3688 psm_name, irq, 3689 iflags.intr_po, 3690 iflags.intr_el, 3691 iflags.bustype, 3692 apic_irq_table[irq]->airq_iflag.intr_po, 3693 apic_irq_table[irq]->airq_iflag.intr_el, 3694 apic_irq_table[irq]->airq_iflag.bustype)); 3695 continue; 3696 } 3697 3698 /* 3699 * If we prefer the irq from _CRS, no need 3700 * to search any further (and make sure 3701 * to add this irq with the highest priority 3702 * so it's tried first). 3703 */ 3704 if (crs_irq == irq && apic_prefer_crs) { 3705 3706 return (acpi_insert_prs_irq_ent( 3707 prsirqlistp, 3708 0 /* Highest priority */, 3709 irq, &iflags, 3710 &irqlistent->acpi_prs_prv)); 3711 } 3712 3713 /* 3714 * Priority is equal to the share count (lower 3715 * share count is higher priority). Note that 3716 * the intr flags passed in here are the ones we 3717 * changed above -- if incorrect, it will be 3718 * caught by the caller's _CRS flags comparison. 3719 */ 3720 prsirqlistp = acpi_insert_prs_irq_ent( 3721 prsirqlistp, 3722 apic_irq_table[irq]->airq_share, irq, 3723 &iflags, &irqlistent->acpi_prs_prv); 3724 } 3725 3726 /* Go to the next irqlist entry */ 3727 irqlistent = irqlistent->next; 3728 } 3729 3730 return (prsirqlistp); 3731 } 3732 3733 /* 3734 * Configures the irq for the interrupt link device identified by 3735 * acpipsmlnkp. 3736 * 3737 * Gets the current and the list of possible irq settings for the 3738 * device. If apic_unconditional_srs is not set, and the current 3739 * resource setting is in the list of possible irq settings, 3740 * current irq resource setting is passed to the caller. 3741 * 3742 * Otherwise, picks an irq number from the list of possible irq 3743 * settings, and sets the irq of the device to this value. 3744 * If prefer_crs is set, among a set of irq numbers in the list that have 3745 * the least number of devices sharing the interrupt, we pick current irq 3746 * resource setting if it is a member of this set. 3747 * 3748 * Passes the irq number in the value pointed to by pci_irqp, and 3749 * polarity and sensitivity in the structure pointed to by dipintrflagp 3750 * to the caller. 3751 * 3752 * Note that if setting the irq resource failed, but successfuly obtained 3753 * the current irq resource settings, passes the current irq resources 3754 * and considers it a success. 3755 * 3756 * Returns: 3757 * ACPI_PSM_SUCCESS on success. 3758 * 3759 * ACPI_PSM_FAILURE if an error occured during the configuration or 3760 * if a suitable irq was not found for this device, or if setting the 3761 * irq resource and obtaining the current resource fails. 3762 * 3763 */ 3764 static int 3765 apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip, 3766 int *pci_irqp, iflag_t *dipintr_flagp) 3767 { 3768 int32_t irq; 3769 int cur_irq = -1; 3770 acpi_irqlist_t *irqlistp; 3771 prs_irq_list_t *prs_irq_listp, *prs_irq_entp; 3772 boolean_t found_irq = B_FALSE; 3773 3774 dipintr_flagp->bustype = BUS_PCI; 3775 3776 if ((acpi_get_possible_irq_resources(acpipsmlnkp, &irqlistp)) 3777 == ACPI_PSM_FAILURE) { 3778 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Unable to determine " 3779 "or assign IRQ for device %s, instance #%d: The system was " 3780 "unable to get the list of potential IRQs from ACPI.", 3781 psm_name, ddi_get_name(dip), ddi_get_instance(dip))); 3782 3783 return (ACPI_PSM_FAILURE); 3784 } 3785 3786 if ((acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq, 3787 dipintr_flagp) == ACPI_PSM_SUCCESS) && (!apic_unconditional_srs) && 3788 (cur_irq > 0)) { 3789 /* 3790 * If an IRQ is set in CRS and that IRQ exists in the set 3791 * returned from _PRS, return that IRQ, otherwise print 3792 * a warning 3793 */ 3794 3795 if (acpi_irqlist_find_irq(irqlistp, cur_irq, NULL) 3796 == ACPI_PSM_SUCCESS) { 3797 3798 ASSERT(pci_irqp != NULL); 3799 *pci_irqp = cur_irq; 3800 acpi_free_irqlist(irqlistp); 3801 return (ACPI_PSM_SUCCESS); 3802 } 3803 3804 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find the " 3805 "current irq %d for device %s, instance #%d in ACPI's " 3806 "list of possible irqs for this device. Picking one from " 3807 " the latter list.", psm_name, cur_irq, ddi_get_name(dip), 3808 ddi_get_instance(dip))); 3809 } 3810 3811 if ((prs_irq_listp = apic_choose_irqs_from_prs(irqlistp, dip, 3812 cur_irq)) == NULL) { 3813 3814 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find a " 3815 "suitable irq from the list of possible irqs for device " 3816 "%s, instance #%d in ACPI's list of possible irqs", 3817 psm_name, ddi_get_name(dip), ddi_get_instance(dip))); 3818 3819 acpi_free_irqlist(irqlistp); 3820 return (ACPI_PSM_FAILURE); 3821 } 3822 3823 acpi_free_irqlist(irqlistp); 3824 3825 for (prs_irq_entp = prs_irq_listp; 3826 prs_irq_entp != NULL && found_irq == B_FALSE; 3827 prs_irq_entp = prs_irq_entp->next) { 3828 3829 acpipsmlnkp->acpi_prs_prv = prs_irq_entp->prsprv; 3830 irq = prs_irq_entp->irq; 3831 3832 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Setting irq %d for " 3833 "device %s instance #%d\n", psm_name, irq, 3834 ddi_get_name(dip), ddi_get_instance(dip))); 3835 3836 if ((acpi_set_irq_resource(acpipsmlnkp, irq)) 3837 == ACPI_PSM_SUCCESS) { 3838 /* 3839 * setting irq was successful, check to make sure CRS 3840 * reflects that. If CRS does not agree with what we 3841 * set, return the irq that was set. 3842 */ 3843 3844 if (acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq, 3845 dipintr_flagp) == ACPI_PSM_SUCCESS) { 3846 3847 if (cur_irq != irq) 3848 APIC_VERBOSE_IRQ((CE_WARN, 3849 "!%s: IRQ resource set " 3850 "(irqno %d) for device %s " 3851 "instance #%d, differs from " 3852 "current setting irqno %d", 3853 psm_name, irq, ddi_get_name(dip), 3854 ddi_get_instance(dip), cur_irq)); 3855 } else { 3856 /* 3857 * On at least one system, there was a bug in 3858 * a DSDT method called by _STA, causing _STA to 3859 * indicate that the link device was disabled 3860 * (when, in fact, it was enabled). Since _SRS 3861 * succeeded, assume that _CRS is lying and use 3862 * the iflags from this _PRS interrupt choice. 3863 * If we're wrong about the flags, the polarity 3864 * will be incorrect and we may get an interrupt 3865 * storm, but there's not much else we can do 3866 * at this point. 3867 */ 3868 *dipintr_flagp = prs_irq_entp->intrflags; 3869 } 3870 3871 /* 3872 * Return the irq that was set, and not what _CRS 3873 * reports, since _CRS has been seen to return 3874 * different IRQs than what was passed to _SRS on some 3875 * systems (and just not return successfully on others). 3876 */ 3877 cur_irq = irq; 3878 found_irq = B_TRUE; 3879 } else { 3880 APIC_VERBOSE_IRQ((CE_WARN, "!%s: set resource " 3881 "irq %d failed for device %s instance #%d", 3882 psm_name, irq, ddi_get_name(dip), 3883 ddi_get_instance(dip))); 3884 3885 if (cur_irq == -1) { 3886 acpi_destroy_prs_irq_list(&prs_irq_listp); 3887 return (ACPI_PSM_FAILURE); 3888 } 3889 } 3890 } 3891 3892 acpi_destroy_prs_irq_list(&prs_irq_listp); 3893 3894 if (!found_irq) 3895 return (ACPI_PSM_FAILURE); 3896 3897 ASSERT(pci_irqp != NULL); 3898 *pci_irqp = cur_irq; 3899 return (ACPI_PSM_SUCCESS); 3900 } 3901 3902 void 3903 ioapic_disable_redirection() 3904 { 3905 int ioapic_ix; 3906 int intin_max; 3907 int intin_ix; 3908 3909 /* Disable the I/O APIC redirection entries */ 3910 for (ioapic_ix = 0; ioapic_ix < apic_io_max; ioapic_ix++) { 3911 3912 /* Bits 23-16 define the maximum redirection entries */ 3913 intin_max = (ioapic_read(ioapic_ix, APIC_VERS_CMD) >> 16) 3914 & 0xff; 3915 3916 for (intin_ix = 0; intin_ix < intin_max; intin_ix++) { 3917 /* 3918 * The assumption here is that this is safe, even for 3919 * systems with IOAPICs that suffer from the hardware 3920 * erratum because all devices have been quiesced before 3921 * this function is called from apic_shutdown() 3922 * (or equivalent). If that assumption turns out to be 3923 * false, this mask operation can induce the same 3924 * erratum result we're trying to avoid. 3925 */ 3926 ioapic_write(ioapic_ix, APIC_RDT_CMD + 2 * intin_ix, 3927 AV_MASK); 3928 } 3929 } 3930 } 3931 3932 /* 3933 * Looks for an IOAPIC with the specified physical address in the /ioapics 3934 * node in the device tree (created by the PCI enumerator). 3935 */ 3936 static boolean_t 3937 apic_is_ioapic_AMD_813x(uint32_t physaddr) 3938 { 3939 /* 3940 * Look in /ioapics, for the ioapic with 3941 * the physical address given 3942 */ 3943 dev_info_t *ioapicsnode = ddi_find_devinfo(IOAPICS_NODE_NAME, -1, 0); 3944 dev_info_t *ioapic_child; 3945 boolean_t rv = B_FALSE; 3946 int vid, did; 3947 uint64_t ioapic_paddr; 3948 boolean_t done = B_FALSE; 3949 3950 if (ioapicsnode == NULL) 3951 return (B_FALSE); 3952 3953 /* Load first child: */ 3954 ioapic_child = ddi_get_child(ioapicsnode); 3955 while (!done && ioapic_child != 0) { /* Iterate over children */ 3956 3957 if ((ioapic_paddr = (uint64_t)ddi_prop_get_int64(DDI_DEV_T_ANY, 3958 ioapic_child, DDI_PROP_DONTPASS, "reg", 0)) 3959 != 0 && physaddr == ioapic_paddr) { 3960 3961 vid = ddi_prop_get_int(DDI_DEV_T_ANY, ioapic_child, 3962 DDI_PROP_DONTPASS, IOAPICS_PROP_VENID, 0); 3963 3964 if (vid == VENID_AMD) { 3965 3966 did = ddi_prop_get_int(DDI_DEV_T_ANY, 3967 ioapic_child, DDI_PROP_DONTPASS, 3968 IOAPICS_PROP_DEVID, 0); 3969 3970 if (did == DEVID_8131_IOAPIC || 3971 did == DEVID_8132_IOAPIC) { 3972 3973 rv = B_TRUE; 3974 done = B_TRUE; 3975 } 3976 } 3977 } 3978 3979 if (!done) 3980 ioapic_child = ddi_get_next_sibling(ioapic_child); 3981 } 3982 3983 /* The ioapics node was held by ddi_find_devinfo, so release it */ 3984 ndi_rele_devi(ioapicsnode); 3985 return (rv); 3986 } 3987