1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * PSMI 1.1 extensions are supported only in 2.6 and later versions. 30 * PSMI 1.2 extensions are supported only in 2.7 and later versions. 31 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10. 32 * PSMI 1.5 extensions are supported in Solaris Nevada. 33 */ 34 #define PSMI_1_5 35 36 #include <sys/processor.h> 37 #include <sys/time.h> 38 #include <sys/psm.h> 39 #include <sys/smp_impldefs.h> 40 #include <sys/cram.h> 41 #include <sys/acpi/acpi.h> 42 #include <sys/acpica.h> 43 #include <sys/psm_common.h> 44 #include <sys/apic.h> 45 #include <sys/pit.h> 46 #include <sys/ddi.h> 47 #include <sys/sunddi.h> 48 #include <sys/ddi_impldefs.h> 49 #include <sys/pci.h> 50 #include <sys/promif.h> 51 #include <sys/x86_archext.h> 52 #include <sys/cpc_impl.h> 53 #include <sys/uadmin.h> 54 #include <sys/panic.h> 55 #include <sys/debug.h> 56 #include <sys/archsystm.h> 57 #include <sys/trap.h> 58 #include <sys/machsystm.h> 59 #include <sys/cpuvar.h> 60 #include <sys/rm_platter.h> 61 #include <sys/privregs.h> 62 #include <sys/cyclic.h> 63 #include <sys/note.h> 64 #include <sys/pci_intr_lib.h> 65 #include <sys/sunndi.h> 66 67 68 /* 69 * Local Function Prototypes 70 */ 71 static int apic_handle_defconf(); 72 static int apic_parse_mpct(caddr_t mpct, int bypass); 73 static struct apic_mpfps_hdr *apic_find_fps_sig(caddr_t fptr, int size); 74 static int apic_checksum(caddr_t bptr, int len); 75 static int apic_find_bus_type(char *bus); 76 static int apic_find_bus(int busid); 77 static int apic_find_bus_id(int bustype); 78 static struct apic_io_intr *apic_find_io_intr(int irqno); 79 static int apic_find_free_irq(int start, int end); 80 static void apic_mark_vector(uchar_t oldvector, uchar_t newvector); 81 static void apic_xlate_vector_free_timeout_handler(void *arg); 82 static void apic_reprogram_timeout_handler(void *arg); 83 static int apic_check_stuck_interrupt(apic_irq_t *irq_ptr, int old_bind_cpu, 84 int new_bind_cpu, int apicindex, int intin_no, int which_irq, 85 struct ioapic_reprogram_data *drep); 86 static void apic_record_rdt_entry(apic_irq_t *irqptr, int irq); 87 static struct apic_io_intr *apic_find_io_intr_w_busid(int irqno, int busid); 88 static int apic_find_intin(uchar_t ioapic, uchar_t intin); 89 static int apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, 90 int child_ipin, struct apic_io_intr **intrp); 91 static int apic_setup_irq_table(dev_info_t *dip, int irqno, 92 struct apic_io_intr *intrp, struct intrspec *ispec, iflag_t *intr_flagp, 93 int type); 94 static int apic_setup_sci_irq_table(int irqno, uchar_t ipl, 95 iflag_t *intr_flagp); 96 static void apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp); 97 static void apic_try_deferred_reprogram(int ipl, int vect); 98 static void delete_defer_repro_ent(int which_irq); 99 static void apic_ioapic_wait_pending_clear(int ioapicindex, 100 int intin_no); 101 static boolean_t apic_is_ioapic_AMD_813x(uint32_t physaddr); 102 103 int apic_debug_mps_id = 0; /* 1 - print MPS ID strings */ 104 105 /* ACPI SCI interrupt configuration; -1 if SCI not used */ 106 int apic_sci_vect = -1; 107 iflag_t apic_sci_flags; 108 109 /* 110 * psm name pointer 111 */ 112 static char *psm_name; 113 114 /* ACPI support routines */ 115 static int acpi_probe(char *); 116 static int apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip, 117 int *pci_irqp, iflag_t *intr_flagp); 118 119 static int apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid, 120 int ipin, int *pci_irqp, iflag_t *intr_flagp); 121 static uchar_t acpi_find_ioapic(int irq); 122 static int acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2); 123 124 125 /* 126 * number of bits per byte, from <sys/param.h> 127 */ 128 #define UCHAR_MAX ((1 << NBBY) - 1) 129 130 /* Max wait time (in repetitions) for flags to clear in an RDT entry. */ 131 int apic_max_reps_clear_pending = 1000; 132 133 /* The irq # is implicit in the array index: */ 134 struct ioapic_reprogram_data apic_reprogram_info[APIC_MAX_VECTOR+1]; 135 /* 136 * APIC_MAX_VECTOR + 1 is the maximum # of IRQs as well. ioapic_reprogram_info 137 * is indexed by IRQ number, NOT by vector number. 138 */ 139 140 int apic_intr_policy = INTR_ROUND_ROBIN_WITH_AFFINITY; 141 142 int apic_next_bind_cpu = 1; /* For round robin assignment */ 143 /* start with cpu 1 */ 144 145 /* 146 * If enabled, the distribution works as follows: 147 * On every interrupt entry, the current ipl for the CPU is set in cpu_info 148 * and the irq corresponding to the ipl is also set in the aci_current array. 149 * interrupt exit and setspl (due to soft interrupts) will cause the current 150 * ipl to be be changed. This is cache friendly as these frequently used 151 * paths write into a per cpu structure. 152 * 153 * Sampling is done by checking the structures for all CPUs and incrementing 154 * the busy field of the irq (if any) executing on each CPU and the busy field 155 * of the corresponding CPU. 156 * In periodic mode this is done on every clock interrupt. 157 * In one-shot mode, this is done thru a cyclic with an interval of 158 * apic_redistribute_sample_interval (default 10 milli sec). 159 * 160 * Every apic_sample_factor_redistribution times we sample, we do computations 161 * to decide which interrupt needs to be migrated (see comments 162 * before apic_intr_redistribute(). 163 */ 164 165 /* 166 * Following 3 variables start as % and can be patched or set using an 167 * API to be defined in future. They will be scaled to 168 * sample_factor_redistribution which is in turn set to hertz+1 (in periodic 169 * mode), or 101 in one-shot mode to stagger it away from one sec processing 170 */ 171 172 int apic_int_busy_mark = 60; 173 int apic_int_free_mark = 20; 174 int apic_diff_for_redistribution = 10; 175 176 /* sampling interval for interrupt redistribution for dynamic migration */ 177 int apic_redistribute_sample_interval = NANOSEC / 100; /* 10 millisec */ 178 179 /* 180 * number of times we sample before deciding to redistribute interrupts 181 * for dynamic migration 182 */ 183 int apic_sample_factor_redistribution = 101; 184 185 /* timeout for xlate_vector, mark_vector */ 186 int apic_revector_timeout = 16 * 10000; /* 160 millisec */ 187 188 int apic_redist_cpu_skip = 0; 189 int apic_num_imbalance = 0; 190 int apic_num_rebind = 0; 191 192 int apic_nproc = 0; 193 size_t apic_cpus_size = 0; 194 int apic_defconf = 0; 195 int apic_irq_translate = 0; 196 int apic_spec_rev = 0; 197 int apic_imcrp = 0; 198 199 int apic_use_acpi = 1; /* 1 = use ACPI, 0 = don't use ACPI */ 200 int apic_use_acpi_madt_only = 0; /* 1=ONLY use MADT from ACPI */ 201 202 /* 203 * For interrupt link devices, if apic_unconditional_srs is set, an irq resource 204 * will be assigned (via _SRS). If it is not set, use the current 205 * irq setting (via _CRS), but only if that irq is in the set of possible 206 * irqs (returned by _PRS) for the device. 207 */ 208 int apic_unconditional_srs = 1; 209 210 /* 211 * For interrupt link devices, if apic_prefer_crs is set when we are 212 * assigning an IRQ resource to a device, prefer the current IRQ setting 213 * over other possible irq settings under same conditions. 214 */ 215 216 int apic_prefer_crs = 1; 217 218 uchar_t apic_io_id[MAX_IO_APIC]; 219 volatile uint32_t *apicioadr[MAX_IO_APIC]; 220 static uchar_t apic_io_ver[MAX_IO_APIC]; 221 static uchar_t apic_io_vectbase[MAX_IO_APIC]; 222 static uchar_t apic_io_vectend[MAX_IO_APIC]; 223 uchar_t apic_reserved_irqlist[MAX_ISA_IRQ + 1]; 224 uint32_t apic_physaddr[MAX_IO_APIC]; 225 226 static boolean_t ioapic_mask_workaround[MAX_IO_APIC]; 227 228 /* 229 * First available slot to be used as IRQ index into the apic_irq_table 230 * for those interrupts (like MSI/X) that don't have a physical IRQ. 231 */ 232 int apic_first_avail_irq = APIC_FIRST_FREE_IRQ; 233 234 /* 235 * apic_ioapic_lock protects the ioapics (reg select), the status, temp_bound 236 * and bound elements of cpus_info and the temp_cpu element of irq_struct 237 */ 238 lock_t apic_ioapic_lock; 239 240 /* 241 * apic_defer_reprogram_lock ensures that only one processor is handling 242 * deferred interrupt programming at apic_intr_exit time. 243 */ 244 static lock_t apic_defer_reprogram_lock; 245 246 /* 247 * The current number of deferred reprogrammings outstanding 248 */ 249 uint_t apic_reprogram_outstanding = 0; 250 251 #ifdef DEBUG 252 /* 253 * Counters that keep track of deferred reprogramming stats 254 */ 255 uint_t apic_intr_deferrals = 0; 256 uint_t apic_intr_deliver_timeouts = 0; 257 uint_t apic_last_ditch_reprogram_failures = 0; 258 uint_t apic_deferred_setup_failures = 0; 259 uint_t apic_defer_repro_total_retries = 0; 260 uint_t apic_defer_repro_successes = 0; 261 uint_t apic_deferred_spurious_enters = 0; 262 #endif 263 264 static int apic_io_max = 0; /* no. of i/o apics enabled */ 265 266 static struct apic_io_intr *apic_io_intrp = 0; 267 static struct apic_bus *apic_busp; 268 269 uchar_t apic_vector_to_irq[APIC_MAX_VECTOR+1]; 270 uchar_t apic_resv_vector[MAXIPL+1]; 271 272 char apic_level_intr[APIC_MAX_VECTOR+1]; 273 274 static uint32_t eisa_level_intr_mask = 0; 275 /* At least MSB will be set if EISA bus */ 276 277 static int apic_pci_bus_total = 0; 278 static uchar_t apic_single_pci_busid = 0; 279 280 /* 281 * airq_mutex protects additions to the apic_irq_table - the first 282 * pointer and any airq_nexts off of that one. It also protects 283 * apic_max_device_irq & apic_min_device_irq. It also guarantees 284 * that share_id is unique as new ids are generated only when new 285 * irq_t structs are linked in. Once linked in the structs are never 286 * deleted. temp_cpu & mps_intr_index field indicate if it is programmed 287 * or allocated. Note that there is a slight gap between allocating in 288 * apic_introp_xlate and programming in addspl. 289 */ 290 kmutex_t airq_mutex; 291 apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1]; 292 int apic_max_device_irq = 0; 293 int apic_min_device_irq = APIC_MAX_VECTOR; 294 295 /* 296 * Following declarations are for revectoring; used when ISRs at different 297 * IPLs share an irq. 298 */ 299 static lock_t apic_revector_lock; 300 int apic_revector_pending = 0; 301 static uchar_t *apic_oldvec_to_newvec; 302 static uchar_t *apic_newvec_to_oldvec; 303 304 typedef struct prs_irq_list_ent { 305 int list_prio; 306 int32_t irq; 307 iflag_t intrflags; 308 acpi_prs_private_t prsprv; 309 struct prs_irq_list_ent *next; 310 } prs_irq_list_t; 311 312 313 /* 314 * ACPI variables 315 */ 316 /* 1 = acpi is enabled & working, 0 = acpi is not enabled or not there */ 317 int apic_enable_acpi = 0; 318 319 /* ACPI Multiple APIC Description Table ptr */ 320 static MULTIPLE_APIC_TABLE *acpi_mapic_dtp = NULL; 321 322 /* ACPI Interrupt Source Override Structure ptr */ 323 static MADT_INTERRUPT_OVERRIDE *acpi_isop = NULL; 324 static int acpi_iso_cnt = 0; 325 326 /* ACPI Non-maskable Interrupt Sources ptr */ 327 static MADT_NMI_SOURCE *acpi_nmi_sp = NULL; 328 static int acpi_nmi_scnt = 0; 329 static MADT_LOCAL_APIC_NMI *acpi_nmi_cp = NULL; 330 static int acpi_nmi_ccnt = 0; 331 332 /* 333 * The following added to identify a software poweroff method if available. 334 */ 335 336 static struct { 337 int poweroff_method; 338 char oem_id[APIC_MPS_OEM_ID_LEN + 1]; /* MAX + 1 for NULL */ 339 char prod_id[APIC_MPS_PROD_ID_LEN + 1]; /* MAX + 1 for NULL */ 340 } apic_mps_ids[] = { 341 { APIC_POWEROFF_VIA_RTC, "INTEL", "ALDER" }, /* 4300 */ 342 { APIC_POWEROFF_VIA_RTC, "NCR", "AMC" }, /* 4300 */ 343 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "A450NX" }, /* 4400? */ 344 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AD450NX" }, /* 4400 */ 345 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AC450NX" }, /* 4400R */ 346 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "S450NX" }, /* S50 */ 347 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "SC450NX" } /* S50? */ 348 }; 349 350 int apic_poweroff_method = APIC_POWEROFF_NONE; 351 352 /* 353 * Auto-configuration routines 354 */ 355 356 /* 357 * Look at MPSpec 1.4 (Intel Order # 242016-005) for details of what we do here 358 * May work with 1.1 - but not guaranteed. 359 * According to the MP Spec, the MP floating pointer structure 360 * will be searched in the order described below: 361 * 1. In the first kilobyte of Extended BIOS Data Area (EBDA) 362 * 2. Within the last kilobyte of system base memory 363 * 3. In the BIOS ROM address space between 0F0000h and 0FFFFh 364 * Once we find the right signature with proper checksum, we call 365 * either handle_defconf or parse_mpct to get all info necessary for 366 * subsequent operations. 367 */ 368 int 369 apic_probe_common(char *modname) 370 { 371 uint32_t mpct_addr, ebda_start = 0, base_mem_end; 372 caddr_t biosdatap; 373 caddr_t mpct; 374 caddr_t fptr; 375 int i, mpct_size, mapsize, retval = PSM_FAILURE; 376 ushort_t ebda_seg, base_mem_size; 377 struct apic_mpfps_hdr *fpsp; 378 struct apic_mp_cnf_hdr *hdrp; 379 int bypass_cpu_and_ioapics_in_mptables; 380 int acpi_user_options; 381 382 if (apic_forceload < 0) 383 return (retval); 384 385 /* 386 * Remember who we are 387 */ 388 psm_name = modname; 389 390 /* Allow override for MADT-only mode */ 391 acpi_user_options = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_root_node(), 0, 392 "acpi-user-options", 0); 393 apic_use_acpi_madt_only = ((acpi_user_options & ACPI_OUSER_MADT) != 0); 394 395 /* Allow apic_use_acpi to override MADT-only mode */ 396 if (!apic_use_acpi) 397 apic_use_acpi_madt_only = 0; 398 399 retval = acpi_probe(modname); 400 401 /* 402 * mapin the bios data area 40:0 403 * 40:13h - two-byte location reports the base memory size 404 * 40:0Eh - two-byte location for the exact starting address of 405 * the EBDA segment for EISA 406 */ 407 biosdatap = psm_map_phys(0x400, 0x20, PROT_READ); 408 if (!biosdatap) 409 return (retval); 410 fpsp = (struct apic_mpfps_hdr *)NULL; 411 mapsize = MPFPS_RAM_WIN_LEN; 412 /*LINTED: pointer cast may result in improper alignment */ 413 ebda_seg = *((ushort_t *)(biosdatap+0xe)); 414 /* check the 1k of EBDA */ 415 if (ebda_seg) { 416 ebda_start = ((uint32_t)ebda_seg) << 4; 417 fptr = psm_map_phys(ebda_start, MPFPS_RAM_WIN_LEN, PROT_READ); 418 if (fptr) { 419 if (!(fpsp = 420 apic_find_fps_sig(fptr, MPFPS_RAM_WIN_LEN))) 421 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN); 422 } 423 } 424 /* If not in EBDA, check the last k of system base memory */ 425 if (!fpsp) { 426 /*LINTED: pointer cast may result in improper alignment */ 427 base_mem_size = *((ushort_t *)(biosdatap + 0x13)); 428 429 if (base_mem_size > 512) 430 base_mem_end = 639 * 1024; 431 else 432 base_mem_end = 511 * 1024; 433 /* if ebda == last k of base mem, skip to check BIOS ROM */ 434 if (base_mem_end != ebda_start) { 435 436 fptr = psm_map_phys(base_mem_end, MPFPS_RAM_WIN_LEN, 437 PROT_READ); 438 439 if (fptr) { 440 if (!(fpsp = apic_find_fps_sig(fptr, 441 MPFPS_RAM_WIN_LEN))) 442 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN); 443 } 444 } 445 } 446 psm_unmap_phys(biosdatap, 0x20); 447 448 /* If still cannot find it, check the BIOS ROM space */ 449 if (!fpsp) { 450 mapsize = MPFPS_ROM_WIN_LEN; 451 fptr = psm_map_phys(MPFPS_ROM_WIN_START, 452 MPFPS_ROM_WIN_LEN, PROT_READ); 453 if (fptr) { 454 if (!(fpsp = 455 apic_find_fps_sig(fptr, MPFPS_ROM_WIN_LEN))) { 456 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 457 return (retval); 458 } 459 } 460 } 461 462 if (apic_checksum((caddr_t)fpsp, fpsp->mpfps_length * 16) != 0) { 463 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 464 return (retval); 465 } 466 467 apic_spec_rev = fpsp->mpfps_spec_rev; 468 if ((apic_spec_rev != 04) && (apic_spec_rev != 01)) { 469 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 470 return (retval); 471 } 472 473 /* check IMCR is present or not */ 474 apic_imcrp = fpsp->mpfps_featinfo2 & MPFPS_FEATINFO2_IMCRP; 475 476 /* check default configuration (dual CPUs) */ 477 if ((apic_defconf = fpsp->mpfps_featinfo1) != 0) { 478 psm_unmap_phys(fptr, mapsize); 479 return (apic_handle_defconf()); 480 } 481 482 /* MP Configuration Table */ 483 mpct_addr = (uint32_t)(fpsp->mpfps_mpct_paddr); 484 485 psm_unmap_phys(fptr, mapsize); /* unmap floating ptr struct */ 486 487 /* 488 * Map in enough memory for the MP Configuration Table Header. 489 * Use this table to read the total length of the BIOS data and 490 * map in all the info 491 */ 492 /*LINTED: pointer cast may result in improper alignment */ 493 hdrp = (struct apic_mp_cnf_hdr *)psm_map_phys(mpct_addr, 494 sizeof (struct apic_mp_cnf_hdr), PROT_READ); 495 if (!hdrp) 496 return (retval); 497 498 /* check mp configuration table signature PCMP */ 499 if (hdrp->mpcnf_sig != 0x504d4350) { 500 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr)); 501 return (retval); 502 } 503 mpct_size = (int)hdrp->mpcnf_tbl_length; 504 505 apic_set_pwroff_method_from_mpcnfhdr(hdrp); 506 507 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr)); 508 509 if ((retval == PSM_SUCCESS) && !apic_use_acpi_madt_only) { 510 /* This is an ACPI machine No need for further checks */ 511 return (retval); 512 } 513 514 /* 515 * Map in the entries for this machine, ie. Processor 516 * Entry Tables, Bus Entry Tables, etc. 517 * They are in fixed order following one another 518 */ 519 mpct = psm_map_phys(mpct_addr, mpct_size, PROT_READ); 520 if (!mpct) 521 return (retval); 522 523 if (apic_checksum(mpct, mpct_size) != 0) 524 goto apic_fail1; 525 526 527 /*LINTED: pointer cast may result in improper alignment */ 528 hdrp = (struct apic_mp_cnf_hdr *)mpct; 529 apicadr = (uint32_t *)mapin_apic((uint32_t)hdrp->mpcnf_local_apic, 530 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE); 531 if (!apicadr) 532 goto apic_fail1; 533 534 /* Parse all information in the tables */ 535 bypass_cpu_and_ioapics_in_mptables = (retval == PSM_SUCCESS); 536 if (apic_parse_mpct(mpct, bypass_cpu_and_ioapics_in_mptables) == 537 PSM_SUCCESS) 538 return (PSM_SUCCESS); 539 540 for (i = 0; i < apic_io_max; i++) 541 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN); 542 if (apic_cpus) 543 kmem_free(apic_cpus, apic_cpus_size); 544 if (apicadr) 545 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 546 apic_fail1: 547 psm_unmap_phys(mpct, mpct_size); 548 return (retval); 549 } 550 551 static void 552 apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp) 553 { 554 int i; 555 556 for (i = 0; i < (sizeof (apic_mps_ids) / sizeof (apic_mps_ids[0])); 557 i++) { 558 if ((strncmp(hdrp->mpcnf_oem_str, apic_mps_ids[i].oem_id, 559 strlen(apic_mps_ids[i].oem_id)) == 0) && 560 (strncmp(hdrp->mpcnf_prod_str, apic_mps_ids[i].prod_id, 561 strlen(apic_mps_ids[i].prod_id)) == 0)) { 562 563 apic_poweroff_method = apic_mps_ids[i].poweroff_method; 564 break; 565 } 566 } 567 568 if (apic_debug_mps_id != 0) { 569 cmn_err(CE_CONT, "%s: MPS OEM ID = '%c%c%c%c%c%c%c%c'" 570 "Product ID = '%c%c%c%c%c%c%c%c%c%c%c%c'\n", 571 psm_name, 572 hdrp->mpcnf_oem_str[0], 573 hdrp->mpcnf_oem_str[1], 574 hdrp->mpcnf_oem_str[2], 575 hdrp->mpcnf_oem_str[3], 576 hdrp->mpcnf_oem_str[4], 577 hdrp->mpcnf_oem_str[5], 578 hdrp->mpcnf_oem_str[6], 579 hdrp->mpcnf_oem_str[7], 580 hdrp->mpcnf_prod_str[0], 581 hdrp->mpcnf_prod_str[1], 582 hdrp->mpcnf_prod_str[2], 583 hdrp->mpcnf_prod_str[3], 584 hdrp->mpcnf_prod_str[4], 585 hdrp->mpcnf_prod_str[5], 586 hdrp->mpcnf_prod_str[6], 587 hdrp->mpcnf_prod_str[7], 588 hdrp->mpcnf_prod_str[8], 589 hdrp->mpcnf_prod_str[9], 590 hdrp->mpcnf_prod_str[10], 591 hdrp->mpcnf_prod_str[11]); 592 } 593 } 594 595 static int 596 acpi_probe(char *modname) 597 { 598 int i, intmax, index, rv; 599 uint32_t id, ver; 600 int acpi_verboseflags = 0; 601 int madt_seen, madt_size; 602 APIC_HEADER *ap; 603 MADT_PROCESSOR_APIC *mpa; 604 MADT_IO_APIC *mia; 605 MADT_IO_SAPIC *misa; 606 MADT_INTERRUPT_OVERRIDE *mio; 607 MADT_NMI_SOURCE *mns; 608 MADT_INTERRUPT_SOURCE *mis; 609 MADT_LOCAL_APIC_NMI *mlan; 610 MADT_ADDRESS_OVERRIDE *mao; 611 ACPI_OBJECT_LIST arglist; 612 ACPI_OBJECT arg; 613 int sci; 614 iflag_t sci_flags; 615 volatile uint32_t *ioapic; 616 int apic_ix; 617 char local_ids[NCPU]; 618 char proc_ids[NCPU]; 619 uchar_t hid; 620 621 if (!apic_use_acpi) 622 return (PSM_FAILURE); 623 624 if (AcpiGetFirmwareTable(APIC_SIG, 1, ACPI_LOGICAL_ADDRESSING, 625 (ACPI_TABLE_HEADER **) &acpi_mapic_dtp) != AE_OK) 626 return (PSM_FAILURE); 627 628 apicadr = mapin_apic((uint32_t)acpi_mapic_dtp->LocalApicAddress, 629 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE); 630 if (!apicadr) 631 return (PSM_FAILURE); 632 633 id = apicadr[APIC_LID_REG]; 634 local_ids[0] = (uchar_t)(id >> 24); 635 apic_nproc = index = 1; 636 CPUSET_ONLY(apic_cpumask, 0); 637 apic_io_max = 0; 638 639 ap = (APIC_HEADER *) (acpi_mapic_dtp + 1); 640 madt_size = acpi_mapic_dtp->Length; 641 madt_seen = sizeof (*acpi_mapic_dtp); 642 643 while (madt_seen < madt_size) { 644 switch (ap->Type) { 645 case APIC_PROCESSOR: 646 mpa = (MADT_PROCESSOR_APIC *) ap; 647 if (mpa->ProcessorEnabled) { 648 if (mpa->LocalApicId == local_ids[0]) { 649 proc_ids[0] = mpa->ProcessorId; 650 acpica_map_cpu(0, mpa); 651 } else if (apic_nproc < NCPU) { 652 local_ids[index] = mpa->LocalApicId; 653 proc_ids[index] = mpa->ProcessorId; 654 CPUSET_ADD(apic_cpumask, index); 655 acpica_map_cpu(index, mpa); 656 index++; 657 apic_nproc++; 658 } else 659 cmn_err(CE_WARN, "%s: exceeded " 660 "maximum no. of CPUs (= %d)", 661 psm_name, NCPU); 662 } 663 break; 664 665 case APIC_IO: 666 mia = (MADT_IO_APIC *) ap; 667 if (apic_io_max < MAX_IO_APIC) { 668 apic_ix = apic_io_max; 669 apic_io_id[apic_io_max] = mia->IoApicId; 670 apic_io_vectbase[apic_io_max] = 671 mia->Interrupt; 672 apic_physaddr[apic_io_max] = 673 (uint32_t)mia->Address; 674 ioapic = apicioadr[apic_io_max] = 675 mapin_ioapic((uint32_t)mia->Address, 676 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 677 if (!ioapic) 678 goto cleanup; 679 ioapic_mask_workaround[apic_io_max] = 680 apic_is_ioapic_AMD_813x(mia->Address); 681 apic_io_max++; 682 } 683 break; 684 685 case APIC_XRUPT_OVERRIDE: 686 mio = (MADT_INTERRUPT_OVERRIDE *) ap; 687 if (acpi_isop == NULL) 688 acpi_isop = mio; 689 acpi_iso_cnt++; 690 break; 691 692 case APIC_NMI: 693 /* UNIMPLEMENTED */ 694 mns = (MADT_NMI_SOURCE *) ap; 695 if (acpi_nmi_sp == NULL) 696 acpi_nmi_sp = mns; 697 acpi_nmi_scnt++; 698 699 cmn_err(CE_NOTE, "!apic: nmi source: %d %d %d\n", 700 mns->Interrupt, mns->Polarity, 701 mns->TriggerMode); 702 break; 703 704 case APIC_LOCAL_NMI: 705 /* UNIMPLEMENTED */ 706 mlan = (MADT_LOCAL_APIC_NMI *) ap; 707 if (acpi_nmi_cp == NULL) 708 acpi_nmi_cp = mlan; 709 acpi_nmi_ccnt++; 710 711 cmn_err(CE_NOTE, "!apic: local nmi: %d %d %d %d\n", 712 mlan->ProcessorId, mlan->Polarity, 713 mlan->TriggerMode, mlan->Lint); 714 break; 715 716 case APIC_ADDRESS_OVERRIDE: 717 /* UNIMPLEMENTED */ 718 mao = (MADT_ADDRESS_OVERRIDE *) ap; 719 cmn_err(CE_NOTE, "!apic: address override: %lx\n", 720 (long)mao->Address); 721 break; 722 723 case APIC_IO_SAPIC: 724 /* UNIMPLEMENTED */ 725 misa = (MADT_IO_SAPIC *) ap; 726 727 cmn_err(CE_NOTE, "!apic: io sapic: %d %d %lx\n", 728 misa->IoSapicId, misa->InterruptBase, 729 (long)misa->Address); 730 break; 731 732 case APIC_XRUPT_SOURCE: 733 /* UNIMPLEMENTED */ 734 mis = (MADT_INTERRUPT_SOURCE *) ap; 735 736 cmn_err(CE_NOTE, 737 "!apic: irq source: %d %d %d %d %d %d %d\n", 738 mis->ProcessorId, mis->ProcessorEid, 739 mis->Interrupt, mis->Polarity, 740 mis->TriggerMode, mis->InterruptType, 741 mis->IoSapicVector); 742 break; 743 default: 744 break; 745 } 746 747 /* advance to next entry */ 748 madt_seen += ap->Length; 749 ap = (APIC_HEADER *)(((char *)ap) + ap->Length); 750 } 751 752 apic_cpus_size = apic_nproc * sizeof (*apic_cpus); 753 if ((apic_cpus = kmem_zalloc(apic_cpus_size, KM_NOSLEEP)) == NULL) 754 goto cleanup; 755 756 /* 757 * ACPI doesn't provide the local apic ver, get it directly from the 758 * local apic 759 */ 760 ver = apicadr[APIC_VERS_REG]; 761 for (i = 0; i < apic_nproc; i++) { 762 apic_cpus[i].aci_local_id = local_ids[i]; 763 apic_cpus[i].aci_local_ver = (uchar_t)(ver & 0xFF); 764 } 765 for (i = 0; i < apic_io_max; i++) { 766 apic_ix = i; 767 768 /* 769 * need to check Sitka on the following acpi problem 770 * On the Sitka, the ioapic's apic_id field isn't reporting 771 * the actual io apic id. We have reported this problem 772 * to Intel. Until they fix the problem, we will get the 773 * actual id directly from the ioapic. 774 */ 775 id = ioapic_read(apic_ix, APIC_ID_CMD); 776 hid = (uchar_t)(id >> 24); 777 778 if (hid != apic_io_id[i]) { 779 if (apic_io_id[i] == 0) 780 apic_io_id[i] = hid; 781 else { /* set ioapic id to whatever reported by ACPI */ 782 id = ((uint32_t)apic_io_id[i]) << 24; 783 ioapic_write(apic_ix, APIC_ID_CMD, id); 784 } 785 } 786 ver = ioapic_read(apic_ix, APIC_VERS_CMD); 787 apic_io_ver[i] = (uchar_t)(ver & 0xff); 788 intmax = (ver >> 16) & 0xff; 789 apic_io_vectend[i] = apic_io_vectbase[i] + intmax; 790 if (apic_first_avail_irq <= apic_io_vectend[i]) 791 apic_first_avail_irq = apic_io_vectend[i] + 1; 792 } 793 794 795 /* 796 * Process SCI configuration here 797 * An error may be returned here if 798 * acpi-user-options specifies legacy mode 799 * (no SCI, no ACPI mode) 800 */ 801 if (acpica_get_sci(&sci, &sci_flags) != AE_OK) 802 sci = -1; 803 804 /* 805 * Now call acpi_init() to generate namespaces 806 * If this fails, we don't attempt to use ACPI 807 * even if we were able to get a MADT above 808 */ 809 if (acpica_init() != AE_OK) 810 goto cleanup; 811 812 /* 813 * Call acpica_build_processor_map() now that we have 814 * ACPI namesspace access 815 */ 816 acpica_build_processor_map(); 817 818 /* 819 * Squirrel away the SCI and flags for later on 820 * in apic_picinit() when we're ready 821 */ 822 apic_sci_vect = sci; 823 apic_sci_flags = sci_flags; 824 825 if (apic_verbose & APIC_VERBOSE_IRQ_FLAG) 826 acpi_verboseflags |= PSM_VERBOSE_IRQ_FLAG; 827 828 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) 829 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_FLAG; 830 831 if (apic_verbose & APIC_VERBOSE_POWEROFF_PAUSE_FLAG) 832 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_PAUSE_FLAG; 833 834 if (acpi_psm_init(modname, acpi_verboseflags) == ACPI_PSM_FAILURE) 835 goto cleanup; 836 837 /* Enable ACPI APIC interrupt routing */ 838 arglist.Count = 1; 839 arglist.Pointer = &arg; 840 arg.Type = ACPI_TYPE_INTEGER; 841 arg.Integer.Value = ACPI_APIC_MODE; /* 1 */ 842 rv = AcpiEvaluateObject(NULL, "\\_PIC", &arglist, NULL); 843 if (rv == AE_OK) { 844 build_reserved_irqlist((uchar_t *)apic_reserved_irqlist); 845 apic_enable_acpi = 1; 846 if (apic_use_acpi_madt_only) { 847 cmn_err(CE_CONT, 848 "?Using ACPI for CPU/IOAPIC information ONLY\n"); 849 } 850 return (PSM_SUCCESS); 851 } 852 /* if setting APIC mode failed above, we fall through to cleanup */ 853 854 cleanup: 855 if (apicadr != NULL) { 856 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 857 apicadr = NULL; 858 } 859 apic_nproc = 0; 860 for (i = 0; i < apic_io_max; i++) { 861 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN); 862 apicioadr[i] = NULL; 863 } 864 apic_io_max = 0; 865 acpi_isop = NULL; 866 acpi_iso_cnt = 0; 867 acpi_nmi_sp = NULL; 868 acpi_nmi_scnt = 0; 869 acpi_nmi_cp = NULL; 870 acpi_nmi_ccnt = 0; 871 return (PSM_FAILURE); 872 } 873 874 /* 875 * Handle default configuration. Fill in reqd global variables & tables 876 * Fill all details as MP table does not give any more info 877 */ 878 static int 879 apic_handle_defconf() 880 { 881 uint_t lid; 882 883 /*LINTED: pointer cast may result in improper alignment */ 884 apicioadr[0] = mapin_ioapic(APIC_IO_ADDR, 885 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 886 /*LINTED: pointer cast may result in improper alignment */ 887 apicadr = (uint32_t *)psm_map_phys(APIC_LOCAL_ADDR, 888 APIC_LOCAL_MEMLEN, PROT_READ); 889 apic_cpus_size = 2 * sizeof (*apic_cpus); 890 apic_cpus = (apic_cpus_info_t *) 891 kmem_zalloc(apic_cpus_size, KM_NOSLEEP); 892 if ((!apicadr) || (!apicioadr[0]) || (!apic_cpus)) 893 goto apic_handle_defconf_fail; 894 CPUSET_ONLY(apic_cpumask, 0); 895 CPUSET_ADD(apic_cpumask, 1); 896 apic_nproc = 2; 897 lid = apicadr[APIC_LID_REG]; 898 apic_cpus[0].aci_local_id = (uchar_t)(lid >> APIC_ID_BIT_OFFSET); 899 /* 900 * According to the PC+MP spec 1.1, the local ids 901 * for the default configuration has to be 0 or 1 902 */ 903 if (apic_cpus[0].aci_local_id == 1) 904 apic_cpus[1].aci_local_id = 0; 905 else if (apic_cpus[0].aci_local_id == 0) 906 apic_cpus[1].aci_local_id = 1; 907 else 908 goto apic_handle_defconf_fail; 909 910 apic_io_id[0] = 2; 911 apic_io_max = 1; 912 if (apic_defconf >= 5) { 913 apic_cpus[0].aci_local_ver = APIC_INTEGRATED_VERS; 914 apic_cpus[1].aci_local_ver = APIC_INTEGRATED_VERS; 915 apic_io_ver[0] = APIC_INTEGRATED_VERS; 916 } else { 917 apic_cpus[0].aci_local_ver = 0; /* 82489 DX */ 918 apic_cpus[1].aci_local_ver = 0; 919 apic_io_ver[0] = 0; 920 } 921 if (apic_defconf == 2 || apic_defconf == 3 || apic_defconf == 6) 922 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) | 923 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1); 924 return (PSM_SUCCESS); 925 926 apic_handle_defconf_fail: 927 if (apic_cpus) 928 kmem_free(apic_cpus, apic_cpus_size); 929 if (apicadr) 930 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 931 if (apicioadr[0]) 932 mapout_ioapic((caddr_t)apicioadr[0], APIC_IO_MEMLEN); 933 return (PSM_FAILURE); 934 } 935 936 /* Parse the entries in MP configuration table and collect info that we need */ 937 static int 938 apic_parse_mpct(caddr_t mpct, int bypass_cpus_and_ioapics) 939 { 940 struct apic_procent *procp; 941 struct apic_bus *busp; 942 struct apic_io_entry *ioapicp; 943 struct apic_io_intr *intrp; 944 int apic_ix; 945 uint_t lid; 946 uint32_t id; 947 uchar_t hid; 948 949 /*LINTED: pointer cast may result in improper alignment */ 950 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr)); 951 952 /* No need to count cpu entries if we won't use them */ 953 if (!bypass_cpus_and_ioapics) { 954 955 /* Find max # of CPUS and allocate structure accordingly */ 956 apic_nproc = 0; 957 CPUSET_ZERO(apic_cpumask); 958 while (procp->proc_entry == APIC_CPU_ENTRY) { 959 if (procp->proc_cpuflags & CPUFLAGS_EN) { 960 if (apic_nproc < NCPU) 961 CPUSET_ADD(apic_cpumask, apic_nproc); 962 apic_nproc++; 963 } 964 procp++; 965 } 966 if (apic_nproc > NCPU) 967 cmn_err(CE_WARN, "%s: exceeded " 968 "maximum no. of CPUs (= %d)", psm_name, NCPU); 969 apic_cpus_size = apic_nproc * sizeof (*apic_cpus); 970 if (!apic_nproc || !(apic_cpus = (apic_cpus_info_t *) 971 kmem_zalloc(apic_cpus_size, KM_NOSLEEP))) 972 return (PSM_FAILURE); 973 } 974 975 /*LINTED: pointer cast may result in improper alignment */ 976 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr)); 977 978 /* 979 * start with index 1 as 0 needs to be filled in with Boot CPU, but 980 * if we're bypassing this information, it has already been filled 981 * in by acpi_probe(), so don't overwrite it. 982 */ 983 if (!bypass_cpus_and_ioapics) 984 apic_nproc = 1; 985 986 while (procp->proc_entry == APIC_CPU_ENTRY) { 987 /* check whether the cpu exists or not */ 988 if (!bypass_cpus_and_ioapics && 989 procp->proc_cpuflags & CPUFLAGS_EN) { 990 if (procp->proc_cpuflags & CPUFLAGS_BP) { /* Boot CPU */ 991 lid = apicadr[APIC_LID_REG]; 992 apic_cpus[0].aci_local_id = procp->proc_apicid; 993 if (apic_cpus[0].aci_local_id != 994 (uchar_t)(lid >> APIC_ID_BIT_OFFSET)) { 995 return (PSM_FAILURE); 996 } 997 apic_cpus[0].aci_local_ver = 998 procp->proc_version; 999 } else { 1000 1001 apic_cpus[apic_nproc].aci_local_id = 1002 procp->proc_apicid; 1003 apic_cpus[apic_nproc].aci_local_ver = 1004 procp->proc_version; 1005 apic_nproc++; 1006 1007 } 1008 } 1009 procp++; 1010 } 1011 1012 /* 1013 * Save start of bus entries for later use. 1014 * Get EISA level cntrl if EISA bus is present. 1015 * Also get the CPI bus id for single CPI bus case 1016 */ 1017 apic_busp = busp = (struct apic_bus *)procp; 1018 while (busp->bus_entry == APIC_BUS_ENTRY) { 1019 lid = apic_find_bus_type((char *)&busp->bus_str1); 1020 if (lid == BUS_EISA) { 1021 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) | 1022 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1); 1023 } else if (lid == BUS_PCI) { 1024 /* 1025 * apic_single_pci_busid will be used only if 1026 * apic_pic_bus_total is equal to 1 1027 */ 1028 apic_pci_bus_total++; 1029 apic_single_pci_busid = busp->bus_id; 1030 } 1031 busp++; 1032 } 1033 1034 ioapicp = (struct apic_io_entry *)busp; 1035 1036 if (!bypass_cpus_and_ioapics) 1037 apic_io_max = 0; 1038 do { 1039 if (!bypass_cpus_and_ioapics && apic_io_max < MAX_IO_APIC) { 1040 if (ioapicp->io_flags & IOAPIC_FLAGS_EN) { 1041 apic_io_id[apic_io_max] = ioapicp->io_apicid; 1042 apic_io_ver[apic_io_max] = ioapicp->io_version; 1043 /*LINTED: pointer cast may result in improper alignment */ 1044 apicioadr[apic_io_max] = 1045 mapin_ioapic( 1046 (uint32_t)ioapicp->io_apic_addr, 1047 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 1048 1049 if (!apicioadr[apic_io_max]) 1050 return (PSM_FAILURE); 1051 1052 ioapic_mask_workaround[apic_io_max] = 1053 apic_is_ioapic_AMD_813x( 1054 ioapicp->io_apic_addr); 1055 1056 apic_ix = apic_io_max; 1057 id = ioapic_read(apic_ix, APIC_ID_CMD); 1058 hid = (uchar_t)(id >> 24); 1059 1060 if (hid != apic_io_id[apic_io_max]) { 1061 if (apic_io_id[apic_io_max] == 0) 1062 apic_io_id[apic_io_max] = hid; 1063 else { 1064 /* 1065 * set ioapic id to whatever 1066 * reported by MPS 1067 * 1068 * may not need to set index 1069 * again ??? 1070 * take it out and try 1071 */ 1072 1073 id = ((uint32_t) 1074 apic_io_id[apic_io_max]) << 1075 24; 1076 1077 ioapic_write(apic_ix, 1078 APIC_ID_CMD, id); 1079 } 1080 } 1081 apic_io_max++; 1082 } 1083 } 1084 ioapicp++; 1085 } while (ioapicp->io_entry == APIC_IO_ENTRY); 1086 1087 apic_io_intrp = (struct apic_io_intr *)ioapicp; 1088 1089 intrp = apic_io_intrp; 1090 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 1091 if ((intrp->intr_irq > APIC_MAX_ISA_IRQ) || 1092 (apic_find_bus(intrp->intr_busid) == BUS_PCI)) { 1093 apic_irq_translate = 1; 1094 break; 1095 } 1096 intrp++; 1097 } 1098 1099 return (PSM_SUCCESS); 1100 } 1101 1102 boolean_t 1103 apic_cpu_in_range(int cpu) 1104 { 1105 return ((cpu & ~IRQ_USER_BOUND) < apic_nproc); 1106 } 1107 1108 uint16_t 1109 apic_get_apic_version() 1110 { 1111 int i; 1112 uchar_t min_io_apic_ver = 0; 1113 static uint16_t version; /* Cache as value is constant */ 1114 static boolean_t found = B_FALSE; /* Accomodate zero version */ 1115 1116 if (found == B_FALSE) { 1117 found = B_TRUE; 1118 1119 /* 1120 * Don't assume all IO APICs in the system are the same. 1121 * 1122 * Set to the minimum version. 1123 */ 1124 for (i = 0; i < apic_io_max; i++) { 1125 if ((apic_io_ver[i] != 0) && 1126 ((min_io_apic_ver == 0) || 1127 (min_io_apic_ver >= apic_io_ver[i]))) 1128 min_io_apic_ver = apic_io_ver[i]; 1129 } 1130 1131 /* Assume all local APICs are of the same version. */ 1132 version = (min_io_apic_ver << 8) | apic_cpus[0].aci_local_ver; 1133 } 1134 return (version); 1135 } 1136 1137 static struct apic_mpfps_hdr * 1138 apic_find_fps_sig(caddr_t cptr, int len) 1139 { 1140 int i; 1141 1142 /* Look for the pattern "_MP_" */ 1143 for (i = 0; i < len; i += 16) { 1144 if ((*(cptr+i) == '_') && 1145 (*(cptr+i+1) == 'M') && 1146 (*(cptr+i+2) == 'P') && 1147 (*(cptr+i+3) == '_')) 1148 /*LINTED: pointer cast may result in improper alignment */ 1149 return ((struct apic_mpfps_hdr *)(cptr + i)); 1150 } 1151 return (NULL); 1152 } 1153 1154 static int 1155 apic_checksum(caddr_t bptr, int len) 1156 { 1157 int i; 1158 uchar_t cksum; 1159 1160 cksum = 0; 1161 for (i = 0; i < len; i++) 1162 cksum += *bptr++; 1163 return ((int)cksum); 1164 } 1165 1166 1167 /* 1168 * Initialise vector->ipl and ipl->pri arrays. level_intr and irqtable 1169 * are also set to NULL. vector->irq is set to a value which cannot map 1170 * to a real irq to show that it is free. 1171 */ 1172 void 1173 apic_init_common() 1174 { 1175 int i, j, indx; 1176 int *iptr; 1177 1178 /* 1179 * Initialize apic_ipls from apic_vectortoipl. This array is 1180 * used in apic_intr_enter to determine the IPL to use for the 1181 * corresponding vector. On some systems, due to hardware errata 1182 * and interrupt sharing, the IPL may not correspond to the IPL listed 1183 * in apic_vectortoipl (see apic_addspl and apic_delspl). 1184 */ 1185 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) { 1186 indx = i * APIC_VECTOR_PER_IPL; 1187 1188 for (j = 0; j < APIC_VECTOR_PER_IPL; j++, indx++) 1189 apic_ipls[indx] = apic_vectortoipl[i]; 1190 } 1191 1192 /* cpu 0 is always up (for now) */ 1193 apic_cpus[0].aci_status = APIC_CPU_ONLINE | APIC_CPU_INTR_ENABLE; 1194 1195 iptr = (int *)&apic_irq_table[0]; 1196 for (i = 0; i <= APIC_MAX_VECTOR; i++) { 1197 apic_level_intr[i] = 0; 1198 *iptr++ = NULL; 1199 apic_vector_to_irq[i] = APIC_RESV_IRQ; 1200 1201 /* These *must* be initted to B_TRUE! */ 1202 apic_reprogram_info[i].done = B_TRUE; 1203 apic_reprogram_info[i].irqp = NULL; 1204 apic_reprogram_info[i].tries = 0; 1205 apic_reprogram_info[i].bindcpu = 0; 1206 } 1207 1208 /* 1209 * Allocate a dummy irq table entry for the reserved entry. 1210 * This takes care of the race between removing an irq and 1211 * clock detecting a CPU in that irq during interrupt load 1212 * sampling. 1213 */ 1214 apic_irq_table[APIC_RESV_IRQ] = 1215 kmem_zalloc(sizeof (apic_irq_t), KM_NOSLEEP); 1216 1217 mutex_init(&airq_mutex, NULL, MUTEX_DEFAULT, NULL); 1218 } 1219 1220 void 1221 ioapic_init_intr(int mask_apic) 1222 { 1223 int apic_ix; 1224 struct intrspec ispec; 1225 apic_irq_t *irqptr; 1226 int i, j; 1227 ulong_t iflag; 1228 1229 LOCK_INIT_CLEAR(&apic_revector_lock); 1230 LOCK_INIT_CLEAR(&apic_defer_reprogram_lock); 1231 1232 /* mask interrupt vectors */ 1233 for (j = 0; j < apic_io_max && mask_apic; j++) { 1234 int intin_max; 1235 1236 apic_ix = j; 1237 /* Bits 23-16 define the maximum redirection entries */ 1238 intin_max = (ioapic_read(apic_ix, APIC_VERS_CMD) >> 16) & 0xff; 1239 for (i = 0; i < intin_max; i++) 1240 ioapic_write(apic_ix, APIC_RDT_CMD + 2 * i, AV_MASK); 1241 } 1242 1243 /* 1244 * Hack alert: deal with ACPI SCI interrupt chicken/egg here 1245 */ 1246 if (apic_sci_vect > 0) { 1247 /* 1248 * acpica has already done add_avintr(); we just 1249 * to finish the job by mimicing translate_irq() 1250 * 1251 * Fake up an intrspec and setup the tables 1252 */ 1253 ispec.intrspec_vec = apic_sci_vect; 1254 ispec.intrspec_pri = SCI_IPL; 1255 1256 if (apic_setup_irq_table(NULL, apic_sci_vect, NULL, 1257 &ispec, &apic_sci_flags, DDI_INTR_TYPE_FIXED) < 0) { 1258 cmn_err(CE_WARN, "!apic: SCI setup failed"); 1259 return; 1260 } 1261 irqptr = apic_irq_table[apic_sci_vect]; 1262 1263 iflag = intr_clear(); 1264 lock_set(&apic_ioapic_lock); 1265 1266 /* Program I/O APIC */ 1267 (void) apic_setup_io_intr(irqptr, apic_sci_vect, B_FALSE); 1268 1269 lock_clear(&apic_ioapic_lock); 1270 intr_restore(iflag); 1271 1272 irqptr->airq_share++; 1273 } 1274 } 1275 1276 /* 1277 * Add mask bits to disable interrupt vector from happening 1278 * at or above IPL. In addition, it should remove mask bits 1279 * to enable interrupt vectors below the given IPL. 1280 * 1281 * Both add and delspl are complicated by the fact that different interrupts 1282 * may share IRQs. This can happen in two ways. 1283 * 1. The same H/W line is shared by more than 1 device 1284 * 1a. with interrupts at different IPLs 1285 * 1b. with interrupts at same IPL 1286 * 2. We ran out of vectors at a given IPL and started sharing vectors. 1287 * 1b and 2 should be handled gracefully, except for the fact some ISRs 1288 * will get called often when no interrupt is pending for the device. 1289 * For 1a, we just hope that the machine blows up with the person who 1290 * set it up that way!. In the meantime, we handle it at the higher IPL. 1291 */ 1292 /*ARGSUSED*/ 1293 int 1294 apic_addspl_common(int irqno, int ipl, int min_ipl, int max_ipl) 1295 { 1296 uchar_t vector; 1297 ulong_t iflag; 1298 apic_irq_t *irqptr, *irqheadptr; 1299 int irqindex; 1300 1301 ASSERT(max_ipl <= UCHAR_MAX); 1302 irqindex = IRQINDEX(irqno); 1303 1304 if ((irqindex == -1) || (!apic_irq_table[irqindex])) 1305 return (PSM_FAILURE); 1306 1307 mutex_enter(&airq_mutex); 1308 irqptr = irqheadptr = apic_irq_table[irqindex]; 1309 1310 DDI_INTR_IMPLDBG((CE_CONT, "apic_addspl: dip=0x%p type=%d irqno=0x%x " 1311 "vector=0x%x\n", (void *)irqptr->airq_dip, 1312 irqptr->airq_mps_intr_index, irqno, irqptr->airq_vector)); 1313 1314 while (irqptr) { 1315 if (VIRTIRQ(irqindex, irqptr->airq_share_id) == irqno) 1316 break; 1317 irqptr = irqptr->airq_next; 1318 } 1319 irqptr->airq_share++; 1320 1321 mutex_exit(&airq_mutex); 1322 1323 /* return if it is not hardware interrupt */ 1324 if (irqptr->airq_mps_intr_index == RESERVE_INDEX) 1325 return (PSM_SUCCESS); 1326 1327 /* Or if there are more interupts at a higher IPL */ 1328 if (ipl != max_ipl) 1329 return (PSM_SUCCESS); 1330 1331 /* 1332 * if apic_picinit() has not been called yet, just return. 1333 * At the end of apic_picinit(), we will call setup_io_intr(). 1334 */ 1335 1336 if (!apic_flag) 1337 return (PSM_SUCCESS); 1338 1339 /* 1340 * Upgrade vector if max_ipl is not earlier ipl. If we cannot allocate, 1341 * return failure. Not very elegant, but then we hope the 1342 * machine will blow up with ... 1343 */ 1344 if (irqptr->airq_ipl != max_ipl && 1345 !ioapic_mask_workaround[irqptr->airq_ioapicindex]) { 1346 1347 vector = apic_allocate_vector(max_ipl, irqindex, 1); 1348 if (vector == 0) { 1349 irqptr->airq_share--; 1350 return (PSM_FAILURE); 1351 } 1352 irqptr = irqheadptr; 1353 apic_mark_vector(irqptr->airq_vector, vector); 1354 while (irqptr) { 1355 irqptr->airq_vector = vector; 1356 irqptr->airq_ipl = (uchar_t)max_ipl; 1357 /* 1358 * reprogram irq being added and every one else 1359 * who is not in the UNINIT state 1360 */ 1361 if ((VIRTIRQ(irqindex, irqptr->airq_share_id) == 1362 irqno) || (irqptr->airq_temp_cpu != IRQ_UNINIT)) { 1363 apic_record_rdt_entry(irqptr, irqindex); 1364 1365 iflag = intr_clear(); 1366 lock_set(&apic_ioapic_lock); 1367 1368 (void) apic_setup_io_intr(irqptr, irqindex, 1369 B_FALSE); 1370 1371 lock_clear(&apic_ioapic_lock); 1372 intr_restore(iflag); 1373 } 1374 irqptr = irqptr->airq_next; 1375 } 1376 return (PSM_SUCCESS); 1377 1378 } else if (irqptr->airq_ipl != max_ipl && 1379 ioapic_mask_workaround[irqptr->airq_ioapicindex]) { 1380 /* 1381 * We cannot upgrade the vector, but we can change 1382 * the IPL that this vector induces. 1383 * 1384 * Note that we subtract APIC_BASE_VECT from the vector 1385 * here because this array is used in apic_intr_enter 1386 * (no need to add APIC_BASE_VECT in that hot code 1387 * path since we can do it in the rarely-executed path 1388 * here). 1389 */ 1390 apic_ipls[irqptr->airq_vector - APIC_BASE_VECT] = 1391 (uchar_t)max_ipl; 1392 1393 irqptr = irqheadptr; 1394 while (irqptr) { 1395 irqptr->airq_ipl = (uchar_t)max_ipl; 1396 irqptr = irqptr->airq_next; 1397 } 1398 1399 return (PSM_SUCCESS); 1400 } 1401 1402 ASSERT(irqptr); 1403 1404 iflag = intr_clear(); 1405 lock_set(&apic_ioapic_lock); 1406 1407 (void) apic_setup_io_intr(irqptr, irqindex, B_FALSE); 1408 1409 lock_clear(&apic_ioapic_lock); 1410 intr_restore(iflag); 1411 1412 return (PSM_SUCCESS); 1413 } 1414 1415 /* 1416 * Recompute mask bits for the given interrupt vector. 1417 * If there is no interrupt servicing routine for this 1418 * vector, this function should disable interrupt vector 1419 * from happening at all IPLs. If there are still 1420 * handlers using the given vector, this function should 1421 * disable the given vector from happening below the lowest 1422 * IPL of the remaining hadlers. 1423 */ 1424 /*ARGSUSED*/ 1425 int 1426 apic_delspl_common(int irqno, int ipl, int min_ipl, int max_ipl) 1427 { 1428 uchar_t vector, bind_cpu; 1429 int intin, irqindex; 1430 int apic_ix; 1431 apic_irq_t *irqptr, *irqheadptr, *irqp; 1432 ulong_t iflag; 1433 1434 mutex_enter(&airq_mutex); 1435 irqindex = IRQINDEX(irqno); 1436 irqptr = irqheadptr = apic_irq_table[irqindex]; 1437 1438 DDI_INTR_IMPLDBG((CE_CONT, "apic_delspl: dip=0x%p type=%d irqno=0x%x " 1439 "vector=0x%x\n", (void *)irqptr->airq_dip, 1440 irqptr->airq_mps_intr_index, irqno, irqptr->airq_vector)); 1441 1442 while (irqptr) { 1443 if (VIRTIRQ(irqindex, irqptr->airq_share_id) == irqno) 1444 break; 1445 irqptr = irqptr->airq_next; 1446 } 1447 ASSERT(irqptr); 1448 1449 irqptr->airq_share--; 1450 1451 mutex_exit(&airq_mutex); 1452 1453 if (ipl < max_ipl) 1454 return (PSM_SUCCESS); 1455 1456 /* return if it is not hardware interrupt */ 1457 if (irqptr->airq_mps_intr_index == RESERVE_INDEX) 1458 return (PSM_SUCCESS); 1459 1460 if (!apic_flag) { 1461 /* 1462 * Clear irq_struct. If two devices shared an intpt 1463 * line & 1 unloaded before picinit, we are hosed. But, then 1464 * we hope the machine will ... 1465 */ 1466 irqptr->airq_mps_intr_index = FREE_INDEX; 1467 irqptr->airq_temp_cpu = IRQ_UNINIT; 1468 apic_free_vector(irqptr->airq_vector); 1469 return (PSM_SUCCESS); 1470 } 1471 /* 1472 * Downgrade vector to new max_ipl if needed.If we cannot allocate, 1473 * use old IPL. Not very elegant, but then we hope ... 1474 */ 1475 if ((irqptr->airq_ipl != max_ipl) && (max_ipl != PSM_INVALID_IPL) && 1476 !ioapic_mask_workaround[irqptr->airq_ioapicindex]) { 1477 apic_irq_t *irqp; 1478 if (vector = apic_allocate_vector(max_ipl, irqno, 1)) { 1479 apic_mark_vector(irqheadptr->airq_vector, vector); 1480 irqp = irqheadptr; 1481 while (irqp) { 1482 irqp->airq_vector = vector; 1483 irqp->airq_ipl = (uchar_t)max_ipl; 1484 if (irqp->airq_temp_cpu != IRQ_UNINIT) { 1485 apic_record_rdt_entry(irqp, irqindex); 1486 1487 iflag = intr_clear(); 1488 lock_set(&apic_ioapic_lock); 1489 1490 (void) apic_setup_io_intr(irqp, 1491 irqindex, B_FALSE); 1492 1493 lock_clear(&apic_ioapic_lock); 1494 intr_restore(iflag); 1495 } 1496 irqp = irqp->airq_next; 1497 } 1498 } 1499 1500 } else if (irqptr->airq_ipl != max_ipl && 1501 max_ipl != PSM_INVALID_IPL && 1502 ioapic_mask_workaround[irqptr->airq_ioapicindex]) { 1503 1504 /* 1505 * We cannot downgrade the IPL of the vector below the vector's 1506 * hardware priority. If we did, it would be possible for a 1507 * higher-priority hardware vector to interrupt a CPU running at an IPL 1508 * lower than the hardware priority of the interrupting vector (but 1509 * higher than the soft IPL of this IRQ). When this happens, we would 1510 * then try to drop the IPL BELOW what it was (effectively dropping 1511 * below base_spl) which would be potentially catastrophic. 1512 * 1513 * (e.g. Suppose the hardware vector associated with this IRQ is 0x40 1514 * (hardware IPL of 4). Further assume that the old IPL of this IRQ 1515 * was 4, but the new IPL is 1. If we forced vector 0x40 to result in 1516 * an IPL of 1, it would be possible for the processor to be executing 1517 * at IPL 3 and for an interrupt to come in on vector 0x40, interrupting 1518 * the currently-executing ISR. When apic_intr_enter consults 1519 * apic_irqs[], it will return 1, bringing the IPL of the CPU down to 1 1520 * so even though the processor was running at IPL 4, an IPL 1 1521 * interrupt will have interrupted it, which must not happen)). 1522 * 1523 * Effectively, this means that the hardware priority corresponding to 1524 * the IRQ's IPL (in apic_ipls[]) cannot be lower than the vector's 1525 * hardware priority. 1526 * 1527 * (In the above example, then, after removal of the IPL 4 device's 1528 * interrupt handler, the new IPL will continue to be 4 because the 1529 * hardware priority that IPL 1 implies is lower than the hardware 1530 * priority of the vector used.) 1531 */ 1532 /* apic_ipls is indexed by vector, starting at APIC_BASE_VECT */ 1533 const int apic_ipls_index = irqptr->airq_vector - 1534 APIC_BASE_VECT; 1535 const int vect_inherent_hwpri = irqptr->airq_vector >> 1536 APIC_IPL_SHIFT; 1537 1538 /* 1539 * If there are still devices using this IRQ, determine the 1540 * new ipl to use. 1541 */ 1542 if (irqptr->airq_share) { 1543 int vect_desired_hwpri, hwpri; 1544 1545 ASSERT(max_ipl < MAXIPL); 1546 vect_desired_hwpri = apic_ipltopri[max_ipl] >> 1547 APIC_IPL_SHIFT; 1548 1549 /* 1550 * If the desired IPL's hardware priority is lower 1551 * than that of the vector, use the hardware priority 1552 * of the vector to determine the new IPL. 1553 */ 1554 hwpri = (vect_desired_hwpri < vect_inherent_hwpri) ? 1555 vect_inherent_hwpri : vect_desired_hwpri; 1556 1557 /* 1558 * Now, to get the right index for apic_vectortoipl, 1559 * we need to subtract APIC_BASE_VECT from the 1560 * hardware-vector-equivalent (in hwpri). Since hwpri 1561 * is already shifted, we shift APIC_BASE_VECT before 1562 * doing the subtraction. 1563 */ 1564 hwpri -= (APIC_BASE_VECT >> APIC_IPL_SHIFT); 1565 1566 ASSERT(hwpri >= 0); 1567 ASSERT(hwpri < MAXIPL); 1568 max_ipl = apic_vectortoipl[hwpri]; 1569 apic_ipls[apic_ipls_index] = max_ipl; 1570 1571 irqp = irqheadptr; 1572 while (irqp) { 1573 irqp->airq_ipl = (uchar_t)max_ipl; 1574 irqp = irqp->airq_next; 1575 } 1576 } else { 1577 /* 1578 * No more devices on this IRQ, so reset this vector's 1579 * element in apic_ipls to the original IPL for this 1580 * vector 1581 */ 1582 apic_ipls[apic_ipls_index] = 1583 apic_vectortoipl[vect_inherent_hwpri]; 1584 } 1585 } 1586 1587 if (irqptr->airq_share) 1588 return (PSM_SUCCESS); 1589 1590 iflag = intr_clear(); 1591 lock_set(&apic_ioapic_lock); 1592 1593 if (irqptr->airq_mps_intr_index == MSI_INDEX) { 1594 /* 1595 * Disable the MSI vector 1596 * Make sure we only disable on the last 1597 * of the multi-MSI support 1598 */ 1599 if (i_ddi_intr_get_current_nintrs(irqptr->airq_dip) == 1) { 1600 apic_pci_msi_unconfigure(irqptr->airq_dip, 1601 DDI_INTR_TYPE_MSI, irqptr->airq_ioapicindex); 1602 1603 apic_pci_msi_disable_mode(irqptr->airq_dip, 1604 DDI_INTR_TYPE_MSI); 1605 } 1606 } else if (irqptr->airq_mps_intr_index == MSIX_INDEX) { 1607 /* 1608 * Disable the MSI-X vector 1609 * needs to clear its mask and addr/data for each MSI-X 1610 */ 1611 apic_pci_msi_unconfigure(irqptr->airq_dip, DDI_INTR_TYPE_MSIX, 1612 irqptr->airq_origirq); 1613 /* 1614 * Make sure we only disable on the last MSI-X 1615 */ 1616 if (i_ddi_intr_get_current_nintrs(irqptr->airq_dip) == 1) { 1617 apic_pci_msi_disable_mode(irqptr->airq_dip, 1618 DDI_INTR_TYPE_MSIX); 1619 } 1620 } else { 1621 /* 1622 * The assumption here is that this is safe, even for 1623 * systems with IOAPICs that suffer from the hardware 1624 * erratum because all devices have been quiesced before 1625 * they unregister their interrupt handlers. If that 1626 * assumption turns out to be false, this mask operation 1627 * can induce the same erratum result we're trying to 1628 * avoid. 1629 */ 1630 apic_ix = irqptr->airq_ioapicindex; 1631 intin = irqptr->airq_intin_no; 1632 ioapic_write(apic_ix, APIC_RDT_CMD + 2 * intin, AV_MASK); 1633 } 1634 1635 if (max_ipl == PSM_INVALID_IPL) { 1636 ASSERT(irqheadptr == irqptr); 1637 bind_cpu = irqptr->airq_temp_cpu; 1638 if (((uchar_t)bind_cpu != IRQ_UNBOUND) && 1639 ((uchar_t)bind_cpu != IRQ_UNINIT)) { 1640 ASSERT((bind_cpu & ~IRQ_USER_BOUND) < apic_nproc); 1641 if (bind_cpu & IRQ_USER_BOUND) { 1642 /* If hardbound, temp_cpu == cpu */ 1643 bind_cpu &= ~IRQ_USER_BOUND; 1644 apic_cpus[bind_cpu].aci_bound--; 1645 } else 1646 apic_cpus[bind_cpu].aci_temp_bound--; 1647 } 1648 irqptr->airq_temp_cpu = IRQ_UNINIT; 1649 irqptr->airq_mps_intr_index = FREE_INDEX; 1650 lock_clear(&apic_ioapic_lock); 1651 intr_restore(iflag); 1652 apic_free_vector(irqptr->airq_vector); 1653 return (PSM_SUCCESS); 1654 } 1655 lock_clear(&apic_ioapic_lock); 1656 intr_restore(iflag); 1657 1658 mutex_enter(&airq_mutex); 1659 if ((irqptr == apic_irq_table[irqindex])) { 1660 apic_irq_t *oldirqptr; 1661 /* Move valid irq entry to the head */ 1662 irqheadptr = oldirqptr = irqptr; 1663 irqptr = irqptr->airq_next; 1664 ASSERT(irqptr); 1665 while (irqptr) { 1666 if (irqptr->airq_mps_intr_index != FREE_INDEX) 1667 break; 1668 oldirqptr = irqptr; 1669 irqptr = irqptr->airq_next; 1670 } 1671 /* remove all invalid ones from the beginning */ 1672 apic_irq_table[irqindex] = irqptr; 1673 /* 1674 * and link them back after the head. The invalid ones 1675 * begin with irqheadptr and end at oldirqptr 1676 */ 1677 oldirqptr->airq_next = irqptr->airq_next; 1678 irqptr->airq_next = irqheadptr; 1679 } 1680 mutex_exit(&airq_mutex); 1681 1682 irqptr->airq_temp_cpu = IRQ_UNINIT; 1683 irqptr->airq_mps_intr_index = FREE_INDEX; 1684 1685 return (PSM_SUCCESS); 1686 } 1687 1688 /* 1689 * apic_introp_xlate() replaces apic_translate_irq() and is 1690 * called only from apic_intr_ops(). With the new ADII framework, 1691 * the priority can no longer be retrieved through i_ddi_get_intrspec(). 1692 * It has to be passed in from the caller. 1693 */ 1694 int 1695 apic_introp_xlate(dev_info_t *dip, struct intrspec *ispec, int type) 1696 { 1697 char dev_type[16]; 1698 int dev_len, pci_irq, newirq, bustype, devid, busid, i; 1699 int irqno = ispec->intrspec_vec; 1700 ddi_acc_handle_t cfg_handle; 1701 uchar_t ipin; 1702 struct apic_io_intr *intrp; 1703 iflag_t intr_flag; 1704 APIC_HEADER *hp; 1705 MADT_INTERRUPT_OVERRIDE *isop; 1706 apic_irq_t *airqp; 1707 int parent_is_pci_or_pciex = 0; 1708 int child_is_pciex = 0; 1709 1710 DDI_INTR_IMPLDBG((CE_CONT, "apic_introp_xlate: dip=0x%p name=%s " 1711 "type=%d irqno=0x%x\n", (void *)dip, ddi_get_name(dip), type, 1712 irqno)); 1713 1714 dev_len = sizeof (dev_type); 1715 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, ddi_get_parent(dip), 1716 DDI_PROP_DONTPASS, "device_type", (caddr_t)dev_type, 1717 &dev_len) == DDI_PROP_SUCCESS) { 1718 if ((strcmp(dev_type, "pci") == 0) || 1719 (strcmp(dev_type, "pciex") == 0)) 1720 parent_is_pci_or_pciex = 1; 1721 } 1722 1723 if (parent_is_pci_or_pciex && ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1724 DDI_PROP_DONTPASS, "pcie-capid-pointer", PCI_CAP_NEXT_PTR_NULL) != 1725 PCI_CAP_NEXT_PTR_NULL) { 1726 child_is_pciex = 1; 1727 } 1728 1729 if (DDI_INTR_IS_MSI_OR_MSIX(type)) { 1730 if ((airqp = apic_find_irq(dip, ispec, type)) != NULL) { 1731 airqp->airq_iflag.bustype = 1732 child_is_pciex ? BUS_PCIE : BUS_PCI; 1733 return (apic_vector_to_irq[airqp->airq_vector]); 1734 } 1735 return (apic_setup_irq_table(dip, irqno, NULL, ispec, 1736 NULL, type)); 1737 } 1738 1739 bustype = 0; 1740 1741 /* check if we have already translated this irq */ 1742 mutex_enter(&airq_mutex); 1743 newirq = apic_min_device_irq; 1744 for (; newirq <= apic_max_device_irq; newirq++) { 1745 airqp = apic_irq_table[newirq]; 1746 while (airqp) { 1747 if ((airqp->airq_dip == dip) && 1748 (airqp->airq_origirq == irqno) && 1749 (airqp->airq_mps_intr_index != FREE_INDEX)) { 1750 1751 mutex_exit(&airq_mutex); 1752 return (VIRTIRQ(newirq, airqp->airq_share_id)); 1753 } 1754 airqp = airqp->airq_next; 1755 } 1756 } 1757 mutex_exit(&airq_mutex); 1758 1759 if (apic_defconf) 1760 goto defconf; 1761 1762 if ((dip == NULL) || (!apic_irq_translate && !apic_enable_acpi)) 1763 goto nonpci; 1764 1765 if (parent_is_pci_or_pciex) { 1766 /* pci device */ 1767 if (acpica_get_bdf(dip, &busid, &devid, NULL) != 0) 1768 goto nonpci; 1769 if (busid == 0 && apic_pci_bus_total == 1) 1770 busid = (int)apic_single_pci_busid; 1771 1772 if (pci_config_setup(dip, &cfg_handle) != DDI_SUCCESS) 1773 goto nonpci; 1774 ipin = pci_config_get8(cfg_handle, PCI_CONF_IPIN) - PCI_INTA; 1775 pci_config_teardown(&cfg_handle); 1776 if (apic_enable_acpi && !apic_use_acpi_madt_only) { 1777 if (apic_acpi_translate_pci_irq(dip, busid, devid, 1778 ipin, &pci_irq, &intr_flag) != ACPI_PSM_SUCCESS) 1779 goto nonpci; 1780 1781 intr_flag.bustype = child_is_pciex ? BUS_PCIE : BUS_PCI; 1782 if ((newirq = apic_setup_irq_table(dip, pci_irq, NULL, 1783 ispec, &intr_flag, type)) == -1) 1784 goto nonpci; 1785 return (newirq); 1786 } else { 1787 pci_irq = ((devid & 0x1f) << 2) | (ipin & 0x3); 1788 if ((intrp = apic_find_io_intr_w_busid(pci_irq, busid)) 1789 == NULL) { 1790 if ((pci_irq = apic_handle_pci_pci_bridge(dip, 1791 devid, ipin, &intrp)) == -1) 1792 goto nonpci; 1793 } 1794 if ((newirq = apic_setup_irq_table(dip, pci_irq, intrp, 1795 ispec, NULL, type)) == -1) 1796 goto nonpci; 1797 return (newirq); 1798 } 1799 } else if (strcmp(dev_type, "isa") == 0) 1800 bustype = BUS_ISA; 1801 else if (strcmp(dev_type, "eisa") == 0) 1802 bustype = BUS_EISA; 1803 1804 nonpci: 1805 if (apic_enable_acpi && !apic_use_acpi_madt_only) { 1806 /* search iso entries first */ 1807 if (acpi_iso_cnt != 0) { 1808 hp = (APIC_HEADER *)acpi_isop; 1809 i = 0; 1810 while (i < acpi_iso_cnt) { 1811 if (hp->Type == APIC_XRUPT_OVERRIDE) { 1812 isop = (MADT_INTERRUPT_OVERRIDE *)hp; 1813 if (isop->Bus == 0 && 1814 isop->Source == irqno) { 1815 newirq = isop->Interrupt; 1816 intr_flag.intr_po = 1817 isop->Polarity; 1818 intr_flag.intr_el = 1819 isop->TriggerMode; 1820 intr_flag.bustype = BUS_ISA; 1821 1822 return (apic_setup_irq_table( 1823 dip, newirq, NULL, ispec, 1824 &intr_flag, type)); 1825 1826 } 1827 i++; 1828 } 1829 hp = (APIC_HEADER *)(((char *)hp) + 1830 hp->Length); 1831 } 1832 } 1833 intr_flag.intr_po = INTR_PO_ACTIVE_HIGH; 1834 intr_flag.intr_el = INTR_EL_EDGE; 1835 intr_flag.bustype = BUS_ISA; 1836 return (apic_setup_irq_table(dip, irqno, NULL, ispec, 1837 &intr_flag, type)); 1838 } else { 1839 if (bustype == 0) 1840 bustype = eisa_level_intr_mask ? BUS_EISA : BUS_ISA; 1841 for (i = 0; i < 2; i++) { 1842 if (((busid = apic_find_bus_id(bustype)) != -1) && 1843 ((intrp = apic_find_io_intr_w_busid(irqno, busid)) 1844 != NULL)) { 1845 if ((newirq = apic_setup_irq_table(dip, irqno, 1846 intrp, ispec, NULL, type)) != -1) { 1847 return (newirq); 1848 } 1849 goto defconf; 1850 } 1851 bustype = (bustype == BUS_EISA) ? BUS_ISA : BUS_EISA; 1852 } 1853 } 1854 1855 /* MPS default configuration */ 1856 defconf: 1857 newirq = apic_setup_irq_table(dip, irqno, NULL, ispec, NULL, type); 1858 if (newirq == -1) 1859 return (newirq); 1860 ASSERT(IRQINDEX(newirq) == irqno); 1861 ASSERT(apic_irq_table[irqno]); 1862 return (newirq); 1863 } 1864 1865 1866 1867 1868 1869 1870 /* 1871 * On machines with PCI-PCI bridges, a device behind a PCI-PCI bridge 1872 * needs special handling. We may need to chase up the device tree, 1873 * using the PCI-PCI Bridge specification's "rotating IPIN assumptions", 1874 * to find the IPIN at the root bus that relates to the IPIN on the 1875 * subsidiary bus (for ACPI or MP). We may, however, have an entry 1876 * in the MP table or the ACPI namespace for this device itself. 1877 * We handle both cases in the search below. 1878 */ 1879 /* this is the non-acpi version */ 1880 static int 1881 apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, int child_ipin, 1882 struct apic_io_intr **intrp) 1883 { 1884 dev_info_t *dipp, *dip; 1885 int pci_irq; 1886 ddi_acc_handle_t cfg_handle; 1887 int bridge_devno, bridge_bus; 1888 int ipin; 1889 1890 dip = idip; 1891 1892 /*CONSTCOND*/ 1893 while (1) { 1894 if (((dipp = ddi_get_parent(dip)) == (dev_info_t *)NULL) || 1895 (pci_config_setup(dipp, &cfg_handle) != DDI_SUCCESS)) 1896 return (-1); 1897 if ((pci_config_get8(cfg_handle, PCI_CONF_BASCLASS) == 1898 PCI_CLASS_BRIDGE) && (pci_config_get8(cfg_handle, 1899 PCI_CONF_SUBCLASS) == PCI_BRIDGE_PCI)) { 1900 pci_config_teardown(&cfg_handle); 1901 if (acpica_get_bdf(dipp, &bridge_bus, &bridge_devno, 1902 NULL) != 0) 1903 return (-1); 1904 /* 1905 * This is the rotating scheme documented in the 1906 * PCI-to-PCI spec. If the PCI-to-PCI bridge is 1907 * behind another PCI-to-PCI bridge, then it needs 1908 * to keep ascending until an interrupt entry is 1909 * found or the root is reached. 1910 */ 1911 ipin = (child_devno + child_ipin) % PCI_INTD; 1912 if (bridge_bus == 0 && apic_pci_bus_total == 1) 1913 bridge_bus = (int)apic_single_pci_busid; 1914 pci_irq = ((bridge_devno & 0x1f) << 2) | 1915 (ipin & 0x3); 1916 if ((*intrp = apic_find_io_intr_w_busid(pci_irq, 1917 bridge_bus)) != NULL) { 1918 return (pci_irq); 1919 } 1920 dip = dipp; 1921 child_devno = bridge_devno; 1922 child_ipin = ipin; 1923 } else { 1924 pci_config_teardown(&cfg_handle); 1925 return (-1); 1926 } 1927 } 1928 /*LINTED: function will not fall off the bottom */ 1929 } 1930 1931 1932 1933 1934 static uchar_t 1935 acpi_find_ioapic(int irq) 1936 { 1937 int i; 1938 1939 for (i = 0; i < apic_io_max; i++) { 1940 if (irq >= apic_io_vectbase[i] && irq <= apic_io_vectend[i]) 1941 return (i); 1942 } 1943 return (0xFF); /* shouldn't happen */ 1944 } 1945 1946 /* 1947 * See if two irqs are compatible for sharing a vector. 1948 * Currently we only support sharing of PCI devices. 1949 */ 1950 static int 1951 acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2) 1952 { 1953 uint_t level1, po1; 1954 uint_t level2, po2; 1955 1956 /* Assume active high by default */ 1957 po1 = 0; 1958 po2 = 0; 1959 1960 if (iflag1.bustype != iflag2.bustype || iflag1.bustype != BUS_PCI) 1961 return (0); 1962 1963 if (iflag1.intr_el == INTR_EL_CONFORM) 1964 level1 = AV_LEVEL; 1965 else 1966 level1 = (iflag1.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0; 1967 1968 if (level1 && ((iflag1.intr_po == INTR_PO_ACTIVE_LOW) || 1969 (iflag1.intr_po == INTR_PO_CONFORM))) 1970 po1 = AV_ACTIVE_LOW; 1971 1972 if (iflag2.intr_el == INTR_EL_CONFORM) 1973 level2 = AV_LEVEL; 1974 else 1975 level2 = (iflag2.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0; 1976 1977 if (level2 && ((iflag2.intr_po == INTR_PO_ACTIVE_LOW) || 1978 (iflag2.intr_po == INTR_PO_CONFORM))) 1979 po2 = AV_ACTIVE_LOW; 1980 1981 if ((level1 == level2) && (po1 == po2)) 1982 return (1); 1983 1984 return (0); 1985 } 1986 1987 /* 1988 * Attempt to share vector with someone else 1989 */ 1990 static int 1991 apic_share_vector(int irqno, iflag_t *intr_flagp, short intr_index, int ipl, 1992 uchar_t ioapicindex, uchar_t ipin, apic_irq_t **irqptrp) 1993 { 1994 #ifdef DEBUG 1995 apic_irq_t *tmpirqp = NULL; 1996 #endif /* DEBUG */ 1997 apic_irq_t *irqptr, dummyirq; 1998 int newirq, chosen_irq = -1, share = 127; 1999 int lowest, highest, i; 2000 uchar_t share_id; 2001 2002 DDI_INTR_IMPLDBG((CE_CONT, "apic_share_vector: irqno=0x%x " 2003 "intr_index=0x%x ipl=0x%x\n", irqno, intr_index, ipl)); 2004 2005 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK; 2006 lowest = apic_ipltopri[ipl-1] + APIC_VECTOR_PER_IPL; 2007 2008 if (highest < lowest) /* Both ipl and ipl-1 map to same pri */ 2009 lowest -= APIC_VECTOR_PER_IPL; 2010 dummyirq.airq_mps_intr_index = intr_index; 2011 dummyirq.airq_ioapicindex = ioapicindex; 2012 dummyirq.airq_intin_no = ipin; 2013 if (intr_flagp) 2014 dummyirq.airq_iflag = *intr_flagp; 2015 apic_record_rdt_entry(&dummyirq, irqno); 2016 for (i = lowest; i <= highest; i++) { 2017 newirq = apic_vector_to_irq[i]; 2018 if (newirq == APIC_RESV_IRQ) 2019 continue; 2020 irqptr = apic_irq_table[newirq]; 2021 2022 if ((dummyirq.airq_rdt_entry & 0xFF00) != 2023 (irqptr->airq_rdt_entry & 0xFF00)) 2024 /* not compatible */ 2025 continue; 2026 2027 if (irqptr->airq_share < share) { 2028 share = irqptr->airq_share; 2029 chosen_irq = newirq; 2030 } 2031 } 2032 if (chosen_irq != -1) { 2033 /* 2034 * Assign a share id which is free or which is larger 2035 * than the largest one. 2036 */ 2037 share_id = 1; 2038 mutex_enter(&airq_mutex); 2039 irqptr = apic_irq_table[chosen_irq]; 2040 while (irqptr) { 2041 if (irqptr->airq_mps_intr_index == FREE_INDEX) { 2042 share_id = irqptr->airq_share_id; 2043 break; 2044 } 2045 if (share_id <= irqptr->airq_share_id) 2046 share_id = irqptr->airq_share_id + 1; 2047 #ifdef DEBUG 2048 tmpirqp = irqptr; 2049 #endif /* DEBUG */ 2050 irqptr = irqptr->airq_next; 2051 } 2052 if (!irqptr) { 2053 irqptr = kmem_zalloc(sizeof (apic_irq_t), KM_SLEEP); 2054 irqptr->airq_temp_cpu = IRQ_UNINIT; 2055 irqptr->airq_next = 2056 apic_irq_table[chosen_irq]->airq_next; 2057 apic_irq_table[chosen_irq]->airq_next = irqptr; 2058 #ifdef DEBUG 2059 tmpirqp = apic_irq_table[chosen_irq]; 2060 #endif /* DEBUG */ 2061 } 2062 irqptr->airq_mps_intr_index = intr_index; 2063 irqptr->airq_ioapicindex = ioapicindex; 2064 irqptr->airq_intin_no = ipin; 2065 if (intr_flagp) 2066 irqptr->airq_iflag = *intr_flagp; 2067 irqptr->airq_vector = apic_irq_table[chosen_irq]->airq_vector; 2068 irqptr->airq_share_id = share_id; 2069 apic_record_rdt_entry(irqptr, irqno); 2070 *irqptrp = irqptr; 2071 #ifdef DEBUG 2072 /* shuffle the pointers to test apic_delspl path */ 2073 if (tmpirqp) { 2074 tmpirqp->airq_next = irqptr->airq_next; 2075 irqptr->airq_next = apic_irq_table[chosen_irq]; 2076 apic_irq_table[chosen_irq] = irqptr; 2077 } 2078 #endif /* DEBUG */ 2079 mutex_exit(&airq_mutex); 2080 return (VIRTIRQ(chosen_irq, share_id)); 2081 } 2082 return (-1); 2083 } 2084 2085 /* 2086 * 2087 */ 2088 static int 2089 apic_setup_irq_table(dev_info_t *dip, int irqno, struct apic_io_intr *intrp, 2090 struct intrspec *ispec, iflag_t *intr_flagp, int type) 2091 { 2092 int origirq = ispec->intrspec_vec; 2093 uchar_t ipl = ispec->intrspec_pri; 2094 int newirq, intr_index; 2095 uchar_t ipin, ioapic, ioapicindex, vector; 2096 apic_irq_t *irqptr; 2097 major_t major; 2098 dev_info_t *sdip; 2099 2100 DDI_INTR_IMPLDBG((CE_CONT, "apic_setup_irq_table: dip=0x%p type=%d " 2101 "irqno=0x%x origirq=0x%x\n", (void *)dip, type, irqno, origirq)); 2102 2103 ASSERT(ispec != NULL); 2104 2105 major = (dip != NULL) ? ddi_name_to_major(ddi_get_name(dip)) : 0; 2106 2107 if (DDI_INTR_IS_MSI_OR_MSIX(type)) { 2108 /* MSI/X doesn't need to setup ioapic stuffs */ 2109 ioapicindex = 0xff; 2110 ioapic = 0xff; 2111 ipin = (uchar_t)0xff; 2112 intr_index = (type == DDI_INTR_TYPE_MSI) ? MSI_INDEX : 2113 MSIX_INDEX; 2114 mutex_enter(&airq_mutex); 2115 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) == -1) { 2116 mutex_exit(&airq_mutex); 2117 /* need an irq for MSI/X to index into autovect[] */ 2118 cmn_err(CE_WARN, "No interrupt irq: %s instance %d", 2119 ddi_get_name(dip), ddi_get_instance(dip)); 2120 return (-1); 2121 } 2122 mutex_exit(&airq_mutex); 2123 2124 } else if (intrp != NULL) { 2125 intr_index = (int)(intrp - apic_io_intrp); 2126 ioapic = intrp->intr_destid; 2127 ipin = intrp->intr_destintin; 2128 /* Find ioapicindex. If destid was ALL, we will exit with 0. */ 2129 for (ioapicindex = apic_io_max - 1; ioapicindex; ioapicindex--) 2130 if (apic_io_id[ioapicindex] == ioapic) 2131 break; 2132 ASSERT((ioapic == apic_io_id[ioapicindex]) || 2133 (ioapic == INTR_ALL_APIC)); 2134 2135 /* check whether this intin# has been used by another irqno */ 2136 if ((newirq = apic_find_intin(ioapicindex, ipin)) != -1) { 2137 return (newirq); 2138 } 2139 2140 } else if (intr_flagp != NULL) { 2141 /* ACPI case */ 2142 intr_index = ACPI_INDEX; 2143 ioapicindex = acpi_find_ioapic(irqno); 2144 ASSERT(ioapicindex != 0xFF); 2145 ioapic = apic_io_id[ioapicindex]; 2146 ipin = irqno - apic_io_vectbase[ioapicindex]; 2147 if (apic_irq_table[irqno] && 2148 apic_irq_table[irqno]->airq_mps_intr_index == ACPI_INDEX) { 2149 ASSERT(apic_irq_table[irqno]->airq_intin_no == ipin && 2150 apic_irq_table[irqno]->airq_ioapicindex == 2151 ioapicindex); 2152 return (irqno); 2153 } 2154 2155 } else { 2156 /* default configuration */ 2157 ioapicindex = 0; 2158 ioapic = apic_io_id[ioapicindex]; 2159 ipin = (uchar_t)irqno; 2160 intr_index = DEFAULT_INDEX; 2161 } 2162 2163 if (ispec == NULL) { 2164 APIC_VERBOSE_IOAPIC((CE_WARN, "No intrspec for irqno = %x\n", 2165 irqno)); 2166 } else if ((vector = apic_allocate_vector(ipl, irqno, 0)) == 0) { 2167 if ((newirq = apic_share_vector(irqno, intr_flagp, intr_index, 2168 ipl, ioapicindex, ipin, &irqptr)) != -1) { 2169 irqptr->airq_ipl = ipl; 2170 irqptr->airq_origirq = (uchar_t)origirq; 2171 irqptr->airq_dip = dip; 2172 irqptr->airq_major = major; 2173 sdip = apic_irq_table[IRQINDEX(newirq)]->airq_dip; 2174 /* This is OK to do really */ 2175 if (sdip == NULL) { 2176 cmn_err(CE_WARN, "Sharing vectors: %s" 2177 " instance %d and SCI", 2178 ddi_get_name(dip), ddi_get_instance(dip)); 2179 } else { 2180 cmn_err(CE_WARN, "Sharing vectors: %s" 2181 " instance %d and %s instance %d", 2182 ddi_get_name(sdip), ddi_get_instance(sdip), 2183 ddi_get_name(dip), ddi_get_instance(dip)); 2184 } 2185 return (newirq); 2186 } 2187 /* try high priority allocation now that share has failed */ 2188 if ((vector = apic_allocate_vector(ipl, irqno, 1)) == 0) { 2189 cmn_err(CE_WARN, "No interrupt vector: %s instance %d", 2190 ddi_get_name(dip), ddi_get_instance(dip)); 2191 return (-1); 2192 } 2193 } 2194 2195 mutex_enter(&airq_mutex); 2196 if (apic_irq_table[irqno] == NULL) { 2197 irqptr = kmem_zalloc(sizeof (apic_irq_t), KM_SLEEP); 2198 irqptr->airq_temp_cpu = IRQ_UNINIT; 2199 apic_irq_table[irqno] = irqptr; 2200 } else { 2201 irqptr = apic_irq_table[irqno]; 2202 if (irqptr->airq_mps_intr_index != FREE_INDEX) { 2203 /* 2204 * The slot is used by another irqno, so allocate 2205 * a free irqno for this interrupt 2206 */ 2207 newirq = apic_allocate_irq(apic_first_avail_irq); 2208 if (newirq == -1) { 2209 mutex_exit(&airq_mutex); 2210 return (-1); 2211 } 2212 irqno = newirq; 2213 irqptr = apic_irq_table[irqno]; 2214 if (irqptr == NULL) { 2215 irqptr = kmem_zalloc(sizeof (apic_irq_t), 2216 KM_SLEEP); 2217 irqptr->airq_temp_cpu = IRQ_UNINIT; 2218 apic_irq_table[irqno] = irqptr; 2219 } 2220 vector = apic_modify_vector(vector, newirq); 2221 } 2222 } 2223 apic_max_device_irq = max(irqno, apic_max_device_irq); 2224 apic_min_device_irq = min(irqno, apic_min_device_irq); 2225 mutex_exit(&airq_mutex); 2226 irqptr->airq_ioapicindex = ioapicindex; 2227 irqptr->airq_intin_no = ipin; 2228 irqptr->airq_ipl = ipl; 2229 irqptr->airq_vector = vector; 2230 irqptr->airq_origirq = (uchar_t)origirq; 2231 irqptr->airq_share_id = 0; 2232 irqptr->airq_mps_intr_index = (short)intr_index; 2233 irqptr->airq_dip = dip; 2234 irqptr->airq_major = major; 2235 irqptr->airq_cpu = apic_bind_intr(dip, irqno, ioapic, ipin); 2236 if (intr_flagp) 2237 irqptr->airq_iflag = *intr_flagp; 2238 2239 if (!DDI_INTR_IS_MSI_OR_MSIX(type)) { 2240 /* setup I/O APIC entry for non-MSI/X interrupts */ 2241 apic_record_rdt_entry(irqptr, irqno); 2242 } 2243 return (irqno); 2244 } 2245 2246 /* 2247 * return the cpu to which this intr should be bound. 2248 * Check properties or any other mechanism to see if user wants it 2249 * bound to a specific CPU. If so, return the cpu id with high bit set. 2250 * If not, use the policy to choose a cpu and return the id. 2251 */ 2252 uchar_t 2253 apic_bind_intr(dev_info_t *dip, int irq, uchar_t ioapicid, uchar_t intin) 2254 { 2255 int instance, instno, prop_len, bind_cpu, count; 2256 uint_t i, rc; 2257 uchar_t cpu; 2258 major_t major; 2259 char *name, *drv_name, *prop_val, *cptr; 2260 char prop_name[32]; 2261 2262 2263 if (apic_intr_policy == INTR_LOWEST_PRIORITY) 2264 return (IRQ_UNBOUND); 2265 2266 drv_name = NULL; 2267 rc = DDI_PROP_NOT_FOUND; 2268 major = (major_t)-1; 2269 if (dip != NULL) { 2270 name = ddi_get_name(dip); 2271 major = ddi_name_to_major(name); 2272 drv_name = ddi_major_to_name(major); 2273 instance = ddi_get_instance(dip); 2274 if (apic_intr_policy == INTR_ROUND_ROBIN_WITH_AFFINITY) { 2275 i = apic_min_device_irq; 2276 for (; i <= apic_max_device_irq; i++) { 2277 2278 if ((i == irq) || (apic_irq_table[i] == NULL) || 2279 (apic_irq_table[i]->airq_mps_intr_index 2280 == FREE_INDEX)) 2281 continue; 2282 2283 if ((apic_irq_table[i]->airq_major == major) && 2284 (!(apic_irq_table[i]->airq_cpu & 2285 IRQ_USER_BOUND))) { 2286 2287 cpu = apic_irq_table[i]->airq_cpu; 2288 2289 cmn_err(CE_CONT, 2290 "!%s: %s (%s) instance #%d " 2291 "vector 0x%x ioapic 0x%x " 2292 "intin 0x%x is bound to cpu %d\n", 2293 psm_name, 2294 name, drv_name, instance, irq, 2295 ioapicid, intin, cpu); 2296 return (cpu); 2297 } 2298 } 2299 } 2300 /* 2301 * search for "drvname"_intpt_bind_cpus property first, the 2302 * syntax of the property should be "a[,b,c,...]" where 2303 * instance 0 binds to cpu a, instance 1 binds to cpu b, 2304 * instance 3 binds to cpu c... 2305 * ddi_getlongprop() will search /option first, then / 2306 * if "drvname"_intpt_bind_cpus doesn't exist, then find 2307 * intpt_bind_cpus property. The syntax is the same, and 2308 * it applies to all the devices if its "drvname" specific 2309 * property doesn't exist 2310 */ 2311 (void) strcpy(prop_name, drv_name); 2312 (void) strcat(prop_name, "_intpt_bind_cpus"); 2313 rc = ddi_getlongprop(DDI_DEV_T_ANY, dip, 0, prop_name, 2314 (caddr_t)&prop_val, &prop_len); 2315 if (rc != DDI_PROP_SUCCESS) { 2316 rc = ddi_getlongprop(DDI_DEV_T_ANY, dip, 0, 2317 "intpt_bind_cpus", (caddr_t)&prop_val, &prop_len); 2318 } 2319 } 2320 if (rc == DDI_PROP_SUCCESS) { 2321 for (i = count = 0; i < (prop_len - 1); i++) 2322 if (prop_val[i] == ',') 2323 count++; 2324 if (prop_val[i-1] != ',') 2325 count++; 2326 /* 2327 * if somehow the binding instances defined in the 2328 * property are not enough for this instno., then 2329 * reuse the pattern for the next instance until 2330 * it reaches the requested instno 2331 */ 2332 instno = instance % count; 2333 i = 0; 2334 cptr = prop_val; 2335 while (i < instno) 2336 if (*cptr++ == ',') 2337 i++; 2338 bind_cpu = stoi(&cptr); 2339 kmem_free(prop_val, prop_len); 2340 /* if specific cpu is bogus, then default to cpu 0 */ 2341 if (bind_cpu >= apic_nproc) { 2342 cmn_err(CE_WARN, "%s: %s=%s: CPU %d not present", 2343 psm_name, prop_name, prop_val, bind_cpu); 2344 bind_cpu = 0; 2345 } else { 2346 /* indicate that we are bound at user request */ 2347 bind_cpu |= IRQ_USER_BOUND; 2348 } 2349 /* 2350 * no need to check apic_cpus[].aci_status, if specific cpu is 2351 * not up, then post_cpu_start will handle it. 2352 */ 2353 } else { 2354 bind_cpu = apic_next_bind_cpu++; 2355 if (bind_cpu >= apic_nproc) { 2356 apic_next_bind_cpu = 1; 2357 bind_cpu = 0; 2358 } 2359 } 2360 if (drv_name != NULL) 2361 cmn_err(CE_CONT, "!%s: %s (%s) instance %d " 2362 "vector 0x%x ioapic 0x%x intin 0x%x is bound to cpu %d\n", 2363 psm_name, name, drv_name, instance, 2364 irq, ioapicid, intin, bind_cpu & ~IRQ_USER_BOUND); 2365 else 2366 cmn_err(CE_CONT, "!%s: " 2367 "vector 0x%x ioapic 0x%x intin 0x%x is bound to cpu %d\n", 2368 psm_name, irq, ioapicid, intin, bind_cpu & ~IRQ_USER_BOUND); 2369 2370 return ((uchar_t)bind_cpu); 2371 } 2372 2373 static struct apic_io_intr * 2374 apic_find_io_intr_w_busid(int irqno, int busid) 2375 { 2376 struct apic_io_intr *intrp; 2377 2378 /* 2379 * It can have more than 1 entry with same source bus IRQ, 2380 * but unique with the source bus id 2381 */ 2382 intrp = apic_io_intrp; 2383 if (intrp != NULL) { 2384 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 2385 if (intrp->intr_irq == irqno && 2386 intrp->intr_busid == busid && 2387 intrp->intr_type == IO_INTR_INT) 2388 return (intrp); 2389 intrp++; 2390 } 2391 } 2392 APIC_VERBOSE_IOAPIC((CE_NOTE, "Did not find io intr for irqno:" 2393 "busid %x:%x\n", irqno, busid)); 2394 return ((struct apic_io_intr *)NULL); 2395 } 2396 2397 2398 struct mps_bus_info { 2399 char *bus_name; 2400 int bus_id; 2401 } bus_info_array[] = { 2402 "ISA ", BUS_ISA, 2403 "PCI ", BUS_PCI, 2404 "EISA ", BUS_EISA, 2405 "XPRESS", BUS_XPRESS, 2406 "PCMCIA", BUS_PCMCIA, 2407 "VL ", BUS_VL, 2408 "CBUS ", BUS_CBUS, 2409 "CBUSII", BUS_CBUSII, 2410 "FUTURE", BUS_FUTURE, 2411 "INTERN", BUS_INTERN, 2412 "MBI ", BUS_MBI, 2413 "MBII ", BUS_MBII, 2414 "MPI ", BUS_MPI, 2415 "MPSA ", BUS_MPSA, 2416 "NUBUS ", BUS_NUBUS, 2417 "TC ", BUS_TC, 2418 "VME ", BUS_VME, 2419 "PCI-E ", BUS_PCIE 2420 }; 2421 2422 static int 2423 apic_find_bus_type(char *bus) 2424 { 2425 int i = 0; 2426 2427 for (; i < sizeof (bus_info_array)/sizeof (struct mps_bus_info); i++) 2428 if (strncmp(bus, bus_info_array[i].bus_name, 2429 strlen(bus_info_array[i].bus_name)) == 0) 2430 return (bus_info_array[i].bus_id); 2431 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus type for bus %s", bus)); 2432 return (0); 2433 } 2434 2435 static int 2436 apic_find_bus(int busid) 2437 { 2438 struct apic_bus *busp; 2439 2440 busp = apic_busp; 2441 while (busp->bus_entry == APIC_BUS_ENTRY) { 2442 if (busp->bus_id == busid) 2443 return (apic_find_bus_type((char *)&busp->bus_str1)); 2444 busp++; 2445 } 2446 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus for bus id %x", busid)); 2447 return (0); 2448 } 2449 2450 static int 2451 apic_find_bus_id(int bustype) 2452 { 2453 struct apic_bus *busp; 2454 2455 busp = apic_busp; 2456 while (busp->bus_entry == APIC_BUS_ENTRY) { 2457 if (apic_find_bus_type((char *)&busp->bus_str1) == bustype) 2458 return (busp->bus_id); 2459 busp++; 2460 } 2461 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus id for bustype %x", 2462 bustype)); 2463 return (-1); 2464 } 2465 2466 /* 2467 * Check if a particular irq need to be reserved for any io_intr 2468 */ 2469 static struct apic_io_intr * 2470 apic_find_io_intr(int irqno) 2471 { 2472 struct apic_io_intr *intrp; 2473 2474 intrp = apic_io_intrp; 2475 if (intrp != NULL) { 2476 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 2477 if (intrp->intr_irq == irqno && 2478 intrp->intr_type == IO_INTR_INT) 2479 return (intrp); 2480 intrp++; 2481 } 2482 } 2483 return ((struct apic_io_intr *)NULL); 2484 } 2485 2486 /* 2487 * Check if the given ioapicindex intin combination has already been assigned 2488 * an irq. If so return irqno. Else -1 2489 */ 2490 static int 2491 apic_find_intin(uchar_t ioapic, uchar_t intin) 2492 { 2493 apic_irq_t *irqptr; 2494 int i; 2495 2496 /* find ioapic and intin in the apic_irq_table[] and return the index */ 2497 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) { 2498 irqptr = apic_irq_table[i]; 2499 while (irqptr) { 2500 if ((irqptr->airq_mps_intr_index >= 0) && 2501 (irqptr->airq_intin_no == intin) && 2502 (irqptr->airq_ioapicindex == ioapic)) { 2503 APIC_VERBOSE_IOAPIC((CE_NOTE, "!Found irq " 2504 "entry for ioapic:intin %x:%x " 2505 "shared interrupts ?", ioapic, intin)); 2506 return (i); 2507 } 2508 irqptr = irqptr->airq_next; 2509 } 2510 } 2511 return (-1); 2512 } 2513 2514 int 2515 apic_allocate_irq(int irq) 2516 { 2517 int freeirq, i; 2518 2519 if ((freeirq = apic_find_free_irq(irq, (APIC_RESV_IRQ - 1))) == -1) 2520 if ((freeirq = apic_find_free_irq(APIC_FIRST_FREE_IRQ, 2521 (irq - 1))) == -1) { 2522 /* 2523 * if BIOS really defines every single irq in the mps 2524 * table, then don't worry about conflicting with 2525 * them, just use any free slot in apic_irq_table 2526 */ 2527 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) { 2528 if ((apic_irq_table[i] == NULL) || 2529 apic_irq_table[i]->airq_mps_intr_index == 2530 FREE_INDEX) { 2531 freeirq = i; 2532 break; 2533 } 2534 } 2535 if (freeirq == -1) { 2536 /* This shouldn't happen, but just in case */ 2537 cmn_err(CE_WARN, "%s: NO available IRQ", psm_name); 2538 return (-1); 2539 } 2540 } 2541 if (apic_irq_table[freeirq] == NULL) { 2542 apic_irq_table[freeirq] = 2543 kmem_zalloc(sizeof (apic_irq_t), KM_NOSLEEP); 2544 if (apic_irq_table[freeirq] == NULL) { 2545 cmn_err(CE_WARN, "%s: NO memory to allocate IRQ", 2546 psm_name); 2547 return (-1); 2548 } 2549 apic_irq_table[freeirq]->airq_mps_intr_index = FREE_INDEX; 2550 } 2551 return (freeirq); 2552 } 2553 2554 static int 2555 apic_find_free_irq(int start, int end) 2556 { 2557 int i; 2558 2559 for (i = start; i <= end; i++) 2560 /* Check if any I/O entry needs this IRQ */ 2561 if (apic_find_io_intr(i) == NULL) { 2562 /* Then see if it is free */ 2563 if ((apic_irq_table[i] == NULL) || 2564 (apic_irq_table[i]->airq_mps_intr_index == 2565 FREE_INDEX)) { 2566 return (i); 2567 } 2568 } 2569 return (-1); 2570 } 2571 2572 2573 /* 2574 * Mark vector as being in the process of being deleted. Interrupts 2575 * may still come in on some CPU. The moment an interrupt comes with 2576 * the new vector, we know we can free the old one. Called only from 2577 * addspl and delspl with interrupts disabled. Because an interrupt 2578 * can be shared, but no interrupt from either device may come in, 2579 * we also use a timeout mechanism, which we arbitrarily set to 2580 * apic_revector_timeout microseconds. 2581 */ 2582 static void 2583 apic_mark_vector(uchar_t oldvector, uchar_t newvector) 2584 { 2585 ulong_t iflag; 2586 2587 iflag = intr_clear(); 2588 lock_set(&apic_revector_lock); 2589 if (!apic_oldvec_to_newvec) { 2590 apic_oldvec_to_newvec = 2591 kmem_zalloc(sizeof (newvector) * APIC_MAX_VECTOR * 2, 2592 KM_NOSLEEP); 2593 2594 if (!apic_oldvec_to_newvec) { 2595 /* 2596 * This failure is not catastrophic. 2597 * But, the oldvec will never be freed. 2598 */ 2599 apic_error |= APIC_ERR_MARK_VECTOR_FAIL; 2600 lock_clear(&apic_revector_lock); 2601 intr_restore(iflag); 2602 return; 2603 } 2604 apic_newvec_to_oldvec = &apic_oldvec_to_newvec[APIC_MAX_VECTOR]; 2605 } 2606 2607 /* See if we already did this for drivers which do double addintrs */ 2608 if (apic_oldvec_to_newvec[oldvector] != newvector) { 2609 apic_oldvec_to_newvec[oldvector] = newvector; 2610 apic_newvec_to_oldvec[newvector] = oldvector; 2611 apic_revector_pending++; 2612 } 2613 lock_clear(&apic_revector_lock); 2614 intr_restore(iflag); 2615 (void) timeout(apic_xlate_vector_free_timeout_handler, 2616 (void *)(uintptr_t)oldvector, drv_usectohz(apic_revector_timeout)); 2617 } 2618 2619 /* 2620 * xlate_vector is called from intr_enter if revector_pending is set. 2621 * It will xlate it if needed and mark the old vector as free. 2622 */ 2623 uchar_t 2624 apic_xlate_vector(uchar_t vector) 2625 { 2626 uchar_t newvector, oldvector = 0; 2627 2628 lock_set(&apic_revector_lock); 2629 /* Do we really need to do this ? */ 2630 if (!apic_revector_pending) { 2631 lock_clear(&apic_revector_lock); 2632 return (vector); 2633 } 2634 if ((newvector = apic_oldvec_to_newvec[vector]) != 0) 2635 oldvector = vector; 2636 else { 2637 /* 2638 * The incoming vector is new . See if a stale entry is 2639 * remaining 2640 */ 2641 if ((oldvector = apic_newvec_to_oldvec[vector]) != 0) 2642 newvector = vector; 2643 } 2644 2645 if (oldvector) { 2646 apic_revector_pending--; 2647 apic_oldvec_to_newvec[oldvector] = 0; 2648 apic_newvec_to_oldvec[newvector] = 0; 2649 apic_free_vector(oldvector); 2650 lock_clear(&apic_revector_lock); 2651 /* There could have been more than one reprogramming! */ 2652 return (apic_xlate_vector(newvector)); 2653 } 2654 lock_clear(&apic_revector_lock); 2655 return (vector); 2656 } 2657 2658 void 2659 apic_xlate_vector_free_timeout_handler(void *arg) 2660 { 2661 ulong_t iflag; 2662 uchar_t oldvector, newvector; 2663 2664 oldvector = (uchar_t)(uintptr_t)arg; 2665 iflag = intr_clear(); 2666 lock_set(&apic_revector_lock); 2667 if ((newvector = apic_oldvec_to_newvec[oldvector]) != 0) { 2668 apic_free_vector(oldvector); 2669 apic_oldvec_to_newvec[oldvector] = 0; 2670 apic_newvec_to_oldvec[newvector] = 0; 2671 apic_revector_pending--; 2672 } 2673 2674 lock_clear(&apic_revector_lock); 2675 intr_restore(iflag); 2676 } 2677 2678 2679 /* 2680 * compute the polarity, trigger mode and vector for programming into 2681 * the I/O apic and record in airq_rdt_entry. 2682 */ 2683 static void 2684 apic_record_rdt_entry(apic_irq_t *irqptr, int irq) 2685 { 2686 int ioapicindex, bus_type, vector; 2687 short intr_index; 2688 uint_t level, po, io_po; 2689 struct apic_io_intr *iointrp; 2690 2691 intr_index = irqptr->airq_mps_intr_index; 2692 DDI_INTR_IMPLDBG((CE_CONT, "apic_record_rdt_entry: intr_index=%d " 2693 "irq = 0x%x dip = 0x%p vector = 0x%x\n", intr_index, irq, 2694 (void *)irqptr->airq_dip, irqptr->airq_vector)); 2695 2696 if (intr_index == RESERVE_INDEX) { 2697 apic_error |= APIC_ERR_INVALID_INDEX; 2698 return; 2699 } else if (APIC_IS_MSI_OR_MSIX_INDEX(intr_index)) { 2700 return; 2701 } 2702 2703 vector = irqptr->airq_vector; 2704 ioapicindex = irqptr->airq_ioapicindex; 2705 /* Assume edge triggered by default */ 2706 level = 0; 2707 /* Assume active high by default */ 2708 po = 0; 2709 2710 if (intr_index == DEFAULT_INDEX || intr_index == FREE_INDEX) { 2711 ASSERT(irq < 16); 2712 if (eisa_level_intr_mask & (1 << irq)) 2713 level = AV_LEVEL; 2714 if (intr_index == FREE_INDEX && apic_defconf == 0) 2715 apic_error |= APIC_ERR_INVALID_INDEX; 2716 } else if (intr_index == ACPI_INDEX) { 2717 bus_type = irqptr->airq_iflag.bustype; 2718 if (irqptr->airq_iflag.intr_el == INTR_EL_CONFORM) { 2719 if (bus_type == BUS_PCI) 2720 level = AV_LEVEL; 2721 } else 2722 level = (irqptr->airq_iflag.intr_el == INTR_EL_LEVEL) ? 2723 AV_LEVEL : 0; 2724 if (level && 2725 ((irqptr->airq_iflag.intr_po == INTR_PO_ACTIVE_LOW) || 2726 (irqptr->airq_iflag.intr_po == INTR_PO_CONFORM && 2727 bus_type == BUS_PCI))) 2728 po = AV_ACTIVE_LOW; 2729 } else { 2730 iointrp = apic_io_intrp + intr_index; 2731 bus_type = apic_find_bus(iointrp->intr_busid); 2732 if (iointrp->intr_el == INTR_EL_CONFORM) { 2733 if ((irq < 16) && (eisa_level_intr_mask & (1 << irq))) 2734 level = AV_LEVEL; 2735 else if (bus_type == BUS_PCI) 2736 level = AV_LEVEL; 2737 } else 2738 level = (iointrp->intr_el == INTR_EL_LEVEL) ? 2739 AV_LEVEL : 0; 2740 if (level && ((iointrp->intr_po == INTR_PO_ACTIVE_LOW) || 2741 (iointrp->intr_po == INTR_PO_CONFORM && 2742 bus_type == BUS_PCI))) 2743 po = AV_ACTIVE_LOW; 2744 } 2745 if (level) 2746 apic_level_intr[irq] = 1; 2747 /* 2748 * The 82489DX External APIC cannot do active low polarity interrupts. 2749 */ 2750 if (po && (apic_io_ver[ioapicindex] != IOAPIC_VER_82489DX)) 2751 io_po = po; 2752 else 2753 io_po = 0; 2754 2755 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) 2756 printf("setio: ioapic=%x intin=%x level=%x po=%x vector=%x\n", 2757 ioapicindex, irqptr->airq_intin_no, level, io_po, vector); 2758 2759 irqptr->airq_rdt_entry = level|io_po|vector; 2760 } 2761 2762 /* 2763 * Bind interrupt corresponding to irq_ptr to bind_cpu. 2764 * Must be called with interrupts disabled and apic_ioapic_lock held 2765 */ 2766 int 2767 apic_rebind(apic_irq_t *irq_ptr, int bind_cpu, 2768 struct ioapic_reprogram_data *drep) 2769 { 2770 int ioapicindex, intin_no; 2771 uchar_t airq_temp_cpu; 2772 apic_cpus_info_t *cpu_infop; 2773 uint32_t rdt_entry; 2774 int which_irq; 2775 2776 which_irq = apic_vector_to_irq[irq_ptr->airq_vector]; 2777 2778 intin_no = irq_ptr->airq_intin_no; 2779 ioapicindex = irq_ptr->airq_ioapicindex; 2780 airq_temp_cpu = irq_ptr->airq_temp_cpu; 2781 if (airq_temp_cpu != IRQ_UNINIT && airq_temp_cpu != IRQ_UNBOUND) { 2782 if (airq_temp_cpu & IRQ_USER_BOUND) 2783 /* Mask off high bit so it can be used as array index */ 2784 airq_temp_cpu &= ~IRQ_USER_BOUND; 2785 2786 ASSERT(airq_temp_cpu < apic_nproc); 2787 } 2788 2789 /* 2790 * Can't bind to a CPU that's not accepting interrupts: 2791 */ 2792 cpu_infop = &apic_cpus[bind_cpu & ~IRQ_USER_BOUND]; 2793 if (!(cpu_infop->aci_status & APIC_CPU_INTR_ENABLE)) 2794 return (1); 2795 2796 /* 2797 * If we are about to change the interrupt vector for this interrupt, 2798 * and this interrupt is level-triggered, attached to an IOAPIC, 2799 * has been delivered to a CPU and that CPU has not handled it 2800 * yet, we cannot reprogram the IOAPIC now. 2801 */ 2802 if (!APIC_IS_MSI_OR_MSIX_INDEX(irq_ptr->airq_mps_intr_index)) { 2803 2804 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, 2805 intin_no); 2806 2807 if ((irq_ptr->airq_vector != RDT_VECTOR(rdt_entry)) && 2808 apic_check_stuck_interrupt(irq_ptr, airq_temp_cpu, 2809 bind_cpu, ioapicindex, intin_no, which_irq, drep) != 0) { 2810 2811 return (0); 2812 } 2813 2814 /* 2815 * NOTE: We do not unmask the RDT here, as an interrupt MAY 2816 * still come in before we have a chance to reprogram it below. 2817 * The reprogramming below will simultaneously change and 2818 * unmask the RDT entry. 2819 */ 2820 2821 if ((uchar_t)bind_cpu == IRQ_UNBOUND) { 2822 rdt_entry = AV_LDEST | AV_LOPRI | 2823 irq_ptr->airq_rdt_entry; 2824 2825 /* Write the RDT entry -- no specific CPU binding */ 2826 WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapicindex, intin_no, 2827 AV_TOALL); 2828 2829 if (airq_temp_cpu != IRQ_UNINIT && airq_temp_cpu != 2830 IRQ_UNBOUND) 2831 apic_cpus[airq_temp_cpu].aci_temp_bound--; 2832 2833 /* 2834 * Write the vector, trigger, and polarity portion of 2835 * the RDT 2836 */ 2837 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, intin_no, 2838 rdt_entry); 2839 2840 irq_ptr->airq_temp_cpu = IRQ_UNBOUND; 2841 return (0); 2842 } 2843 } 2844 2845 if (bind_cpu & IRQ_USER_BOUND) { 2846 cpu_infop->aci_bound++; 2847 } else { 2848 cpu_infop->aci_temp_bound++; 2849 } 2850 ASSERT((bind_cpu & ~IRQ_USER_BOUND) < apic_nproc); 2851 if (!APIC_IS_MSI_OR_MSIX_INDEX(irq_ptr->airq_mps_intr_index)) { 2852 /* Write the RDT entry -- bind to a specific CPU: */ 2853 WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapicindex, intin_no, 2854 cpu_infop->aci_local_id << APIC_ID_BIT_OFFSET); 2855 } 2856 if ((airq_temp_cpu != IRQ_UNBOUND) && (airq_temp_cpu != IRQ_UNINIT)) { 2857 apic_cpus[airq_temp_cpu].aci_temp_bound--; 2858 } 2859 if (!APIC_IS_MSI_OR_MSIX_INDEX(irq_ptr->airq_mps_intr_index)) { 2860 2861 rdt_entry = AV_PDEST | AV_FIXED | irq_ptr->airq_rdt_entry; 2862 2863 /* Write the vector, trigger, and polarity portion of the RDT */ 2864 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, intin_no, 2865 rdt_entry); 2866 2867 } else { 2868 int type = (irq_ptr->airq_mps_intr_index == MSI_INDEX) ? 2869 DDI_INTR_TYPE_MSI : DDI_INTR_TYPE_MSIX; 2870 if (type == DDI_INTR_TYPE_MSI) { 2871 if (irq_ptr->airq_ioapicindex == 2872 irq_ptr->airq_origirq) { 2873 /* first one */ 2874 DDI_INTR_IMPLDBG((CE_CONT, "apic_rebind: call " 2875 "apic_pci_msi_enable_vector\n")); 2876 apic_pci_msi_enable_vector(irq_ptr->airq_dip, 2877 type, which_irq, irq_ptr->airq_vector, 2878 irq_ptr->airq_intin_no, 2879 cpu_infop->aci_local_id); 2880 } 2881 if ((irq_ptr->airq_ioapicindex + 2882 irq_ptr->airq_intin_no - 1) == 2883 irq_ptr->airq_origirq) { /* last one */ 2884 DDI_INTR_IMPLDBG((CE_CONT, "apic_rebind: call " 2885 "apic_pci_msi_enable_mode\n")); 2886 apic_pci_msi_enable_mode(irq_ptr->airq_dip, 2887 type, which_irq); 2888 } 2889 } else { /* MSI-X */ 2890 apic_pci_msi_enable_vector(irq_ptr->airq_dip, type, 2891 irq_ptr->airq_origirq, irq_ptr->airq_vector, 1, 2892 cpu_infop->aci_local_id); 2893 apic_pci_msi_enable_mode(irq_ptr->airq_dip, type, 2894 irq_ptr->airq_origirq); 2895 } 2896 } 2897 irq_ptr->airq_temp_cpu = (uchar_t)bind_cpu; 2898 apic_redist_cpu_skip &= ~(1 << (bind_cpu & ~IRQ_USER_BOUND)); 2899 return (0); 2900 } 2901 2902 static void 2903 apic_last_ditch_clear_remote_irr(int ioapic_ix, int intin_no) 2904 { 2905 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no) 2906 & AV_REMOTE_IRR) != 0) { 2907 /* 2908 * Trying to clear the bit through normal 2909 * channels has failed. So as a last-ditch 2910 * effort, try to set the trigger mode to 2911 * edge, then to level. This has been 2912 * observed to work on many systems. 2913 */ 2914 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 2915 intin_no, 2916 READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 2917 intin_no) & ~AV_LEVEL); 2918 2919 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 2920 intin_no, 2921 READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 2922 intin_no) | AV_LEVEL); 2923 2924 /* 2925 * If the bit's STILL set, this interrupt may 2926 * be hosed. 2927 */ 2928 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 2929 intin_no) & AV_REMOTE_IRR) != 0) { 2930 2931 prom_printf("%s: Remote IRR still " 2932 "not clear for IOAPIC %d intin %d.\n" 2933 "\tInterrupts to this pin may cease " 2934 "functioning.\n", psm_name, ioapic_ix, 2935 intin_no); 2936 #ifdef DEBUG 2937 apic_last_ditch_reprogram_failures++; 2938 #endif 2939 } 2940 } 2941 } 2942 2943 /* 2944 * This function is protected by apic_ioapic_lock coupled with the 2945 * fact that interrupts are disabled. 2946 */ 2947 static void 2948 delete_defer_repro_ent(int which_irq) 2949 { 2950 ASSERT(which_irq >= 0); 2951 ASSERT(which_irq <= 255); 2952 2953 if (apic_reprogram_info[which_irq].done) 2954 return; 2955 2956 apic_reprogram_info[which_irq].done = B_TRUE; 2957 2958 #ifdef DEBUG 2959 apic_defer_repro_total_retries += 2960 apic_reprogram_info[which_irq].tries; 2961 2962 apic_defer_repro_successes++; 2963 #endif 2964 2965 if (--apic_reprogram_outstanding == 0) { 2966 2967 setlvlx = apic_intr_exit; 2968 } 2969 } 2970 2971 2972 /* 2973 * Interrupts must be disabled during this function to prevent 2974 * self-deadlock. Interrupts are disabled because this function 2975 * is called from apic_check_stuck_interrupt(), which is called 2976 * from apic_rebind(), which requires its caller to disable interrupts. 2977 */ 2978 static void 2979 add_defer_repro_ent(apic_irq_t *irq_ptr, int which_irq, int new_bind_cpu) 2980 { 2981 ASSERT(which_irq >= 0); 2982 ASSERT(which_irq <= 255); 2983 2984 /* 2985 * On the off-chance that there's already a deferred 2986 * reprogramming on this irq, check, and if so, just update the 2987 * CPU and irq pointer to which the interrupt is targeted, then return. 2988 */ 2989 if (!apic_reprogram_info[which_irq].done) { 2990 apic_reprogram_info[which_irq].bindcpu = new_bind_cpu; 2991 apic_reprogram_info[which_irq].irqp = irq_ptr; 2992 return; 2993 } 2994 2995 apic_reprogram_info[which_irq].irqp = irq_ptr; 2996 apic_reprogram_info[which_irq].bindcpu = new_bind_cpu; 2997 apic_reprogram_info[which_irq].tries = 0; 2998 /* 2999 * This must be the last thing set, since we're not 3000 * grabbing any locks, apic_try_deferred_reprogram() will 3001 * make its decision about using this entry iff done 3002 * is false. 3003 */ 3004 apic_reprogram_info[which_irq].done = B_FALSE; 3005 3006 /* 3007 * If there were previously no deferred reprogrammings, change 3008 * setlvlx to call apic_try_deferred_reprogram() 3009 */ 3010 if (++apic_reprogram_outstanding == 1) { 3011 3012 setlvlx = apic_try_deferred_reprogram; 3013 } 3014 } 3015 3016 static void 3017 apic_try_deferred_reprogram(int prev_ipl, int irq) 3018 { 3019 int reproirq, iflag; 3020 struct ioapic_reprogram_data *drep; 3021 3022 apic_intr_exit(prev_ipl, irq); 3023 3024 if (!lock_try(&apic_defer_reprogram_lock)) { 3025 return; 3026 } 3027 3028 /* 3029 * Acquire the apic_ioapic_lock so that any other operations that 3030 * may affect the apic_reprogram_info state are serialized. 3031 * It's still possible for the last deferred reprogramming to clear 3032 * between the time we entered this function and the time we get to 3033 * the for loop below. In that case, *setlvlx will have been set 3034 * back to apic_intr_exit and drep will be NULL. (There's no way to 3035 * stop that from happening -- we would need to grab a lock before 3036 * calling *setlvlx, which is neither realistic nor prudent). 3037 */ 3038 iflag = intr_clear(); 3039 lock_set(&apic_ioapic_lock); 3040 3041 /* 3042 * For each deferred RDT entry, try to reprogram it now. Note that 3043 * there is no lock acquisition to read apic_reprogram_info because 3044 * '.done' is set only after the other fields in the structure are set. 3045 */ 3046 3047 drep = NULL; 3048 for (reproirq = 0; reproirq <= APIC_MAX_VECTOR; reproirq++) { 3049 if (apic_reprogram_info[reproirq].done == B_FALSE) { 3050 drep = &apic_reprogram_info[reproirq]; 3051 break; 3052 } 3053 } 3054 3055 /* 3056 * Either we found a deferred action to perform, or 3057 * we entered this function spuriously, after *setlvlx 3058 * was restored to point to apic_intr_enter. Any other 3059 * permutation is invalid. 3060 */ 3061 ASSERT(drep != NULL || *setlvlx == apic_intr_exit); 3062 3063 /* 3064 * Though we can't really do anything about errors 3065 * at this point, keep track of them for reporting. 3066 * Note that it is very possible for apic_setup_io_intr 3067 * to re-register this very timeout if the Remote IRR bit 3068 * has not yet cleared. 3069 */ 3070 3071 #ifdef DEBUG 3072 if (drep != NULL) { 3073 if (apic_setup_io_intr(drep, reproirq, B_TRUE) != 0) { 3074 apic_deferred_setup_failures++; 3075 } 3076 } else { 3077 apic_deferred_spurious_enters++; 3078 } 3079 #else 3080 if (drep != NULL) 3081 (void) apic_setup_io_intr(drep, reproirq, B_TRUE); 3082 #endif 3083 3084 lock_clear(&apic_ioapic_lock); 3085 intr_restore(iflag); 3086 3087 lock_clear(&apic_defer_reprogram_lock); 3088 } 3089 3090 static void 3091 apic_ioapic_wait_pending_clear(int ioapic_ix, int intin_no) 3092 { 3093 int waited; 3094 3095 /* 3096 * Wait for the delivery pending bit to clear. 3097 */ 3098 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no) & 3099 (AV_LEVEL|AV_PENDING)) == (AV_LEVEL|AV_PENDING)) { 3100 3101 /* 3102 * If we're still waiting on the delivery of this interrupt, 3103 * continue to wait here until it is delivered (this should be 3104 * a very small amount of time, but include a timeout just in 3105 * case). 3106 */ 3107 for (waited = 0; waited < apic_max_reps_clear_pending; 3108 waited++) { 3109 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 3110 intin_no) & AV_PENDING) == 0) { 3111 break; 3112 } 3113 } 3114 } 3115 } 3116 3117 3118 /* 3119 * Checks to see if the IOAPIC interrupt entry specified has its Remote IRR 3120 * bit set. Calls functions that modify the function that setlvlx points to, 3121 * so that the reprogramming can be retried very shortly. 3122 * 3123 * This function will mask the RDT entry if the interrupt is level-triggered. 3124 * (The caller is responsible for unmasking the RDT entry.) 3125 * 3126 * Returns non-zero if the caller should defer IOAPIC reprogramming. 3127 */ 3128 static int 3129 apic_check_stuck_interrupt(apic_irq_t *irq_ptr, int old_bind_cpu, 3130 int new_bind_cpu, int ioapic_ix, int intin_no, int which_irq, 3131 struct ioapic_reprogram_data *drep) 3132 { 3133 int32_t rdt_entry; 3134 int waited; 3135 int reps = 0; 3136 3137 /* 3138 * Wait for the delivery pending bit to clear. 3139 */ 3140 do { 3141 ++reps; 3142 3143 apic_ioapic_wait_pending_clear(ioapic_ix, intin_no); 3144 3145 /* 3146 * Mask the RDT entry, but only if it's a level-triggered 3147 * interrupt 3148 */ 3149 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 3150 intin_no); 3151 if ((rdt_entry & (AV_LEVEL|AV_MASK)) == AV_LEVEL) { 3152 3153 /* Mask it */ 3154 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no, 3155 AV_MASK | rdt_entry); 3156 } 3157 3158 if ((rdt_entry & AV_LEVEL) == AV_LEVEL) { 3159 /* 3160 * If there was a race and an interrupt was injected 3161 * just before we masked, check for that case here. 3162 * Then, unmask the RDT entry and try again. If we're 3163 * on our last try, don't unmask (because we want the 3164 * RDT entry to remain masked for the rest of the 3165 * function). 3166 */ 3167 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 3168 intin_no); 3169 if ((rdt_entry & AV_PENDING) && 3170 (reps < apic_max_reps_clear_pending)) { 3171 /* Unmask it */ 3172 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 3173 intin_no, rdt_entry & ~AV_MASK); 3174 } 3175 } 3176 3177 } while ((rdt_entry & AV_PENDING) && 3178 (reps < apic_max_reps_clear_pending)); 3179 3180 #ifdef DEBUG 3181 if (rdt_entry & AV_PENDING) 3182 apic_intr_deliver_timeouts++; 3183 #endif 3184 3185 /* 3186 * If the remote IRR bit is set, then the interrupt has been sent 3187 * to a CPU for processing. We have no choice but to wait for 3188 * that CPU to process the interrupt, at which point the remote IRR 3189 * bit will be cleared. 3190 */ 3191 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no) & 3192 (AV_LEVEL|AV_REMOTE_IRR)) == (AV_LEVEL|AV_REMOTE_IRR)) { 3193 3194 /* 3195 * If the CPU that this RDT is bound to is NOT the current 3196 * CPU, wait until that CPU handles the interrupt and ACKs 3197 * it. If this interrupt is not bound to any CPU (that is, 3198 * if it's bound to the logical destination of "anyone"), it 3199 * may have been delivered to the current CPU so handle that 3200 * case by deferring the reprogramming (below). 3201 */ 3202 if ((old_bind_cpu != IRQ_UNBOUND) && 3203 (old_bind_cpu != IRQ_UNINIT) && 3204 (old_bind_cpu != psm_get_cpu_id())) { 3205 for (waited = 0; waited < apic_max_reps_clear_pending; 3206 waited++) { 3207 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 3208 intin_no) & AV_REMOTE_IRR) == 0) { 3209 3210 delete_defer_repro_ent(which_irq); 3211 3212 /* Remote IRR has cleared! */ 3213 return (0); 3214 } 3215 } 3216 } 3217 3218 /* 3219 * If we waited and the Remote IRR bit is still not cleared, 3220 * AND if we've invoked the timeout APIC_REPROGRAM_MAX_TIMEOUTS 3221 * times for this interrupt, try the last-ditch workaround: 3222 */ 3223 if (drep && drep->tries >= APIC_REPROGRAM_MAX_TRIES) { 3224 3225 apic_last_ditch_clear_remote_irr(ioapic_ix, intin_no); 3226 3227 /* Mark this one as reprogrammed: */ 3228 delete_defer_repro_ent(which_irq); 3229 3230 return (0); 3231 } else { 3232 #ifdef DEBUG 3233 apic_intr_deferrals++; 3234 #endif 3235 3236 /* 3237 * If waiting for the Remote IRR bit (above) didn't 3238 * allow it to clear, defer the reprogramming. 3239 * Add a new deferred-programming entry if the 3240 * caller passed a NULL one (and update the existing one 3241 * in case anything changed). 3242 */ 3243 add_defer_repro_ent(irq_ptr, which_irq, new_bind_cpu); 3244 if (drep) 3245 drep->tries++; 3246 3247 /* Inform caller to defer IOAPIC programming: */ 3248 return (1); 3249 } 3250 3251 } 3252 3253 /* Remote IRR is clear */ 3254 delete_defer_repro_ent(which_irq); 3255 3256 return (0); 3257 } 3258 3259 /* 3260 * Called to migrate all interrupts at an irq to another cpu. 3261 * Must be called with interrupts disabled and apic_ioapic_lock held 3262 */ 3263 int 3264 apic_rebind_all(apic_irq_t *irq_ptr, int bind_cpu) 3265 { 3266 apic_irq_t *irqptr = irq_ptr; 3267 int retval = 0; 3268 3269 while (irqptr) { 3270 if (irqptr->airq_temp_cpu != IRQ_UNINIT) 3271 retval |= apic_rebind(irqptr, bind_cpu, NULL); 3272 irqptr = irqptr->airq_next; 3273 } 3274 3275 return (retval); 3276 } 3277 3278 /* 3279 * apic_intr_redistribute does all the messy computations for identifying 3280 * which interrupt to move to which CPU. Currently we do just one interrupt 3281 * at a time. This reduces the time we spent doing all this within clock 3282 * interrupt. When it is done in idle, we could do more than 1. 3283 * First we find the most busy and the most free CPU (time in ISR only) 3284 * skipping those CPUs that has been identified as being ineligible (cpu_skip) 3285 * Then we look for IRQs which are closest to the difference between the 3286 * most busy CPU and the average ISR load. We try to find one whose load 3287 * is less than difference.If none exists, then we chose one larger than the 3288 * difference, provided it does not make the most idle CPU worse than the 3289 * most busy one. In the end, we clear all the busy fields for CPUs. For 3290 * IRQs, they are cleared as they are scanned. 3291 */ 3292 void 3293 apic_intr_redistribute() 3294 { 3295 int busiest_cpu, most_free_cpu; 3296 int cpu_free, cpu_busy, max_busy, min_busy; 3297 int min_free, diff; 3298 int average_busy, cpus_online; 3299 int i, busy, iflag; 3300 apic_cpus_info_t *cpu_infop; 3301 apic_irq_t *min_busy_irq = NULL; 3302 apic_irq_t *max_busy_irq = NULL; 3303 3304 busiest_cpu = most_free_cpu = -1; 3305 cpu_free = cpu_busy = max_busy = average_busy = 0; 3306 min_free = apic_sample_factor_redistribution; 3307 cpus_online = 0; 3308 /* 3309 * Below we will check for CPU_INTR_ENABLE, bound, temp_bound, temp_cpu 3310 * without ioapic_lock. That is OK as we are just doing statistical 3311 * sampling anyway and any inaccuracy now will get corrected next time 3312 * The call to rebind which actually changes things will make sure 3313 * we are consistent. 3314 */ 3315 for (i = 0; i < apic_nproc; i++) { 3316 if (!(apic_redist_cpu_skip & (1 << i)) && 3317 (apic_cpus[i].aci_status & APIC_CPU_INTR_ENABLE)) { 3318 3319 cpu_infop = &apic_cpus[i]; 3320 /* 3321 * If no unbound interrupts or only 1 total on this 3322 * CPU, skip 3323 */ 3324 if (!cpu_infop->aci_temp_bound || 3325 (cpu_infop->aci_bound + cpu_infop->aci_temp_bound) 3326 == 1) { 3327 apic_redist_cpu_skip |= 1 << i; 3328 continue; 3329 } 3330 3331 busy = cpu_infop->aci_busy; 3332 average_busy += busy; 3333 cpus_online++; 3334 if (max_busy < busy) { 3335 max_busy = busy; 3336 busiest_cpu = i; 3337 } 3338 if (min_free > busy) { 3339 min_free = busy; 3340 most_free_cpu = i; 3341 } 3342 if (busy > apic_int_busy_mark) { 3343 cpu_busy |= 1 << i; 3344 } else { 3345 if (busy < apic_int_free_mark) 3346 cpu_free |= 1 << i; 3347 } 3348 } 3349 } 3350 if ((cpu_busy && cpu_free) || 3351 (max_busy >= (min_free + apic_diff_for_redistribution))) { 3352 3353 apic_num_imbalance++; 3354 #ifdef DEBUG 3355 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) { 3356 prom_printf( 3357 "redistribute busy=%x free=%x max=%x min=%x", 3358 cpu_busy, cpu_free, max_busy, min_free); 3359 } 3360 #endif /* DEBUG */ 3361 3362 3363 average_busy /= cpus_online; 3364 3365 diff = max_busy - average_busy; 3366 min_busy = max_busy; /* start with the max possible value */ 3367 max_busy = 0; 3368 min_busy_irq = max_busy_irq = NULL; 3369 i = apic_min_device_irq; 3370 for (; i < apic_max_device_irq; i++) { 3371 apic_irq_t *irq_ptr; 3372 /* Change to linked list per CPU ? */ 3373 if ((irq_ptr = apic_irq_table[i]) == NULL) 3374 continue; 3375 /* Check for irq_busy & decide which one to move */ 3376 /* Also zero them for next round */ 3377 if ((irq_ptr->airq_temp_cpu == busiest_cpu) && 3378 irq_ptr->airq_busy) { 3379 if (irq_ptr->airq_busy < diff) { 3380 /* 3381 * Check for least busy CPU, 3382 * best fit or what ? 3383 */ 3384 if (max_busy < irq_ptr->airq_busy) { 3385 /* 3386 * Most busy within the 3387 * required differential 3388 */ 3389 max_busy = irq_ptr->airq_busy; 3390 max_busy_irq = irq_ptr; 3391 } 3392 } else { 3393 if (min_busy > irq_ptr->airq_busy) { 3394 /* 3395 * least busy, but more than 3396 * the reqd diff 3397 */ 3398 if (min_busy < 3399 (diff + average_busy - 3400 min_free)) { 3401 /* 3402 * Making sure new cpu 3403 * will not end up 3404 * worse 3405 */ 3406 min_busy = 3407 irq_ptr->airq_busy; 3408 3409 min_busy_irq = irq_ptr; 3410 } 3411 } 3412 } 3413 } 3414 irq_ptr->airq_busy = 0; 3415 } 3416 3417 if (max_busy_irq != NULL) { 3418 #ifdef DEBUG 3419 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) { 3420 prom_printf("rebinding %x to %x", 3421 max_busy_irq->airq_vector, most_free_cpu); 3422 } 3423 #endif /* DEBUG */ 3424 iflag = intr_clear(); 3425 if (lock_try(&apic_ioapic_lock)) { 3426 if (apic_rebind_all(max_busy_irq, 3427 most_free_cpu) == 0) { 3428 /* Make change permenant */ 3429 max_busy_irq->airq_cpu = 3430 (uchar_t)most_free_cpu; 3431 } 3432 lock_clear(&apic_ioapic_lock); 3433 } 3434 intr_restore(iflag); 3435 3436 } else if (min_busy_irq != NULL) { 3437 #ifdef DEBUG 3438 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) { 3439 prom_printf("rebinding %x to %x", 3440 min_busy_irq->airq_vector, most_free_cpu); 3441 } 3442 #endif /* DEBUG */ 3443 3444 iflag = intr_clear(); 3445 if (lock_try(&apic_ioapic_lock)) { 3446 if (apic_rebind_all(min_busy_irq, 3447 most_free_cpu) == 0) { 3448 /* Make change permenant */ 3449 min_busy_irq->airq_cpu = 3450 (uchar_t)most_free_cpu; 3451 } 3452 lock_clear(&apic_ioapic_lock); 3453 } 3454 intr_restore(iflag); 3455 3456 } else { 3457 if (cpu_busy != (1 << busiest_cpu)) { 3458 apic_redist_cpu_skip |= 1 << busiest_cpu; 3459 /* 3460 * We leave cpu_skip set so that next time we 3461 * can choose another cpu 3462 */ 3463 } 3464 } 3465 apic_num_rebind++; 3466 } else { 3467 /* 3468 * found nothing. Could be that we skipped over valid CPUs 3469 * or we have balanced everything. If we had a variable 3470 * ticks_for_redistribution, it could be increased here. 3471 * apic_int_busy, int_free etc would also need to be 3472 * changed. 3473 */ 3474 if (apic_redist_cpu_skip) 3475 apic_redist_cpu_skip = 0; 3476 } 3477 for (i = 0; i < apic_nproc; i++) { 3478 apic_cpus[i].aci_busy = 0; 3479 } 3480 } 3481 3482 void 3483 apic_cleanup_busy() 3484 { 3485 int i; 3486 apic_irq_t *irq_ptr; 3487 3488 for (i = 0; i < apic_nproc; i++) { 3489 apic_cpus[i].aci_busy = 0; 3490 } 3491 3492 for (i = apic_min_device_irq; i < apic_max_device_irq; i++) { 3493 if ((irq_ptr = apic_irq_table[i]) != NULL) 3494 irq_ptr->airq_busy = 0; 3495 } 3496 } 3497 3498 3499 static int 3500 apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid, 3501 int ipin, int *pci_irqp, iflag_t *intr_flagp) 3502 { 3503 3504 int status; 3505 acpi_psm_lnk_t acpipsmlnk; 3506 3507 if ((status = acpi_get_irq_cache_ent(busid, devid, ipin, pci_irqp, 3508 intr_flagp)) == ACPI_PSM_SUCCESS) { 3509 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Found irqno %d " 3510 "from cache for device %s, instance #%d\n", psm_name, 3511 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip))); 3512 return (status); 3513 } 3514 3515 bzero(&acpipsmlnk, sizeof (acpi_psm_lnk_t)); 3516 3517 if ((status = acpi_translate_pci_irq(dip, ipin, pci_irqp, intr_flagp, 3518 &acpipsmlnk)) == ACPI_PSM_FAILURE) { 3519 APIC_VERBOSE_IRQ((CE_WARN, "%s: " 3520 " acpi_translate_pci_irq failed for device %s, instance" 3521 " #%d", psm_name, ddi_get_name(dip), 3522 ddi_get_instance(dip))); 3523 return (status); 3524 } 3525 3526 if (status == ACPI_PSM_PARTIAL && acpipsmlnk.lnkobj != NULL) { 3527 status = apic_acpi_irq_configure(&acpipsmlnk, dip, pci_irqp, 3528 intr_flagp); 3529 if (status != ACPI_PSM_SUCCESS) { 3530 status = acpi_get_current_irq_resource(&acpipsmlnk, 3531 pci_irqp, intr_flagp); 3532 } 3533 } 3534 3535 if (status == ACPI_PSM_SUCCESS) { 3536 acpi_new_irq_cache_ent(busid, devid, ipin, *pci_irqp, 3537 intr_flagp, &acpipsmlnk); 3538 3539 APIC_VERBOSE_IRQ((CE_CONT, "%s: [ACPI] " 3540 "new irq %d for device %s, instance #%d\n", psm_name, 3541 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip))); 3542 } 3543 3544 return (status); 3545 } 3546 3547 /* 3548 * Adds an entry to the irq list passed in, and returns the new list. 3549 * Entries are added in priority order (lower numerical priorities are 3550 * placed closer to the head of the list) 3551 */ 3552 static prs_irq_list_t * 3553 acpi_insert_prs_irq_ent(prs_irq_list_t *listp, int priority, int irq, 3554 iflag_t *iflagp, acpi_prs_private_t *prsprvp) 3555 { 3556 struct prs_irq_list_ent *newent, *prevp = NULL, *origlistp; 3557 3558 newent = kmem_zalloc(sizeof (struct prs_irq_list_ent), KM_SLEEP); 3559 3560 newent->list_prio = priority; 3561 newent->irq = irq; 3562 newent->intrflags = *iflagp; 3563 newent->prsprv = *prsprvp; 3564 /* ->next is NULL from kmem_zalloc */ 3565 3566 /* 3567 * New list -- return the new entry as the list. 3568 */ 3569 if (listp == NULL) 3570 return (newent); 3571 3572 /* 3573 * Save original list pointer for return (since we're not modifying 3574 * the head) 3575 */ 3576 origlistp = listp; 3577 3578 /* 3579 * Insertion sort, with entries with identical keys stored AFTER 3580 * existing entries (the less-than-or-equal test of priority does 3581 * this for us). 3582 */ 3583 while (listp != NULL && listp->list_prio <= priority) { 3584 prevp = listp; 3585 listp = listp->next; 3586 } 3587 3588 newent->next = listp; 3589 3590 if (prevp == NULL) { /* Add at head of list (newent is the new head) */ 3591 return (newent); 3592 } else { 3593 prevp->next = newent; 3594 return (origlistp); 3595 } 3596 } 3597 3598 /* 3599 * Frees the list passed in, deallocating all memory and leaving *listpp 3600 * set to NULL. 3601 */ 3602 static void 3603 acpi_destroy_prs_irq_list(prs_irq_list_t **listpp) 3604 { 3605 struct prs_irq_list_ent *nextp; 3606 3607 ASSERT(listpp != NULL); 3608 3609 while (*listpp != NULL) { 3610 nextp = (*listpp)->next; 3611 kmem_free(*listpp, sizeof (struct prs_irq_list_ent)); 3612 *listpp = nextp; 3613 } 3614 } 3615 3616 /* 3617 * apic_choose_irqs_from_prs returns a list of irqs selected from the list of 3618 * irqs returned by the link device's _PRS method. The irqs are chosen 3619 * to minimize contention in situations where the interrupt link device 3620 * can be programmed to steer interrupts to different interrupt controller 3621 * inputs (some of which may already be in use). The list is sorted in order 3622 * of irqs to use, with the highest priority given to interrupt controller 3623 * inputs that are not shared. When an interrupt controller input 3624 * must be shared, apic_choose_irqs_from_prs adds the possible irqs to the 3625 * returned list in the order that minimizes sharing (thereby ensuring lowest 3626 * possible latency from interrupt trigger time to ISR execution time). 3627 */ 3628 static prs_irq_list_t * 3629 apic_choose_irqs_from_prs(acpi_irqlist_t *irqlistent, dev_info_t *dip, 3630 int crs_irq) 3631 { 3632 int32_t irq; 3633 int i; 3634 prs_irq_list_t *prsirqlistp = NULL; 3635 iflag_t iflags; 3636 3637 while (irqlistent != NULL) { 3638 irqlistent->intr_flags.bustype = BUS_PCI; 3639 3640 for (i = 0; i < irqlistent->num_irqs; i++) { 3641 3642 irq = irqlistent->irqs[i]; 3643 3644 if (irq <= 0) { 3645 /* invalid irq number */ 3646 continue; 3647 } 3648 3649 if ((irq < 16) && (apic_reserved_irqlist[irq])) 3650 continue; 3651 3652 if ((apic_irq_table[irq] == NULL) || 3653 (apic_irq_table[irq]->airq_dip == dip)) { 3654 3655 prsirqlistp = acpi_insert_prs_irq_ent( 3656 prsirqlistp, 0 /* Highest priority */, irq, 3657 &irqlistent->intr_flags, 3658 &irqlistent->acpi_prs_prv); 3659 3660 /* 3661 * If we do not prefer the current irq from _CRS 3662 * or if we do and this irq is the same as the 3663 * current irq from _CRS, this is the one 3664 * to pick. 3665 */ 3666 if (!(apic_prefer_crs) || (irq == crs_irq)) { 3667 return (prsirqlistp); 3668 } 3669 continue; 3670 } 3671 3672 /* 3673 * Edge-triggered interrupts cannot be shared 3674 */ 3675 if (irqlistent->intr_flags.intr_el == INTR_EL_EDGE) 3676 continue; 3677 3678 /* 3679 * To work around BIOSes that contain incorrect 3680 * interrupt polarity information in interrupt 3681 * descriptors returned by _PRS, we assume that 3682 * the polarity of the other device sharing this 3683 * interrupt controller input is compatible. 3684 * If it's not, the caller will catch it when 3685 * the caller invokes the link device's _CRS method 3686 * (after invoking its _SRS method). 3687 */ 3688 iflags = irqlistent->intr_flags; 3689 iflags.intr_po = 3690 apic_irq_table[irq]->airq_iflag.intr_po; 3691 3692 if (!acpi_intr_compatible(iflags, 3693 apic_irq_table[irq]->airq_iflag)) { 3694 APIC_VERBOSE_IRQ((CE_CONT, "!%s: irq %d " 3695 "not compatible [%x:%x:%x !~ %x:%x:%x]", 3696 psm_name, irq, 3697 iflags.intr_po, 3698 iflags.intr_el, 3699 iflags.bustype, 3700 apic_irq_table[irq]->airq_iflag.intr_po, 3701 apic_irq_table[irq]->airq_iflag.intr_el, 3702 apic_irq_table[irq]->airq_iflag.bustype)); 3703 continue; 3704 } 3705 3706 /* 3707 * If we prefer the irq from _CRS, no need 3708 * to search any further (and make sure 3709 * to add this irq with the highest priority 3710 * so it's tried first). 3711 */ 3712 if (crs_irq == irq && apic_prefer_crs) { 3713 3714 return (acpi_insert_prs_irq_ent( 3715 prsirqlistp, 3716 0 /* Highest priority */, 3717 irq, &iflags, 3718 &irqlistent->acpi_prs_prv)); 3719 } 3720 3721 /* 3722 * Priority is equal to the share count (lower 3723 * share count is higher priority). Note that 3724 * the intr flags passed in here are the ones we 3725 * changed above -- if incorrect, it will be 3726 * caught by the caller's _CRS flags comparison. 3727 */ 3728 prsirqlistp = acpi_insert_prs_irq_ent( 3729 prsirqlistp, 3730 apic_irq_table[irq]->airq_share, irq, 3731 &iflags, &irqlistent->acpi_prs_prv); 3732 } 3733 3734 /* Go to the next irqlist entry */ 3735 irqlistent = irqlistent->next; 3736 } 3737 3738 return (prsirqlistp); 3739 } 3740 3741 /* 3742 * Configures the irq for the interrupt link device identified by 3743 * acpipsmlnkp. 3744 * 3745 * Gets the current and the list of possible irq settings for the 3746 * device. If apic_unconditional_srs is not set, and the current 3747 * resource setting is in the list of possible irq settings, 3748 * current irq resource setting is passed to the caller. 3749 * 3750 * Otherwise, picks an irq number from the list of possible irq 3751 * settings, and sets the irq of the device to this value. 3752 * If prefer_crs is set, among a set of irq numbers in the list that have 3753 * the least number of devices sharing the interrupt, we pick current irq 3754 * resource setting if it is a member of this set. 3755 * 3756 * Passes the irq number in the value pointed to by pci_irqp, and 3757 * polarity and sensitivity in the structure pointed to by dipintrflagp 3758 * to the caller. 3759 * 3760 * Note that if setting the irq resource failed, but successfuly obtained 3761 * the current irq resource settings, passes the current irq resources 3762 * and considers it a success. 3763 * 3764 * Returns: 3765 * ACPI_PSM_SUCCESS on success. 3766 * 3767 * ACPI_PSM_FAILURE if an error occured during the configuration or 3768 * if a suitable irq was not found for this device, or if setting the 3769 * irq resource and obtaining the current resource fails. 3770 * 3771 */ 3772 static int 3773 apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip, 3774 int *pci_irqp, iflag_t *dipintr_flagp) 3775 { 3776 int32_t irq; 3777 int cur_irq = -1; 3778 acpi_irqlist_t *irqlistp; 3779 prs_irq_list_t *prs_irq_listp, *prs_irq_entp; 3780 boolean_t found_irq = B_FALSE; 3781 3782 dipintr_flagp->bustype = BUS_PCI; 3783 3784 if ((acpi_get_possible_irq_resources(acpipsmlnkp, &irqlistp)) 3785 == ACPI_PSM_FAILURE) { 3786 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Unable to determine " 3787 "or assign IRQ for device %s, instance #%d: The system was " 3788 "unable to get the list of potential IRQs from ACPI.", 3789 psm_name, ddi_get_name(dip), ddi_get_instance(dip))); 3790 3791 return (ACPI_PSM_FAILURE); 3792 } 3793 3794 if ((acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq, 3795 dipintr_flagp) == ACPI_PSM_SUCCESS) && (!apic_unconditional_srs) && 3796 (cur_irq > 0)) { 3797 /* 3798 * If an IRQ is set in CRS and that IRQ exists in the set 3799 * returned from _PRS, return that IRQ, otherwise print 3800 * a warning 3801 */ 3802 3803 if (acpi_irqlist_find_irq(irqlistp, cur_irq, NULL) 3804 == ACPI_PSM_SUCCESS) { 3805 3806 ASSERT(pci_irqp != NULL); 3807 *pci_irqp = cur_irq; 3808 acpi_free_irqlist(irqlistp); 3809 return (ACPI_PSM_SUCCESS); 3810 } 3811 3812 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find the " 3813 "current irq %d for device %s, instance #%d in ACPI's " 3814 "list of possible irqs for this device. Picking one from " 3815 " the latter list.", psm_name, cur_irq, ddi_get_name(dip), 3816 ddi_get_instance(dip))); 3817 } 3818 3819 if ((prs_irq_listp = apic_choose_irqs_from_prs(irqlistp, dip, 3820 cur_irq)) == NULL) { 3821 3822 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find a " 3823 "suitable irq from the list of possible irqs for device " 3824 "%s, instance #%d in ACPI's list of possible irqs", 3825 psm_name, ddi_get_name(dip), ddi_get_instance(dip))); 3826 3827 acpi_free_irqlist(irqlistp); 3828 return (ACPI_PSM_FAILURE); 3829 } 3830 3831 acpi_free_irqlist(irqlistp); 3832 3833 for (prs_irq_entp = prs_irq_listp; 3834 prs_irq_entp != NULL && found_irq == B_FALSE; 3835 prs_irq_entp = prs_irq_entp->next) { 3836 3837 acpipsmlnkp->acpi_prs_prv = prs_irq_entp->prsprv; 3838 irq = prs_irq_entp->irq; 3839 3840 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Setting irq %d for " 3841 "device %s instance #%d\n", psm_name, irq, 3842 ddi_get_name(dip), ddi_get_instance(dip))); 3843 3844 if ((acpi_set_irq_resource(acpipsmlnkp, irq)) 3845 == ACPI_PSM_SUCCESS) { 3846 /* 3847 * setting irq was successful, check to make sure CRS 3848 * reflects that. If CRS does not agree with what we 3849 * set, return the irq that was set. 3850 */ 3851 3852 if (acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq, 3853 dipintr_flagp) == ACPI_PSM_SUCCESS) { 3854 3855 if (cur_irq != irq) 3856 APIC_VERBOSE_IRQ((CE_WARN, 3857 "!%s: IRQ resource set " 3858 "(irqno %d) for device %s " 3859 "instance #%d, differs from " 3860 "current setting irqno %d", 3861 psm_name, irq, ddi_get_name(dip), 3862 ddi_get_instance(dip), cur_irq)); 3863 } else { 3864 /* 3865 * On at least one system, there was a bug in 3866 * a DSDT method called by _STA, causing _STA to 3867 * indicate that the link device was disabled 3868 * (when, in fact, it was enabled). Since _SRS 3869 * succeeded, assume that _CRS is lying and use 3870 * the iflags from this _PRS interrupt choice. 3871 * If we're wrong about the flags, the polarity 3872 * will be incorrect and we may get an interrupt 3873 * storm, but there's not much else we can do 3874 * at this point. 3875 */ 3876 *dipintr_flagp = prs_irq_entp->intrflags; 3877 } 3878 3879 /* 3880 * Return the irq that was set, and not what _CRS 3881 * reports, since _CRS has been seen to return 3882 * different IRQs than what was passed to _SRS on some 3883 * systems (and just not return successfully on others). 3884 */ 3885 cur_irq = irq; 3886 found_irq = B_TRUE; 3887 } else { 3888 APIC_VERBOSE_IRQ((CE_WARN, "!%s: set resource " 3889 "irq %d failed for device %s instance #%d", 3890 psm_name, irq, ddi_get_name(dip), 3891 ddi_get_instance(dip))); 3892 3893 if (cur_irq == -1) { 3894 acpi_destroy_prs_irq_list(&prs_irq_listp); 3895 return (ACPI_PSM_FAILURE); 3896 } 3897 } 3898 } 3899 3900 acpi_destroy_prs_irq_list(&prs_irq_listp); 3901 3902 if (!found_irq) 3903 return (ACPI_PSM_FAILURE); 3904 3905 ASSERT(pci_irqp != NULL); 3906 *pci_irqp = cur_irq; 3907 return (ACPI_PSM_SUCCESS); 3908 } 3909 3910 void 3911 ioapic_disable_redirection() 3912 { 3913 int ioapic_ix; 3914 int intin_max; 3915 int intin_ix; 3916 3917 /* Disable the I/O APIC redirection entries */ 3918 for (ioapic_ix = 0; ioapic_ix < apic_io_max; ioapic_ix++) { 3919 3920 /* Bits 23-16 define the maximum redirection entries */ 3921 intin_max = (ioapic_read(ioapic_ix, APIC_VERS_CMD) >> 16) 3922 & 0xff; 3923 3924 for (intin_ix = 0; intin_ix < intin_max; intin_ix++) { 3925 /* 3926 * The assumption here is that this is safe, even for 3927 * systems with IOAPICs that suffer from the hardware 3928 * erratum because all devices have been quiesced before 3929 * this function is called from apic_shutdown() 3930 * (or equivalent). If that assumption turns out to be 3931 * false, this mask operation can induce the same 3932 * erratum result we're trying to avoid. 3933 */ 3934 ioapic_write(ioapic_ix, APIC_RDT_CMD + 2 * intin_ix, 3935 AV_MASK); 3936 } 3937 } 3938 } 3939 3940 /* 3941 * Looks for an IOAPIC with the specified physical address in the /ioapics 3942 * node in the device tree (created by the PCI enumerator). 3943 */ 3944 static boolean_t 3945 apic_is_ioapic_AMD_813x(uint32_t physaddr) 3946 { 3947 /* 3948 * Look in /ioapics, for the ioapic with 3949 * the physical address given 3950 */ 3951 dev_info_t *ioapicsnode = ddi_find_devinfo(IOAPICS_NODE_NAME, -1, 0); 3952 dev_info_t *ioapic_child; 3953 boolean_t rv = B_FALSE; 3954 int vid, did; 3955 uint64_t ioapic_paddr; 3956 boolean_t done = B_FALSE; 3957 3958 if (ioapicsnode == NULL) 3959 return (B_FALSE); 3960 3961 /* Load first child: */ 3962 ioapic_child = ddi_get_child(ioapicsnode); 3963 while (!done && ioapic_child != 0) { /* Iterate over children */ 3964 3965 if ((ioapic_paddr = (uint64_t)ddi_prop_get_int64(DDI_DEV_T_ANY, 3966 ioapic_child, DDI_PROP_DONTPASS, "reg", 0)) 3967 != 0 && physaddr == ioapic_paddr) { 3968 3969 vid = ddi_prop_get_int(DDI_DEV_T_ANY, ioapic_child, 3970 DDI_PROP_DONTPASS, IOAPICS_PROP_VENID, 0); 3971 3972 if (vid == VENID_AMD) { 3973 3974 did = ddi_prop_get_int(DDI_DEV_T_ANY, 3975 ioapic_child, DDI_PROP_DONTPASS, 3976 IOAPICS_PROP_DEVID, 0); 3977 3978 if (did == DEVID_8131_IOAPIC || 3979 did == DEVID_8132_IOAPIC) { 3980 3981 rv = B_TRUE; 3982 done = B_TRUE; 3983 } 3984 } 3985 } 3986 3987 if (!done) 3988 ioapic_child = ddi_get_next_sibling(ioapic_child); 3989 } 3990 3991 /* The ioapics node was held by ddi_find_devinfo, so release it */ 3992 ndi_rele_devi(ioapicsnode); 3993 return (rv); 3994 } 3995