1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * PSMI 1.1 extensions are supported only in 2.6 and later versions. 30 * PSMI 1.2 extensions are supported only in 2.7 and later versions. 31 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10. 32 * PSMI 1.5 extensions are supported in Solaris Nevada. 33 */ 34 #define PSMI_1_5 35 36 #include <sys/processor.h> 37 #include <sys/time.h> 38 #include <sys/psm.h> 39 #include <sys/smp_impldefs.h> 40 #include <sys/cram.h> 41 #include <sys/acpi/acpi.h> 42 #include <sys/acpica.h> 43 #include <sys/psm_common.h> 44 #include <sys/apic.h> 45 #include <sys/pit.h> 46 #include <sys/ddi.h> 47 #include <sys/sunddi.h> 48 #include <sys/ddi_impldefs.h> 49 #include <sys/pci.h> 50 #include <sys/promif.h> 51 #include <sys/x86_archext.h> 52 #include <sys/cpc_impl.h> 53 #include <sys/uadmin.h> 54 #include <sys/panic.h> 55 #include <sys/debug.h> 56 #include <sys/archsystm.h> 57 #include <sys/trap.h> 58 #include <sys/machsystm.h> 59 #include <sys/cpuvar.h> 60 #include <sys/rm_platter.h> 61 #include <sys/privregs.h> 62 #include <sys/cyclic.h> 63 #include <sys/note.h> 64 #include <sys/pci_intr_lib.h> 65 #include <sys/sunndi.h> 66 67 68 /* 69 * Local Function Prototypes 70 */ 71 static int apic_handle_defconf(); 72 static int apic_parse_mpct(caddr_t mpct, int bypass); 73 static struct apic_mpfps_hdr *apic_find_fps_sig(caddr_t fptr, int size); 74 static int apic_checksum(caddr_t bptr, int len); 75 static int apic_find_bus_type(char *bus); 76 static int apic_find_bus(int busid); 77 static int apic_find_bus_id(int bustype); 78 static struct apic_io_intr *apic_find_io_intr(int irqno); 79 static int apic_find_free_irq(int start, int end); 80 static void apic_mark_vector(uchar_t oldvector, uchar_t newvector); 81 static void apic_xlate_vector_free_timeout_handler(void *arg); 82 static void apic_reprogram_timeout_handler(void *arg); 83 static int apic_check_stuck_interrupt(apic_irq_t *irq_ptr, int old_bind_cpu, 84 int new_bind_cpu, int apicindex, int intin_no, int which_irq, 85 struct ioapic_reprogram_data *drep); 86 static void apic_record_rdt_entry(apic_irq_t *irqptr, int irq); 87 static struct apic_io_intr *apic_find_io_intr_w_busid(int irqno, int busid); 88 static int apic_find_intin(uchar_t ioapic, uchar_t intin); 89 static int apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, 90 int child_ipin, struct apic_io_intr **intrp); 91 static int apic_setup_irq_table(dev_info_t *dip, int irqno, 92 struct apic_io_intr *intrp, struct intrspec *ispec, iflag_t *intr_flagp, 93 int type); 94 static int apic_setup_sci_irq_table(int irqno, uchar_t ipl, 95 iflag_t *intr_flagp); 96 static void apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp); 97 static void apic_try_deferred_reprogram(int ipl, int vect); 98 static void delete_defer_repro_ent(int which_irq); 99 static void apic_ioapic_wait_pending_clear(int ioapicindex, 100 int intin_no); 101 static boolean_t apic_is_ioapic_AMD_813x(uint32_t physaddr); 102 103 int apic_debug_mps_id = 0; /* 1 - print MPS ID strings */ 104 105 /* ACPI SCI interrupt configuration; -1 if SCI not used */ 106 int apic_sci_vect = -1; 107 iflag_t apic_sci_flags; 108 109 /* 110 * psm name pointer 111 */ 112 static char *psm_name; 113 114 /* ACPI support routines */ 115 static int acpi_probe(char *); 116 static int apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip, 117 int *pci_irqp, iflag_t *intr_flagp); 118 119 static int apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid, 120 int ipin, int *pci_irqp, iflag_t *intr_flagp); 121 static uchar_t acpi_find_ioapic(int irq); 122 static int acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2); 123 124 125 /* 126 * number of bits per byte, from <sys/param.h> 127 */ 128 #define UCHAR_MAX ((1 << NBBY) - 1) 129 130 /* Max wait time (in repetitions) for flags to clear in an RDT entry. */ 131 int apic_max_reps_clear_pending = 1000; 132 133 /* The irq # is implicit in the array index: */ 134 struct ioapic_reprogram_data apic_reprogram_info[APIC_MAX_VECTOR+1]; 135 /* 136 * APIC_MAX_VECTOR + 1 is the maximum # of IRQs as well. ioapic_reprogram_info 137 * is indexed by IRQ number, NOT by vector number. 138 */ 139 140 int apic_intr_policy = INTR_ROUND_ROBIN_WITH_AFFINITY; 141 142 int apic_next_bind_cpu = 1; /* For round robin assignment */ 143 /* start with cpu 1 */ 144 145 /* 146 * If enabled, the distribution works as follows: 147 * On every interrupt entry, the current ipl for the CPU is set in cpu_info 148 * and the irq corresponding to the ipl is also set in the aci_current array. 149 * interrupt exit and setspl (due to soft interrupts) will cause the current 150 * ipl to be be changed. This is cache friendly as these frequently used 151 * paths write into a per cpu structure. 152 * 153 * Sampling is done by checking the structures for all CPUs and incrementing 154 * the busy field of the irq (if any) executing on each CPU and the busy field 155 * of the corresponding CPU. 156 * In periodic mode this is done on every clock interrupt. 157 * In one-shot mode, this is done thru a cyclic with an interval of 158 * apic_redistribute_sample_interval (default 10 milli sec). 159 * 160 * Every apic_sample_factor_redistribution times we sample, we do computations 161 * to decide which interrupt needs to be migrated (see comments 162 * before apic_intr_redistribute(). 163 */ 164 165 /* 166 * Following 3 variables start as % and can be patched or set using an 167 * API to be defined in future. They will be scaled to 168 * sample_factor_redistribution which is in turn set to hertz+1 (in periodic 169 * mode), or 101 in one-shot mode to stagger it away from one sec processing 170 */ 171 172 int apic_int_busy_mark = 60; 173 int apic_int_free_mark = 20; 174 int apic_diff_for_redistribution = 10; 175 176 /* sampling interval for interrupt redistribution for dynamic migration */ 177 int apic_redistribute_sample_interval = NANOSEC / 100; /* 10 millisec */ 178 179 /* 180 * number of times we sample before deciding to redistribute interrupts 181 * for dynamic migration 182 */ 183 int apic_sample_factor_redistribution = 101; 184 185 /* timeout for xlate_vector, mark_vector */ 186 int apic_revector_timeout = 16 * 10000; /* 160 millisec */ 187 188 int apic_redist_cpu_skip = 0; 189 int apic_num_imbalance = 0; 190 int apic_num_rebind = 0; 191 192 int apic_nproc = 0; 193 size_t apic_cpus_size = 0; 194 int apic_defconf = 0; 195 int apic_irq_translate = 0; 196 int apic_spec_rev = 0; 197 int apic_imcrp = 0; 198 199 int apic_use_acpi = 1; /* 1 = use ACPI, 0 = don't use ACPI */ 200 int apic_use_acpi_madt_only = 0; /* 1=ONLY use MADT from ACPI */ 201 202 /* 203 * For interrupt link devices, if apic_unconditional_srs is set, an irq resource 204 * will be assigned (via _SRS). If it is not set, use the current 205 * irq setting (via _CRS), but only if that irq is in the set of possible 206 * irqs (returned by _PRS) for the device. 207 */ 208 int apic_unconditional_srs = 1; 209 210 /* 211 * For interrupt link devices, if apic_prefer_crs is set when we are 212 * assigning an IRQ resource to a device, prefer the current IRQ setting 213 * over other possible irq settings under same conditions. 214 */ 215 216 int apic_prefer_crs = 1; 217 218 uchar_t apic_io_id[MAX_IO_APIC]; 219 volatile uint32_t *apicioadr[MAX_IO_APIC]; 220 static uchar_t apic_io_ver[MAX_IO_APIC]; 221 static uchar_t apic_io_vectbase[MAX_IO_APIC]; 222 static uchar_t apic_io_vectend[MAX_IO_APIC]; 223 uchar_t apic_reserved_irqlist[MAX_ISA_IRQ + 1]; 224 uint32_t apic_physaddr[MAX_IO_APIC]; 225 226 static boolean_t ioapic_mask_workaround[MAX_IO_APIC]; 227 228 /* 229 * First available slot to be used as IRQ index into the apic_irq_table 230 * for those interrupts (like MSI/X) that don't have a physical IRQ. 231 */ 232 int apic_first_avail_irq = APIC_FIRST_FREE_IRQ; 233 234 /* 235 * apic_ioapic_lock protects the ioapics (reg select), the status, temp_bound 236 * and bound elements of cpus_info and the temp_cpu element of irq_struct 237 */ 238 lock_t apic_ioapic_lock; 239 240 /* 241 * apic_defer_reprogram_lock ensures that only one processor is handling 242 * deferred interrupt programming at apic_intr_exit time. 243 */ 244 static lock_t apic_defer_reprogram_lock; 245 246 /* 247 * The current number of deferred reprogrammings outstanding 248 */ 249 uint_t apic_reprogram_outstanding = 0; 250 251 #ifdef DEBUG 252 /* 253 * Counters that keep track of deferred reprogramming stats 254 */ 255 uint_t apic_intr_deferrals = 0; 256 uint_t apic_intr_deliver_timeouts = 0; 257 uint_t apic_last_ditch_reprogram_failures = 0; 258 uint_t apic_deferred_setup_failures = 0; 259 uint_t apic_defer_repro_total_retries = 0; 260 uint_t apic_defer_repro_successes = 0; 261 uint_t apic_deferred_spurious_enters = 0; 262 #endif 263 264 static int apic_io_max = 0; /* no. of i/o apics enabled */ 265 266 static struct apic_io_intr *apic_io_intrp = 0; 267 static struct apic_bus *apic_busp; 268 269 uchar_t apic_vector_to_irq[APIC_MAX_VECTOR+1]; 270 uchar_t apic_resv_vector[MAXIPL+1]; 271 272 char apic_level_intr[APIC_MAX_VECTOR+1]; 273 274 static uint32_t eisa_level_intr_mask = 0; 275 /* At least MSB will be set if EISA bus */ 276 277 static int apic_pci_bus_total = 0; 278 static uchar_t apic_single_pci_busid = 0; 279 280 /* 281 * airq_mutex protects additions to the apic_irq_table - the first 282 * pointer and any airq_nexts off of that one. It also protects 283 * apic_max_device_irq & apic_min_device_irq. It also guarantees 284 * that share_id is unique as new ids are generated only when new 285 * irq_t structs are linked in. Once linked in the structs are never 286 * deleted. temp_cpu & mps_intr_index field indicate if it is programmed 287 * or allocated. Note that there is a slight gap between allocating in 288 * apic_introp_xlate and programming in addspl. 289 */ 290 kmutex_t airq_mutex; 291 apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1]; 292 int apic_max_device_irq = 0; 293 int apic_min_device_irq = APIC_MAX_VECTOR; 294 295 /* 296 * Following declarations are for revectoring; used when ISRs at different 297 * IPLs share an irq. 298 */ 299 static lock_t apic_revector_lock; 300 int apic_revector_pending = 0; 301 static uchar_t *apic_oldvec_to_newvec; 302 static uchar_t *apic_newvec_to_oldvec; 303 304 typedef struct prs_irq_list_ent { 305 int list_prio; 306 int32_t irq; 307 iflag_t intrflags; 308 acpi_prs_private_t prsprv; 309 struct prs_irq_list_ent *next; 310 } prs_irq_list_t; 311 312 313 /* 314 * ACPI variables 315 */ 316 /* 1 = acpi is enabled & working, 0 = acpi is not enabled or not there */ 317 int apic_enable_acpi = 0; 318 319 /* ACPI Multiple APIC Description Table ptr */ 320 static MULTIPLE_APIC_TABLE *acpi_mapic_dtp = NULL; 321 322 /* ACPI Interrupt Source Override Structure ptr */ 323 static MADT_INTERRUPT_OVERRIDE *acpi_isop = NULL; 324 static int acpi_iso_cnt = 0; 325 326 /* ACPI Non-maskable Interrupt Sources ptr */ 327 static MADT_NMI_SOURCE *acpi_nmi_sp = NULL; 328 static int acpi_nmi_scnt = 0; 329 static MADT_LOCAL_APIC_NMI *acpi_nmi_cp = NULL; 330 static int acpi_nmi_ccnt = 0; 331 332 extern int apic_pci_msi_enable_vector(dev_info_t *, int, int, 333 int, int, int); 334 extern apic_irq_t *apic_find_irq(dev_info_t *, struct intrspec *, int); 335 336 /* 337 * The following added to identify a software poweroff method if available. 338 */ 339 340 static struct { 341 int poweroff_method; 342 char oem_id[APIC_MPS_OEM_ID_LEN + 1]; /* MAX + 1 for NULL */ 343 char prod_id[APIC_MPS_PROD_ID_LEN + 1]; /* MAX + 1 for NULL */ 344 } apic_mps_ids[] = { 345 { APIC_POWEROFF_VIA_RTC, "INTEL", "ALDER" }, /* 4300 */ 346 { APIC_POWEROFF_VIA_RTC, "NCR", "AMC" }, /* 4300 */ 347 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "A450NX" }, /* 4400? */ 348 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AD450NX" }, /* 4400 */ 349 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AC450NX" }, /* 4400R */ 350 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "S450NX" }, /* S50 */ 351 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "SC450NX" } /* S50? */ 352 }; 353 354 int apic_poweroff_method = APIC_POWEROFF_NONE; 355 356 /* 357 * Auto-configuration routines 358 */ 359 360 /* 361 * Look at MPSpec 1.4 (Intel Order # 242016-005) for details of what we do here 362 * May work with 1.1 - but not guaranteed. 363 * According to the MP Spec, the MP floating pointer structure 364 * will be searched in the order described below: 365 * 1. In the first kilobyte of Extended BIOS Data Area (EBDA) 366 * 2. Within the last kilobyte of system base memory 367 * 3. In the BIOS ROM address space between 0F0000h and 0FFFFh 368 * Once we find the right signature with proper checksum, we call 369 * either handle_defconf or parse_mpct to get all info necessary for 370 * subsequent operations. 371 */ 372 int 373 apic_probe_common(char *modname) 374 { 375 uint32_t mpct_addr, ebda_start = 0, base_mem_end; 376 caddr_t biosdatap; 377 caddr_t mpct; 378 caddr_t fptr; 379 int i, mpct_size, mapsize, retval = PSM_FAILURE; 380 ushort_t ebda_seg, base_mem_size; 381 struct apic_mpfps_hdr *fpsp; 382 struct apic_mp_cnf_hdr *hdrp; 383 int bypass_cpu_and_ioapics_in_mptables; 384 int acpi_user_options; 385 386 if (apic_forceload < 0) 387 return (retval); 388 389 /* 390 * Remember who we are 391 */ 392 psm_name = modname; 393 394 /* Allow override for MADT-only mode */ 395 acpi_user_options = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_root_node(), 0, 396 "acpi-user-options", 0); 397 apic_use_acpi_madt_only = ((acpi_user_options & ACPI_OUSER_MADT) != 0); 398 399 /* Allow apic_use_acpi to override MADT-only mode */ 400 if (!apic_use_acpi) 401 apic_use_acpi_madt_only = 0; 402 403 retval = acpi_probe(modname); 404 405 /* 406 * mapin the bios data area 40:0 407 * 40:13h - two-byte location reports the base memory size 408 * 40:0Eh - two-byte location for the exact starting address of 409 * the EBDA segment for EISA 410 */ 411 biosdatap = psm_map_phys(0x400, 0x20, PROT_READ); 412 if (!biosdatap) 413 return (retval); 414 fpsp = (struct apic_mpfps_hdr *)NULL; 415 mapsize = MPFPS_RAM_WIN_LEN; 416 /*LINTED: pointer cast may result in improper alignment */ 417 ebda_seg = *((ushort_t *)(biosdatap+0xe)); 418 /* check the 1k of EBDA */ 419 if (ebda_seg) { 420 ebda_start = ((uint32_t)ebda_seg) << 4; 421 fptr = psm_map_phys(ebda_start, MPFPS_RAM_WIN_LEN, PROT_READ); 422 if (fptr) { 423 if (!(fpsp = 424 apic_find_fps_sig(fptr, MPFPS_RAM_WIN_LEN))) 425 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN); 426 } 427 } 428 /* If not in EBDA, check the last k of system base memory */ 429 if (!fpsp) { 430 /*LINTED: pointer cast may result in improper alignment */ 431 base_mem_size = *((ushort_t *)(biosdatap + 0x13)); 432 433 if (base_mem_size > 512) 434 base_mem_end = 639 * 1024; 435 else 436 base_mem_end = 511 * 1024; 437 /* if ebda == last k of base mem, skip to check BIOS ROM */ 438 if (base_mem_end != ebda_start) { 439 440 fptr = psm_map_phys(base_mem_end, MPFPS_RAM_WIN_LEN, 441 PROT_READ); 442 443 if (fptr) { 444 if (!(fpsp = apic_find_fps_sig(fptr, 445 MPFPS_RAM_WIN_LEN))) 446 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN); 447 } 448 } 449 } 450 psm_unmap_phys(biosdatap, 0x20); 451 452 /* If still cannot find it, check the BIOS ROM space */ 453 if (!fpsp) { 454 mapsize = MPFPS_ROM_WIN_LEN; 455 fptr = psm_map_phys(MPFPS_ROM_WIN_START, 456 MPFPS_ROM_WIN_LEN, PROT_READ); 457 if (fptr) { 458 if (!(fpsp = 459 apic_find_fps_sig(fptr, MPFPS_ROM_WIN_LEN))) { 460 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 461 return (retval); 462 } 463 } 464 } 465 466 if (apic_checksum((caddr_t)fpsp, fpsp->mpfps_length * 16) != 0) { 467 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 468 return (retval); 469 } 470 471 apic_spec_rev = fpsp->mpfps_spec_rev; 472 if ((apic_spec_rev != 04) && (apic_spec_rev != 01)) { 473 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 474 return (retval); 475 } 476 477 /* check IMCR is present or not */ 478 apic_imcrp = fpsp->mpfps_featinfo2 & MPFPS_FEATINFO2_IMCRP; 479 480 /* check default configuration (dual CPUs) */ 481 if ((apic_defconf = fpsp->mpfps_featinfo1) != 0) { 482 psm_unmap_phys(fptr, mapsize); 483 return (apic_handle_defconf()); 484 } 485 486 /* MP Configuration Table */ 487 mpct_addr = (uint32_t)(fpsp->mpfps_mpct_paddr); 488 489 psm_unmap_phys(fptr, mapsize); /* unmap floating ptr struct */ 490 491 /* 492 * Map in enough memory for the MP Configuration Table Header. 493 * Use this table to read the total length of the BIOS data and 494 * map in all the info 495 */ 496 /*LINTED: pointer cast may result in improper alignment */ 497 hdrp = (struct apic_mp_cnf_hdr *)psm_map_phys(mpct_addr, 498 sizeof (struct apic_mp_cnf_hdr), PROT_READ); 499 if (!hdrp) 500 return (retval); 501 502 /* check mp configuration table signature PCMP */ 503 if (hdrp->mpcnf_sig != 0x504d4350) { 504 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr)); 505 return (retval); 506 } 507 mpct_size = (int)hdrp->mpcnf_tbl_length; 508 509 apic_set_pwroff_method_from_mpcnfhdr(hdrp); 510 511 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr)); 512 513 if ((retval == PSM_SUCCESS) && !apic_use_acpi_madt_only) { 514 /* This is an ACPI machine No need for further checks */ 515 return (retval); 516 } 517 518 /* 519 * Map in the entries for this machine, ie. Processor 520 * Entry Tables, Bus Entry Tables, etc. 521 * They are in fixed order following one another 522 */ 523 mpct = psm_map_phys(mpct_addr, mpct_size, PROT_READ); 524 if (!mpct) 525 return (retval); 526 527 if (apic_checksum(mpct, mpct_size) != 0) 528 goto apic_fail1; 529 530 531 /*LINTED: pointer cast may result in improper alignment */ 532 hdrp = (struct apic_mp_cnf_hdr *)mpct; 533 apicadr = (uint32_t *)mapin_apic((uint32_t)hdrp->mpcnf_local_apic, 534 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE); 535 if (!apicadr) 536 goto apic_fail1; 537 538 /* Parse all information in the tables */ 539 bypass_cpu_and_ioapics_in_mptables = (retval == PSM_SUCCESS); 540 if (apic_parse_mpct(mpct, bypass_cpu_and_ioapics_in_mptables) == 541 PSM_SUCCESS) 542 return (PSM_SUCCESS); 543 544 for (i = 0; i < apic_io_max; i++) 545 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN); 546 if (apic_cpus) 547 kmem_free(apic_cpus, apic_cpus_size); 548 if (apicadr) 549 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 550 apic_fail1: 551 psm_unmap_phys(mpct, mpct_size); 552 return (retval); 553 } 554 555 static void 556 apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp) 557 { 558 int i; 559 560 for (i = 0; i < (sizeof (apic_mps_ids) / sizeof (apic_mps_ids[0])); 561 i++) { 562 if ((strncmp(hdrp->mpcnf_oem_str, apic_mps_ids[i].oem_id, 563 strlen(apic_mps_ids[i].oem_id)) == 0) && 564 (strncmp(hdrp->mpcnf_prod_str, apic_mps_ids[i].prod_id, 565 strlen(apic_mps_ids[i].prod_id)) == 0)) { 566 567 apic_poweroff_method = apic_mps_ids[i].poweroff_method; 568 break; 569 } 570 } 571 572 if (apic_debug_mps_id != 0) { 573 cmn_err(CE_CONT, "%s: MPS OEM ID = '%c%c%c%c%c%c%c%c'" 574 "Product ID = '%c%c%c%c%c%c%c%c%c%c%c%c'\n", 575 psm_name, 576 hdrp->mpcnf_oem_str[0], 577 hdrp->mpcnf_oem_str[1], 578 hdrp->mpcnf_oem_str[2], 579 hdrp->mpcnf_oem_str[3], 580 hdrp->mpcnf_oem_str[4], 581 hdrp->mpcnf_oem_str[5], 582 hdrp->mpcnf_oem_str[6], 583 hdrp->mpcnf_oem_str[7], 584 hdrp->mpcnf_prod_str[0], 585 hdrp->mpcnf_prod_str[1], 586 hdrp->mpcnf_prod_str[2], 587 hdrp->mpcnf_prod_str[3], 588 hdrp->mpcnf_prod_str[4], 589 hdrp->mpcnf_prod_str[5], 590 hdrp->mpcnf_prod_str[6], 591 hdrp->mpcnf_prod_str[7], 592 hdrp->mpcnf_prod_str[8], 593 hdrp->mpcnf_prod_str[9], 594 hdrp->mpcnf_prod_str[10], 595 hdrp->mpcnf_prod_str[11]); 596 } 597 } 598 599 static int 600 acpi_probe(char *modname) 601 { 602 int i, intmax, index, rv; 603 uint32_t id, ver; 604 int acpi_verboseflags = 0; 605 int madt_seen, madt_size; 606 APIC_HEADER *ap; 607 MADT_PROCESSOR_APIC *mpa; 608 MADT_IO_APIC *mia; 609 MADT_IO_SAPIC *misa; 610 MADT_INTERRUPT_OVERRIDE *mio; 611 MADT_NMI_SOURCE *mns; 612 MADT_INTERRUPT_SOURCE *mis; 613 MADT_LOCAL_APIC_NMI *mlan; 614 MADT_ADDRESS_OVERRIDE *mao; 615 ACPI_OBJECT_LIST arglist; 616 ACPI_OBJECT arg; 617 int sci; 618 iflag_t sci_flags; 619 volatile uint32_t *ioapic; 620 int apic_ix; 621 char local_ids[NCPU]; 622 char proc_ids[NCPU]; 623 uchar_t hid; 624 625 if (!apic_use_acpi) 626 return (PSM_FAILURE); 627 628 if (AcpiGetFirmwareTable(APIC_SIG, 1, ACPI_LOGICAL_ADDRESSING, 629 (ACPI_TABLE_HEADER **) &acpi_mapic_dtp) != AE_OK) 630 return (PSM_FAILURE); 631 632 apicadr = mapin_apic((uint32_t)acpi_mapic_dtp->LocalApicAddress, 633 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE); 634 if (!apicadr) 635 return (PSM_FAILURE); 636 637 id = apicadr[APIC_LID_REG]; 638 local_ids[0] = (uchar_t)(id >> 24); 639 apic_nproc = index = 1; 640 CPUSET_ONLY(apic_cpumask, 0); 641 apic_io_max = 0; 642 643 ap = (APIC_HEADER *) (acpi_mapic_dtp + 1); 644 madt_size = acpi_mapic_dtp->Length; 645 madt_seen = sizeof (*acpi_mapic_dtp); 646 647 while (madt_seen < madt_size) { 648 switch (ap->Type) { 649 case APIC_PROCESSOR: 650 mpa = (MADT_PROCESSOR_APIC *) ap; 651 if (mpa->ProcessorEnabled) { 652 if (mpa->LocalApicId == local_ids[0]) 653 proc_ids[0] = mpa->ProcessorId; 654 else if (apic_nproc < NCPU) { 655 local_ids[index] = mpa->LocalApicId; 656 proc_ids[index] = mpa->ProcessorId; 657 CPUSET_ADD(apic_cpumask, index); 658 index++; 659 apic_nproc++; 660 } else 661 cmn_err(CE_WARN, "%s: exceeded " 662 "maximum no. of CPUs (= %d)", 663 psm_name, NCPU); 664 } 665 break; 666 667 case APIC_IO: 668 mia = (MADT_IO_APIC *) ap; 669 if (apic_io_max < MAX_IO_APIC) { 670 apic_ix = apic_io_max; 671 apic_io_id[apic_io_max] = mia->IoApicId; 672 apic_io_vectbase[apic_io_max] = 673 mia->Interrupt; 674 apic_physaddr[apic_io_max] = 675 (uint32_t)mia->Address; 676 ioapic = apicioadr[apic_io_max] = 677 mapin_ioapic((uint32_t)mia->Address, 678 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 679 if (!ioapic) 680 goto cleanup; 681 ioapic_mask_workaround[apic_io_max] = 682 apic_is_ioapic_AMD_813x(mia->Address); 683 apic_io_max++; 684 } 685 break; 686 687 case APIC_XRUPT_OVERRIDE: 688 mio = (MADT_INTERRUPT_OVERRIDE *) ap; 689 if (acpi_isop == NULL) 690 acpi_isop = mio; 691 acpi_iso_cnt++; 692 break; 693 694 case APIC_NMI: 695 /* UNIMPLEMENTED */ 696 mns = (MADT_NMI_SOURCE *) ap; 697 if (acpi_nmi_sp == NULL) 698 acpi_nmi_sp = mns; 699 acpi_nmi_scnt++; 700 701 cmn_err(CE_NOTE, "!apic: nmi source: %d %d %d\n", 702 mns->Interrupt, mns->Polarity, 703 mns->TriggerMode); 704 break; 705 706 case APIC_LOCAL_NMI: 707 /* UNIMPLEMENTED */ 708 mlan = (MADT_LOCAL_APIC_NMI *) ap; 709 if (acpi_nmi_cp == NULL) 710 acpi_nmi_cp = mlan; 711 acpi_nmi_ccnt++; 712 713 cmn_err(CE_NOTE, "!apic: local nmi: %d %d %d %d\n", 714 mlan->ProcessorId, mlan->Polarity, 715 mlan->TriggerMode, mlan->Lint); 716 break; 717 718 case APIC_ADDRESS_OVERRIDE: 719 /* UNIMPLEMENTED */ 720 mao = (MADT_ADDRESS_OVERRIDE *) ap; 721 cmn_err(CE_NOTE, "!apic: address override: %lx\n", 722 (long)mao->Address); 723 break; 724 725 case APIC_IO_SAPIC: 726 /* UNIMPLEMENTED */ 727 misa = (MADT_IO_SAPIC *) ap; 728 729 cmn_err(CE_NOTE, "!apic: io sapic: %d %d %lx\n", 730 misa->IoSapicId, misa->InterruptBase, 731 (long)misa->Address); 732 break; 733 734 case APIC_XRUPT_SOURCE: 735 /* UNIMPLEMENTED */ 736 mis = (MADT_INTERRUPT_SOURCE *) ap; 737 738 cmn_err(CE_NOTE, 739 "!apic: irq source: %d %d %d %d %d %d %d\n", 740 mis->ProcessorId, mis->ProcessorEid, 741 mis->Interrupt, mis->Polarity, 742 mis->TriggerMode, mis->InterruptType, 743 mis->IoSapicVector); 744 break; 745 default: 746 break; 747 } 748 749 /* advance to next entry */ 750 madt_seen += ap->Length; 751 ap = (APIC_HEADER *)(((char *)ap) + ap->Length); 752 } 753 754 apic_cpus_size = apic_nproc * sizeof (*apic_cpus); 755 if ((apic_cpus = kmem_zalloc(apic_cpus_size, KM_NOSLEEP)) == NULL) 756 goto cleanup; 757 758 /* 759 * ACPI doesn't provide the local apic ver, get it directly from the 760 * local apic 761 */ 762 ver = apicadr[APIC_VERS_REG]; 763 for (i = 0; i < apic_nproc; i++) { 764 apic_cpus[i].aci_local_id = local_ids[i]; 765 apic_cpus[i].aci_local_ver = (uchar_t)(ver & 0xFF); 766 } 767 for (i = 0; i < apic_io_max; i++) { 768 apic_ix = i; 769 770 /* 771 * need to check Sitka on the following acpi problem 772 * On the Sitka, the ioapic's apic_id field isn't reporting 773 * the actual io apic id. We have reported this problem 774 * to Intel. Until they fix the problem, we will get the 775 * actual id directly from the ioapic. 776 */ 777 id = ioapic_read(apic_ix, APIC_ID_CMD); 778 hid = (uchar_t)(id >> 24); 779 780 if (hid != apic_io_id[i]) { 781 if (apic_io_id[i] == 0) 782 apic_io_id[i] = hid; 783 else { /* set ioapic id to whatever reported by ACPI */ 784 id = ((uint32_t)apic_io_id[i]) << 24; 785 ioapic_write(apic_ix, APIC_ID_CMD, id); 786 } 787 } 788 ver = ioapic_read(apic_ix, APIC_VERS_CMD); 789 apic_io_ver[i] = (uchar_t)(ver & 0xff); 790 intmax = (ver >> 16) & 0xff; 791 apic_io_vectend[i] = apic_io_vectbase[i] + intmax; 792 if (apic_first_avail_irq <= apic_io_vectend[i]) 793 apic_first_avail_irq = apic_io_vectend[i] + 1; 794 } 795 796 797 /* 798 * Process SCI configuration here 799 * An error may be returned here if 800 * acpi-user-options specifies legacy mode 801 * (no SCI, no ACPI mode) 802 */ 803 if (acpica_get_sci(&sci, &sci_flags) != AE_OK) 804 sci = -1; 805 806 /* 807 * Now call acpi_init() to generate namespaces 808 * If this fails, we don't attempt to use ACPI 809 * even if we were able to get a MADT above 810 */ 811 if (acpica_init() != AE_OK) 812 goto cleanup; 813 814 /* 815 * Squirrel away the SCI and flags for later on 816 * in apic_picinit() when we're ready 817 */ 818 apic_sci_vect = sci; 819 apic_sci_flags = sci_flags; 820 821 if (apic_verbose & APIC_VERBOSE_IRQ_FLAG) 822 acpi_verboseflags |= PSM_VERBOSE_IRQ_FLAG; 823 824 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) 825 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_FLAG; 826 827 if (apic_verbose & APIC_VERBOSE_POWEROFF_PAUSE_FLAG) 828 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_PAUSE_FLAG; 829 830 if (acpi_psm_init(modname, acpi_verboseflags) == ACPI_PSM_FAILURE) 831 goto cleanup; 832 833 /* Enable ACPI APIC interrupt routing */ 834 arglist.Count = 1; 835 arglist.Pointer = &arg; 836 arg.Type = ACPI_TYPE_INTEGER; 837 arg.Integer.Value = ACPI_APIC_MODE; /* 1 */ 838 rv = AcpiEvaluateObject(NULL, "\\_PIC", &arglist, NULL); 839 if (rv == AE_OK) { 840 build_reserved_irqlist((uchar_t *)apic_reserved_irqlist); 841 apic_enable_acpi = 1; 842 if (apic_use_acpi_madt_only) { 843 cmn_err(CE_CONT, 844 "?Using ACPI for CPU/IOAPIC information ONLY\n"); 845 } 846 return (PSM_SUCCESS); 847 } 848 /* if setting APIC mode failed above, we fall through to cleanup */ 849 850 cleanup: 851 if (apicadr != NULL) { 852 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 853 apicadr = NULL; 854 } 855 apic_nproc = 0; 856 for (i = 0; i < apic_io_max; i++) { 857 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN); 858 apicioadr[i] = NULL; 859 } 860 apic_io_max = 0; 861 acpi_isop = NULL; 862 acpi_iso_cnt = 0; 863 acpi_nmi_sp = NULL; 864 acpi_nmi_scnt = 0; 865 acpi_nmi_cp = NULL; 866 acpi_nmi_ccnt = 0; 867 return (PSM_FAILURE); 868 } 869 870 /* 871 * Handle default configuration. Fill in reqd global variables & tables 872 * Fill all details as MP table does not give any more info 873 */ 874 static int 875 apic_handle_defconf() 876 { 877 uint_t lid; 878 879 /*LINTED: pointer cast may result in improper alignment */ 880 apicioadr[0] = mapin_ioapic(APIC_IO_ADDR, 881 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 882 /*LINTED: pointer cast may result in improper alignment */ 883 apicadr = (uint32_t *)psm_map_phys(APIC_LOCAL_ADDR, 884 APIC_LOCAL_MEMLEN, PROT_READ); 885 apic_cpus_size = 2 * sizeof (*apic_cpus); 886 apic_cpus = (apic_cpus_info_t *) 887 kmem_zalloc(apic_cpus_size, KM_NOSLEEP); 888 if ((!apicadr) || (!apicioadr[0]) || (!apic_cpus)) 889 goto apic_handle_defconf_fail; 890 CPUSET_ONLY(apic_cpumask, 0); 891 CPUSET_ADD(apic_cpumask, 1); 892 apic_nproc = 2; 893 lid = apicadr[APIC_LID_REG]; 894 apic_cpus[0].aci_local_id = (uchar_t)(lid >> APIC_ID_BIT_OFFSET); 895 /* 896 * According to the PC+MP spec 1.1, the local ids 897 * for the default configuration has to be 0 or 1 898 */ 899 if (apic_cpus[0].aci_local_id == 1) 900 apic_cpus[1].aci_local_id = 0; 901 else if (apic_cpus[0].aci_local_id == 0) 902 apic_cpus[1].aci_local_id = 1; 903 else 904 goto apic_handle_defconf_fail; 905 906 apic_io_id[0] = 2; 907 apic_io_max = 1; 908 if (apic_defconf >= 5) { 909 apic_cpus[0].aci_local_ver = APIC_INTEGRATED_VERS; 910 apic_cpus[1].aci_local_ver = APIC_INTEGRATED_VERS; 911 apic_io_ver[0] = APIC_INTEGRATED_VERS; 912 } else { 913 apic_cpus[0].aci_local_ver = 0; /* 82489 DX */ 914 apic_cpus[1].aci_local_ver = 0; 915 apic_io_ver[0] = 0; 916 } 917 if (apic_defconf == 2 || apic_defconf == 3 || apic_defconf == 6) 918 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) | 919 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1); 920 return (PSM_SUCCESS); 921 922 apic_handle_defconf_fail: 923 if (apic_cpus) 924 kmem_free(apic_cpus, apic_cpus_size); 925 if (apicadr) 926 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 927 if (apicioadr[0]) 928 mapout_ioapic((caddr_t)apicioadr[0], APIC_IO_MEMLEN); 929 return (PSM_FAILURE); 930 } 931 932 /* Parse the entries in MP configuration table and collect info that we need */ 933 static int 934 apic_parse_mpct(caddr_t mpct, int bypass_cpus_and_ioapics) 935 { 936 struct apic_procent *procp; 937 struct apic_bus *busp; 938 struct apic_io_entry *ioapicp; 939 struct apic_io_intr *intrp; 940 int apic_ix; 941 uint_t lid; 942 uint32_t id; 943 uchar_t hid; 944 945 /*LINTED: pointer cast may result in improper alignment */ 946 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr)); 947 948 /* No need to count cpu entries if we won't use them */ 949 if (!bypass_cpus_and_ioapics) { 950 951 /* Find max # of CPUS and allocate structure accordingly */ 952 apic_nproc = 0; 953 CPUSET_ZERO(apic_cpumask); 954 while (procp->proc_entry == APIC_CPU_ENTRY) { 955 if (procp->proc_cpuflags & CPUFLAGS_EN) { 956 if (apic_nproc < NCPU) 957 CPUSET_ADD(apic_cpumask, apic_nproc); 958 apic_nproc++; 959 } 960 procp++; 961 } 962 if (apic_nproc > NCPU) 963 cmn_err(CE_WARN, "%s: exceeded " 964 "maximum no. of CPUs (= %d)", psm_name, NCPU); 965 apic_cpus_size = apic_nproc * sizeof (*apic_cpus); 966 if (!apic_nproc || !(apic_cpus = (apic_cpus_info_t *) 967 kmem_zalloc(apic_cpus_size, KM_NOSLEEP))) 968 return (PSM_FAILURE); 969 } 970 971 /*LINTED: pointer cast may result in improper alignment */ 972 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr)); 973 974 /* 975 * start with index 1 as 0 needs to be filled in with Boot CPU, but 976 * if we're bypassing this information, it has already been filled 977 * in by acpi_probe(), so don't overwrite it. 978 */ 979 if (!bypass_cpus_and_ioapics) 980 apic_nproc = 1; 981 982 while (procp->proc_entry == APIC_CPU_ENTRY) { 983 /* check whether the cpu exists or not */ 984 if (!bypass_cpus_and_ioapics && 985 procp->proc_cpuflags & CPUFLAGS_EN) { 986 if (procp->proc_cpuflags & CPUFLAGS_BP) { /* Boot CPU */ 987 lid = apicadr[APIC_LID_REG]; 988 apic_cpus[0].aci_local_id = procp->proc_apicid; 989 if (apic_cpus[0].aci_local_id != 990 (uchar_t)(lid >> APIC_ID_BIT_OFFSET)) { 991 return (PSM_FAILURE); 992 } 993 apic_cpus[0].aci_local_ver = 994 procp->proc_version; 995 } else { 996 997 apic_cpus[apic_nproc].aci_local_id = 998 procp->proc_apicid; 999 apic_cpus[apic_nproc].aci_local_ver = 1000 procp->proc_version; 1001 apic_nproc++; 1002 1003 } 1004 } 1005 procp++; 1006 } 1007 1008 /* 1009 * Save start of bus entries for later use. 1010 * Get EISA level cntrl if EISA bus is present. 1011 * Also get the CPI bus id for single CPI bus case 1012 */ 1013 apic_busp = busp = (struct apic_bus *)procp; 1014 while (busp->bus_entry == APIC_BUS_ENTRY) { 1015 lid = apic_find_bus_type((char *)&busp->bus_str1); 1016 if (lid == BUS_EISA) { 1017 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) | 1018 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1); 1019 } else if (lid == BUS_PCI) { 1020 /* 1021 * apic_single_pci_busid will be used only if 1022 * apic_pic_bus_total is equal to 1 1023 */ 1024 apic_pci_bus_total++; 1025 apic_single_pci_busid = busp->bus_id; 1026 } 1027 busp++; 1028 } 1029 1030 ioapicp = (struct apic_io_entry *)busp; 1031 1032 if (!bypass_cpus_and_ioapics) 1033 apic_io_max = 0; 1034 do { 1035 if (!bypass_cpus_and_ioapics && apic_io_max < MAX_IO_APIC) { 1036 if (ioapicp->io_flags & IOAPIC_FLAGS_EN) { 1037 apic_io_id[apic_io_max] = ioapicp->io_apicid; 1038 apic_io_ver[apic_io_max] = ioapicp->io_version; 1039 /*LINTED: pointer cast may result in improper alignment */ 1040 apicioadr[apic_io_max] = 1041 mapin_ioapic( 1042 (uint32_t)ioapicp->io_apic_addr, 1043 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 1044 1045 if (!apicioadr[apic_io_max]) 1046 return (PSM_FAILURE); 1047 1048 ioapic_mask_workaround[apic_io_max] = 1049 apic_is_ioapic_AMD_813x( 1050 ioapicp->io_apic_addr); 1051 1052 apic_ix = apic_io_max; 1053 id = ioapic_read(apic_ix, APIC_ID_CMD); 1054 hid = (uchar_t)(id >> 24); 1055 1056 if (hid != apic_io_id[apic_io_max]) { 1057 if (apic_io_id[apic_io_max] == 0) 1058 apic_io_id[apic_io_max] = hid; 1059 else { 1060 /* 1061 * set ioapic id to whatever 1062 * reported by MPS 1063 * 1064 * may not need to set index 1065 * again ??? 1066 * take it out and try 1067 */ 1068 1069 id = ((uint32_t) 1070 apic_io_id[apic_io_max]) << 1071 24; 1072 1073 ioapic_write(apic_ix, 1074 APIC_ID_CMD, id); 1075 } 1076 } 1077 apic_io_max++; 1078 } 1079 } 1080 ioapicp++; 1081 } while (ioapicp->io_entry == APIC_IO_ENTRY); 1082 1083 apic_io_intrp = (struct apic_io_intr *)ioapicp; 1084 1085 intrp = apic_io_intrp; 1086 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 1087 if ((intrp->intr_irq > APIC_MAX_ISA_IRQ) || 1088 (apic_find_bus(intrp->intr_busid) == BUS_PCI)) { 1089 apic_irq_translate = 1; 1090 break; 1091 } 1092 intrp++; 1093 } 1094 1095 return (PSM_SUCCESS); 1096 } 1097 1098 boolean_t 1099 apic_cpu_in_range(int cpu) 1100 { 1101 return ((cpu & ~IRQ_USER_BOUND) < apic_nproc); 1102 } 1103 1104 uint16_t 1105 apic_get_apic_version() 1106 { 1107 int i; 1108 uchar_t min_io_apic_ver = 0; 1109 static uint16_t version; /* Cache as value is constant */ 1110 static boolean_t found = B_FALSE; /* Accomodate zero version */ 1111 1112 if (found == B_FALSE) { 1113 found = B_TRUE; 1114 1115 /* 1116 * Don't assume all IO APICs in the system are the same. 1117 * 1118 * Set to the minimum version. 1119 */ 1120 for (i = 0; i < apic_io_max; i++) { 1121 if ((apic_io_ver[i] != 0) && 1122 ((min_io_apic_ver == 0) || 1123 (min_io_apic_ver >= apic_io_ver[i]))) 1124 min_io_apic_ver = apic_io_ver[i]; 1125 } 1126 1127 /* Assume all local APICs are of the same version. */ 1128 version = (min_io_apic_ver << 8) | apic_cpus[0].aci_local_ver; 1129 } 1130 return (version); 1131 } 1132 1133 static struct apic_mpfps_hdr * 1134 apic_find_fps_sig(caddr_t cptr, int len) 1135 { 1136 int i; 1137 1138 /* Look for the pattern "_MP_" */ 1139 for (i = 0; i < len; i += 16) { 1140 if ((*(cptr+i) == '_') && 1141 (*(cptr+i+1) == 'M') && 1142 (*(cptr+i+2) == 'P') && 1143 (*(cptr+i+3) == '_')) 1144 /*LINTED: pointer cast may result in improper alignment */ 1145 return ((struct apic_mpfps_hdr *)(cptr + i)); 1146 } 1147 return (NULL); 1148 } 1149 1150 static int 1151 apic_checksum(caddr_t bptr, int len) 1152 { 1153 int i; 1154 uchar_t cksum; 1155 1156 cksum = 0; 1157 for (i = 0; i < len; i++) 1158 cksum += *bptr++; 1159 return ((int)cksum); 1160 } 1161 1162 1163 /* 1164 * Initialise vector->ipl and ipl->pri arrays. level_intr and irqtable 1165 * are also set to NULL. vector->irq is set to a value which cannot map 1166 * to a real irq to show that it is free. 1167 */ 1168 void 1169 apic_init_common() 1170 { 1171 int i, j, indx; 1172 int *iptr; 1173 1174 /* 1175 * Initialize apic_ipls from apic_vectortoipl. This array is 1176 * used in apic_intr_enter to determine the IPL to use for the 1177 * corresponding vector. On some systems, due to hardware errata 1178 * and interrupt sharing, the IPL may not correspond to the IPL listed 1179 * in apic_vectortoipl (see apic_addspl and apic_delspl). 1180 */ 1181 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) { 1182 indx = i * APIC_VECTOR_PER_IPL; 1183 1184 for (j = 0; j < APIC_VECTOR_PER_IPL; j++, indx++) 1185 apic_ipls[indx] = apic_vectortoipl[i]; 1186 } 1187 1188 /* cpu 0 is always up (for now) */ 1189 apic_cpus[0].aci_status = APIC_CPU_ONLINE | APIC_CPU_INTR_ENABLE; 1190 1191 iptr = (int *)&apic_irq_table[0]; 1192 for (i = 0; i <= APIC_MAX_VECTOR; i++) { 1193 apic_level_intr[i] = 0; 1194 *iptr++ = NULL; 1195 apic_vector_to_irq[i] = APIC_RESV_IRQ; 1196 1197 /* These *must* be initted to B_TRUE! */ 1198 apic_reprogram_info[i].done = B_TRUE; 1199 apic_reprogram_info[i].irqp = NULL; 1200 apic_reprogram_info[i].tries = 0; 1201 apic_reprogram_info[i].bindcpu = 0; 1202 } 1203 1204 /* 1205 * Allocate a dummy irq table entry for the reserved entry. 1206 * This takes care of the race between removing an irq and 1207 * clock detecting a CPU in that irq during interrupt load 1208 * sampling. 1209 */ 1210 apic_irq_table[APIC_RESV_IRQ] = 1211 kmem_zalloc(sizeof (apic_irq_t), KM_NOSLEEP); 1212 1213 mutex_init(&airq_mutex, NULL, MUTEX_DEFAULT, NULL); 1214 } 1215 1216 void 1217 ioapic_init_intr(int mask_apic) 1218 { 1219 int apic_ix; 1220 struct intrspec ispec; 1221 apic_irq_t *irqptr; 1222 int i, j; 1223 ulong_t iflag; 1224 1225 LOCK_INIT_CLEAR(&apic_revector_lock); 1226 LOCK_INIT_CLEAR(&apic_defer_reprogram_lock); 1227 1228 /* mask interrupt vectors */ 1229 for (j = 0; j < apic_io_max && mask_apic; j++) { 1230 int intin_max; 1231 1232 apic_ix = j; 1233 /* Bits 23-16 define the maximum redirection entries */ 1234 intin_max = (ioapic_read(apic_ix, APIC_VERS_CMD) >> 16) & 0xff; 1235 for (i = 0; i < intin_max; i++) 1236 ioapic_write(apic_ix, APIC_RDT_CMD + 2 * i, AV_MASK); 1237 } 1238 1239 /* 1240 * Hack alert: deal with ACPI SCI interrupt chicken/egg here 1241 */ 1242 if (apic_sci_vect > 0) { 1243 /* 1244 * acpica has already done add_avintr(); we just 1245 * to finish the job by mimicing translate_irq() 1246 * 1247 * Fake up an intrspec and setup the tables 1248 */ 1249 ispec.intrspec_vec = apic_sci_vect; 1250 ispec.intrspec_pri = SCI_IPL; 1251 1252 if (apic_setup_irq_table(NULL, apic_sci_vect, NULL, 1253 &ispec, &apic_sci_flags, DDI_INTR_TYPE_FIXED) < 0) { 1254 cmn_err(CE_WARN, "!apic: SCI setup failed"); 1255 return; 1256 } 1257 irqptr = apic_irq_table[apic_sci_vect]; 1258 1259 iflag = intr_clear(); 1260 lock_set(&apic_ioapic_lock); 1261 1262 /* Program I/O APIC */ 1263 (void) apic_setup_io_intr(irqptr, apic_sci_vect, B_FALSE); 1264 1265 lock_clear(&apic_ioapic_lock); 1266 intr_restore(iflag); 1267 1268 irqptr->airq_share++; 1269 } 1270 } 1271 1272 /* 1273 * Add mask bits to disable interrupt vector from happening 1274 * at or above IPL. In addition, it should remove mask bits 1275 * to enable interrupt vectors below the given IPL. 1276 * 1277 * Both add and delspl are complicated by the fact that different interrupts 1278 * may share IRQs. This can happen in two ways. 1279 * 1. The same H/W line is shared by more than 1 device 1280 * 1a. with interrupts at different IPLs 1281 * 1b. with interrupts at same IPL 1282 * 2. We ran out of vectors at a given IPL and started sharing vectors. 1283 * 1b and 2 should be handled gracefully, except for the fact some ISRs 1284 * will get called often when no interrupt is pending for the device. 1285 * For 1a, we just hope that the machine blows up with the person who 1286 * set it up that way!. In the meantime, we handle it at the higher IPL. 1287 */ 1288 /*ARGSUSED*/ 1289 int 1290 apic_addspl_common(int irqno, int ipl, int min_ipl, int max_ipl) 1291 { 1292 uchar_t vector; 1293 ulong_t iflag; 1294 apic_irq_t *irqptr, *irqheadptr; 1295 int irqindex; 1296 1297 ASSERT(max_ipl <= UCHAR_MAX); 1298 irqindex = IRQINDEX(irqno); 1299 1300 if ((irqindex == -1) || (!apic_irq_table[irqindex])) 1301 return (PSM_FAILURE); 1302 1303 mutex_enter(&airq_mutex); 1304 irqptr = irqheadptr = apic_irq_table[irqindex]; 1305 1306 DDI_INTR_IMPLDBG((CE_CONT, "apic_addspl: dip=0x%p type=%d irqno=0x%x " 1307 "vector=0x%x\n", (void *)irqptr->airq_dip, 1308 irqptr->airq_mps_intr_index, irqno, irqptr->airq_vector)); 1309 1310 while (irqptr) { 1311 if (VIRTIRQ(irqindex, irqptr->airq_share_id) == irqno) 1312 break; 1313 irqptr = irqptr->airq_next; 1314 } 1315 irqptr->airq_share++; 1316 1317 mutex_exit(&airq_mutex); 1318 1319 /* return if it is not hardware interrupt */ 1320 if (irqptr->airq_mps_intr_index == RESERVE_INDEX) 1321 return (PSM_SUCCESS); 1322 1323 /* Or if there are more interupts at a higher IPL */ 1324 if (ipl != max_ipl) 1325 return (PSM_SUCCESS); 1326 1327 /* 1328 * if apic_picinit() has not been called yet, just return. 1329 * At the end of apic_picinit(), we will call setup_io_intr(). 1330 */ 1331 1332 if (!apic_flag) 1333 return (PSM_SUCCESS); 1334 1335 /* 1336 * Upgrade vector if max_ipl is not earlier ipl. If we cannot allocate, 1337 * return failure. Not very elegant, but then we hope the 1338 * machine will blow up with ... 1339 */ 1340 if (irqptr->airq_ipl != max_ipl && 1341 !ioapic_mask_workaround[irqptr->airq_ioapicindex]) { 1342 1343 vector = apic_allocate_vector(max_ipl, irqindex, 1); 1344 if (vector == 0) { 1345 irqptr->airq_share--; 1346 return (PSM_FAILURE); 1347 } 1348 irqptr = irqheadptr; 1349 apic_mark_vector(irqptr->airq_vector, vector); 1350 while (irqptr) { 1351 irqptr->airq_vector = vector; 1352 irqptr->airq_ipl = (uchar_t)max_ipl; 1353 /* 1354 * reprogram irq being added and every one else 1355 * who is not in the UNINIT state 1356 */ 1357 if ((VIRTIRQ(irqindex, irqptr->airq_share_id) == 1358 irqno) || (irqptr->airq_temp_cpu != IRQ_UNINIT)) { 1359 apic_record_rdt_entry(irqptr, irqindex); 1360 1361 iflag = intr_clear(); 1362 lock_set(&apic_ioapic_lock); 1363 1364 (void) apic_setup_io_intr(irqptr, irqindex, 1365 B_FALSE); 1366 1367 lock_clear(&apic_ioapic_lock); 1368 intr_restore(iflag); 1369 } 1370 irqptr = irqptr->airq_next; 1371 } 1372 return (PSM_SUCCESS); 1373 1374 } else if (irqptr->airq_ipl != max_ipl && 1375 ioapic_mask_workaround[irqptr->airq_ioapicindex]) { 1376 /* 1377 * We cannot upgrade the vector, but we can change 1378 * the IPL that this vector induces. 1379 * 1380 * Note that we subtract APIC_BASE_VECT from the vector 1381 * here because this array is used in apic_intr_enter 1382 * (no need to add APIC_BASE_VECT in that hot code 1383 * path since we can do it in the rarely-executed path 1384 * here). 1385 */ 1386 apic_ipls[irqptr->airq_vector - APIC_BASE_VECT] = 1387 (uchar_t)max_ipl; 1388 1389 irqptr = irqheadptr; 1390 while (irqptr) { 1391 irqptr->airq_ipl = (uchar_t)max_ipl; 1392 irqptr = irqptr->airq_next; 1393 } 1394 1395 return (PSM_SUCCESS); 1396 } 1397 1398 ASSERT(irqptr); 1399 1400 iflag = intr_clear(); 1401 lock_set(&apic_ioapic_lock); 1402 1403 (void) apic_setup_io_intr(irqptr, irqindex, B_FALSE); 1404 1405 lock_clear(&apic_ioapic_lock); 1406 intr_restore(iflag); 1407 1408 return (PSM_SUCCESS); 1409 } 1410 1411 /* 1412 * Recompute mask bits for the given interrupt vector. 1413 * If there is no interrupt servicing routine for this 1414 * vector, this function should disable interrupt vector 1415 * from happening at all IPLs. If there are still 1416 * handlers using the given vector, this function should 1417 * disable the given vector from happening below the lowest 1418 * IPL of the remaining hadlers. 1419 */ 1420 /*ARGSUSED*/ 1421 int 1422 apic_delspl_common(int irqno, int ipl, int min_ipl, int max_ipl) 1423 { 1424 uchar_t vector, bind_cpu; 1425 int intin, irqindex; 1426 int apic_ix; 1427 apic_irq_t *irqptr, *irqheadptr, *irqp; 1428 ulong_t iflag; 1429 1430 mutex_enter(&airq_mutex); 1431 irqindex = IRQINDEX(irqno); 1432 irqptr = irqheadptr = apic_irq_table[irqindex]; 1433 1434 DDI_INTR_IMPLDBG((CE_CONT, "apic_delspl: dip=0x%p type=%d irqno=0x%x " 1435 "vector=0x%x\n", (void *)irqptr->airq_dip, 1436 irqptr->airq_mps_intr_index, irqno, irqptr->airq_vector)); 1437 1438 while (irqptr) { 1439 if (VIRTIRQ(irqindex, irqptr->airq_share_id) == irqno) 1440 break; 1441 irqptr = irqptr->airq_next; 1442 } 1443 ASSERT(irqptr); 1444 1445 irqptr->airq_share--; 1446 1447 mutex_exit(&airq_mutex); 1448 1449 if (ipl < max_ipl) 1450 return (PSM_SUCCESS); 1451 1452 /* return if it is not hardware interrupt */ 1453 if (irqptr->airq_mps_intr_index == RESERVE_INDEX) 1454 return (PSM_SUCCESS); 1455 1456 if (!apic_flag) { 1457 /* 1458 * Clear irq_struct. If two devices shared an intpt 1459 * line & 1 unloaded before picinit, we are hosed. But, then 1460 * we hope the machine will ... 1461 */ 1462 irqptr->airq_mps_intr_index = FREE_INDEX; 1463 irqptr->airq_temp_cpu = IRQ_UNINIT; 1464 apic_free_vector(irqptr->airq_vector); 1465 return (PSM_SUCCESS); 1466 } 1467 /* 1468 * Downgrade vector to new max_ipl if needed.If we cannot allocate, 1469 * use old IPL. Not very elegant, but then we hope ... 1470 */ 1471 if ((irqptr->airq_ipl != max_ipl) && (max_ipl != PSM_INVALID_IPL) && 1472 !ioapic_mask_workaround[irqptr->airq_ioapicindex]) { 1473 apic_irq_t *irqp; 1474 if (vector = apic_allocate_vector(max_ipl, irqno, 1)) { 1475 apic_mark_vector(irqheadptr->airq_vector, vector); 1476 irqp = irqheadptr; 1477 while (irqp) { 1478 irqp->airq_vector = vector; 1479 irqp->airq_ipl = (uchar_t)max_ipl; 1480 if (irqp->airq_temp_cpu != IRQ_UNINIT) { 1481 apic_record_rdt_entry(irqp, irqindex); 1482 1483 iflag = intr_clear(); 1484 lock_set(&apic_ioapic_lock); 1485 1486 (void) apic_setup_io_intr(irqp, 1487 irqindex, B_FALSE); 1488 1489 lock_clear(&apic_ioapic_lock); 1490 intr_restore(iflag); 1491 } 1492 irqp = irqp->airq_next; 1493 } 1494 } 1495 1496 } else if (irqptr->airq_ipl != max_ipl && 1497 max_ipl != PSM_INVALID_IPL && 1498 ioapic_mask_workaround[irqptr->airq_ioapicindex]) { 1499 1500 /* 1501 * We cannot downgrade the IPL of the vector below the vector's 1502 * hardware priority. If we did, it would be possible for a 1503 * higher-priority hardware vector to interrupt a CPU running at an IPL 1504 * lower than the hardware priority of the interrupting vector (but 1505 * higher than the soft IPL of this IRQ). When this happens, we would 1506 * then try to drop the IPL BELOW what it was (effectively dropping 1507 * below base_spl) which would be potentially catastrophic. 1508 * 1509 * (e.g. Suppose the hardware vector associated with this IRQ is 0x40 1510 * (hardware IPL of 4). Further assume that the old IPL of this IRQ 1511 * was 4, but the new IPL is 1. If we forced vector 0x40 to result in 1512 * an IPL of 1, it would be possible for the processor to be executing 1513 * at IPL 3 and for an interrupt to come in on vector 0x40, interrupting 1514 * the currently-executing ISR. When apic_intr_enter consults 1515 * apic_irqs[], it will return 1, bringing the IPL of the CPU down to 1 1516 * so even though the processor was running at IPL 4, an IPL 1 1517 * interrupt will have interrupted it, which must not happen)). 1518 * 1519 * Effectively, this means that the hardware priority corresponding to 1520 * the IRQ's IPL (in apic_ipls[]) cannot be lower than the vector's 1521 * hardware priority. 1522 * 1523 * (In the above example, then, after removal of the IPL 4 device's 1524 * interrupt handler, the new IPL will continue to be 4 because the 1525 * hardware priority that IPL 1 implies is lower than the hardware 1526 * priority of the vector used.) 1527 */ 1528 /* apic_ipls is indexed by vector, starting at APIC_BASE_VECT */ 1529 const int apic_ipls_index = irqptr->airq_vector - 1530 APIC_BASE_VECT; 1531 const int vect_inherent_hwpri = irqptr->airq_vector >> 1532 APIC_IPL_SHIFT; 1533 1534 /* 1535 * If there are still devices using this IRQ, determine the 1536 * new ipl to use. 1537 */ 1538 if (irqptr->airq_share) { 1539 int vect_desired_hwpri, hwpri; 1540 1541 ASSERT(max_ipl < MAXIPL); 1542 vect_desired_hwpri = apic_ipltopri[max_ipl] >> 1543 APIC_IPL_SHIFT; 1544 1545 /* 1546 * If the desired IPL's hardware priority is lower 1547 * than that of the vector, use the hardware priority 1548 * of the vector to determine the new IPL. 1549 */ 1550 hwpri = (vect_desired_hwpri < vect_inherent_hwpri) ? 1551 vect_inherent_hwpri : vect_desired_hwpri; 1552 1553 /* 1554 * Now, to get the right index for apic_vectortoipl, 1555 * we need to subtract APIC_BASE_VECT from the 1556 * hardware-vector-equivalent (in hwpri). Since hwpri 1557 * is already shifted, we shift APIC_BASE_VECT before 1558 * doing the subtraction. 1559 */ 1560 hwpri -= (APIC_BASE_VECT >> APIC_IPL_SHIFT); 1561 1562 ASSERT(hwpri >= 0); 1563 ASSERT(hwpri < MAXIPL); 1564 max_ipl = apic_vectortoipl[hwpri]; 1565 apic_ipls[apic_ipls_index] = max_ipl; 1566 1567 irqp = irqheadptr; 1568 while (irqp) { 1569 irqp->airq_ipl = (uchar_t)max_ipl; 1570 irqp = irqp->airq_next; 1571 } 1572 } else { 1573 /* 1574 * No more devices on this IRQ, so reset this vector's 1575 * element in apic_ipls to the original IPL for this 1576 * vector 1577 */ 1578 apic_ipls[apic_ipls_index] = 1579 apic_vectortoipl[vect_inherent_hwpri]; 1580 } 1581 } 1582 1583 if (irqptr->airq_share) 1584 return (PSM_SUCCESS); 1585 1586 iflag = intr_clear(); 1587 lock_set(&apic_ioapic_lock); 1588 1589 /* Disable the MSI/X vector */ 1590 if (APIC_IS_MSI_OR_MSIX_INDEX(irqptr->airq_mps_intr_index)) { 1591 int type = (irqptr->airq_mps_intr_index == MSI_INDEX) ? 1592 DDI_INTR_TYPE_MSI : DDI_INTR_TYPE_MSIX; 1593 1594 /* 1595 * Make sure we only disable on the last 1596 * of the multi-MSI support 1597 */ 1598 if (i_ddi_intr_get_current_nintrs(irqptr->airq_dip) == 1) { 1599 (void) apic_pci_msi_unconfigure(irqptr->airq_dip, 1600 type, irqptr->airq_ioapicindex); 1601 1602 (void) apic_pci_msi_disable_mode(irqptr->airq_dip, 1603 type, irqptr->airq_ioapicindex); 1604 } 1605 } else { 1606 /* 1607 * The assumption here is that this is safe, even for 1608 * systems with IOAPICs that suffer from the hardware 1609 * erratum because all devices have been quiesced before 1610 * they unregister their interrupt handlers. If that 1611 * assumption turns out to be false, this mask operation 1612 * can induce the same erratum result we're trying to 1613 * avoid. 1614 */ 1615 apic_ix = irqptr->airq_ioapicindex; 1616 intin = irqptr->airq_intin_no; 1617 ioapic_write(apic_ix, APIC_RDT_CMD + 2 * intin, AV_MASK); 1618 } 1619 1620 if (max_ipl == PSM_INVALID_IPL) { 1621 ASSERT(irqheadptr == irqptr); 1622 bind_cpu = irqptr->airq_temp_cpu; 1623 if (((uchar_t)bind_cpu != IRQ_UNBOUND) && 1624 ((uchar_t)bind_cpu != IRQ_UNINIT)) { 1625 ASSERT((bind_cpu & ~IRQ_USER_BOUND) < apic_nproc); 1626 if (bind_cpu & IRQ_USER_BOUND) { 1627 /* If hardbound, temp_cpu == cpu */ 1628 bind_cpu &= ~IRQ_USER_BOUND; 1629 apic_cpus[bind_cpu].aci_bound--; 1630 } else 1631 apic_cpus[bind_cpu].aci_temp_bound--; 1632 } 1633 irqptr->airq_temp_cpu = IRQ_UNINIT; 1634 irqptr->airq_mps_intr_index = FREE_INDEX; 1635 lock_clear(&apic_ioapic_lock); 1636 intr_restore(iflag); 1637 apic_free_vector(irqptr->airq_vector); 1638 return (PSM_SUCCESS); 1639 } 1640 lock_clear(&apic_ioapic_lock); 1641 intr_restore(iflag); 1642 1643 mutex_enter(&airq_mutex); 1644 if ((irqptr == apic_irq_table[irqindex])) { 1645 apic_irq_t *oldirqptr; 1646 /* Move valid irq entry to the head */ 1647 irqheadptr = oldirqptr = irqptr; 1648 irqptr = irqptr->airq_next; 1649 ASSERT(irqptr); 1650 while (irqptr) { 1651 if (irqptr->airq_mps_intr_index != FREE_INDEX) 1652 break; 1653 oldirqptr = irqptr; 1654 irqptr = irqptr->airq_next; 1655 } 1656 /* remove all invalid ones from the beginning */ 1657 apic_irq_table[irqindex] = irqptr; 1658 /* 1659 * and link them back after the head. The invalid ones 1660 * begin with irqheadptr and end at oldirqptr 1661 */ 1662 oldirqptr->airq_next = irqptr->airq_next; 1663 irqptr->airq_next = irqheadptr; 1664 } 1665 mutex_exit(&airq_mutex); 1666 1667 irqptr->airq_temp_cpu = IRQ_UNINIT; 1668 irqptr->airq_mps_intr_index = FREE_INDEX; 1669 1670 return (PSM_SUCCESS); 1671 } 1672 1673 /* 1674 * apic_introp_xlate() replaces apic_translate_irq() and is 1675 * called only from apic_intr_ops(). With the new ADII framework, 1676 * the priority can no longer be retrieved through i_ddi_get_intrspec(). 1677 * It has to be passed in from the caller. 1678 */ 1679 int 1680 apic_introp_xlate(dev_info_t *dip, struct intrspec *ispec, int type) 1681 { 1682 char dev_type[16]; 1683 int dev_len, pci_irq, newirq, bustype, devid, busid, i; 1684 int irqno = ispec->intrspec_vec; 1685 ddi_acc_handle_t cfg_handle; 1686 uchar_t ipin; 1687 struct apic_io_intr *intrp; 1688 iflag_t intr_flag; 1689 APIC_HEADER *hp; 1690 MADT_INTERRUPT_OVERRIDE *isop; 1691 apic_irq_t *airqp; 1692 int parent_is_pci_or_pciex = 0; 1693 int child_is_pciex = 0; 1694 1695 DDI_INTR_IMPLDBG((CE_CONT, "apic_introp_xlate: dip=0x%p name=%s " 1696 "type=%d irqno=0x%x\n", (void *)dip, ddi_get_name(dip), type, 1697 irqno)); 1698 1699 dev_len = sizeof (dev_type); 1700 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, ddi_get_parent(dip), 1701 DDI_PROP_DONTPASS, "device_type", (caddr_t)dev_type, 1702 &dev_len) == DDI_PROP_SUCCESS) { 1703 if ((strcmp(dev_type, "pci") == 0) || 1704 (strcmp(dev_type, "pciex") == 0)) 1705 parent_is_pci_or_pciex = 1; 1706 } 1707 1708 if (parent_is_pci_or_pciex && ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1709 DDI_PROP_DONTPASS, "pcie-capid-pointer", PCI_CAP_NEXT_PTR_NULL) != 1710 PCI_CAP_NEXT_PTR_NULL) { 1711 child_is_pciex = 1; 1712 } 1713 1714 if (DDI_INTR_IS_MSI_OR_MSIX(type)) { 1715 if ((airqp = apic_find_irq(dip, ispec, type)) != NULL) { 1716 airqp->airq_iflag.bustype = 1717 child_is_pciex ? BUS_PCIE : BUS_PCI; 1718 return (apic_vector_to_irq[airqp->airq_vector]); 1719 } 1720 return (apic_setup_irq_table(dip, irqno, NULL, ispec, 1721 NULL, type)); 1722 } 1723 1724 bustype = 0; 1725 1726 /* check if we have already translated this irq */ 1727 mutex_enter(&airq_mutex); 1728 newirq = apic_min_device_irq; 1729 for (; newirq <= apic_max_device_irq; newirq++) { 1730 airqp = apic_irq_table[newirq]; 1731 while (airqp) { 1732 if ((airqp->airq_dip == dip) && 1733 (airqp->airq_origirq == irqno) && 1734 (airqp->airq_mps_intr_index != FREE_INDEX)) { 1735 1736 mutex_exit(&airq_mutex); 1737 return (VIRTIRQ(newirq, airqp->airq_share_id)); 1738 } 1739 airqp = airqp->airq_next; 1740 } 1741 } 1742 mutex_exit(&airq_mutex); 1743 1744 if (apic_defconf) 1745 goto defconf; 1746 1747 if ((dip == NULL) || (!apic_irq_translate && !apic_enable_acpi)) 1748 goto nonpci; 1749 1750 if (parent_is_pci_or_pciex) { 1751 /* pci device */ 1752 if (acpica_get_bdf(dip, &busid, &devid, NULL) != 0) 1753 goto nonpci; 1754 if (busid == 0 && apic_pci_bus_total == 1) 1755 busid = (int)apic_single_pci_busid; 1756 1757 if (pci_config_setup(dip, &cfg_handle) != DDI_SUCCESS) 1758 goto nonpci; 1759 ipin = pci_config_get8(cfg_handle, PCI_CONF_IPIN) - PCI_INTA; 1760 pci_config_teardown(&cfg_handle); 1761 if (apic_enable_acpi && !apic_use_acpi_madt_only) { 1762 if (apic_acpi_translate_pci_irq(dip, busid, devid, 1763 ipin, &pci_irq, &intr_flag) != ACPI_PSM_SUCCESS) 1764 goto nonpci; 1765 1766 intr_flag.bustype = child_is_pciex ? BUS_PCIE : BUS_PCI; 1767 if ((newirq = apic_setup_irq_table(dip, pci_irq, NULL, 1768 ispec, &intr_flag, type)) == -1) 1769 goto nonpci; 1770 return (newirq); 1771 } else { 1772 pci_irq = ((devid & 0x1f) << 2) | (ipin & 0x3); 1773 if ((intrp = apic_find_io_intr_w_busid(pci_irq, busid)) 1774 == NULL) { 1775 if ((pci_irq = apic_handle_pci_pci_bridge(dip, 1776 devid, ipin, &intrp)) == -1) 1777 goto nonpci; 1778 } 1779 if ((newirq = apic_setup_irq_table(dip, pci_irq, intrp, 1780 ispec, NULL, type)) == -1) 1781 goto nonpci; 1782 return (newirq); 1783 } 1784 } else if (strcmp(dev_type, "isa") == 0) 1785 bustype = BUS_ISA; 1786 else if (strcmp(dev_type, "eisa") == 0) 1787 bustype = BUS_EISA; 1788 1789 nonpci: 1790 if (apic_enable_acpi && !apic_use_acpi_madt_only) { 1791 /* search iso entries first */ 1792 if (acpi_iso_cnt != 0) { 1793 hp = (APIC_HEADER *)acpi_isop; 1794 i = 0; 1795 while (i < acpi_iso_cnt) { 1796 if (hp->Type == APIC_XRUPT_OVERRIDE) { 1797 isop = (MADT_INTERRUPT_OVERRIDE *)hp; 1798 if (isop->Bus == 0 && 1799 isop->Source == irqno) { 1800 newirq = isop->Interrupt; 1801 intr_flag.intr_po = 1802 isop->Polarity; 1803 intr_flag.intr_el = 1804 isop->TriggerMode; 1805 intr_flag.bustype = BUS_ISA; 1806 1807 return (apic_setup_irq_table( 1808 dip, newirq, NULL, ispec, 1809 &intr_flag, type)); 1810 1811 } 1812 i++; 1813 } 1814 hp = (APIC_HEADER *)(((char *)hp) + 1815 hp->Length); 1816 } 1817 } 1818 intr_flag.intr_po = INTR_PO_ACTIVE_HIGH; 1819 intr_flag.intr_el = INTR_EL_EDGE; 1820 intr_flag.bustype = BUS_ISA; 1821 return (apic_setup_irq_table(dip, irqno, NULL, ispec, 1822 &intr_flag, type)); 1823 } else { 1824 if (bustype == 0) 1825 bustype = eisa_level_intr_mask ? BUS_EISA : BUS_ISA; 1826 for (i = 0; i < 2; i++) { 1827 if (((busid = apic_find_bus_id(bustype)) != -1) && 1828 ((intrp = apic_find_io_intr_w_busid(irqno, busid)) 1829 != NULL)) { 1830 if ((newirq = apic_setup_irq_table(dip, irqno, 1831 intrp, ispec, NULL, type)) != -1) { 1832 return (newirq); 1833 } 1834 goto defconf; 1835 } 1836 bustype = (bustype == BUS_EISA) ? BUS_ISA : BUS_EISA; 1837 } 1838 } 1839 1840 /* MPS default configuration */ 1841 defconf: 1842 newirq = apic_setup_irq_table(dip, irqno, NULL, ispec, NULL, type); 1843 if (newirq == -1) 1844 return (newirq); 1845 ASSERT(IRQINDEX(newirq) == irqno); 1846 ASSERT(apic_irq_table[irqno]); 1847 return (newirq); 1848 } 1849 1850 1851 1852 1853 1854 1855 /* 1856 * On machines with PCI-PCI bridges, a device behind a PCI-PCI bridge 1857 * needs special handling. We may need to chase up the device tree, 1858 * using the PCI-PCI Bridge specification's "rotating IPIN assumptions", 1859 * to find the IPIN at the root bus that relates to the IPIN on the 1860 * subsidiary bus (for ACPI or MP). We may, however, have an entry 1861 * in the MP table or the ACPI namespace for this device itself. 1862 * We handle both cases in the search below. 1863 */ 1864 /* this is the non-acpi version */ 1865 static int 1866 apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, int child_ipin, 1867 struct apic_io_intr **intrp) 1868 { 1869 dev_info_t *dipp, *dip; 1870 int pci_irq; 1871 ddi_acc_handle_t cfg_handle; 1872 int bridge_devno, bridge_bus; 1873 int ipin; 1874 1875 dip = idip; 1876 1877 /*CONSTCOND*/ 1878 while (1) { 1879 if (((dipp = ddi_get_parent(dip)) == (dev_info_t *)NULL) || 1880 (pci_config_setup(dipp, &cfg_handle) != DDI_SUCCESS)) 1881 return (-1); 1882 if ((pci_config_get8(cfg_handle, PCI_CONF_BASCLASS) == 1883 PCI_CLASS_BRIDGE) && (pci_config_get8(cfg_handle, 1884 PCI_CONF_SUBCLASS) == PCI_BRIDGE_PCI)) { 1885 pci_config_teardown(&cfg_handle); 1886 if (acpica_get_bdf(dipp, &bridge_bus, &bridge_devno, 1887 NULL) != 0) 1888 return (-1); 1889 /* 1890 * This is the rotating scheme documented in the 1891 * PCI-to-PCI spec. If the PCI-to-PCI bridge is 1892 * behind another PCI-to-PCI bridge, then it needs 1893 * to keep ascending until an interrupt entry is 1894 * found or the root is reached. 1895 */ 1896 ipin = (child_devno + child_ipin) % PCI_INTD; 1897 if (bridge_bus == 0 && apic_pci_bus_total == 1) 1898 bridge_bus = (int)apic_single_pci_busid; 1899 pci_irq = ((bridge_devno & 0x1f) << 2) | 1900 (ipin & 0x3); 1901 if ((*intrp = apic_find_io_intr_w_busid(pci_irq, 1902 bridge_bus)) != NULL) { 1903 return (pci_irq); 1904 } 1905 dip = dipp; 1906 child_devno = bridge_devno; 1907 child_ipin = ipin; 1908 } else { 1909 pci_config_teardown(&cfg_handle); 1910 return (-1); 1911 } 1912 } 1913 /*LINTED: function will not fall off the bottom */ 1914 } 1915 1916 1917 1918 1919 static uchar_t 1920 acpi_find_ioapic(int irq) 1921 { 1922 int i; 1923 1924 for (i = 0; i < apic_io_max; i++) { 1925 if (irq >= apic_io_vectbase[i] && irq <= apic_io_vectend[i]) 1926 return (i); 1927 } 1928 return (0xFF); /* shouldn't happen */ 1929 } 1930 1931 /* 1932 * See if two irqs are compatible for sharing a vector. 1933 * Currently we only support sharing of PCI devices. 1934 */ 1935 static int 1936 acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2) 1937 { 1938 uint_t level1, po1; 1939 uint_t level2, po2; 1940 1941 /* Assume active high by default */ 1942 po1 = 0; 1943 po2 = 0; 1944 1945 if (iflag1.bustype != iflag2.bustype || iflag1.bustype != BUS_PCI) 1946 return (0); 1947 1948 if (iflag1.intr_el == INTR_EL_CONFORM) 1949 level1 = AV_LEVEL; 1950 else 1951 level1 = (iflag1.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0; 1952 1953 if (level1 && ((iflag1.intr_po == INTR_PO_ACTIVE_LOW) || 1954 (iflag1.intr_po == INTR_PO_CONFORM))) 1955 po1 = AV_ACTIVE_LOW; 1956 1957 if (iflag2.intr_el == INTR_EL_CONFORM) 1958 level2 = AV_LEVEL; 1959 else 1960 level2 = (iflag2.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0; 1961 1962 if (level2 && ((iflag2.intr_po == INTR_PO_ACTIVE_LOW) || 1963 (iflag2.intr_po == INTR_PO_CONFORM))) 1964 po2 = AV_ACTIVE_LOW; 1965 1966 if ((level1 == level2) && (po1 == po2)) 1967 return (1); 1968 1969 return (0); 1970 } 1971 1972 /* 1973 * Attempt to share vector with someone else 1974 */ 1975 static int 1976 apic_share_vector(int irqno, iflag_t *intr_flagp, short intr_index, int ipl, 1977 uchar_t ioapicindex, uchar_t ipin, apic_irq_t **irqptrp) 1978 { 1979 #ifdef DEBUG 1980 apic_irq_t *tmpirqp = NULL; 1981 #endif /* DEBUG */ 1982 apic_irq_t *irqptr, dummyirq; 1983 int newirq, chosen_irq = -1, share = 127; 1984 int lowest, highest, i; 1985 uchar_t share_id; 1986 1987 DDI_INTR_IMPLDBG((CE_CONT, "apic_share_vector: irqno=0x%x " 1988 "intr_index=0x%x ipl=0x%x\n", irqno, intr_index, ipl)); 1989 1990 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK; 1991 lowest = apic_ipltopri[ipl-1] + APIC_VECTOR_PER_IPL; 1992 1993 if (highest < lowest) /* Both ipl and ipl-1 map to same pri */ 1994 lowest -= APIC_VECTOR_PER_IPL; 1995 dummyirq.airq_mps_intr_index = intr_index; 1996 dummyirq.airq_ioapicindex = ioapicindex; 1997 dummyirq.airq_intin_no = ipin; 1998 if (intr_flagp) 1999 dummyirq.airq_iflag = *intr_flagp; 2000 apic_record_rdt_entry(&dummyirq, irqno); 2001 for (i = lowest; i <= highest; i++) { 2002 newirq = apic_vector_to_irq[i]; 2003 if (newirq == APIC_RESV_IRQ) 2004 continue; 2005 irqptr = apic_irq_table[newirq]; 2006 2007 if ((dummyirq.airq_rdt_entry & 0xFF00) != 2008 (irqptr->airq_rdt_entry & 0xFF00)) 2009 /* not compatible */ 2010 continue; 2011 2012 if (irqptr->airq_share < share) { 2013 share = irqptr->airq_share; 2014 chosen_irq = newirq; 2015 } 2016 } 2017 if (chosen_irq != -1) { 2018 /* 2019 * Assign a share id which is free or which is larger 2020 * than the largest one. 2021 */ 2022 share_id = 1; 2023 mutex_enter(&airq_mutex); 2024 irqptr = apic_irq_table[chosen_irq]; 2025 while (irqptr) { 2026 if (irqptr->airq_mps_intr_index == FREE_INDEX) { 2027 share_id = irqptr->airq_share_id; 2028 break; 2029 } 2030 if (share_id <= irqptr->airq_share_id) 2031 share_id = irqptr->airq_share_id + 1; 2032 #ifdef DEBUG 2033 tmpirqp = irqptr; 2034 #endif /* DEBUG */ 2035 irqptr = irqptr->airq_next; 2036 } 2037 if (!irqptr) { 2038 irqptr = kmem_zalloc(sizeof (apic_irq_t), KM_SLEEP); 2039 irqptr->airq_temp_cpu = IRQ_UNINIT; 2040 irqptr->airq_next = 2041 apic_irq_table[chosen_irq]->airq_next; 2042 apic_irq_table[chosen_irq]->airq_next = irqptr; 2043 #ifdef DEBUG 2044 tmpirqp = apic_irq_table[chosen_irq]; 2045 #endif /* DEBUG */ 2046 } 2047 irqptr->airq_mps_intr_index = intr_index; 2048 irqptr->airq_ioapicindex = ioapicindex; 2049 irqptr->airq_intin_no = ipin; 2050 if (intr_flagp) 2051 irqptr->airq_iflag = *intr_flagp; 2052 irqptr->airq_vector = apic_irq_table[chosen_irq]->airq_vector; 2053 irqptr->airq_share_id = share_id; 2054 apic_record_rdt_entry(irqptr, irqno); 2055 *irqptrp = irqptr; 2056 #ifdef DEBUG 2057 /* shuffle the pointers to test apic_delspl path */ 2058 if (tmpirqp) { 2059 tmpirqp->airq_next = irqptr->airq_next; 2060 irqptr->airq_next = apic_irq_table[chosen_irq]; 2061 apic_irq_table[chosen_irq] = irqptr; 2062 } 2063 #endif /* DEBUG */ 2064 mutex_exit(&airq_mutex); 2065 return (VIRTIRQ(chosen_irq, share_id)); 2066 } 2067 return (-1); 2068 } 2069 2070 /* 2071 * 2072 */ 2073 static int 2074 apic_setup_irq_table(dev_info_t *dip, int irqno, struct apic_io_intr *intrp, 2075 struct intrspec *ispec, iflag_t *intr_flagp, int type) 2076 { 2077 int origirq = ispec->intrspec_vec; 2078 uchar_t ipl = ispec->intrspec_pri; 2079 int newirq, intr_index; 2080 uchar_t ipin, ioapic, ioapicindex, vector; 2081 apic_irq_t *irqptr; 2082 major_t major; 2083 dev_info_t *sdip; 2084 2085 DDI_INTR_IMPLDBG((CE_CONT, "apic_setup_irq_table: dip=0x%p type=%d " 2086 "irqno=0x%x origirq=0x%x\n", (void *)dip, type, irqno, origirq)); 2087 2088 ASSERT(ispec != NULL); 2089 2090 major = (dip != NULL) ? ddi_name_to_major(ddi_get_name(dip)) : 0; 2091 2092 if (DDI_INTR_IS_MSI_OR_MSIX(type)) { 2093 /* MSI/X doesn't need to setup ioapic stuffs */ 2094 ioapicindex = 0xff; 2095 ioapic = 0xff; 2096 ipin = (uchar_t)0xff; 2097 intr_index = (type == DDI_INTR_TYPE_MSI) ? MSI_INDEX : 2098 MSIX_INDEX; 2099 mutex_enter(&airq_mutex); 2100 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) == -1) { 2101 mutex_exit(&airq_mutex); 2102 /* need an irq for MSI/X to index into autovect[] */ 2103 cmn_err(CE_WARN, "No interrupt irq: %s instance %d", 2104 ddi_get_name(dip), ddi_get_instance(dip)); 2105 return (-1); 2106 } 2107 mutex_exit(&airq_mutex); 2108 2109 } else if (intrp != NULL) { 2110 intr_index = (int)(intrp - apic_io_intrp); 2111 ioapic = intrp->intr_destid; 2112 ipin = intrp->intr_destintin; 2113 /* Find ioapicindex. If destid was ALL, we will exit with 0. */ 2114 for (ioapicindex = apic_io_max - 1; ioapicindex; ioapicindex--) 2115 if (apic_io_id[ioapicindex] == ioapic) 2116 break; 2117 ASSERT((ioapic == apic_io_id[ioapicindex]) || 2118 (ioapic == INTR_ALL_APIC)); 2119 2120 /* check whether this intin# has been used by another irqno */ 2121 if ((newirq = apic_find_intin(ioapicindex, ipin)) != -1) { 2122 return (newirq); 2123 } 2124 2125 } else if (intr_flagp != NULL) { 2126 /* ACPI case */ 2127 intr_index = ACPI_INDEX; 2128 ioapicindex = acpi_find_ioapic(irqno); 2129 ASSERT(ioapicindex != 0xFF); 2130 ioapic = apic_io_id[ioapicindex]; 2131 ipin = irqno - apic_io_vectbase[ioapicindex]; 2132 if (apic_irq_table[irqno] && 2133 apic_irq_table[irqno]->airq_mps_intr_index == ACPI_INDEX) { 2134 ASSERT(apic_irq_table[irqno]->airq_intin_no == ipin && 2135 apic_irq_table[irqno]->airq_ioapicindex == 2136 ioapicindex); 2137 return (irqno); 2138 } 2139 2140 } else { 2141 /* default configuration */ 2142 ioapicindex = 0; 2143 ioapic = apic_io_id[ioapicindex]; 2144 ipin = (uchar_t)irqno; 2145 intr_index = DEFAULT_INDEX; 2146 } 2147 2148 if (ispec == NULL) { 2149 APIC_VERBOSE_IOAPIC((CE_WARN, "No intrspec for irqno = %x\n", 2150 irqno)); 2151 } else if ((vector = apic_allocate_vector(ipl, irqno, 0)) == 0) { 2152 if ((newirq = apic_share_vector(irqno, intr_flagp, intr_index, 2153 ipl, ioapicindex, ipin, &irqptr)) != -1) { 2154 irqptr->airq_ipl = ipl; 2155 irqptr->airq_origirq = (uchar_t)origirq; 2156 irqptr->airq_dip = dip; 2157 irqptr->airq_major = major; 2158 sdip = apic_irq_table[IRQINDEX(newirq)]->airq_dip; 2159 /* This is OK to do really */ 2160 if (sdip == NULL) { 2161 cmn_err(CE_WARN, "Sharing vectors: %s" 2162 " instance %d and SCI", 2163 ddi_get_name(dip), ddi_get_instance(dip)); 2164 } else { 2165 cmn_err(CE_WARN, "Sharing vectors: %s" 2166 " instance %d and %s instance %d", 2167 ddi_get_name(sdip), ddi_get_instance(sdip), 2168 ddi_get_name(dip), ddi_get_instance(dip)); 2169 } 2170 return (newirq); 2171 } 2172 /* try high priority allocation now that share has failed */ 2173 if ((vector = apic_allocate_vector(ipl, irqno, 1)) == 0) { 2174 cmn_err(CE_WARN, "No interrupt vector: %s instance %d", 2175 ddi_get_name(dip), ddi_get_instance(dip)); 2176 return (-1); 2177 } 2178 } 2179 2180 mutex_enter(&airq_mutex); 2181 if (apic_irq_table[irqno] == NULL) { 2182 irqptr = kmem_zalloc(sizeof (apic_irq_t), KM_SLEEP); 2183 irqptr->airq_temp_cpu = IRQ_UNINIT; 2184 apic_irq_table[irqno] = irqptr; 2185 } else { 2186 irqptr = apic_irq_table[irqno]; 2187 if (irqptr->airq_mps_intr_index != FREE_INDEX) { 2188 /* 2189 * The slot is used by another irqno, so allocate 2190 * a free irqno for this interrupt 2191 */ 2192 newirq = apic_allocate_irq(apic_first_avail_irq); 2193 if (newirq == -1) { 2194 mutex_exit(&airq_mutex); 2195 return (-1); 2196 } 2197 irqno = newirq; 2198 irqptr = apic_irq_table[irqno]; 2199 if (irqptr == NULL) { 2200 irqptr = kmem_zalloc(sizeof (apic_irq_t), 2201 KM_SLEEP); 2202 irqptr->airq_temp_cpu = IRQ_UNINIT; 2203 apic_irq_table[irqno] = irqptr; 2204 } 2205 vector = apic_modify_vector(vector, newirq); 2206 } 2207 } 2208 apic_max_device_irq = max(irqno, apic_max_device_irq); 2209 apic_min_device_irq = min(irqno, apic_min_device_irq); 2210 mutex_exit(&airq_mutex); 2211 irqptr->airq_ioapicindex = ioapicindex; 2212 irqptr->airq_intin_no = ipin; 2213 irqptr->airq_ipl = ipl; 2214 irqptr->airq_vector = vector; 2215 irqptr->airq_origirq = (uchar_t)origirq; 2216 irqptr->airq_share_id = 0; 2217 irqptr->airq_mps_intr_index = (short)intr_index; 2218 irqptr->airq_dip = dip; 2219 irqptr->airq_major = major; 2220 irqptr->airq_cpu = apic_bind_intr(dip, irqno, ioapic, ipin); 2221 if (intr_flagp) 2222 irqptr->airq_iflag = *intr_flagp; 2223 2224 if (!DDI_INTR_IS_MSI_OR_MSIX(type)) { 2225 /* setup I/O APIC entry for non-MSI/X interrupts */ 2226 apic_record_rdt_entry(irqptr, irqno); 2227 } 2228 return (irqno); 2229 } 2230 2231 /* 2232 * return the cpu to which this intr should be bound. 2233 * Check properties or any other mechanism to see if user wants it 2234 * bound to a specific CPU. If so, return the cpu id with high bit set. 2235 * If not, use the policy to choose a cpu and return the id. 2236 */ 2237 uchar_t 2238 apic_bind_intr(dev_info_t *dip, int irq, uchar_t ioapicid, uchar_t intin) 2239 { 2240 int instance, instno, prop_len, bind_cpu, count; 2241 uint_t i, rc; 2242 uchar_t cpu; 2243 major_t major; 2244 char *name, *drv_name, *prop_val, *cptr; 2245 char prop_name[32]; 2246 2247 2248 if (apic_intr_policy == INTR_LOWEST_PRIORITY) 2249 return (IRQ_UNBOUND); 2250 2251 drv_name = NULL; 2252 rc = DDI_PROP_NOT_FOUND; 2253 major = (major_t)-1; 2254 if (dip != NULL) { 2255 name = ddi_get_name(dip); 2256 major = ddi_name_to_major(name); 2257 drv_name = ddi_major_to_name(major); 2258 instance = ddi_get_instance(dip); 2259 if (apic_intr_policy == INTR_ROUND_ROBIN_WITH_AFFINITY) { 2260 i = apic_min_device_irq; 2261 for (; i <= apic_max_device_irq; i++) { 2262 2263 if ((i == irq) || (apic_irq_table[i] == NULL) || 2264 (apic_irq_table[i]->airq_mps_intr_index 2265 == FREE_INDEX)) 2266 continue; 2267 2268 if ((apic_irq_table[i]->airq_major == major) && 2269 (!(apic_irq_table[i]->airq_cpu & 2270 IRQ_USER_BOUND))) { 2271 2272 cpu = apic_irq_table[i]->airq_cpu; 2273 2274 cmn_err(CE_CONT, 2275 "!%s: %s (%s) instance #%d " 2276 "vector 0x%x ioapic 0x%x " 2277 "intin 0x%x is bound to cpu %d\n", 2278 psm_name, 2279 name, drv_name, instance, irq, 2280 ioapicid, intin, cpu); 2281 return (cpu); 2282 } 2283 } 2284 } 2285 /* 2286 * search for "drvname"_intpt_bind_cpus property first, the 2287 * syntax of the property should be "a[,b,c,...]" where 2288 * instance 0 binds to cpu a, instance 1 binds to cpu b, 2289 * instance 3 binds to cpu c... 2290 * ddi_getlongprop() will search /option first, then / 2291 * if "drvname"_intpt_bind_cpus doesn't exist, then find 2292 * intpt_bind_cpus property. The syntax is the same, and 2293 * it applies to all the devices if its "drvname" specific 2294 * property doesn't exist 2295 */ 2296 (void) strcpy(prop_name, drv_name); 2297 (void) strcat(prop_name, "_intpt_bind_cpus"); 2298 rc = ddi_getlongprop(DDI_DEV_T_ANY, dip, 0, prop_name, 2299 (caddr_t)&prop_val, &prop_len); 2300 if (rc != DDI_PROP_SUCCESS) { 2301 rc = ddi_getlongprop(DDI_DEV_T_ANY, dip, 0, 2302 "intpt_bind_cpus", (caddr_t)&prop_val, &prop_len); 2303 } 2304 } 2305 if (rc == DDI_PROP_SUCCESS) { 2306 for (i = count = 0; i < (prop_len - 1); i++) 2307 if (prop_val[i] == ',') 2308 count++; 2309 if (prop_val[i-1] != ',') 2310 count++; 2311 /* 2312 * if somehow the binding instances defined in the 2313 * property are not enough for this instno., then 2314 * reuse the pattern for the next instance until 2315 * it reaches the requested instno 2316 */ 2317 instno = instance % count; 2318 i = 0; 2319 cptr = prop_val; 2320 while (i < instno) 2321 if (*cptr++ == ',') 2322 i++; 2323 bind_cpu = stoi(&cptr); 2324 kmem_free(prop_val, prop_len); 2325 /* if specific cpu is bogus, then default to cpu 0 */ 2326 if (bind_cpu >= apic_nproc) { 2327 cmn_err(CE_WARN, "%s: %s=%s: CPU %d not present", 2328 psm_name, prop_name, prop_val, bind_cpu); 2329 bind_cpu = 0; 2330 } else { 2331 /* indicate that we are bound at user request */ 2332 bind_cpu |= IRQ_USER_BOUND; 2333 } 2334 /* 2335 * no need to check apic_cpus[].aci_status, if specific cpu is 2336 * not up, then post_cpu_start will handle it. 2337 */ 2338 } else { 2339 bind_cpu = apic_next_bind_cpu++; 2340 if (bind_cpu >= apic_nproc) { 2341 apic_next_bind_cpu = 1; 2342 bind_cpu = 0; 2343 } 2344 } 2345 if (drv_name != NULL) 2346 cmn_err(CE_CONT, "!%s: %s (%s) instance %d " 2347 "vector 0x%x ioapic 0x%x intin 0x%x is bound to cpu %d\n", 2348 psm_name, name, drv_name, instance, 2349 irq, ioapicid, intin, bind_cpu & ~IRQ_USER_BOUND); 2350 else 2351 cmn_err(CE_CONT, "!%s: " 2352 "vector 0x%x ioapic 0x%x intin 0x%x is bound to cpu %d\n", 2353 psm_name, irq, ioapicid, intin, bind_cpu & ~IRQ_USER_BOUND); 2354 2355 return ((uchar_t)bind_cpu); 2356 } 2357 2358 static struct apic_io_intr * 2359 apic_find_io_intr_w_busid(int irqno, int busid) 2360 { 2361 struct apic_io_intr *intrp; 2362 2363 /* 2364 * It can have more than 1 entry with same source bus IRQ, 2365 * but unique with the source bus id 2366 */ 2367 intrp = apic_io_intrp; 2368 if (intrp != NULL) { 2369 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 2370 if (intrp->intr_irq == irqno && 2371 intrp->intr_busid == busid && 2372 intrp->intr_type == IO_INTR_INT) 2373 return (intrp); 2374 intrp++; 2375 } 2376 } 2377 APIC_VERBOSE_IOAPIC((CE_NOTE, "Did not find io intr for irqno:" 2378 "busid %x:%x\n", irqno, busid)); 2379 return ((struct apic_io_intr *)NULL); 2380 } 2381 2382 2383 struct mps_bus_info { 2384 char *bus_name; 2385 int bus_id; 2386 } bus_info_array[] = { 2387 "ISA ", BUS_ISA, 2388 "PCI ", BUS_PCI, 2389 "EISA ", BUS_EISA, 2390 "XPRESS", BUS_XPRESS, 2391 "PCMCIA", BUS_PCMCIA, 2392 "VL ", BUS_VL, 2393 "CBUS ", BUS_CBUS, 2394 "CBUSII", BUS_CBUSII, 2395 "FUTURE", BUS_FUTURE, 2396 "INTERN", BUS_INTERN, 2397 "MBI ", BUS_MBI, 2398 "MBII ", BUS_MBII, 2399 "MPI ", BUS_MPI, 2400 "MPSA ", BUS_MPSA, 2401 "NUBUS ", BUS_NUBUS, 2402 "TC ", BUS_TC, 2403 "VME ", BUS_VME, 2404 "PCI-E ", BUS_PCIE 2405 }; 2406 2407 static int 2408 apic_find_bus_type(char *bus) 2409 { 2410 int i = 0; 2411 2412 for (; i < sizeof (bus_info_array)/sizeof (struct mps_bus_info); i++) 2413 if (strncmp(bus, bus_info_array[i].bus_name, 2414 strlen(bus_info_array[i].bus_name)) == 0) 2415 return (bus_info_array[i].bus_id); 2416 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus type for bus %s", bus)); 2417 return (0); 2418 } 2419 2420 static int 2421 apic_find_bus(int busid) 2422 { 2423 struct apic_bus *busp; 2424 2425 busp = apic_busp; 2426 while (busp->bus_entry == APIC_BUS_ENTRY) { 2427 if (busp->bus_id == busid) 2428 return (apic_find_bus_type((char *)&busp->bus_str1)); 2429 busp++; 2430 } 2431 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus for bus id %x", busid)); 2432 return (0); 2433 } 2434 2435 static int 2436 apic_find_bus_id(int bustype) 2437 { 2438 struct apic_bus *busp; 2439 2440 busp = apic_busp; 2441 while (busp->bus_entry == APIC_BUS_ENTRY) { 2442 if (apic_find_bus_type((char *)&busp->bus_str1) == bustype) 2443 return (busp->bus_id); 2444 busp++; 2445 } 2446 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus id for bustype %x", 2447 bustype)); 2448 return (-1); 2449 } 2450 2451 /* 2452 * Check if a particular irq need to be reserved for any io_intr 2453 */ 2454 static struct apic_io_intr * 2455 apic_find_io_intr(int irqno) 2456 { 2457 struct apic_io_intr *intrp; 2458 2459 intrp = apic_io_intrp; 2460 if (intrp != NULL) { 2461 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 2462 if (intrp->intr_irq == irqno && 2463 intrp->intr_type == IO_INTR_INT) 2464 return (intrp); 2465 intrp++; 2466 } 2467 } 2468 return ((struct apic_io_intr *)NULL); 2469 } 2470 2471 /* 2472 * Check if the given ioapicindex intin combination has already been assigned 2473 * an irq. If so return irqno. Else -1 2474 */ 2475 static int 2476 apic_find_intin(uchar_t ioapic, uchar_t intin) 2477 { 2478 apic_irq_t *irqptr; 2479 int i; 2480 2481 /* find ioapic and intin in the apic_irq_table[] and return the index */ 2482 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) { 2483 irqptr = apic_irq_table[i]; 2484 while (irqptr) { 2485 if ((irqptr->airq_mps_intr_index >= 0) && 2486 (irqptr->airq_intin_no == intin) && 2487 (irqptr->airq_ioapicindex == ioapic)) { 2488 APIC_VERBOSE_IOAPIC((CE_NOTE, "!Found irq " 2489 "entry for ioapic:intin %x:%x " 2490 "shared interrupts ?", ioapic, intin)); 2491 return (i); 2492 } 2493 irqptr = irqptr->airq_next; 2494 } 2495 } 2496 return (-1); 2497 } 2498 2499 int 2500 apic_allocate_irq(int irq) 2501 { 2502 int freeirq, i; 2503 2504 if ((freeirq = apic_find_free_irq(irq, (APIC_RESV_IRQ - 1))) == -1) 2505 if ((freeirq = apic_find_free_irq(APIC_FIRST_FREE_IRQ, 2506 (irq - 1))) == -1) { 2507 /* 2508 * if BIOS really defines every single irq in the mps 2509 * table, then don't worry about conflicting with 2510 * them, just use any free slot in apic_irq_table 2511 */ 2512 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) { 2513 if ((apic_irq_table[i] == NULL) || 2514 apic_irq_table[i]->airq_mps_intr_index == 2515 FREE_INDEX) { 2516 freeirq = i; 2517 break; 2518 } 2519 } 2520 if (freeirq == -1) { 2521 /* This shouldn't happen, but just in case */ 2522 cmn_err(CE_WARN, "%s: NO available IRQ", psm_name); 2523 return (-1); 2524 } 2525 } 2526 if (apic_irq_table[freeirq] == NULL) { 2527 apic_irq_table[freeirq] = 2528 kmem_zalloc(sizeof (apic_irq_t), KM_NOSLEEP); 2529 if (apic_irq_table[freeirq] == NULL) { 2530 cmn_err(CE_WARN, "%s: NO memory to allocate IRQ", 2531 psm_name); 2532 return (-1); 2533 } 2534 apic_irq_table[freeirq]->airq_mps_intr_index = FREE_INDEX; 2535 } 2536 return (freeirq); 2537 } 2538 2539 static int 2540 apic_find_free_irq(int start, int end) 2541 { 2542 int i; 2543 2544 for (i = start; i <= end; i++) 2545 /* Check if any I/O entry needs this IRQ */ 2546 if (apic_find_io_intr(i) == NULL) { 2547 /* Then see if it is free */ 2548 if ((apic_irq_table[i] == NULL) || 2549 (apic_irq_table[i]->airq_mps_intr_index == 2550 FREE_INDEX)) { 2551 return (i); 2552 } 2553 } 2554 return (-1); 2555 } 2556 2557 2558 /* 2559 * Mark vector as being in the process of being deleted. Interrupts 2560 * may still come in on some CPU. The moment an interrupt comes with 2561 * the new vector, we know we can free the old one. Called only from 2562 * addspl and delspl with interrupts disabled. Because an interrupt 2563 * can be shared, but no interrupt from either device may come in, 2564 * we also use a timeout mechanism, which we arbitrarily set to 2565 * apic_revector_timeout microseconds. 2566 */ 2567 static void 2568 apic_mark_vector(uchar_t oldvector, uchar_t newvector) 2569 { 2570 ulong_t iflag; 2571 2572 iflag = intr_clear(); 2573 lock_set(&apic_revector_lock); 2574 if (!apic_oldvec_to_newvec) { 2575 apic_oldvec_to_newvec = 2576 kmem_zalloc(sizeof (newvector) * APIC_MAX_VECTOR * 2, 2577 KM_NOSLEEP); 2578 2579 if (!apic_oldvec_to_newvec) { 2580 /* 2581 * This failure is not catastrophic. 2582 * But, the oldvec will never be freed. 2583 */ 2584 apic_error |= APIC_ERR_MARK_VECTOR_FAIL; 2585 lock_clear(&apic_revector_lock); 2586 intr_restore(iflag); 2587 return; 2588 } 2589 apic_newvec_to_oldvec = &apic_oldvec_to_newvec[APIC_MAX_VECTOR]; 2590 } 2591 2592 /* See if we already did this for drivers which do double addintrs */ 2593 if (apic_oldvec_to_newvec[oldvector] != newvector) { 2594 apic_oldvec_to_newvec[oldvector] = newvector; 2595 apic_newvec_to_oldvec[newvector] = oldvector; 2596 apic_revector_pending++; 2597 } 2598 lock_clear(&apic_revector_lock); 2599 intr_restore(iflag); 2600 (void) timeout(apic_xlate_vector_free_timeout_handler, 2601 (void *)(uintptr_t)oldvector, drv_usectohz(apic_revector_timeout)); 2602 } 2603 2604 /* 2605 * xlate_vector is called from intr_enter if revector_pending is set. 2606 * It will xlate it if needed and mark the old vector as free. 2607 */ 2608 uchar_t 2609 apic_xlate_vector(uchar_t vector) 2610 { 2611 uchar_t newvector, oldvector = 0; 2612 2613 lock_set(&apic_revector_lock); 2614 /* Do we really need to do this ? */ 2615 if (!apic_revector_pending) { 2616 lock_clear(&apic_revector_lock); 2617 return (vector); 2618 } 2619 if ((newvector = apic_oldvec_to_newvec[vector]) != 0) 2620 oldvector = vector; 2621 else { 2622 /* 2623 * The incoming vector is new . See if a stale entry is 2624 * remaining 2625 */ 2626 if ((oldvector = apic_newvec_to_oldvec[vector]) != 0) 2627 newvector = vector; 2628 } 2629 2630 if (oldvector) { 2631 apic_revector_pending--; 2632 apic_oldvec_to_newvec[oldvector] = 0; 2633 apic_newvec_to_oldvec[newvector] = 0; 2634 apic_free_vector(oldvector); 2635 lock_clear(&apic_revector_lock); 2636 /* There could have been more than one reprogramming! */ 2637 return (apic_xlate_vector(newvector)); 2638 } 2639 lock_clear(&apic_revector_lock); 2640 return (vector); 2641 } 2642 2643 void 2644 apic_xlate_vector_free_timeout_handler(void *arg) 2645 { 2646 ulong_t iflag; 2647 uchar_t oldvector, newvector; 2648 2649 oldvector = (uchar_t)(uintptr_t)arg; 2650 iflag = intr_clear(); 2651 lock_set(&apic_revector_lock); 2652 if ((newvector = apic_oldvec_to_newvec[oldvector]) != 0) { 2653 apic_free_vector(oldvector); 2654 apic_oldvec_to_newvec[oldvector] = 0; 2655 apic_newvec_to_oldvec[newvector] = 0; 2656 apic_revector_pending--; 2657 } 2658 2659 lock_clear(&apic_revector_lock); 2660 intr_restore(iflag); 2661 } 2662 2663 2664 /* 2665 * compute the polarity, trigger mode and vector for programming into 2666 * the I/O apic and record in airq_rdt_entry. 2667 */ 2668 static void 2669 apic_record_rdt_entry(apic_irq_t *irqptr, int irq) 2670 { 2671 int ioapicindex, bus_type, vector; 2672 short intr_index; 2673 uint_t level, po, io_po; 2674 struct apic_io_intr *iointrp; 2675 2676 intr_index = irqptr->airq_mps_intr_index; 2677 DDI_INTR_IMPLDBG((CE_CONT, "apic_record_rdt_entry: intr_index=%d " 2678 "irq = 0x%x dip = 0x%p vector = 0x%x\n", intr_index, irq, 2679 (void *)irqptr->airq_dip, irqptr->airq_vector)); 2680 2681 if (intr_index == RESERVE_INDEX) { 2682 apic_error |= APIC_ERR_INVALID_INDEX; 2683 return; 2684 } else if (APIC_IS_MSI_OR_MSIX_INDEX(intr_index)) { 2685 return; 2686 } 2687 2688 vector = irqptr->airq_vector; 2689 ioapicindex = irqptr->airq_ioapicindex; 2690 /* Assume edge triggered by default */ 2691 level = 0; 2692 /* Assume active high by default */ 2693 po = 0; 2694 2695 if (intr_index == DEFAULT_INDEX || intr_index == FREE_INDEX) { 2696 ASSERT(irq < 16); 2697 if (eisa_level_intr_mask & (1 << irq)) 2698 level = AV_LEVEL; 2699 if (intr_index == FREE_INDEX && apic_defconf == 0) 2700 apic_error |= APIC_ERR_INVALID_INDEX; 2701 } else if (intr_index == ACPI_INDEX) { 2702 bus_type = irqptr->airq_iflag.bustype; 2703 if (irqptr->airq_iflag.intr_el == INTR_EL_CONFORM) { 2704 if (bus_type == BUS_PCI) 2705 level = AV_LEVEL; 2706 } else 2707 level = (irqptr->airq_iflag.intr_el == INTR_EL_LEVEL) ? 2708 AV_LEVEL : 0; 2709 if (level && 2710 ((irqptr->airq_iflag.intr_po == INTR_PO_ACTIVE_LOW) || 2711 (irqptr->airq_iflag.intr_po == INTR_PO_CONFORM && 2712 bus_type == BUS_PCI))) 2713 po = AV_ACTIVE_LOW; 2714 } else { 2715 iointrp = apic_io_intrp + intr_index; 2716 bus_type = apic_find_bus(iointrp->intr_busid); 2717 if (iointrp->intr_el == INTR_EL_CONFORM) { 2718 if ((irq < 16) && (eisa_level_intr_mask & (1 << irq))) 2719 level = AV_LEVEL; 2720 else if (bus_type == BUS_PCI) 2721 level = AV_LEVEL; 2722 } else 2723 level = (iointrp->intr_el == INTR_EL_LEVEL) ? 2724 AV_LEVEL : 0; 2725 if (level && ((iointrp->intr_po == INTR_PO_ACTIVE_LOW) || 2726 (iointrp->intr_po == INTR_PO_CONFORM && 2727 bus_type == BUS_PCI))) 2728 po = AV_ACTIVE_LOW; 2729 } 2730 if (level) 2731 apic_level_intr[irq] = 1; 2732 /* 2733 * The 82489DX External APIC cannot do active low polarity interrupts. 2734 */ 2735 if (po && (apic_io_ver[ioapicindex] != IOAPIC_VER_82489DX)) 2736 io_po = po; 2737 else 2738 io_po = 0; 2739 2740 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) 2741 printf("setio: ioapic=%x intin=%x level=%x po=%x vector=%x\n", 2742 ioapicindex, irqptr->airq_intin_no, level, io_po, vector); 2743 2744 irqptr->airq_rdt_entry = level|io_po|vector; 2745 } 2746 2747 /* 2748 * Bind interrupt corresponding to irq_ptr to bind_cpu. 2749 * Must be called with interrupts disabled and apic_ioapic_lock held 2750 */ 2751 int 2752 apic_rebind(apic_irq_t *irq_ptr, int bind_cpu, 2753 struct ioapic_reprogram_data *drep) 2754 { 2755 int ioapicindex, intin_no; 2756 uchar_t airq_temp_cpu; 2757 apic_cpus_info_t *cpu_infop; 2758 uint32_t rdt_entry; 2759 int which_irq; 2760 2761 which_irq = apic_vector_to_irq[irq_ptr->airq_vector]; 2762 2763 intin_no = irq_ptr->airq_intin_no; 2764 ioapicindex = irq_ptr->airq_ioapicindex; 2765 airq_temp_cpu = irq_ptr->airq_temp_cpu; 2766 if (airq_temp_cpu != IRQ_UNINIT && airq_temp_cpu != IRQ_UNBOUND) { 2767 if (airq_temp_cpu & IRQ_USER_BOUND) 2768 /* Mask off high bit so it can be used as array index */ 2769 airq_temp_cpu &= ~IRQ_USER_BOUND; 2770 2771 ASSERT(airq_temp_cpu < apic_nproc); 2772 } 2773 2774 /* 2775 * Can't bind to a CPU that's not accepting interrupts: 2776 */ 2777 cpu_infop = &apic_cpus[bind_cpu & ~IRQ_USER_BOUND]; 2778 if (!(cpu_infop->aci_status & APIC_CPU_INTR_ENABLE)) 2779 return (1); 2780 2781 /* 2782 * If we are about to change the interrupt vector for this interrupt, 2783 * and this interrupt is level-triggered, attached to an IOAPIC, 2784 * has been delivered to a CPU and that CPU has not handled it 2785 * yet, we cannot reprogram the IOAPIC now. 2786 */ 2787 if (!APIC_IS_MSI_OR_MSIX_INDEX(irq_ptr->airq_mps_intr_index)) { 2788 2789 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, 2790 intin_no); 2791 2792 if ((irq_ptr->airq_vector != RDT_VECTOR(rdt_entry)) && 2793 apic_check_stuck_interrupt(irq_ptr, airq_temp_cpu, 2794 bind_cpu, ioapicindex, intin_no, which_irq, drep) != 0) { 2795 2796 return (0); 2797 } 2798 2799 /* 2800 * NOTE: We do not unmask the RDT here, as an interrupt MAY 2801 * still come in before we have a chance to reprogram it below. 2802 * The reprogramming below will simultaneously change and 2803 * unmask the RDT entry. 2804 */ 2805 2806 if ((uchar_t)bind_cpu == IRQ_UNBOUND) { 2807 rdt_entry = AV_LDEST | AV_LOPRI | 2808 irq_ptr->airq_rdt_entry; 2809 2810 /* Write the RDT entry -- no specific CPU binding */ 2811 WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapicindex, intin_no, 2812 AV_TOALL); 2813 2814 if (airq_temp_cpu != IRQ_UNINIT && airq_temp_cpu != 2815 IRQ_UNBOUND) 2816 apic_cpus[airq_temp_cpu].aci_temp_bound--; 2817 2818 /* 2819 * Write the vector, trigger, and polarity portion of 2820 * the RDT 2821 */ 2822 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, intin_no, 2823 rdt_entry); 2824 2825 irq_ptr->airq_temp_cpu = IRQ_UNBOUND; 2826 return (0); 2827 } 2828 } 2829 2830 if (bind_cpu & IRQ_USER_BOUND) { 2831 cpu_infop->aci_bound++; 2832 } else { 2833 cpu_infop->aci_temp_bound++; 2834 } 2835 ASSERT((bind_cpu & ~IRQ_USER_BOUND) < apic_nproc); 2836 if (!APIC_IS_MSI_OR_MSIX_INDEX(irq_ptr->airq_mps_intr_index)) { 2837 /* Write the RDT entry -- bind to a specific CPU: */ 2838 WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapicindex, intin_no, 2839 cpu_infop->aci_local_id << APIC_ID_BIT_OFFSET); 2840 } 2841 if ((airq_temp_cpu != IRQ_UNBOUND) && (airq_temp_cpu != IRQ_UNINIT)) { 2842 apic_cpus[airq_temp_cpu].aci_temp_bound--; 2843 } 2844 if (!APIC_IS_MSI_OR_MSIX_INDEX(irq_ptr->airq_mps_intr_index)) { 2845 2846 rdt_entry = AV_PDEST | AV_FIXED | irq_ptr->airq_rdt_entry; 2847 2848 /* Write the vector, trigger, and polarity portion of the RDT */ 2849 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, intin_no, 2850 rdt_entry); 2851 2852 } else { 2853 int type = (irq_ptr->airq_mps_intr_index == MSI_INDEX) ? 2854 DDI_INTR_TYPE_MSI : DDI_INTR_TYPE_MSIX; 2855 if (ioapicindex == irq_ptr->airq_origirq) { 2856 /* first one */ 2857 DDI_INTR_IMPLDBG((CE_CONT, "apic_rebind: call " 2858 "apic_pci_msi_enable_vector\n")); 2859 if (apic_pci_msi_enable_vector(irq_ptr->airq_dip, type, 2860 which_irq, irq_ptr->airq_vector, 2861 irq_ptr->airq_intin_no, 2862 cpu_infop->aci_local_id) != PSM_SUCCESS) { 2863 cmn_err(CE_WARN, "pcplusmp: " 2864 "apic_pci_msi_enable_vector " 2865 "returned PSM_FAILURE"); 2866 } 2867 } 2868 if ((ioapicindex + irq_ptr->airq_intin_no - 1) == 2869 irq_ptr->airq_origirq) { /* last one */ 2870 DDI_INTR_IMPLDBG((CE_CONT, "apic_rebind: call " 2871 "pci_msi_enable_mode\n")); 2872 if (apic_pci_msi_enable_mode(irq_ptr->airq_dip, 2873 type, which_irq) != PSM_SUCCESS) { 2874 DDI_INTR_IMPLDBG((CE_CONT, "pcplusmp: " 2875 "pci_msi_enable failed\n")); 2876 (void) apic_pci_msi_unconfigure( 2877 irq_ptr->airq_dip, type, which_irq); 2878 } 2879 } 2880 } 2881 irq_ptr->airq_temp_cpu = (uchar_t)bind_cpu; 2882 apic_redist_cpu_skip &= ~(1 << (bind_cpu & ~IRQ_USER_BOUND)); 2883 return (0); 2884 } 2885 2886 static void 2887 apic_last_ditch_clear_remote_irr(int ioapic_ix, int intin_no) 2888 { 2889 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no) 2890 & AV_REMOTE_IRR) != 0) { 2891 /* 2892 * Trying to clear the bit through normal 2893 * channels has failed. So as a last-ditch 2894 * effort, try to set the trigger mode to 2895 * edge, then to level. This has been 2896 * observed to work on many systems. 2897 */ 2898 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 2899 intin_no, 2900 READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 2901 intin_no) & ~AV_LEVEL); 2902 2903 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 2904 intin_no, 2905 READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 2906 intin_no) | AV_LEVEL); 2907 2908 /* 2909 * If the bit's STILL set, this interrupt may 2910 * be hosed. 2911 */ 2912 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 2913 intin_no) & AV_REMOTE_IRR) != 0) { 2914 2915 prom_printf("%s: Remote IRR still " 2916 "not clear for IOAPIC %d intin %d.\n" 2917 "\tInterrupts to this pin may cease " 2918 "functioning.\n", psm_name, ioapic_ix, 2919 intin_no); 2920 #ifdef DEBUG 2921 apic_last_ditch_reprogram_failures++; 2922 #endif 2923 } 2924 } 2925 } 2926 2927 /* 2928 * This function is protected by apic_ioapic_lock coupled with the 2929 * fact that interrupts are disabled. 2930 */ 2931 static void 2932 delete_defer_repro_ent(int which_irq) 2933 { 2934 ASSERT(which_irq >= 0); 2935 ASSERT(which_irq <= 255); 2936 2937 if (apic_reprogram_info[which_irq].done) 2938 return; 2939 2940 apic_reprogram_info[which_irq].done = B_TRUE; 2941 2942 #ifdef DEBUG 2943 apic_defer_repro_total_retries += 2944 apic_reprogram_info[which_irq].tries; 2945 2946 apic_defer_repro_successes++; 2947 #endif 2948 2949 if (--apic_reprogram_outstanding == 0) { 2950 2951 setlvlx = apic_intr_exit; 2952 } 2953 } 2954 2955 2956 /* 2957 * Interrupts must be disabled during this function to prevent 2958 * self-deadlock. Interrupts are disabled because this function 2959 * is called from apic_check_stuck_interrupt(), which is called 2960 * from apic_rebind(), which requires its caller to disable interrupts. 2961 */ 2962 static void 2963 add_defer_repro_ent(apic_irq_t *irq_ptr, int which_irq, int new_bind_cpu) 2964 { 2965 ASSERT(which_irq >= 0); 2966 ASSERT(which_irq <= 255); 2967 2968 /* 2969 * On the off-chance that there's already a deferred 2970 * reprogramming on this irq, check, and if so, just update the 2971 * CPU and irq pointer to which the interrupt is targeted, then return. 2972 */ 2973 if (!apic_reprogram_info[which_irq].done) { 2974 apic_reprogram_info[which_irq].bindcpu = new_bind_cpu; 2975 apic_reprogram_info[which_irq].irqp = irq_ptr; 2976 return; 2977 } 2978 2979 apic_reprogram_info[which_irq].irqp = irq_ptr; 2980 apic_reprogram_info[which_irq].bindcpu = new_bind_cpu; 2981 apic_reprogram_info[which_irq].tries = 0; 2982 /* 2983 * This must be the last thing set, since we're not 2984 * grabbing any locks, apic_try_deferred_reprogram() will 2985 * make its decision about using this entry iff done 2986 * is false. 2987 */ 2988 apic_reprogram_info[which_irq].done = B_FALSE; 2989 2990 /* 2991 * If there were previously no deferred reprogrammings, change 2992 * setlvlx to call apic_try_deferred_reprogram() 2993 */ 2994 if (++apic_reprogram_outstanding == 1) { 2995 2996 setlvlx = apic_try_deferred_reprogram; 2997 } 2998 } 2999 3000 static void 3001 apic_try_deferred_reprogram(int prev_ipl, int irq) 3002 { 3003 int reproirq, iflag; 3004 struct ioapic_reprogram_data *drep; 3005 3006 apic_intr_exit(prev_ipl, irq); 3007 3008 if (!lock_try(&apic_defer_reprogram_lock)) { 3009 return; 3010 } 3011 3012 /* 3013 * Acquire the apic_ioapic_lock so that any other operations that 3014 * may affect the apic_reprogram_info state are serialized. 3015 * It's still possible for the last deferred reprogramming to clear 3016 * between the time we entered this function and the time we get to 3017 * the for loop below. In that case, *setlvlx will have been set 3018 * back to apic_intr_exit and drep will be NULL. (There's no way to 3019 * stop that from happening -- we would need to grab a lock before 3020 * calling *setlvlx, which is neither realistic nor prudent). 3021 */ 3022 iflag = intr_clear(); 3023 lock_set(&apic_ioapic_lock); 3024 3025 /* 3026 * For each deferred RDT entry, try to reprogram it now. Note that 3027 * there is no lock acquisition to read apic_reprogram_info because 3028 * '.done' is set only after the other fields in the structure are set. 3029 */ 3030 3031 drep = NULL; 3032 for (reproirq = 0; reproirq <= APIC_MAX_VECTOR; reproirq++) { 3033 if (apic_reprogram_info[reproirq].done == B_FALSE) { 3034 drep = &apic_reprogram_info[reproirq]; 3035 break; 3036 } 3037 } 3038 3039 /* 3040 * Either we found a deferred action to perform, or 3041 * we entered this function spuriously, after *setlvlx 3042 * was restored to point to apic_intr_enter. Any other 3043 * permutation is invalid. 3044 */ 3045 ASSERT(drep != NULL || *setlvlx == apic_intr_exit); 3046 3047 /* 3048 * Though we can't really do anything about errors 3049 * at this point, keep track of them for reporting. 3050 * Note that it is very possible for apic_setup_io_intr 3051 * to re-register this very timeout if the Remote IRR bit 3052 * has not yet cleared. 3053 */ 3054 3055 #ifdef DEBUG 3056 if (drep != NULL) { 3057 if (apic_setup_io_intr(drep, reproirq, B_TRUE) != 0) { 3058 apic_deferred_setup_failures++; 3059 } 3060 } else { 3061 apic_deferred_spurious_enters++; 3062 } 3063 #else 3064 if (drep != NULL) 3065 (void) apic_setup_io_intr(drep, reproirq, B_TRUE); 3066 #endif 3067 3068 lock_clear(&apic_ioapic_lock); 3069 intr_restore(iflag); 3070 3071 lock_clear(&apic_defer_reprogram_lock); 3072 } 3073 3074 static void 3075 apic_ioapic_wait_pending_clear(int ioapic_ix, int intin_no) 3076 { 3077 int waited; 3078 3079 /* 3080 * Wait for the delivery pending bit to clear. 3081 */ 3082 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no) & 3083 (AV_LEVEL|AV_PENDING)) == (AV_LEVEL|AV_PENDING)) { 3084 3085 /* 3086 * If we're still waiting on the delivery of this interrupt, 3087 * continue to wait here until it is delivered (this should be 3088 * a very small amount of time, but include a timeout just in 3089 * case). 3090 */ 3091 for (waited = 0; waited < apic_max_reps_clear_pending; 3092 waited++) { 3093 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 3094 intin_no) & AV_PENDING) == 0) { 3095 break; 3096 } 3097 } 3098 } 3099 } 3100 3101 3102 /* 3103 * Checks to see if the IOAPIC interrupt entry specified has its Remote IRR 3104 * bit set. Calls functions that modify the function that setlvlx points to, 3105 * so that the reprogramming can be retried very shortly. 3106 * 3107 * This function will mask the RDT entry if the interrupt is level-triggered. 3108 * (The caller is responsible for unmasking the RDT entry.) 3109 * 3110 * Returns non-zero if the caller should defer IOAPIC reprogramming. 3111 */ 3112 static int 3113 apic_check_stuck_interrupt(apic_irq_t *irq_ptr, int old_bind_cpu, 3114 int new_bind_cpu, int ioapic_ix, int intin_no, int which_irq, 3115 struct ioapic_reprogram_data *drep) 3116 { 3117 int32_t rdt_entry; 3118 int waited; 3119 int reps = 0; 3120 3121 /* 3122 * Wait for the delivery pending bit to clear. 3123 */ 3124 do { 3125 ++reps; 3126 3127 apic_ioapic_wait_pending_clear(ioapic_ix, intin_no); 3128 3129 /* 3130 * Mask the RDT entry, but only if it's a level-triggered 3131 * interrupt 3132 */ 3133 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 3134 intin_no); 3135 if ((rdt_entry & (AV_LEVEL|AV_MASK)) == AV_LEVEL) { 3136 3137 /* Mask it */ 3138 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no, 3139 AV_MASK | rdt_entry); 3140 } 3141 3142 if ((rdt_entry & AV_LEVEL) == AV_LEVEL) { 3143 /* 3144 * If there was a race and an interrupt was injected 3145 * just before we masked, check for that case here. 3146 * Then, unmask the RDT entry and try again. If we're 3147 * on our last try, don't unmask (because we want the 3148 * RDT entry to remain masked for the rest of the 3149 * function). 3150 */ 3151 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 3152 intin_no); 3153 if ((rdt_entry & AV_PENDING) && 3154 (reps < apic_max_reps_clear_pending)) { 3155 /* Unmask it */ 3156 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 3157 intin_no, rdt_entry & ~AV_MASK); 3158 } 3159 } 3160 3161 } while ((rdt_entry & AV_PENDING) && 3162 (reps < apic_max_reps_clear_pending)); 3163 3164 #ifdef DEBUG 3165 if (rdt_entry & AV_PENDING) 3166 apic_intr_deliver_timeouts++; 3167 #endif 3168 3169 /* 3170 * If the remote IRR bit is set, then the interrupt has been sent 3171 * to a CPU for processing. We have no choice but to wait for 3172 * that CPU to process the interrupt, at which point the remote IRR 3173 * bit will be cleared. 3174 */ 3175 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no) & 3176 (AV_LEVEL|AV_REMOTE_IRR)) == (AV_LEVEL|AV_REMOTE_IRR)) { 3177 3178 /* 3179 * If the CPU that this RDT is bound to is NOT the current 3180 * CPU, wait until that CPU handles the interrupt and ACKs 3181 * it. If this interrupt is not bound to any CPU (that is, 3182 * if it's bound to the logical destination of "anyone"), it 3183 * may have been delivered to the current CPU so handle that 3184 * case by deferring the reprogramming (below). 3185 */ 3186 if ((old_bind_cpu != IRQ_UNBOUND) && 3187 (old_bind_cpu != IRQ_UNINIT) && 3188 (old_bind_cpu != psm_get_cpu_id())) { 3189 for (waited = 0; waited < apic_max_reps_clear_pending; 3190 waited++) { 3191 if ((READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 3192 intin_no) & AV_REMOTE_IRR) == 0) { 3193 3194 delete_defer_repro_ent(which_irq); 3195 3196 /* Remote IRR has cleared! */ 3197 return (0); 3198 } 3199 } 3200 } 3201 3202 /* 3203 * If we waited and the Remote IRR bit is still not cleared, 3204 * AND if we've invoked the timeout APIC_REPROGRAM_MAX_TIMEOUTS 3205 * times for this interrupt, try the last-ditch workaround: 3206 */ 3207 if (drep && drep->tries >= APIC_REPROGRAM_MAX_TRIES) { 3208 3209 apic_last_ditch_clear_remote_irr(ioapic_ix, intin_no); 3210 3211 /* Mark this one as reprogrammed: */ 3212 delete_defer_repro_ent(which_irq); 3213 3214 return (0); 3215 } else { 3216 #ifdef DEBUG 3217 apic_intr_deferrals++; 3218 #endif 3219 3220 /* 3221 * If waiting for the Remote IRR bit (above) didn't 3222 * allow it to clear, defer the reprogramming. 3223 * Add a new deferred-programming entry if the 3224 * caller passed a NULL one (and update the existing one 3225 * in case anything changed). 3226 */ 3227 add_defer_repro_ent(irq_ptr, which_irq, new_bind_cpu); 3228 if (drep) 3229 drep->tries++; 3230 3231 /* Inform caller to defer IOAPIC programming: */ 3232 return (1); 3233 } 3234 3235 } 3236 3237 /* Remote IRR is clear */ 3238 delete_defer_repro_ent(which_irq); 3239 3240 return (0); 3241 } 3242 3243 /* 3244 * Called to migrate all interrupts at an irq to another cpu. 3245 * Must be called with interrupts disabled and apic_ioapic_lock held 3246 */ 3247 int 3248 apic_rebind_all(apic_irq_t *irq_ptr, int bind_cpu) 3249 { 3250 apic_irq_t *irqptr = irq_ptr; 3251 int retval = 0; 3252 3253 while (irqptr) { 3254 if (irqptr->airq_temp_cpu != IRQ_UNINIT) 3255 retval |= apic_rebind(irqptr, bind_cpu, NULL); 3256 irqptr = irqptr->airq_next; 3257 } 3258 3259 return (retval); 3260 } 3261 3262 /* 3263 * apic_intr_redistribute does all the messy computations for identifying 3264 * which interrupt to move to which CPU. Currently we do just one interrupt 3265 * at a time. This reduces the time we spent doing all this within clock 3266 * interrupt. When it is done in idle, we could do more than 1. 3267 * First we find the most busy and the most free CPU (time in ISR only) 3268 * skipping those CPUs that has been identified as being ineligible (cpu_skip) 3269 * Then we look for IRQs which are closest to the difference between the 3270 * most busy CPU and the average ISR load. We try to find one whose load 3271 * is less than difference.If none exists, then we chose one larger than the 3272 * difference, provided it does not make the most idle CPU worse than the 3273 * most busy one. In the end, we clear all the busy fields for CPUs. For 3274 * IRQs, they are cleared as they are scanned. 3275 */ 3276 void 3277 apic_intr_redistribute() 3278 { 3279 int busiest_cpu, most_free_cpu; 3280 int cpu_free, cpu_busy, max_busy, min_busy; 3281 int min_free, diff; 3282 int average_busy, cpus_online; 3283 int i, busy, iflag; 3284 apic_cpus_info_t *cpu_infop; 3285 apic_irq_t *min_busy_irq = NULL; 3286 apic_irq_t *max_busy_irq = NULL; 3287 3288 busiest_cpu = most_free_cpu = -1; 3289 cpu_free = cpu_busy = max_busy = average_busy = 0; 3290 min_free = apic_sample_factor_redistribution; 3291 cpus_online = 0; 3292 /* 3293 * Below we will check for CPU_INTR_ENABLE, bound, temp_bound, temp_cpu 3294 * without ioapic_lock. That is OK as we are just doing statistical 3295 * sampling anyway and any inaccuracy now will get corrected next time 3296 * The call to rebind which actually changes things will make sure 3297 * we are consistent. 3298 */ 3299 for (i = 0; i < apic_nproc; i++) { 3300 if (!(apic_redist_cpu_skip & (1 << i)) && 3301 (apic_cpus[i].aci_status & APIC_CPU_INTR_ENABLE)) { 3302 3303 cpu_infop = &apic_cpus[i]; 3304 /* 3305 * If no unbound interrupts or only 1 total on this 3306 * CPU, skip 3307 */ 3308 if (!cpu_infop->aci_temp_bound || 3309 (cpu_infop->aci_bound + cpu_infop->aci_temp_bound) 3310 == 1) { 3311 apic_redist_cpu_skip |= 1 << i; 3312 continue; 3313 } 3314 3315 busy = cpu_infop->aci_busy; 3316 average_busy += busy; 3317 cpus_online++; 3318 if (max_busy < busy) { 3319 max_busy = busy; 3320 busiest_cpu = i; 3321 } 3322 if (min_free > busy) { 3323 min_free = busy; 3324 most_free_cpu = i; 3325 } 3326 if (busy > apic_int_busy_mark) { 3327 cpu_busy |= 1 << i; 3328 } else { 3329 if (busy < apic_int_free_mark) 3330 cpu_free |= 1 << i; 3331 } 3332 } 3333 } 3334 if ((cpu_busy && cpu_free) || 3335 (max_busy >= (min_free + apic_diff_for_redistribution))) { 3336 3337 apic_num_imbalance++; 3338 #ifdef DEBUG 3339 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) { 3340 prom_printf( 3341 "redistribute busy=%x free=%x max=%x min=%x", 3342 cpu_busy, cpu_free, max_busy, min_free); 3343 } 3344 #endif /* DEBUG */ 3345 3346 3347 average_busy /= cpus_online; 3348 3349 diff = max_busy - average_busy; 3350 min_busy = max_busy; /* start with the max possible value */ 3351 max_busy = 0; 3352 min_busy_irq = max_busy_irq = NULL; 3353 i = apic_min_device_irq; 3354 for (; i < apic_max_device_irq; i++) { 3355 apic_irq_t *irq_ptr; 3356 /* Change to linked list per CPU ? */ 3357 if ((irq_ptr = apic_irq_table[i]) == NULL) 3358 continue; 3359 /* Check for irq_busy & decide which one to move */ 3360 /* Also zero them for next round */ 3361 if ((irq_ptr->airq_temp_cpu == busiest_cpu) && 3362 irq_ptr->airq_busy) { 3363 if (irq_ptr->airq_busy < diff) { 3364 /* 3365 * Check for least busy CPU, 3366 * best fit or what ? 3367 */ 3368 if (max_busy < irq_ptr->airq_busy) { 3369 /* 3370 * Most busy within the 3371 * required differential 3372 */ 3373 max_busy = irq_ptr->airq_busy; 3374 max_busy_irq = irq_ptr; 3375 } 3376 } else { 3377 if (min_busy > irq_ptr->airq_busy) { 3378 /* 3379 * least busy, but more than 3380 * the reqd diff 3381 */ 3382 if (min_busy < 3383 (diff + average_busy - 3384 min_free)) { 3385 /* 3386 * Making sure new cpu 3387 * will not end up 3388 * worse 3389 */ 3390 min_busy = 3391 irq_ptr->airq_busy; 3392 3393 min_busy_irq = irq_ptr; 3394 } 3395 } 3396 } 3397 } 3398 irq_ptr->airq_busy = 0; 3399 } 3400 3401 if (max_busy_irq != NULL) { 3402 #ifdef DEBUG 3403 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) { 3404 prom_printf("rebinding %x to %x", 3405 max_busy_irq->airq_vector, most_free_cpu); 3406 } 3407 #endif /* DEBUG */ 3408 iflag = intr_clear(); 3409 if (lock_try(&apic_ioapic_lock)) { 3410 if (apic_rebind_all(max_busy_irq, 3411 most_free_cpu) == 0) { 3412 /* Make change permenant */ 3413 max_busy_irq->airq_cpu = 3414 (uchar_t)most_free_cpu; 3415 } 3416 lock_clear(&apic_ioapic_lock); 3417 } 3418 intr_restore(iflag); 3419 3420 } else if (min_busy_irq != NULL) { 3421 #ifdef DEBUG 3422 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) { 3423 prom_printf("rebinding %x to %x", 3424 min_busy_irq->airq_vector, most_free_cpu); 3425 } 3426 #endif /* DEBUG */ 3427 3428 iflag = intr_clear(); 3429 if (lock_try(&apic_ioapic_lock)) { 3430 if (apic_rebind_all(min_busy_irq, 3431 most_free_cpu) == 0) { 3432 /* Make change permenant */ 3433 min_busy_irq->airq_cpu = 3434 (uchar_t)most_free_cpu; 3435 } 3436 lock_clear(&apic_ioapic_lock); 3437 } 3438 intr_restore(iflag); 3439 3440 } else { 3441 if (cpu_busy != (1 << busiest_cpu)) { 3442 apic_redist_cpu_skip |= 1 << busiest_cpu; 3443 /* 3444 * We leave cpu_skip set so that next time we 3445 * can choose another cpu 3446 */ 3447 } 3448 } 3449 apic_num_rebind++; 3450 } else { 3451 /* 3452 * found nothing. Could be that we skipped over valid CPUs 3453 * or we have balanced everything. If we had a variable 3454 * ticks_for_redistribution, it could be increased here. 3455 * apic_int_busy, int_free etc would also need to be 3456 * changed. 3457 */ 3458 if (apic_redist_cpu_skip) 3459 apic_redist_cpu_skip = 0; 3460 } 3461 for (i = 0; i < apic_nproc; i++) { 3462 apic_cpus[i].aci_busy = 0; 3463 } 3464 } 3465 3466 void 3467 apic_cleanup_busy() 3468 { 3469 int i; 3470 apic_irq_t *irq_ptr; 3471 3472 for (i = 0; i < apic_nproc; i++) { 3473 apic_cpus[i].aci_busy = 0; 3474 } 3475 3476 for (i = apic_min_device_irq; i < apic_max_device_irq; i++) { 3477 if ((irq_ptr = apic_irq_table[i]) != NULL) 3478 irq_ptr->airq_busy = 0; 3479 } 3480 } 3481 3482 3483 static int 3484 apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid, 3485 int ipin, int *pci_irqp, iflag_t *intr_flagp) 3486 { 3487 3488 int status; 3489 acpi_psm_lnk_t acpipsmlnk; 3490 3491 if ((status = acpi_get_irq_cache_ent(busid, devid, ipin, pci_irqp, 3492 intr_flagp)) == ACPI_PSM_SUCCESS) { 3493 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Found irqno %d " 3494 "from cache for device %s, instance #%d\n", psm_name, 3495 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip))); 3496 return (status); 3497 } 3498 3499 bzero(&acpipsmlnk, sizeof (acpi_psm_lnk_t)); 3500 3501 if ((status = acpi_translate_pci_irq(dip, ipin, pci_irqp, intr_flagp, 3502 &acpipsmlnk)) == ACPI_PSM_FAILURE) { 3503 APIC_VERBOSE_IRQ((CE_WARN, "%s: " 3504 " acpi_translate_pci_irq failed for device %s, instance" 3505 " #%d", psm_name, ddi_get_name(dip), 3506 ddi_get_instance(dip))); 3507 return (status); 3508 } 3509 3510 if (status == ACPI_PSM_PARTIAL && acpipsmlnk.lnkobj != NULL) { 3511 status = apic_acpi_irq_configure(&acpipsmlnk, dip, pci_irqp, 3512 intr_flagp); 3513 if (status != ACPI_PSM_SUCCESS) { 3514 status = acpi_get_current_irq_resource(&acpipsmlnk, 3515 pci_irqp, intr_flagp); 3516 } 3517 } 3518 3519 if (status == ACPI_PSM_SUCCESS) { 3520 acpi_new_irq_cache_ent(busid, devid, ipin, *pci_irqp, 3521 intr_flagp, &acpipsmlnk); 3522 3523 APIC_VERBOSE_IRQ((CE_CONT, "%s: [ACPI] " 3524 "new irq %d for device %s, instance #%d\n", psm_name, 3525 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip))); 3526 } 3527 3528 return (status); 3529 } 3530 3531 /* 3532 * Adds an entry to the irq list passed in, and returns the new list. 3533 * Entries are added in priority order (lower numerical priorities are 3534 * placed closer to the head of the list) 3535 */ 3536 static prs_irq_list_t * 3537 acpi_insert_prs_irq_ent(prs_irq_list_t *listp, int priority, int irq, 3538 iflag_t *iflagp, acpi_prs_private_t *prsprvp) 3539 { 3540 struct prs_irq_list_ent *newent, *prevp = NULL, *origlistp; 3541 3542 newent = kmem_zalloc(sizeof (struct prs_irq_list_ent), KM_SLEEP); 3543 3544 newent->list_prio = priority; 3545 newent->irq = irq; 3546 newent->intrflags = *iflagp; 3547 newent->prsprv = *prsprvp; 3548 /* ->next is NULL from kmem_zalloc */ 3549 3550 /* 3551 * New list -- return the new entry as the list. 3552 */ 3553 if (listp == NULL) 3554 return (newent); 3555 3556 /* 3557 * Save original list pointer for return (since we're not modifying 3558 * the head) 3559 */ 3560 origlistp = listp; 3561 3562 /* 3563 * Insertion sort, with entries with identical keys stored AFTER 3564 * existing entries (the less-than-or-equal test of priority does 3565 * this for us). 3566 */ 3567 while (listp != NULL && listp->list_prio <= priority) { 3568 prevp = listp; 3569 listp = listp->next; 3570 } 3571 3572 newent->next = listp; 3573 3574 if (prevp == NULL) { /* Add at head of list (newent is the new head) */ 3575 return (newent); 3576 } else { 3577 prevp->next = newent; 3578 return (origlistp); 3579 } 3580 } 3581 3582 /* 3583 * Frees the list passed in, deallocating all memory and leaving *listpp 3584 * set to NULL. 3585 */ 3586 static void 3587 acpi_destroy_prs_irq_list(prs_irq_list_t **listpp) 3588 { 3589 struct prs_irq_list_ent *nextp; 3590 3591 ASSERT(listpp != NULL); 3592 3593 while (*listpp != NULL) { 3594 nextp = (*listpp)->next; 3595 kmem_free(*listpp, sizeof (struct prs_irq_list_ent)); 3596 *listpp = nextp; 3597 } 3598 } 3599 3600 /* 3601 * apic_choose_irqs_from_prs returns a list of irqs selected from the list of 3602 * irqs returned by the link device's _PRS method. The irqs are chosen 3603 * to minimize contention in situations where the interrupt link device 3604 * can be programmed to steer interrupts to different interrupt controller 3605 * inputs (some of which may already be in use). The list is sorted in order 3606 * of irqs to use, with the highest priority given to interrupt controller 3607 * inputs that are not shared. When an interrupt controller input 3608 * must be shared, apic_choose_irqs_from_prs adds the possible irqs to the 3609 * returned list in the order that minimizes sharing (thereby ensuring lowest 3610 * possible latency from interrupt trigger time to ISR execution time). 3611 */ 3612 static prs_irq_list_t * 3613 apic_choose_irqs_from_prs(acpi_irqlist_t *irqlistent, dev_info_t *dip, 3614 int crs_irq) 3615 { 3616 int32_t irq; 3617 int i; 3618 prs_irq_list_t *prsirqlistp = NULL; 3619 iflag_t iflags; 3620 3621 while (irqlistent != NULL) { 3622 irqlistent->intr_flags.bustype = BUS_PCI; 3623 3624 for (i = 0; i < irqlistent->num_irqs; i++) { 3625 3626 irq = irqlistent->irqs[i]; 3627 3628 if (irq <= 0) { 3629 /* invalid irq number */ 3630 continue; 3631 } 3632 3633 if ((irq < 16) && (apic_reserved_irqlist[irq])) 3634 continue; 3635 3636 if ((apic_irq_table[irq] == NULL) || 3637 (apic_irq_table[irq]->airq_dip == dip)) { 3638 3639 prsirqlistp = acpi_insert_prs_irq_ent( 3640 prsirqlistp, 0 /* Highest priority */, irq, 3641 &irqlistent->intr_flags, 3642 &irqlistent->acpi_prs_prv); 3643 3644 /* 3645 * If we do not prefer the current irq from _CRS 3646 * or if we do and this irq is the same as the 3647 * current irq from _CRS, this is the one 3648 * to pick. 3649 */ 3650 if (!(apic_prefer_crs) || (irq == crs_irq)) { 3651 return (prsirqlistp); 3652 } 3653 continue; 3654 } 3655 3656 /* 3657 * Edge-triggered interrupts cannot be shared 3658 */ 3659 if (irqlistent->intr_flags.intr_el == INTR_EL_EDGE) 3660 continue; 3661 3662 /* 3663 * To work around BIOSes that contain incorrect 3664 * interrupt polarity information in interrupt 3665 * descriptors returned by _PRS, we assume that 3666 * the polarity of the other device sharing this 3667 * interrupt controller input is compatible. 3668 * If it's not, the caller will catch it when 3669 * the caller invokes the link device's _CRS method 3670 * (after invoking its _SRS method). 3671 */ 3672 iflags = irqlistent->intr_flags; 3673 iflags.intr_po = 3674 apic_irq_table[irq]->airq_iflag.intr_po; 3675 3676 if (!acpi_intr_compatible(iflags, 3677 apic_irq_table[irq]->airq_iflag)) { 3678 APIC_VERBOSE_IRQ((CE_CONT, "!%s: irq %d " 3679 "not compatible [%x:%x:%x !~ %x:%x:%x]", 3680 psm_name, irq, 3681 iflags.intr_po, 3682 iflags.intr_el, 3683 iflags.bustype, 3684 apic_irq_table[irq]->airq_iflag.intr_po, 3685 apic_irq_table[irq]->airq_iflag.intr_el, 3686 apic_irq_table[irq]->airq_iflag.bustype)); 3687 continue; 3688 } 3689 3690 /* 3691 * If we prefer the irq from _CRS, no need 3692 * to search any further (and make sure 3693 * to add this irq with the highest priority 3694 * so it's tried first). 3695 */ 3696 if (crs_irq == irq && apic_prefer_crs) { 3697 3698 return (acpi_insert_prs_irq_ent( 3699 prsirqlistp, 3700 0 /* Highest priority */, 3701 irq, &iflags, 3702 &irqlistent->acpi_prs_prv)); 3703 } 3704 3705 /* 3706 * Priority is equal to the share count (lower 3707 * share count is higher priority). Note that 3708 * the intr flags passed in here are the ones we 3709 * changed above -- if incorrect, it will be 3710 * caught by the caller's _CRS flags comparison. 3711 */ 3712 prsirqlistp = acpi_insert_prs_irq_ent( 3713 prsirqlistp, 3714 apic_irq_table[irq]->airq_share, irq, 3715 &iflags, &irqlistent->acpi_prs_prv); 3716 } 3717 3718 /* Go to the next irqlist entry */ 3719 irqlistent = irqlistent->next; 3720 } 3721 3722 return (prsirqlistp); 3723 } 3724 3725 /* 3726 * Configures the irq for the interrupt link device identified by 3727 * acpipsmlnkp. 3728 * 3729 * Gets the current and the list of possible irq settings for the 3730 * device. If apic_unconditional_srs is not set, and the current 3731 * resource setting is in the list of possible irq settings, 3732 * current irq resource setting is passed to the caller. 3733 * 3734 * Otherwise, picks an irq number from the list of possible irq 3735 * settings, and sets the irq of the device to this value. 3736 * If prefer_crs is set, among a set of irq numbers in the list that have 3737 * the least number of devices sharing the interrupt, we pick current irq 3738 * resource setting if it is a member of this set. 3739 * 3740 * Passes the irq number in the value pointed to by pci_irqp, and 3741 * polarity and sensitivity in the structure pointed to by dipintrflagp 3742 * to the caller. 3743 * 3744 * Note that if setting the irq resource failed, but successfuly obtained 3745 * the current irq resource settings, passes the current irq resources 3746 * and considers it a success. 3747 * 3748 * Returns: 3749 * ACPI_PSM_SUCCESS on success. 3750 * 3751 * ACPI_PSM_FAILURE if an error occured during the configuration or 3752 * if a suitable irq was not found for this device, or if setting the 3753 * irq resource and obtaining the current resource fails. 3754 * 3755 */ 3756 static int 3757 apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip, 3758 int *pci_irqp, iflag_t *dipintr_flagp) 3759 { 3760 int32_t irq; 3761 int cur_irq = -1; 3762 acpi_irqlist_t *irqlistp; 3763 prs_irq_list_t *prs_irq_listp, *prs_irq_entp; 3764 boolean_t found_irq = B_FALSE; 3765 3766 dipintr_flagp->bustype = BUS_PCI; 3767 3768 if ((acpi_get_possible_irq_resources(acpipsmlnkp, &irqlistp)) 3769 == ACPI_PSM_FAILURE) { 3770 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Unable to determine " 3771 "or assign IRQ for device %s, instance #%d: The system was " 3772 "unable to get the list of potential IRQs from ACPI.", 3773 psm_name, ddi_get_name(dip), ddi_get_instance(dip))); 3774 3775 return (ACPI_PSM_FAILURE); 3776 } 3777 3778 if ((acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq, 3779 dipintr_flagp) == ACPI_PSM_SUCCESS) && (!apic_unconditional_srs) && 3780 (cur_irq > 0)) { 3781 /* 3782 * If an IRQ is set in CRS and that IRQ exists in the set 3783 * returned from _PRS, return that IRQ, otherwise print 3784 * a warning 3785 */ 3786 3787 if (acpi_irqlist_find_irq(irqlistp, cur_irq, NULL) 3788 == ACPI_PSM_SUCCESS) { 3789 3790 ASSERT(pci_irqp != NULL); 3791 *pci_irqp = cur_irq; 3792 acpi_free_irqlist(irqlistp); 3793 return (ACPI_PSM_SUCCESS); 3794 } 3795 3796 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find the " 3797 "current irq %d for device %s, instance #%d in ACPI's " 3798 "list of possible irqs for this device. Picking one from " 3799 " the latter list.", psm_name, cur_irq, ddi_get_name(dip), 3800 ddi_get_instance(dip))); 3801 } 3802 3803 if ((prs_irq_listp = apic_choose_irqs_from_prs(irqlistp, dip, 3804 cur_irq)) == NULL) { 3805 3806 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find a " 3807 "suitable irq from the list of possible irqs for device " 3808 "%s, instance #%d in ACPI's list of possible irqs", 3809 psm_name, ddi_get_name(dip), ddi_get_instance(dip))); 3810 3811 acpi_free_irqlist(irqlistp); 3812 return (ACPI_PSM_FAILURE); 3813 } 3814 3815 acpi_free_irqlist(irqlistp); 3816 3817 for (prs_irq_entp = prs_irq_listp; 3818 prs_irq_entp != NULL && found_irq == B_FALSE; 3819 prs_irq_entp = prs_irq_entp->next) { 3820 3821 acpipsmlnkp->acpi_prs_prv = prs_irq_entp->prsprv; 3822 irq = prs_irq_entp->irq; 3823 3824 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Setting irq %d for " 3825 "device %s instance #%d\n", psm_name, irq, 3826 ddi_get_name(dip), ddi_get_instance(dip))); 3827 3828 if ((acpi_set_irq_resource(acpipsmlnkp, irq)) 3829 == ACPI_PSM_SUCCESS) { 3830 /* 3831 * setting irq was successful, check to make sure CRS 3832 * reflects that. If CRS does not agree with what we 3833 * set, return the irq that was set. 3834 */ 3835 3836 if (acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq, 3837 dipintr_flagp) == ACPI_PSM_SUCCESS) { 3838 3839 if (cur_irq != irq) 3840 APIC_VERBOSE_IRQ((CE_WARN, 3841 "!%s: IRQ resource set " 3842 "(irqno %d) for device %s " 3843 "instance #%d, differs from " 3844 "current setting irqno %d", 3845 psm_name, irq, ddi_get_name(dip), 3846 ddi_get_instance(dip), cur_irq)); 3847 } else { 3848 /* 3849 * On at least one system, there was a bug in 3850 * a DSDT method called by _STA, causing _STA to 3851 * indicate that the link device was disabled 3852 * (when, in fact, it was enabled). Since _SRS 3853 * succeeded, assume that _CRS is lying and use 3854 * the iflags from this _PRS interrupt choice. 3855 * If we're wrong about the flags, the polarity 3856 * will be incorrect and we may get an interrupt 3857 * storm, but there's not much else we can do 3858 * at this point. 3859 */ 3860 *dipintr_flagp = prs_irq_entp->intrflags; 3861 } 3862 3863 /* 3864 * Return the irq that was set, and not what _CRS 3865 * reports, since _CRS has been seen to return 3866 * different IRQs than what was passed to _SRS on some 3867 * systems (and just not return successfully on others). 3868 */ 3869 cur_irq = irq; 3870 found_irq = B_TRUE; 3871 } else { 3872 APIC_VERBOSE_IRQ((CE_WARN, "!%s: set resource " 3873 "irq %d failed for device %s instance #%d", 3874 psm_name, irq, ddi_get_name(dip), 3875 ddi_get_instance(dip))); 3876 3877 if (cur_irq == -1) { 3878 acpi_destroy_prs_irq_list(&prs_irq_listp); 3879 return (ACPI_PSM_FAILURE); 3880 } 3881 } 3882 } 3883 3884 acpi_destroy_prs_irq_list(&prs_irq_listp); 3885 3886 if (!found_irq) 3887 return (ACPI_PSM_FAILURE); 3888 3889 ASSERT(pci_irqp != NULL); 3890 *pci_irqp = cur_irq; 3891 return (ACPI_PSM_SUCCESS); 3892 } 3893 3894 void 3895 ioapic_disable_redirection() 3896 { 3897 int ioapic_ix; 3898 int intin_max; 3899 int intin_ix; 3900 3901 /* Disable the I/O APIC redirection entries */ 3902 for (ioapic_ix = 0; ioapic_ix < apic_io_max; ioapic_ix++) { 3903 3904 /* Bits 23-16 define the maximum redirection entries */ 3905 intin_max = (ioapic_read(ioapic_ix, APIC_VERS_CMD) >> 16) 3906 & 0xff; 3907 3908 for (intin_ix = 0; intin_ix < intin_max; intin_ix++) { 3909 /* 3910 * The assumption here is that this is safe, even for 3911 * systems with IOAPICs that suffer from the hardware 3912 * erratum because all devices have been quiesced before 3913 * this function is called from apic_shutdown() 3914 * (or equivalent). If that assumption turns out to be 3915 * false, this mask operation can induce the same 3916 * erratum result we're trying to avoid. 3917 */ 3918 ioapic_write(ioapic_ix, APIC_RDT_CMD + 2 * intin_ix, 3919 AV_MASK); 3920 } 3921 } 3922 } 3923 3924 /* 3925 * Looks for an IOAPIC with the specified physical address in the /ioapics 3926 * node in the device tree (created by the PCI enumerator). 3927 */ 3928 static boolean_t 3929 apic_is_ioapic_AMD_813x(uint32_t physaddr) 3930 { 3931 /* 3932 * Look in /ioapics, for the ioapic with 3933 * the physical address given 3934 */ 3935 dev_info_t *ioapicsnode = ddi_find_devinfo(IOAPICS_NODE_NAME, -1, 0); 3936 dev_info_t *ioapic_child; 3937 boolean_t rv = B_FALSE; 3938 int vid, did; 3939 uint64_t ioapic_paddr; 3940 boolean_t done = B_FALSE; 3941 3942 if (ioapicsnode == NULL) 3943 return (B_FALSE); 3944 3945 /* Load first child: */ 3946 ioapic_child = ddi_get_child(ioapicsnode); 3947 while (!done && ioapic_child != 0) { /* Iterate over children */ 3948 3949 if ((ioapic_paddr = (uint64_t)ddi_prop_get_int64(DDI_DEV_T_ANY, 3950 ioapic_child, DDI_PROP_DONTPASS, "reg", 0)) 3951 != 0 && physaddr == ioapic_paddr) { 3952 3953 vid = ddi_prop_get_int(DDI_DEV_T_ANY, ioapic_child, 3954 DDI_PROP_DONTPASS, IOAPICS_PROP_VENID, 0); 3955 3956 if (vid == VENID_AMD) { 3957 3958 did = ddi_prop_get_int(DDI_DEV_T_ANY, 3959 ioapic_child, DDI_PROP_DONTPASS, 3960 IOAPICS_PROP_DEVID, 0); 3961 3962 if (did == DEVID_8131_IOAPIC || 3963 did == DEVID_8132_IOAPIC) { 3964 3965 rv = B_TRUE; 3966 done = B_TRUE; 3967 } 3968 } 3969 } 3970 3971 if (!done) 3972 ioapic_child = ddi_get_next_sibling(ioapic_child); 3973 } 3974 3975 /* The ioapics node was held by ddi_find_devinfo, so release it */ 3976 ndi_rele_devi(ioapicsnode); 3977 return (rv); 3978 } 3979