1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright 2016 Nexenta Systems, Inc. 24 * Copyright (c) 2017 by Delphix. All rights reserved. 25 */ 26 /* 27 * Copyright (c) 2010, Intel Corporation. 28 * All rights reserved. 29 */ 30 31 /* 32 * PSMI 1.1 extensions are supported only in 2.6 and later versions. 33 * PSMI 1.2 extensions are supported only in 2.7 and later versions. 34 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10. 35 * PSMI 1.5 extensions are supported in Solaris Nevada. 36 * PSMI 1.6 extensions are supported in Solaris Nevada. 37 * PSMI 1.7 extensions are supported in Solaris Nevada. 38 */ 39 #define PSMI_1_7 40 41 #include <sys/processor.h> 42 #include <sys/time.h> 43 #include <sys/psm.h> 44 #include <sys/smp_impldefs.h> 45 #include <sys/cram.h> 46 #include <sys/acpi/acpi.h> 47 #include <sys/acpica.h> 48 #include <sys/psm_common.h> 49 #include <sys/apic.h> 50 #include <sys/apic_timer.h> 51 #include <sys/pit.h> 52 #include <sys/ddi.h> 53 #include <sys/sunddi.h> 54 #include <sys/ddi_impldefs.h> 55 #include <sys/pci.h> 56 #include <sys/promif.h> 57 #include <sys/x86_archext.h> 58 #include <sys/cpc_impl.h> 59 #include <sys/uadmin.h> 60 #include <sys/panic.h> 61 #include <sys/debug.h> 62 #include <sys/archsystm.h> 63 #include <sys/trap.h> 64 #include <sys/machsystm.h> 65 #include <sys/cpuvar.h> 66 #include <sys/rm_platter.h> 67 #include <sys/privregs.h> 68 #include <sys/cyclic.h> 69 #include <sys/note.h> 70 #include <sys/pci_intr_lib.h> 71 #include <sys/sunndi.h> 72 #if !defined(__xpv) 73 #include <sys/hpet.h> 74 #include <sys/clock.h> 75 #endif 76 77 /* 78 * Local Function Prototypes 79 */ 80 static int apic_handle_defconf(); 81 static int apic_parse_mpct(caddr_t mpct, int bypass); 82 static struct apic_mpfps_hdr *apic_find_fps_sig(caddr_t fptr, int size); 83 static int apic_checksum(caddr_t bptr, int len); 84 static int apic_find_bus_type(char *bus); 85 static int apic_find_bus(int busid); 86 static struct apic_io_intr *apic_find_io_intr(int irqno); 87 static int apic_find_free_irq(int start, int end); 88 struct apic_io_intr *apic_find_io_intr_w_busid(int irqno, int busid); 89 static void apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp); 90 static void apic_free_apic_cpus(void); 91 static boolean_t apic_is_ioapic_AMD_813x(uint32_t physaddr); 92 static int apic_acpi_enter_apicmode(void); 93 94 int apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, 95 int child_ipin, struct apic_io_intr **intrp); 96 int apic_find_bus_id(int bustype); 97 int apic_find_intin(uchar_t ioapic, uchar_t intin); 98 void apic_record_rdt_entry(apic_irq_t *irqptr, int irq); 99 100 int apic_debug_mps_id = 0; /* 1 - print MPS ID strings */ 101 102 /* ACPI SCI interrupt configuration; -1 if SCI not used */ 103 int apic_sci_vect = -1; 104 iflag_t apic_sci_flags; 105 106 #if !defined(__xpv) 107 /* ACPI HPET interrupt configuration; -1 if HPET not used */ 108 int apic_hpet_vect = -1; 109 iflag_t apic_hpet_flags; 110 #endif 111 112 /* 113 * psm name pointer 114 */ 115 char *psm_name; 116 117 /* ACPI support routines */ 118 static int acpi_probe(char *); 119 static int apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip, 120 int *pci_irqp, iflag_t *intr_flagp); 121 122 int apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid, 123 int ipin, int *pci_irqp, iflag_t *intr_flagp); 124 uchar_t acpi_find_ioapic(int irq); 125 static int acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2); 126 127 /* Max wait time (in repetitions) for flags to clear in an RDT entry. */ 128 int apic_max_reps_clear_pending = 1000; 129 130 int apic_intr_policy = INTR_ROUND_ROBIN; 131 132 int apic_next_bind_cpu = 1; /* For round robin assignment */ 133 /* start with cpu 1 */ 134 135 /* 136 * If enabled, the distribution works as follows: 137 * On every interrupt entry, the current ipl for the CPU is set in cpu_info 138 * and the irq corresponding to the ipl is also set in the aci_current array. 139 * interrupt exit and setspl (due to soft interrupts) will cause the current 140 * ipl to be be changed. This is cache friendly as these frequently used 141 * paths write into a per cpu structure. 142 * 143 * Sampling is done by checking the structures for all CPUs and incrementing 144 * the busy field of the irq (if any) executing on each CPU and the busy field 145 * of the corresponding CPU. 146 * In periodic mode this is done on every clock interrupt. 147 * In one-shot mode, this is done thru a cyclic with an interval of 148 * apic_redistribute_sample_interval (default 10 milli sec). 149 * 150 * Every apic_sample_factor_redistribution times we sample, we do computations 151 * to decide which interrupt needs to be migrated (see comments 152 * before apic_intr_redistribute(). 153 */ 154 155 /* 156 * Following 3 variables start as % and can be patched or set using an 157 * API to be defined in future. They will be scaled to 158 * sample_factor_redistribution which is in turn set to hertz+1 (in periodic 159 * mode), or 101 in one-shot mode to stagger it away from one sec processing 160 */ 161 162 int apic_int_busy_mark = 60; 163 int apic_int_free_mark = 20; 164 int apic_diff_for_redistribution = 10; 165 166 /* sampling interval for interrupt redistribution for dynamic migration */ 167 int apic_redistribute_sample_interval = NANOSEC / 100; /* 10 millisec */ 168 169 /* 170 * number of times we sample before deciding to redistribute interrupts 171 * for dynamic migration 172 */ 173 int apic_sample_factor_redistribution = 101; 174 175 int apic_redist_cpu_skip = 0; 176 int apic_num_imbalance = 0; 177 int apic_num_rebind = 0; 178 179 /* 180 * Maximum number of APIC CPUs in the system, -1 indicates that dynamic 181 * allocation of CPU ids is disabled. 182 */ 183 int apic_max_nproc = -1; 184 int apic_nproc = 0; 185 size_t apic_cpus_size = 0; 186 int apic_defconf = 0; 187 int apic_irq_translate = 0; 188 int apic_spec_rev = 0; 189 int apic_imcrp = 0; 190 191 int apic_use_acpi = 1; /* 1 = use ACPI, 0 = don't use ACPI */ 192 int apic_use_acpi_madt_only = 0; /* 1=ONLY use MADT from ACPI */ 193 194 /* 195 * For interrupt link devices, if apic_unconditional_srs is set, an irq resource 196 * will be assigned (via _SRS). If it is not set, use the current 197 * irq setting (via _CRS), but only if that irq is in the set of possible 198 * irqs (returned by _PRS) for the device. 199 */ 200 int apic_unconditional_srs = 1; 201 202 /* 203 * For interrupt link devices, if apic_prefer_crs is set when we are 204 * assigning an IRQ resource to a device, prefer the current IRQ setting 205 * over other possible irq settings under same conditions. 206 */ 207 208 int apic_prefer_crs = 1; 209 210 uchar_t apic_io_id[MAX_IO_APIC]; 211 volatile uint32_t *apicioadr[MAX_IO_APIC]; 212 uchar_t apic_io_ver[MAX_IO_APIC]; 213 uchar_t apic_io_vectbase[MAX_IO_APIC]; 214 uchar_t apic_io_vectend[MAX_IO_APIC]; 215 uchar_t apic_reserved_irqlist[MAX_ISA_IRQ + 1]; 216 uint32_t apic_physaddr[MAX_IO_APIC]; 217 218 boolean_t ioapic_mask_workaround[MAX_IO_APIC]; 219 220 /* 221 * First available slot to be used as IRQ index into the apic_irq_table 222 * for those interrupts (like MSI/X) that don't have a physical IRQ. 223 */ 224 int apic_first_avail_irq = APIC_FIRST_FREE_IRQ; 225 226 /* 227 * apic_ioapic_lock protects the ioapics (reg select), the status, temp_bound 228 * and bound elements of cpus_info and the temp_cpu element of irq_struct 229 */ 230 lock_t apic_ioapic_lock; 231 232 int apic_io_max = 0; /* no. of i/o apics enabled */ 233 234 struct apic_io_intr *apic_io_intrp = NULL; 235 static struct apic_bus *apic_busp; 236 237 uchar_t apic_resv_vector[MAXIPL+1]; 238 239 char apic_level_intr[APIC_MAX_VECTOR+1]; 240 241 uint32_t eisa_level_intr_mask = 0; 242 /* At least MSB will be set if EISA bus */ 243 244 int apic_pci_bus_total = 0; 245 uchar_t apic_single_pci_busid = 0; 246 247 /* 248 * airq_mutex protects additions to the apic_irq_table - the first 249 * pointer and any airq_nexts off of that one. It also protects 250 * apic_max_device_irq & apic_min_device_irq. It also guarantees 251 * that share_id is unique as new ids are generated only when new 252 * irq_t structs are linked in. Once linked in the structs are never 253 * deleted. temp_cpu & mps_intr_index field indicate if it is programmed 254 * or allocated. Note that there is a slight gap between allocating in 255 * apic_introp_xlate and programming in addspl. 256 */ 257 kmutex_t airq_mutex; 258 apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1]; 259 int apic_max_device_irq = 0; 260 int apic_min_device_irq = APIC_MAX_VECTOR; 261 262 typedef struct prs_irq_list_ent { 263 int list_prio; 264 int32_t irq; 265 iflag_t intrflags; 266 acpi_prs_private_t prsprv; 267 struct prs_irq_list_ent *next; 268 } prs_irq_list_t; 269 270 271 /* 272 * ACPI variables 273 */ 274 /* 1 = acpi is enabled & working, 0 = acpi is not enabled or not there */ 275 int apic_enable_acpi = 0; 276 277 /* ACPI Multiple APIC Description Table ptr */ 278 static ACPI_TABLE_MADT *acpi_mapic_dtp = NULL; 279 280 /* ACPI Interrupt Source Override Structure ptr */ 281 ACPI_MADT_INTERRUPT_OVERRIDE *acpi_isop = NULL; 282 int acpi_iso_cnt = 0; 283 284 /* ACPI Non-maskable Interrupt Sources ptr */ 285 static ACPI_MADT_NMI_SOURCE *acpi_nmi_sp = NULL; 286 static int acpi_nmi_scnt = 0; 287 static ACPI_MADT_LOCAL_APIC_NMI *acpi_nmi_cp = NULL; 288 static int acpi_nmi_ccnt = 0; 289 290 static boolean_t acpi_found_smp_config = B_FALSE; 291 292 /* 293 * The following added to identify a software poweroff method if available. 294 */ 295 296 static struct { 297 int poweroff_method; 298 char oem_id[APIC_MPS_OEM_ID_LEN + 1]; /* MAX + 1 for NULL */ 299 char prod_id[APIC_MPS_PROD_ID_LEN + 1]; /* MAX + 1 for NULL */ 300 } apic_mps_ids[] = { 301 { APIC_POWEROFF_VIA_RTC, "INTEL", "ALDER" }, /* 4300 */ 302 { APIC_POWEROFF_VIA_RTC, "NCR", "AMC" }, /* 4300 */ 303 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "A450NX" }, /* 4400? */ 304 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AD450NX" }, /* 4400 */ 305 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AC450NX" }, /* 4400R */ 306 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "S450NX" }, /* S50 */ 307 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "SC450NX" } /* S50? */ 308 }; 309 310 int apic_poweroff_method = APIC_POWEROFF_NONE; 311 312 /* 313 * Auto-configuration routines 314 */ 315 316 /* 317 * Look at MPSpec 1.4 (Intel Order # 242016-005) for details of what we do here 318 * May work with 1.1 - but not guaranteed. 319 * According to the MP Spec, the MP floating pointer structure 320 * will be searched in the order described below: 321 * 1. In the first kilobyte of Extended BIOS Data Area (EBDA) 322 * 2. Within the last kilobyte of system base memory 323 * 3. In the BIOS ROM address space between 0F0000h and 0FFFFh 324 * Once we find the right signature with proper checksum, we call 325 * either handle_defconf or parse_mpct to get all info necessary for 326 * subsequent operations. 327 */ 328 int 329 apic_probe_common(char *modname) 330 { 331 uint32_t mpct_addr, ebda_start = 0, base_mem_end; 332 caddr_t biosdatap; 333 caddr_t mpct = 0; 334 caddr_t fptr; 335 int i, mpct_size, mapsize, retval = PSM_FAILURE; 336 ushort_t ebda_seg, base_mem_size; 337 struct apic_mpfps_hdr *fpsp; 338 struct apic_mp_cnf_hdr *hdrp; 339 int bypass_cpu_and_ioapics_in_mptables; 340 int acpi_user_options; 341 342 if (apic_forceload < 0) 343 return (retval); 344 345 /* 346 * Remember who we are 347 */ 348 psm_name = modname; 349 350 /* Allow override for MADT-only mode */ 351 acpi_user_options = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_root_node(), 0, 352 "acpi-user-options", 0); 353 apic_use_acpi_madt_only = ((acpi_user_options & ACPI_OUSER_MADT) != 0); 354 355 /* Allow apic_use_acpi to override MADT-only mode */ 356 if (!apic_use_acpi) 357 apic_use_acpi_madt_only = 0; 358 359 retval = acpi_probe(modname); 360 361 /* 362 * mapin the bios data area 40:0 363 * 40:13h - two-byte location reports the base memory size 364 * 40:0Eh - two-byte location for the exact starting address of 365 * the EBDA segment for EISA 366 */ 367 biosdatap = psm_map_phys(0x400, 0x20, PROT_READ); 368 if (!biosdatap) 369 goto apic_ret; 370 fpsp = (struct apic_mpfps_hdr *)NULL; 371 mapsize = MPFPS_RAM_WIN_LEN; 372 /*LINTED: pointer cast may result in improper alignment */ 373 ebda_seg = *((ushort_t *)(biosdatap+0xe)); 374 /* check the 1k of EBDA */ 375 if (ebda_seg) { 376 ebda_start = ((uint32_t)ebda_seg) << 4; 377 fptr = psm_map_phys(ebda_start, MPFPS_RAM_WIN_LEN, PROT_READ); 378 if (fptr) { 379 if (!(fpsp = 380 apic_find_fps_sig(fptr, MPFPS_RAM_WIN_LEN))) 381 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN); 382 } 383 } 384 /* If not in EBDA, check the last k of system base memory */ 385 if (!fpsp) { 386 /*LINTED: pointer cast may result in improper alignment */ 387 base_mem_size = *((ushort_t *)(biosdatap + 0x13)); 388 389 if (base_mem_size > 512) 390 base_mem_end = 639 * 1024; 391 else 392 base_mem_end = 511 * 1024; 393 /* if ebda == last k of base mem, skip to check BIOS ROM */ 394 if (base_mem_end != ebda_start) { 395 396 fptr = psm_map_phys(base_mem_end, MPFPS_RAM_WIN_LEN, 397 PROT_READ); 398 399 if (fptr) { 400 if (!(fpsp = apic_find_fps_sig(fptr, 401 MPFPS_RAM_WIN_LEN))) 402 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN); 403 } 404 } 405 } 406 psm_unmap_phys(biosdatap, 0x20); 407 408 /* If still cannot find it, check the BIOS ROM space */ 409 if (!fpsp) { 410 mapsize = MPFPS_ROM_WIN_LEN; 411 fptr = psm_map_phys(MPFPS_ROM_WIN_START, 412 MPFPS_ROM_WIN_LEN, PROT_READ); 413 if (fptr) { 414 if (!(fpsp = 415 apic_find_fps_sig(fptr, MPFPS_ROM_WIN_LEN))) { 416 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 417 goto apic_ret; 418 } 419 } 420 } 421 422 if (apic_checksum((caddr_t)fpsp, fpsp->mpfps_length * 16) != 0) { 423 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 424 goto apic_ret; 425 } 426 427 apic_spec_rev = fpsp->mpfps_spec_rev; 428 if ((apic_spec_rev != 04) && (apic_spec_rev != 01)) { 429 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN); 430 goto apic_ret; 431 } 432 433 /* check IMCR is present or not */ 434 apic_imcrp = fpsp->mpfps_featinfo2 & MPFPS_FEATINFO2_IMCRP; 435 436 /* check default configuration (dual CPUs) */ 437 if ((apic_defconf = fpsp->mpfps_featinfo1) != 0) { 438 psm_unmap_phys(fptr, mapsize); 439 if ((retval = apic_handle_defconf()) != PSM_SUCCESS) 440 return (retval); 441 442 goto apic_ret; 443 } 444 445 /* MP Configuration Table */ 446 mpct_addr = (uint32_t)(fpsp->mpfps_mpct_paddr); 447 448 psm_unmap_phys(fptr, mapsize); /* unmap floating ptr struct */ 449 450 /* 451 * Map in enough memory for the MP Configuration Table Header. 452 * Use this table to read the total length of the BIOS data and 453 * map in all the info 454 */ 455 /*LINTED: pointer cast may result in improper alignment */ 456 hdrp = (struct apic_mp_cnf_hdr *)psm_map_phys(mpct_addr, 457 sizeof (struct apic_mp_cnf_hdr), PROT_READ); 458 if (!hdrp) 459 goto apic_ret; 460 461 /* check mp configuration table signature PCMP */ 462 if (hdrp->mpcnf_sig != 0x504d4350) { 463 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr)); 464 goto apic_ret; 465 } 466 mpct_size = (int)hdrp->mpcnf_tbl_length; 467 468 apic_set_pwroff_method_from_mpcnfhdr(hdrp); 469 470 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr)); 471 472 if ((retval == PSM_SUCCESS) && !apic_use_acpi_madt_only) { 473 /* This is an ACPI machine No need for further checks */ 474 goto apic_ret; 475 } 476 477 /* 478 * Map in the entries for this machine, ie. Processor 479 * Entry Tables, Bus Entry Tables, etc. 480 * They are in fixed order following one another 481 */ 482 mpct = psm_map_phys(mpct_addr, mpct_size, PROT_READ); 483 if (!mpct) 484 goto apic_ret; 485 486 if (apic_checksum(mpct, mpct_size) != 0) 487 goto apic_fail1; 488 489 /*LINTED: pointer cast may result in improper alignment */ 490 hdrp = (struct apic_mp_cnf_hdr *)mpct; 491 apicadr = (uint32_t *)mapin_apic((uint32_t)hdrp->mpcnf_local_apic, 492 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE); 493 if (!apicadr) 494 goto apic_fail1; 495 496 /* Parse all information in the tables */ 497 bypass_cpu_and_ioapics_in_mptables = (retval == PSM_SUCCESS); 498 if (apic_parse_mpct(mpct, bypass_cpu_and_ioapics_in_mptables) == 499 PSM_SUCCESS) { 500 retval = PSM_SUCCESS; 501 goto apic_ret; 502 } 503 504 apic_fail1: 505 psm_unmap_phys(mpct, mpct_size); 506 mpct = NULL; 507 508 apic_ret: 509 if (retval == PSM_SUCCESS) { 510 extern int apic_ioapic_method_probe(); 511 512 if ((retval = apic_ioapic_method_probe()) == PSM_SUCCESS) 513 return (PSM_SUCCESS); 514 } 515 516 for (i = 0; i < apic_io_max; i++) 517 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN); 518 if (apic_cpus) { 519 kmem_free(apic_cpus, apic_cpus_size); 520 apic_cpus = NULL; 521 } 522 if (apicadr) { 523 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 524 apicadr = NULL; 525 } 526 if (mpct) 527 psm_unmap_phys(mpct, mpct_size); 528 529 return (retval); 530 } 531 532 static void 533 apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp) 534 { 535 int i; 536 537 for (i = 0; i < (sizeof (apic_mps_ids) / sizeof (apic_mps_ids[0])); 538 i++) { 539 if ((strncmp(hdrp->mpcnf_oem_str, apic_mps_ids[i].oem_id, 540 strlen(apic_mps_ids[i].oem_id)) == 0) && 541 (strncmp(hdrp->mpcnf_prod_str, apic_mps_ids[i].prod_id, 542 strlen(apic_mps_ids[i].prod_id)) == 0)) { 543 544 apic_poweroff_method = apic_mps_ids[i].poweroff_method; 545 break; 546 } 547 } 548 549 if (apic_debug_mps_id != 0) { 550 cmn_err(CE_CONT, "%s: MPS OEM ID = '%c%c%c%c%c%c%c%c'" 551 "Product ID = '%c%c%c%c%c%c%c%c%c%c%c%c'\n", 552 psm_name, 553 hdrp->mpcnf_oem_str[0], 554 hdrp->mpcnf_oem_str[1], 555 hdrp->mpcnf_oem_str[2], 556 hdrp->mpcnf_oem_str[3], 557 hdrp->mpcnf_oem_str[4], 558 hdrp->mpcnf_oem_str[5], 559 hdrp->mpcnf_oem_str[6], 560 hdrp->mpcnf_oem_str[7], 561 hdrp->mpcnf_prod_str[0], 562 hdrp->mpcnf_prod_str[1], 563 hdrp->mpcnf_prod_str[2], 564 hdrp->mpcnf_prod_str[3], 565 hdrp->mpcnf_prod_str[4], 566 hdrp->mpcnf_prod_str[5], 567 hdrp->mpcnf_prod_str[6], 568 hdrp->mpcnf_prod_str[7], 569 hdrp->mpcnf_prod_str[8], 570 hdrp->mpcnf_prod_str[9], 571 hdrp->mpcnf_prod_str[10], 572 hdrp->mpcnf_prod_str[11]); 573 } 574 } 575 576 static void 577 apic_free_apic_cpus(void) 578 { 579 if (apic_cpus != NULL) { 580 kmem_free(apic_cpus, apic_cpus_size); 581 apic_cpus = NULL; 582 apic_cpus_size = 0; 583 } 584 } 585 586 static int 587 acpi_probe(char *modname) 588 { 589 int i, intmax, index; 590 uint32_t id, ver; 591 int acpi_verboseflags = 0; 592 int madt_seen, madt_size; 593 ACPI_SUBTABLE_HEADER *ap; 594 ACPI_MADT_LOCAL_APIC *mpa; 595 ACPI_MADT_LOCAL_X2APIC *mpx2a; 596 ACPI_MADT_IO_APIC *mia; 597 ACPI_MADT_IO_SAPIC *misa; 598 ACPI_MADT_INTERRUPT_OVERRIDE *mio; 599 ACPI_MADT_NMI_SOURCE *mns; 600 ACPI_MADT_INTERRUPT_SOURCE *mis; 601 ACPI_MADT_LOCAL_APIC_NMI *mlan; 602 ACPI_MADT_LOCAL_X2APIC_NMI *mx2alan; 603 ACPI_MADT_LOCAL_APIC_OVERRIDE *mao; 604 int sci; 605 iflag_t sci_flags; 606 volatile uint32_t *ioapic; 607 int ioapic_ix; 608 uint32_t *local_ids; 609 uint32_t *proc_ids; 610 uchar_t hid; 611 int warned = 0; 612 613 if (!apic_use_acpi) 614 return (PSM_FAILURE); 615 616 if (AcpiGetTable(ACPI_SIG_MADT, 1, 617 (ACPI_TABLE_HEADER **) &acpi_mapic_dtp) != AE_OK) { 618 cmn_err(CE_WARN, "!acpi_probe: No MADT found!"); 619 return (PSM_FAILURE); 620 } 621 622 apicadr = mapin_apic((uint32_t)acpi_mapic_dtp->Address, 623 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE); 624 if (!apicadr) 625 return (PSM_FAILURE); 626 627 if ((local_ids = (uint32_t *)kmem_zalloc(NCPU * sizeof (uint32_t), 628 KM_NOSLEEP)) == NULL) 629 return (PSM_FAILURE); 630 631 if ((proc_ids = (uint32_t *)kmem_zalloc(NCPU * sizeof (uint32_t), 632 KM_NOSLEEP)) == NULL) { 633 kmem_free(local_ids, NCPU * sizeof (uint32_t)); 634 return (PSM_FAILURE); 635 } 636 637 id = apic_reg_ops->apic_read(APIC_LID_REG); 638 local_ids[0] = (uchar_t)(id >> 24); 639 apic_nproc = index = 1; 640 apic_io_max = 0; 641 642 ap = (ACPI_SUBTABLE_HEADER *) (acpi_mapic_dtp + 1); 643 madt_size = acpi_mapic_dtp->Header.Length; 644 madt_seen = sizeof (*acpi_mapic_dtp); 645 646 while (madt_seen < madt_size) { 647 switch (ap->Type) { 648 case ACPI_MADT_TYPE_LOCAL_APIC: 649 mpa = (ACPI_MADT_LOCAL_APIC *) ap; 650 if (mpa->LapicFlags & ACPI_MADT_ENABLED) { 651 if (mpa->Id == 255) { 652 cmn_err(CE_WARN, "!%s: encountered " 653 "invalid entry in MADT: CPU %d " 654 "has Local APIC Id equal to 255 ", 655 psm_name, mpa->ProcessorId); 656 } 657 if (mpa->Id == local_ids[0]) { 658 ASSERT(index == 1); 659 proc_ids[0] = mpa->ProcessorId; 660 } else if (apic_nproc < NCPU && use_mp && 661 apic_nproc < boot_ncpus) { 662 local_ids[index] = mpa->Id; 663 proc_ids[index] = mpa->ProcessorId; 664 index++; 665 apic_nproc++; 666 } else if (apic_nproc == NCPU && !warned) { 667 cmn_err(CE_WARN, "%s: CPU limit " 668 "exceeded" 669 #if !defined(__amd64) 670 " for 32-bit mode" 671 #endif 672 "; Solaris will use %d CPUs.", 673 psm_name, NCPU); 674 warned = 1; 675 } 676 } 677 break; 678 679 case ACPI_MADT_TYPE_IO_APIC: 680 mia = (ACPI_MADT_IO_APIC *) ap; 681 if (apic_io_max < MAX_IO_APIC) { 682 ioapic_ix = apic_io_max; 683 apic_io_id[apic_io_max] = mia->Id; 684 apic_io_vectbase[apic_io_max] = 685 mia->GlobalIrqBase; 686 apic_physaddr[apic_io_max] = 687 (uint32_t)mia->Address; 688 ioapic = apicioadr[apic_io_max] = 689 mapin_ioapic((uint32_t)mia->Address, 690 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 691 if (!ioapic) 692 goto cleanup; 693 ioapic_mask_workaround[apic_io_max] = 694 apic_is_ioapic_AMD_813x(mia->Address); 695 apic_io_max++; 696 } 697 break; 698 699 case ACPI_MADT_TYPE_INTERRUPT_OVERRIDE: 700 mio = (ACPI_MADT_INTERRUPT_OVERRIDE *) ap; 701 if (acpi_isop == NULL) 702 acpi_isop = mio; 703 acpi_iso_cnt++; 704 break; 705 706 case ACPI_MADT_TYPE_NMI_SOURCE: 707 /* UNIMPLEMENTED */ 708 mns = (ACPI_MADT_NMI_SOURCE *) ap; 709 if (acpi_nmi_sp == NULL) 710 acpi_nmi_sp = mns; 711 acpi_nmi_scnt++; 712 713 cmn_err(CE_NOTE, "!apic: nmi source: %d 0x%x\n", 714 mns->GlobalIrq, mns->IntiFlags); 715 break; 716 717 case ACPI_MADT_TYPE_LOCAL_APIC_NMI: 718 /* UNIMPLEMENTED */ 719 mlan = (ACPI_MADT_LOCAL_APIC_NMI *) ap; 720 if (acpi_nmi_cp == NULL) 721 acpi_nmi_cp = mlan; 722 acpi_nmi_ccnt++; 723 724 cmn_err(CE_NOTE, "!apic: local nmi: %d 0x%x %d\n", 725 mlan->ProcessorId, mlan->IntiFlags, 726 mlan->Lint); 727 break; 728 729 case ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE: 730 /* UNIMPLEMENTED */ 731 mao = (ACPI_MADT_LOCAL_APIC_OVERRIDE *) ap; 732 cmn_err(CE_NOTE, "!apic: address override: %lx\n", 733 (long)mao->Address); 734 break; 735 736 case ACPI_MADT_TYPE_IO_SAPIC: 737 /* UNIMPLEMENTED */ 738 misa = (ACPI_MADT_IO_SAPIC *) ap; 739 740 cmn_err(CE_NOTE, "!apic: io sapic: %d %d %lx\n", 741 misa->Id, misa->GlobalIrqBase, 742 (long)misa->Address); 743 break; 744 745 case ACPI_MADT_TYPE_INTERRUPT_SOURCE: 746 /* UNIMPLEMENTED */ 747 mis = (ACPI_MADT_INTERRUPT_SOURCE *) ap; 748 749 cmn_err(CE_NOTE, 750 "!apic: irq source: %d %d %d 0x%x %d %d\n", 751 mis->Id, mis->Eid, mis->GlobalIrq, 752 mis->IntiFlags, mis->Type, 753 mis->IoSapicVector); 754 break; 755 756 case ACPI_MADT_TYPE_LOCAL_X2APIC: 757 mpx2a = (ACPI_MADT_LOCAL_X2APIC *) ap; 758 759 /* 760 * All logical processors with APIC ID values 761 * of 255 and greater will have their APIC 762 * reported through Processor X2APIC structure. 763 * All logical processors with APIC ID less than 764 * 255 will have their APIC reported through 765 * Processor Local APIC. 766 * 767 * Some systems apparently don't care and report all 768 * processors through Processor X2APIC structures. We 769 * warn about that but don't ignore those CPUs. 770 */ 771 if (mpx2a->LocalApicId < 255) { 772 cmn_err(CE_WARN, "!%s: ignoring invalid entry " 773 "in MADT: CPU %d has X2APIC Id %d (< 255)", 774 psm_name, mpx2a->Uid, mpx2a->LocalApicId); 775 } 776 if (mpx2a->LapicFlags & ACPI_MADT_ENABLED) { 777 if (mpx2a->LocalApicId == local_ids[0]) { 778 ASSERT(index == 1); 779 proc_ids[0] = mpx2a->Uid; 780 } else if (apic_nproc < NCPU && use_mp && 781 apic_nproc < boot_ncpus) { 782 local_ids[index] = mpx2a->LocalApicId; 783 proc_ids[index] = mpx2a->Uid; 784 index++; 785 apic_nproc++; 786 } else if (apic_nproc == NCPU && !warned) { 787 cmn_err(CE_WARN, "%s: CPU limit " 788 "exceeded" 789 #if !defined(__amd64) 790 " for 32-bit mode" 791 #endif 792 "; Solaris will use %d CPUs.", 793 psm_name, NCPU); 794 warned = 1; 795 } 796 } 797 798 break; 799 800 case ACPI_MADT_TYPE_LOCAL_X2APIC_NMI: 801 /* UNIMPLEMENTED */ 802 mx2alan = (ACPI_MADT_LOCAL_X2APIC_NMI *) ap; 803 if (mx2alan->Uid >> 8) 804 acpi_nmi_ccnt++; 805 806 #ifdef DEBUG 807 cmn_err(CE_NOTE, 808 "!apic: local x2apic nmi: %d 0x%x %d\n", 809 mx2alan->Uid, mx2alan->IntiFlags, mx2alan->Lint); 810 #endif 811 812 break; 813 814 case ACPI_MADT_TYPE_RESERVED: 815 default: 816 break; 817 } 818 819 /* advance to next entry */ 820 madt_seen += ap->Length; 821 ap = (ACPI_SUBTABLE_HEADER *)(((char *)ap) + ap->Length); 822 } 823 824 /* We found multiple enabled cpus via MADT */ 825 if ((apic_nproc > 1) && (apic_io_max > 0)) { 826 acpi_found_smp_config = B_TRUE; 827 cmn_err(CE_NOTE, 828 "!apic: Using ACPI (MADT) for SMP configuration"); 829 } 830 831 /* 832 * allocate enough space for possible hot-adding of CPUs. 833 * max_ncpus may be less than apic_nproc if it's set by user. 834 */ 835 if (plat_dr_support_cpu()) { 836 apic_max_nproc = max_ncpus; 837 } 838 apic_cpus_size = max(apic_nproc, max_ncpus) * sizeof (*apic_cpus); 839 if ((apic_cpus = kmem_zalloc(apic_cpus_size, KM_NOSLEEP)) == NULL) 840 goto cleanup; 841 842 /* 843 * ACPI doesn't provide the local apic ver, get it directly from the 844 * local apic 845 */ 846 ver = apic_reg_ops->apic_read(APIC_VERS_REG); 847 for (i = 0; i < apic_nproc; i++) { 848 apic_cpus[i].aci_local_id = local_ids[i]; 849 apic_cpus[i].aci_local_ver = (uchar_t)(ver & 0xFF); 850 apic_cpus[i].aci_processor_id = proc_ids[i]; 851 /* Only build mapping info for CPUs present at boot. */ 852 if (i < boot_ncpus) 853 (void) acpica_map_cpu(i, proc_ids[i]); 854 } 855 856 /* 857 * To support CPU dynamic reconfiguration, the apic CPU info structure 858 * for each possible CPU will be pre-allocated at boot time. 859 * The state for each apic CPU info structure will be assigned according 860 * to the following rules: 861 * Rule 1: 862 * Slot index range: [0, min(apic_nproc, boot_ncpus)) 863 * State flags: 0 864 * Note: cpu exists and will be configured/enabled at boot time 865 * Rule 2: 866 * Slot index range: [boot_ncpus, apic_nproc) 867 * State flags: APIC_CPU_FREE | APIC_CPU_DIRTY 868 * Note: cpu exists but won't be configured/enabled at boot time 869 * Rule 3: 870 * Slot index range: [apic_nproc, boot_ncpus) 871 * State flags: APIC_CPU_FREE 872 * Note: cpu doesn't exist at boot time 873 * Rule 4: 874 * Slot index range: [max(apic_nproc, boot_ncpus), max_ncpus) 875 * State flags: APIC_CPU_FREE 876 * Note: cpu doesn't exist at boot time 877 */ 878 CPUSET_ZERO(apic_cpumask); 879 for (i = 0; i < min(boot_ncpus, apic_nproc); i++) { 880 CPUSET_ADD(apic_cpumask, i); 881 apic_cpus[i].aci_status = 0; 882 } 883 for (i = boot_ncpus; i < apic_nproc; i++) { 884 apic_cpus[i].aci_status = APIC_CPU_FREE | APIC_CPU_DIRTY; 885 } 886 for (i = apic_nproc; i < boot_ncpus; i++) { 887 apic_cpus[i].aci_status = APIC_CPU_FREE; 888 } 889 for (i = max(boot_ncpus, apic_nproc); i < max_ncpus; i++) { 890 apic_cpus[i].aci_status = APIC_CPU_FREE; 891 } 892 893 for (i = 0; i < apic_io_max; i++) { 894 ioapic_ix = i; 895 896 /* 897 * need to check Sitka on the following acpi problem 898 * On the Sitka, the ioapic's apic_id field isn't reporting 899 * the actual io apic id. We have reported this problem 900 * to Intel. Until they fix the problem, we will get the 901 * actual id directly from the ioapic. 902 */ 903 id = ioapic_read(ioapic_ix, APIC_ID_CMD); 904 hid = (uchar_t)(id >> 24); 905 906 if (hid != apic_io_id[i]) { 907 if (apic_io_id[i] == 0) 908 apic_io_id[i] = hid; 909 else { /* set ioapic id to whatever reported by ACPI */ 910 id = ((uint32_t)apic_io_id[i]) << 24; 911 ioapic_write(ioapic_ix, APIC_ID_CMD, id); 912 } 913 } 914 ver = ioapic_read(ioapic_ix, APIC_VERS_CMD); 915 apic_io_ver[i] = (uchar_t)(ver & 0xff); 916 intmax = (ver >> 16) & 0xff; 917 apic_io_vectend[i] = apic_io_vectbase[i] + intmax; 918 if (apic_first_avail_irq <= apic_io_vectend[i]) 919 apic_first_avail_irq = apic_io_vectend[i] + 1; 920 } 921 922 923 /* 924 * Process SCI configuration here 925 * An error may be returned here if 926 * acpi-user-options specifies legacy mode 927 * (no SCI, no ACPI mode) 928 */ 929 if (acpica_get_sci(&sci, &sci_flags) != AE_OK) 930 sci = -1; 931 932 /* 933 * Now call acpi_init() to generate namespaces 934 * If this fails, we don't attempt to use ACPI 935 * even if we were able to get a MADT above 936 */ 937 if (acpica_init() != AE_OK) { 938 cmn_err(CE_WARN, "!apic: Failed to initialize acpica!"); 939 goto cleanup; 940 } 941 942 /* 943 * Call acpica_build_processor_map() now that we have 944 * ACPI namesspace access 945 */ 946 (void) acpica_build_processor_map(); 947 948 /* 949 * Squirrel away the SCI and flags for later on 950 * in apic_picinit() when we're ready 951 */ 952 apic_sci_vect = sci; 953 apic_sci_flags = sci_flags; 954 955 if (apic_verbose & APIC_VERBOSE_IRQ_FLAG) 956 acpi_verboseflags |= PSM_VERBOSE_IRQ_FLAG; 957 958 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) 959 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_FLAG; 960 961 if (apic_verbose & APIC_VERBOSE_POWEROFF_PAUSE_FLAG) 962 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_PAUSE_FLAG; 963 964 if (acpi_psm_init(modname, acpi_verboseflags) == ACPI_PSM_FAILURE) 965 goto cleanup; 966 967 /* Enable ACPI APIC interrupt routing */ 968 if (apic_acpi_enter_apicmode() != PSM_FAILURE) { 969 cmn_err(CE_NOTE, "!apic: Using APIC interrupt routing mode"); 970 build_reserved_irqlist((uchar_t *)apic_reserved_irqlist); 971 apic_enable_acpi = 1; 972 if (apic_sci_vect > 0) { 973 acpica_set_core_feature(ACPI_FEATURE_SCI_EVENT); 974 } 975 if (apic_use_acpi_madt_only) { 976 cmn_err(CE_CONT, 977 "?Using ACPI for CPU/IOAPIC information ONLY\n"); 978 } 979 980 #if !defined(__xpv) 981 /* 982 * probe ACPI for hpet information here which is used later 983 * in apic_picinit(). 984 */ 985 if (hpet_acpi_init(&apic_hpet_vect, &apic_hpet_flags) < 0) { 986 cmn_err(CE_NOTE, "!ACPI HPET table query failed\n"); 987 } 988 #endif 989 990 kmem_free(local_ids, NCPU * sizeof (uint32_t)); 991 kmem_free(proc_ids, NCPU * sizeof (uint32_t)); 992 return (PSM_SUCCESS); 993 } 994 /* if setting APIC mode failed above, we fall through to cleanup */ 995 996 cleanup: 997 cmn_err(CE_WARN, "!apic: Failed acpi_probe, SMP config was %s", 998 acpi_found_smp_config ? "found" : "not found"); 999 apic_free_apic_cpus(); 1000 if (apicadr != NULL) { 1001 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 1002 apicadr = NULL; 1003 } 1004 apic_max_nproc = -1; 1005 apic_nproc = 0; 1006 for (i = 0; i < apic_io_max; i++) { 1007 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN); 1008 apicioadr[i] = NULL; 1009 } 1010 apic_io_max = 0; 1011 acpi_isop = NULL; 1012 acpi_iso_cnt = 0; 1013 acpi_nmi_sp = NULL; 1014 acpi_nmi_scnt = 0; 1015 acpi_nmi_cp = NULL; 1016 acpi_nmi_ccnt = 0; 1017 acpi_found_smp_config = B_FALSE; 1018 kmem_free(local_ids, NCPU * sizeof (uint32_t)); 1019 kmem_free(proc_ids, NCPU * sizeof (uint32_t)); 1020 return (PSM_FAILURE); 1021 } 1022 1023 /* 1024 * Handle default configuration. Fill in reqd global variables & tables 1025 * Fill all details as MP table does not give any more info 1026 */ 1027 static int 1028 apic_handle_defconf() 1029 { 1030 uint_t lid; 1031 1032 /* Failed to probe ACPI MADT tables, disable CPU DR. */ 1033 apic_max_nproc = -1; 1034 apic_free_apic_cpus(); 1035 plat_dr_disable_cpu(); 1036 1037 apicioadr[0] = (void *)mapin_ioapic(APIC_IO_ADDR, 1038 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 1039 apicadr = (void *)psm_map_phys(APIC_LOCAL_ADDR, 1040 APIC_LOCAL_MEMLEN, PROT_READ); 1041 apic_cpus_size = 2 * sizeof (*apic_cpus); 1042 apic_cpus = (apic_cpus_info_t *) 1043 kmem_zalloc(apic_cpus_size, KM_NOSLEEP); 1044 if ((!apicadr) || (!apicioadr[0]) || (!apic_cpus)) 1045 goto apic_handle_defconf_fail; 1046 CPUSET_ONLY(apic_cpumask, 0); 1047 CPUSET_ADD(apic_cpumask, 1); 1048 apic_nproc = 2; 1049 lid = apic_reg_ops->apic_read(APIC_LID_REG); 1050 apic_cpus[0].aci_local_id = (uchar_t)(lid >> APIC_ID_BIT_OFFSET); 1051 /* 1052 * According to the PC+MP spec 1.1, the local ids 1053 * for the default configuration has to be 0 or 1 1054 */ 1055 if (apic_cpus[0].aci_local_id == 1) 1056 apic_cpus[1].aci_local_id = 0; 1057 else if (apic_cpus[0].aci_local_id == 0) 1058 apic_cpus[1].aci_local_id = 1; 1059 else 1060 goto apic_handle_defconf_fail; 1061 1062 apic_io_id[0] = 2; 1063 apic_io_max = 1; 1064 if (apic_defconf >= 5) { 1065 apic_cpus[0].aci_local_ver = APIC_INTEGRATED_VERS; 1066 apic_cpus[1].aci_local_ver = APIC_INTEGRATED_VERS; 1067 apic_io_ver[0] = APIC_INTEGRATED_VERS; 1068 } else { 1069 apic_cpus[0].aci_local_ver = 0; /* 82489 DX */ 1070 apic_cpus[1].aci_local_ver = 0; 1071 apic_io_ver[0] = 0; 1072 } 1073 if (apic_defconf == 2 || apic_defconf == 3 || apic_defconf == 6) 1074 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) | 1075 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1); 1076 return (PSM_SUCCESS); 1077 1078 apic_handle_defconf_fail: 1079 if (apicadr) 1080 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN); 1081 if (apicioadr[0]) 1082 mapout_ioapic((caddr_t)apicioadr[0], APIC_IO_MEMLEN); 1083 return (PSM_FAILURE); 1084 } 1085 1086 /* Parse the entries in MP configuration table and collect info that we need */ 1087 static int 1088 apic_parse_mpct(caddr_t mpct, int bypass_cpus_and_ioapics) 1089 { 1090 struct apic_procent *procp; 1091 struct apic_bus *busp; 1092 struct apic_io_entry *ioapicp; 1093 struct apic_io_intr *intrp; 1094 int ioapic_ix; 1095 uint_t lid; 1096 uint32_t id; 1097 uchar_t hid; 1098 int warned = 0; 1099 1100 /*LINTED: pointer cast may result in improper alignment */ 1101 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr)); 1102 1103 /* No need to count cpu entries if we won't use them */ 1104 if (!bypass_cpus_and_ioapics) { 1105 1106 /* Find max # of CPUS and allocate structure accordingly */ 1107 apic_nproc = 0; 1108 CPUSET_ZERO(apic_cpumask); 1109 while (procp->proc_entry == APIC_CPU_ENTRY) { 1110 if (procp->proc_cpuflags & CPUFLAGS_EN) { 1111 if (apic_nproc < NCPU && use_mp && 1112 apic_nproc < boot_ncpus) { 1113 CPUSET_ADD(apic_cpumask, apic_nproc); 1114 apic_nproc++; 1115 } else if (apic_nproc == NCPU && !warned) { 1116 cmn_err(CE_WARN, "%s: CPU limit " 1117 "exceeded" 1118 #if !defined(__amd64) 1119 " for 32-bit mode" 1120 #endif 1121 "; Solaris will use %d CPUs.", 1122 psm_name, NCPU); 1123 warned = 1; 1124 } 1125 1126 } 1127 procp++; 1128 } 1129 apic_cpus_size = apic_nproc * sizeof (*apic_cpus); 1130 if (!apic_nproc || !(apic_cpus = (apic_cpus_info_t *) 1131 kmem_zalloc(apic_cpus_size, KM_NOSLEEP))) 1132 return (PSM_FAILURE); 1133 } 1134 1135 /*LINTED: pointer cast may result in improper alignment */ 1136 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr)); 1137 1138 /* 1139 * start with index 1 as 0 needs to be filled in with Boot CPU, but 1140 * if we're bypassing this information, it has already been filled 1141 * in by acpi_probe(), so don't overwrite it. 1142 */ 1143 if (!bypass_cpus_and_ioapics) 1144 apic_nproc = 1; 1145 1146 while (procp->proc_entry == APIC_CPU_ENTRY) { 1147 /* check whether the cpu exists or not */ 1148 if (!bypass_cpus_and_ioapics && 1149 procp->proc_cpuflags & CPUFLAGS_EN) { 1150 if (procp->proc_cpuflags & CPUFLAGS_BP) { /* Boot CPU */ 1151 lid = apic_reg_ops->apic_read(APIC_LID_REG); 1152 apic_cpus[0].aci_local_id = procp->proc_apicid; 1153 if (apic_cpus[0].aci_local_id != 1154 (uchar_t)(lid >> APIC_ID_BIT_OFFSET)) { 1155 return (PSM_FAILURE); 1156 } 1157 apic_cpus[0].aci_local_ver = 1158 procp->proc_version; 1159 } else if (apic_nproc < NCPU && use_mp && 1160 apic_nproc < boot_ncpus) { 1161 apic_cpus[apic_nproc].aci_local_id = 1162 procp->proc_apicid; 1163 1164 apic_cpus[apic_nproc].aci_local_ver = 1165 procp->proc_version; 1166 apic_nproc++; 1167 1168 } 1169 } 1170 procp++; 1171 } 1172 1173 /* 1174 * Save start of bus entries for later use. 1175 * Get EISA level cntrl if EISA bus is present. 1176 * Also get the CPI bus id for single CPI bus case 1177 */ 1178 apic_busp = busp = (struct apic_bus *)procp; 1179 while (busp->bus_entry == APIC_BUS_ENTRY) { 1180 lid = apic_find_bus_type((char *)&busp->bus_str1); 1181 if (lid == BUS_EISA) { 1182 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) | 1183 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1); 1184 } else if (lid == BUS_PCI) { 1185 /* 1186 * apic_single_pci_busid will be used only if 1187 * apic_pic_bus_total is equal to 1 1188 */ 1189 apic_pci_bus_total++; 1190 apic_single_pci_busid = busp->bus_id; 1191 } 1192 busp++; 1193 } 1194 1195 ioapicp = (struct apic_io_entry *)busp; 1196 1197 if (!bypass_cpus_and_ioapics) 1198 apic_io_max = 0; 1199 do { 1200 if (!bypass_cpus_and_ioapics && apic_io_max < MAX_IO_APIC) { 1201 if (ioapicp->io_flags & IOAPIC_FLAGS_EN) { 1202 apic_io_id[apic_io_max] = ioapicp->io_apicid; 1203 apic_io_ver[apic_io_max] = ioapicp->io_version; 1204 apicioadr[apic_io_max] = 1205 (void *)mapin_ioapic( 1206 (uint32_t)ioapicp->io_apic_addr, 1207 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE); 1208 1209 if (!apicioadr[apic_io_max]) 1210 return (PSM_FAILURE); 1211 1212 ioapic_mask_workaround[apic_io_max] = 1213 apic_is_ioapic_AMD_813x( 1214 ioapicp->io_apic_addr); 1215 1216 ioapic_ix = apic_io_max; 1217 id = ioapic_read(ioapic_ix, APIC_ID_CMD); 1218 hid = (uchar_t)(id >> 24); 1219 1220 if (hid != apic_io_id[apic_io_max]) { 1221 if (apic_io_id[apic_io_max] == 0) 1222 apic_io_id[apic_io_max] = hid; 1223 else { 1224 /* 1225 * set ioapic id to whatever 1226 * reported by MPS 1227 * 1228 * may not need to set index 1229 * again ??? 1230 * take it out and try 1231 */ 1232 1233 id = ((uint32_t) 1234 apic_io_id[apic_io_max]) << 1235 24; 1236 1237 ioapic_write(ioapic_ix, 1238 APIC_ID_CMD, id); 1239 } 1240 } 1241 apic_io_max++; 1242 } 1243 } 1244 ioapicp++; 1245 } while (ioapicp->io_entry == APIC_IO_ENTRY); 1246 1247 apic_io_intrp = (struct apic_io_intr *)ioapicp; 1248 1249 intrp = apic_io_intrp; 1250 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 1251 if ((intrp->intr_irq > APIC_MAX_ISA_IRQ) || 1252 (apic_find_bus(intrp->intr_busid) == BUS_PCI)) { 1253 apic_irq_translate = 1; 1254 break; 1255 } 1256 intrp++; 1257 } 1258 1259 return (PSM_SUCCESS); 1260 } 1261 1262 boolean_t 1263 apic_cpu_in_range(int cpu) 1264 { 1265 cpu &= ~IRQ_USER_BOUND; 1266 /* Check whether cpu id is in valid range. */ 1267 if (cpu < 0 || cpu >= apic_nproc) { 1268 return (B_FALSE); 1269 } else if (apic_max_nproc != -1 && cpu >= apic_max_nproc) { 1270 /* 1271 * Check whether cpuid is in valid range if CPU DR is enabled. 1272 */ 1273 return (B_FALSE); 1274 } else if (!CPU_IN_SET(apic_cpumask, cpu)) { 1275 return (B_FALSE); 1276 } 1277 1278 return (B_TRUE); 1279 } 1280 1281 processorid_t 1282 apic_get_next_bind_cpu(void) 1283 { 1284 int i, count; 1285 processorid_t cpuid = 0; 1286 1287 for (count = 0; count < apic_nproc; count++) { 1288 if (apic_next_bind_cpu >= apic_nproc) { 1289 apic_next_bind_cpu = 0; 1290 } 1291 i = apic_next_bind_cpu++; 1292 if (apic_cpu_in_range(i)) { 1293 cpuid = i; 1294 break; 1295 } 1296 } 1297 1298 return (cpuid); 1299 } 1300 1301 uint16_t 1302 apic_get_apic_version() 1303 { 1304 int i; 1305 uchar_t min_io_apic_ver = 0; 1306 static uint16_t version; /* Cache as value is constant */ 1307 static boolean_t found = B_FALSE; /* Accomodate zero version */ 1308 1309 if (found == B_FALSE) { 1310 found = B_TRUE; 1311 1312 /* 1313 * Don't assume all IO APICs in the system are the same. 1314 * 1315 * Set to the minimum version. 1316 */ 1317 for (i = 0; i < apic_io_max; i++) { 1318 if ((apic_io_ver[i] != 0) && 1319 ((min_io_apic_ver == 0) || 1320 (min_io_apic_ver >= apic_io_ver[i]))) 1321 min_io_apic_ver = apic_io_ver[i]; 1322 } 1323 1324 /* Assume all local APICs are of the same version. */ 1325 version = (min_io_apic_ver << 8) | apic_cpus[0].aci_local_ver; 1326 } 1327 return (version); 1328 } 1329 1330 static struct apic_mpfps_hdr * 1331 apic_find_fps_sig(caddr_t cptr, int len) 1332 { 1333 int i; 1334 1335 /* Look for the pattern "_MP_" */ 1336 for (i = 0; i < len; i += 16) { 1337 if ((*(cptr+i) == '_') && 1338 (*(cptr+i+1) == 'M') && 1339 (*(cptr+i+2) == 'P') && 1340 (*(cptr+i+3) == '_')) 1341 /*LINTED: pointer cast may result in improper alignment */ 1342 return ((struct apic_mpfps_hdr *)(cptr + i)); 1343 } 1344 return (NULL); 1345 } 1346 1347 static int 1348 apic_checksum(caddr_t bptr, int len) 1349 { 1350 int i; 1351 uchar_t cksum; 1352 1353 cksum = 0; 1354 for (i = 0; i < len; i++) 1355 cksum += *bptr++; 1356 return ((int)cksum); 1357 } 1358 1359 /* 1360 * On machines with PCI-PCI bridges, a device behind a PCI-PCI bridge 1361 * needs special handling. We may need to chase up the device tree, 1362 * using the PCI-PCI Bridge specification's "rotating IPIN assumptions", 1363 * to find the IPIN at the root bus that relates to the IPIN on the 1364 * subsidiary bus (for ACPI or MP). We may, however, have an entry 1365 * in the MP table or the ACPI namespace for this device itself. 1366 * We handle both cases in the search below. 1367 */ 1368 /* this is the non-acpi version */ 1369 int 1370 apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, int child_ipin, 1371 struct apic_io_intr **intrp) 1372 { 1373 dev_info_t *dipp, *dip; 1374 int pci_irq; 1375 ddi_acc_handle_t cfg_handle; 1376 int bridge_devno, bridge_bus; 1377 int ipin; 1378 1379 dip = idip; 1380 1381 /*CONSTCOND*/ 1382 while (1) { 1383 if (((dipp = ddi_get_parent(dip)) == (dev_info_t *)NULL) || 1384 (pci_config_setup(dipp, &cfg_handle) != DDI_SUCCESS)) 1385 return (-1); 1386 if ((pci_config_get8(cfg_handle, PCI_CONF_BASCLASS) == 1387 PCI_CLASS_BRIDGE) && (pci_config_get8(cfg_handle, 1388 PCI_CONF_SUBCLASS) == PCI_BRIDGE_PCI)) { 1389 pci_config_teardown(&cfg_handle); 1390 if (acpica_get_bdf(dipp, &bridge_bus, &bridge_devno, 1391 NULL) != 0) 1392 return (-1); 1393 /* 1394 * This is the rotating scheme documented in the 1395 * PCI-to-PCI spec. If the PCI-to-PCI bridge is 1396 * behind another PCI-to-PCI bridge, then it needs 1397 * to keep ascending until an interrupt entry is 1398 * found or the root is reached. 1399 */ 1400 ipin = (child_devno + child_ipin) % PCI_INTD; 1401 if (bridge_bus == 0 && apic_pci_bus_total == 1) 1402 bridge_bus = (int)apic_single_pci_busid; 1403 pci_irq = ((bridge_devno & 0x1f) << 2) | 1404 (ipin & 0x3); 1405 if ((*intrp = apic_find_io_intr_w_busid(pci_irq, 1406 bridge_bus)) != NULL) { 1407 return (pci_irq); 1408 } 1409 dip = dipp; 1410 child_devno = bridge_devno; 1411 child_ipin = ipin; 1412 } else { 1413 pci_config_teardown(&cfg_handle); 1414 return (-1); 1415 } 1416 } 1417 /*LINTED: function will not fall off the bottom */ 1418 } 1419 1420 uchar_t 1421 acpi_find_ioapic(int irq) 1422 { 1423 int i; 1424 1425 for (i = 0; i < apic_io_max; i++) { 1426 if (irq >= apic_io_vectbase[i] && irq <= apic_io_vectend[i]) 1427 return ((uchar_t)i); 1428 } 1429 return (0xFF); /* shouldn't happen */ 1430 } 1431 1432 /* 1433 * See if two irqs are compatible for sharing a vector. 1434 * Currently we only support sharing of PCI devices. 1435 */ 1436 static int 1437 acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2) 1438 { 1439 uint_t level1, po1; 1440 uint_t level2, po2; 1441 1442 /* Assume active high by default */ 1443 po1 = 0; 1444 po2 = 0; 1445 1446 if (iflag1.bustype != iflag2.bustype || iflag1.bustype != BUS_PCI) 1447 return (0); 1448 1449 if (iflag1.intr_el == INTR_EL_CONFORM) 1450 level1 = AV_LEVEL; 1451 else 1452 level1 = (iflag1.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0; 1453 1454 if (level1 && ((iflag1.intr_po == INTR_PO_ACTIVE_LOW) || 1455 (iflag1.intr_po == INTR_PO_CONFORM))) 1456 po1 = AV_ACTIVE_LOW; 1457 1458 if (iflag2.intr_el == INTR_EL_CONFORM) 1459 level2 = AV_LEVEL; 1460 else 1461 level2 = (iflag2.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0; 1462 1463 if (level2 && ((iflag2.intr_po == INTR_PO_ACTIVE_LOW) || 1464 (iflag2.intr_po == INTR_PO_CONFORM))) 1465 po2 = AV_ACTIVE_LOW; 1466 1467 if ((level1 == level2) && (po1 == po2)) 1468 return (1); 1469 1470 return (0); 1471 } 1472 1473 struct apic_io_intr * 1474 apic_find_io_intr_w_busid(int irqno, int busid) 1475 { 1476 struct apic_io_intr *intrp; 1477 1478 /* 1479 * It can have more than 1 entry with same source bus IRQ, 1480 * but unique with the source bus id 1481 */ 1482 intrp = apic_io_intrp; 1483 if (intrp != NULL) { 1484 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 1485 if (intrp->intr_irq == irqno && 1486 intrp->intr_busid == busid && 1487 intrp->intr_type == IO_INTR_INT) 1488 return (intrp); 1489 intrp++; 1490 } 1491 } 1492 APIC_VERBOSE_IOAPIC((CE_NOTE, "Did not find io intr for irqno:" 1493 "busid %x:%x\n", irqno, busid)); 1494 return ((struct apic_io_intr *)NULL); 1495 } 1496 1497 1498 struct mps_bus_info { 1499 char *bus_name; 1500 int bus_id; 1501 } bus_info_array[] = { 1502 "ISA ", BUS_ISA, 1503 "PCI ", BUS_PCI, 1504 "EISA ", BUS_EISA, 1505 "XPRESS", BUS_XPRESS, 1506 "PCMCIA", BUS_PCMCIA, 1507 "VL ", BUS_VL, 1508 "CBUS ", BUS_CBUS, 1509 "CBUSII", BUS_CBUSII, 1510 "FUTURE", BUS_FUTURE, 1511 "INTERN", BUS_INTERN, 1512 "MBI ", BUS_MBI, 1513 "MBII ", BUS_MBII, 1514 "MPI ", BUS_MPI, 1515 "MPSA ", BUS_MPSA, 1516 "NUBUS ", BUS_NUBUS, 1517 "TC ", BUS_TC, 1518 "VME ", BUS_VME, 1519 "PCI-E ", BUS_PCIE 1520 }; 1521 1522 static int 1523 apic_find_bus_type(char *bus) 1524 { 1525 int i = 0; 1526 1527 for (; i < sizeof (bus_info_array)/sizeof (struct mps_bus_info); i++) 1528 if (strncmp(bus, bus_info_array[i].bus_name, 1529 strlen(bus_info_array[i].bus_name)) == 0) 1530 return (bus_info_array[i].bus_id); 1531 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus type for bus %s", bus)); 1532 return (0); 1533 } 1534 1535 static int 1536 apic_find_bus(int busid) 1537 { 1538 struct apic_bus *busp; 1539 1540 busp = apic_busp; 1541 while (busp->bus_entry == APIC_BUS_ENTRY) { 1542 if (busp->bus_id == busid) 1543 return (apic_find_bus_type((char *)&busp->bus_str1)); 1544 busp++; 1545 } 1546 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus for bus id %x", busid)); 1547 return (0); 1548 } 1549 1550 int 1551 apic_find_bus_id(int bustype) 1552 { 1553 struct apic_bus *busp; 1554 1555 busp = apic_busp; 1556 while (busp->bus_entry == APIC_BUS_ENTRY) { 1557 if (apic_find_bus_type((char *)&busp->bus_str1) == bustype) 1558 return (busp->bus_id); 1559 busp++; 1560 } 1561 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus id for bustype %x", 1562 bustype)); 1563 return (-1); 1564 } 1565 1566 /* 1567 * Check if a particular irq need to be reserved for any io_intr 1568 */ 1569 static struct apic_io_intr * 1570 apic_find_io_intr(int irqno) 1571 { 1572 struct apic_io_intr *intrp; 1573 1574 intrp = apic_io_intrp; 1575 if (intrp != NULL) { 1576 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) { 1577 if (intrp->intr_irq == irqno && 1578 intrp->intr_type == IO_INTR_INT) 1579 return (intrp); 1580 intrp++; 1581 } 1582 } 1583 return ((struct apic_io_intr *)NULL); 1584 } 1585 1586 /* 1587 * Check if the given ioapicindex intin combination has already been assigned 1588 * an irq. If so return irqno. Else -1 1589 */ 1590 int 1591 apic_find_intin(uchar_t ioapic, uchar_t intin) 1592 { 1593 apic_irq_t *irqptr; 1594 int i; 1595 1596 /* find ioapic and intin in the apic_irq_table[] and return the index */ 1597 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) { 1598 irqptr = apic_irq_table[i]; 1599 while (irqptr) { 1600 if ((irqptr->airq_mps_intr_index >= 0) && 1601 (irqptr->airq_intin_no == intin) && 1602 (irqptr->airq_ioapicindex == ioapic)) { 1603 APIC_VERBOSE_IOAPIC((CE_NOTE, "!Found irq " 1604 "entry for ioapic:intin %x:%x " 1605 "shared interrupts ?", ioapic, intin)); 1606 return (i); 1607 } 1608 irqptr = irqptr->airq_next; 1609 } 1610 } 1611 return (-1); 1612 } 1613 1614 int 1615 apic_allocate_irq(int irq) 1616 { 1617 int freeirq, i; 1618 1619 if ((freeirq = apic_find_free_irq(irq, (APIC_RESV_IRQ - 1))) == -1) 1620 if ((freeirq = apic_find_free_irq(APIC_FIRST_FREE_IRQ, 1621 (irq - 1))) == -1) { 1622 /* 1623 * if BIOS really defines every single irq in the mps 1624 * table, then don't worry about conflicting with 1625 * them, just use any free slot in apic_irq_table 1626 */ 1627 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) { 1628 if ((apic_irq_table[i] == NULL) || 1629 apic_irq_table[i]->airq_mps_intr_index == 1630 FREE_INDEX) { 1631 freeirq = i; 1632 break; 1633 } 1634 } 1635 if (freeirq == -1) { 1636 /* This shouldn't happen, but just in case */ 1637 cmn_err(CE_WARN, "%s: NO available IRQ", psm_name); 1638 return (-1); 1639 } 1640 } 1641 if (apic_irq_table[freeirq] == NULL) { 1642 apic_irq_table[freeirq] = 1643 kmem_zalloc(sizeof (apic_irq_t), KM_NOSLEEP); 1644 if (apic_irq_table[freeirq] == NULL) { 1645 cmn_err(CE_WARN, "%s: NO memory to allocate IRQ", 1646 psm_name); 1647 return (-1); 1648 } 1649 apic_irq_table[freeirq]->airq_temp_cpu = IRQ_UNINIT; 1650 apic_irq_table[freeirq]->airq_mps_intr_index = FREE_INDEX; 1651 } 1652 return (freeirq); 1653 } 1654 1655 static int 1656 apic_find_free_irq(int start, int end) 1657 { 1658 int i; 1659 1660 for (i = start; i <= end; i++) 1661 /* Check if any I/O entry needs this IRQ */ 1662 if (apic_find_io_intr(i) == NULL) { 1663 /* Then see if it is free */ 1664 if ((apic_irq_table[i] == NULL) || 1665 (apic_irq_table[i]->airq_mps_intr_index == 1666 FREE_INDEX)) { 1667 return (i); 1668 } 1669 } 1670 return (-1); 1671 } 1672 1673 /* 1674 * compute the polarity, trigger mode and vector for programming into 1675 * the I/O apic and record in airq_rdt_entry. 1676 */ 1677 void 1678 apic_record_rdt_entry(apic_irq_t *irqptr, int irq) 1679 { 1680 int ioapicindex, bus_type, vector; 1681 short intr_index; 1682 uint_t level, po, io_po; 1683 struct apic_io_intr *iointrp; 1684 1685 intr_index = irqptr->airq_mps_intr_index; 1686 DDI_INTR_IMPLDBG((CE_CONT, "apic_record_rdt_entry: intr_index=%d " 1687 "irq = 0x%x dip = 0x%p vector = 0x%x\n", intr_index, irq, 1688 (void *)irqptr->airq_dip, irqptr->airq_vector)); 1689 1690 if (intr_index == RESERVE_INDEX) { 1691 apic_error |= APIC_ERR_INVALID_INDEX; 1692 return; 1693 } else if (APIC_IS_MSI_OR_MSIX_INDEX(intr_index)) { 1694 return; 1695 } 1696 1697 vector = irqptr->airq_vector; 1698 ioapicindex = irqptr->airq_ioapicindex; 1699 /* Assume edge triggered by default */ 1700 level = 0; 1701 /* Assume active high by default */ 1702 po = 0; 1703 1704 if (intr_index == DEFAULT_INDEX || intr_index == FREE_INDEX) { 1705 ASSERT(irq < 16); 1706 if (eisa_level_intr_mask & (1 << irq)) 1707 level = AV_LEVEL; 1708 if (intr_index == FREE_INDEX && apic_defconf == 0) 1709 apic_error |= APIC_ERR_INVALID_INDEX; 1710 } else if (intr_index == ACPI_INDEX) { 1711 bus_type = irqptr->airq_iflag.bustype; 1712 if (irqptr->airq_iflag.intr_el == INTR_EL_CONFORM) { 1713 if (bus_type == BUS_PCI) 1714 level = AV_LEVEL; 1715 } else 1716 level = (irqptr->airq_iflag.intr_el == INTR_EL_LEVEL) ? 1717 AV_LEVEL : 0; 1718 if (level && 1719 ((irqptr->airq_iflag.intr_po == INTR_PO_ACTIVE_LOW) || 1720 (irqptr->airq_iflag.intr_po == INTR_PO_CONFORM && 1721 bus_type == BUS_PCI))) 1722 po = AV_ACTIVE_LOW; 1723 } else { 1724 iointrp = apic_io_intrp + intr_index; 1725 bus_type = apic_find_bus(iointrp->intr_busid); 1726 if (iointrp->intr_el == INTR_EL_CONFORM) { 1727 if ((irq < 16) && (eisa_level_intr_mask & (1 << irq))) 1728 level = AV_LEVEL; 1729 else if (bus_type == BUS_PCI) 1730 level = AV_LEVEL; 1731 } else 1732 level = (iointrp->intr_el == INTR_EL_LEVEL) ? 1733 AV_LEVEL : 0; 1734 if (level && ((iointrp->intr_po == INTR_PO_ACTIVE_LOW) || 1735 (iointrp->intr_po == INTR_PO_CONFORM && 1736 bus_type == BUS_PCI))) 1737 po = AV_ACTIVE_LOW; 1738 } 1739 if (level) 1740 apic_level_intr[irq] = 1; 1741 /* 1742 * The 82489DX External APIC cannot do active low polarity interrupts. 1743 */ 1744 if (po && (apic_io_ver[ioapicindex] != IOAPIC_VER_82489DX)) 1745 io_po = po; 1746 else 1747 io_po = 0; 1748 1749 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) 1750 prom_printf("setio: ioapic=0x%x intin=0x%x level=0x%x po=0x%x " 1751 "vector=0x%x cpu=0x%x\n\n", ioapicindex, 1752 irqptr->airq_intin_no, level, io_po, vector, 1753 irqptr->airq_cpu); 1754 1755 irqptr->airq_rdt_entry = level|io_po|vector; 1756 } 1757 1758 int 1759 apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid, 1760 int ipin, int *pci_irqp, iflag_t *intr_flagp) 1761 { 1762 1763 int status; 1764 acpi_psm_lnk_t acpipsmlnk; 1765 1766 if ((status = acpi_get_irq_cache_ent(busid, devid, ipin, pci_irqp, 1767 intr_flagp)) == ACPI_PSM_SUCCESS) { 1768 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Found irqno %d " 1769 "from cache for device %s, instance #%d\n", psm_name, 1770 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip))); 1771 return (status); 1772 } 1773 1774 bzero(&acpipsmlnk, sizeof (acpi_psm_lnk_t)); 1775 1776 if ((status = acpi_translate_pci_irq(dip, ipin, pci_irqp, intr_flagp, 1777 &acpipsmlnk)) == ACPI_PSM_FAILURE) { 1778 APIC_VERBOSE_IRQ((CE_WARN, "%s: " 1779 " acpi_translate_pci_irq failed for device %s, instance" 1780 " #%d", psm_name, ddi_get_name(dip), 1781 ddi_get_instance(dip))); 1782 return (status); 1783 } 1784 1785 if (status == ACPI_PSM_PARTIAL && acpipsmlnk.lnkobj != NULL) { 1786 status = apic_acpi_irq_configure(&acpipsmlnk, dip, pci_irqp, 1787 intr_flagp); 1788 if (status != ACPI_PSM_SUCCESS) { 1789 status = acpi_get_current_irq_resource(&acpipsmlnk, 1790 pci_irqp, intr_flagp); 1791 } 1792 } 1793 1794 if (status == ACPI_PSM_SUCCESS) { 1795 acpi_new_irq_cache_ent(busid, devid, ipin, *pci_irqp, 1796 intr_flagp, &acpipsmlnk); 1797 1798 APIC_VERBOSE_IRQ((CE_CONT, "%s: [ACPI] " 1799 "new irq %d for device %s, instance #%d\n", psm_name, 1800 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip))); 1801 } 1802 1803 return (status); 1804 } 1805 1806 /* 1807 * Adds an entry to the irq list passed in, and returns the new list. 1808 * Entries are added in priority order (lower numerical priorities are 1809 * placed closer to the head of the list) 1810 */ 1811 static prs_irq_list_t * 1812 acpi_insert_prs_irq_ent(prs_irq_list_t *listp, int priority, int irq, 1813 iflag_t *iflagp, acpi_prs_private_t *prsprvp) 1814 { 1815 struct prs_irq_list_ent *newent, *prevp = NULL, *origlistp; 1816 1817 newent = kmem_zalloc(sizeof (struct prs_irq_list_ent), KM_SLEEP); 1818 1819 newent->list_prio = priority; 1820 newent->irq = irq; 1821 newent->intrflags = *iflagp; 1822 newent->prsprv = *prsprvp; 1823 /* ->next is NULL from kmem_zalloc */ 1824 1825 /* 1826 * New list -- return the new entry as the list. 1827 */ 1828 if (listp == NULL) 1829 return (newent); 1830 1831 /* 1832 * Save original list pointer for return (since we're not modifying 1833 * the head) 1834 */ 1835 origlistp = listp; 1836 1837 /* 1838 * Insertion sort, with entries with identical keys stored AFTER 1839 * existing entries (the less-than-or-equal test of priority does 1840 * this for us). 1841 */ 1842 while (listp != NULL && listp->list_prio <= priority) { 1843 prevp = listp; 1844 listp = listp->next; 1845 } 1846 1847 newent->next = listp; 1848 1849 if (prevp == NULL) { /* Add at head of list (newent is the new head) */ 1850 return (newent); 1851 } else { 1852 prevp->next = newent; 1853 return (origlistp); 1854 } 1855 } 1856 1857 /* 1858 * Frees the list passed in, deallocating all memory and leaving *listpp 1859 * set to NULL. 1860 */ 1861 static void 1862 acpi_destroy_prs_irq_list(prs_irq_list_t **listpp) 1863 { 1864 struct prs_irq_list_ent *nextp; 1865 1866 ASSERT(listpp != NULL); 1867 1868 while (*listpp != NULL) { 1869 nextp = (*listpp)->next; 1870 kmem_free(*listpp, sizeof (struct prs_irq_list_ent)); 1871 *listpp = nextp; 1872 } 1873 } 1874 1875 /* 1876 * apic_choose_irqs_from_prs returns a list of irqs selected from the list of 1877 * irqs returned by the link device's _PRS method. The irqs are chosen 1878 * to minimize contention in situations where the interrupt link device 1879 * can be programmed to steer interrupts to different interrupt controller 1880 * inputs (some of which may already be in use). The list is sorted in order 1881 * of irqs to use, with the highest priority given to interrupt controller 1882 * inputs that are not shared. When an interrupt controller input 1883 * must be shared, apic_choose_irqs_from_prs adds the possible irqs to the 1884 * returned list in the order that minimizes sharing (thereby ensuring lowest 1885 * possible latency from interrupt trigger time to ISR execution time). 1886 */ 1887 static prs_irq_list_t * 1888 apic_choose_irqs_from_prs(acpi_irqlist_t *irqlistent, dev_info_t *dip, 1889 int crs_irq) 1890 { 1891 int32_t irq; 1892 int i; 1893 prs_irq_list_t *prsirqlistp = NULL; 1894 iflag_t iflags; 1895 1896 while (irqlistent != NULL) { 1897 irqlistent->intr_flags.bustype = BUS_PCI; 1898 1899 for (i = 0; i < irqlistent->num_irqs; i++) { 1900 1901 irq = irqlistent->irqs[i]; 1902 1903 if (irq <= 0) { 1904 /* invalid irq number */ 1905 continue; 1906 } 1907 1908 if ((irq < 16) && (apic_reserved_irqlist[irq])) 1909 continue; 1910 1911 if ((apic_irq_table[irq] == NULL) || 1912 (apic_irq_table[irq]->airq_dip == dip)) { 1913 1914 prsirqlistp = acpi_insert_prs_irq_ent( 1915 prsirqlistp, 0 /* Highest priority */, irq, 1916 &irqlistent->intr_flags, 1917 &irqlistent->acpi_prs_prv); 1918 1919 /* 1920 * If we do not prefer the current irq from _CRS 1921 * or if we do and this irq is the same as the 1922 * current irq from _CRS, this is the one 1923 * to pick. 1924 */ 1925 if (!(apic_prefer_crs) || (irq == crs_irq)) { 1926 return (prsirqlistp); 1927 } 1928 continue; 1929 } 1930 1931 /* 1932 * Edge-triggered interrupts cannot be shared 1933 */ 1934 if (irqlistent->intr_flags.intr_el == INTR_EL_EDGE) 1935 continue; 1936 1937 /* 1938 * To work around BIOSes that contain incorrect 1939 * interrupt polarity information in interrupt 1940 * descriptors returned by _PRS, we assume that 1941 * the polarity of the other device sharing this 1942 * interrupt controller input is compatible. 1943 * If it's not, the caller will catch it when 1944 * the caller invokes the link device's _CRS method 1945 * (after invoking its _SRS method). 1946 */ 1947 iflags = irqlistent->intr_flags; 1948 iflags.intr_po = 1949 apic_irq_table[irq]->airq_iflag.intr_po; 1950 1951 if (!acpi_intr_compatible(iflags, 1952 apic_irq_table[irq]->airq_iflag)) { 1953 APIC_VERBOSE_IRQ((CE_CONT, "!%s: irq %d " 1954 "not compatible [%x:%x:%x !~ %x:%x:%x]", 1955 psm_name, irq, 1956 iflags.intr_po, 1957 iflags.intr_el, 1958 iflags.bustype, 1959 apic_irq_table[irq]->airq_iflag.intr_po, 1960 apic_irq_table[irq]->airq_iflag.intr_el, 1961 apic_irq_table[irq]->airq_iflag.bustype)); 1962 continue; 1963 } 1964 1965 /* 1966 * If we prefer the irq from _CRS, no need 1967 * to search any further (and make sure 1968 * to add this irq with the highest priority 1969 * so it's tried first). 1970 */ 1971 if (crs_irq == irq && apic_prefer_crs) { 1972 1973 return (acpi_insert_prs_irq_ent( 1974 prsirqlistp, 1975 0 /* Highest priority */, 1976 irq, &iflags, 1977 &irqlistent->acpi_prs_prv)); 1978 } 1979 1980 /* 1981 * Priority is equal to the share count (lower 1982 * share count is higher priority). Note that 1983 * the intr flags passed in here are the ones we 1984 * changed above -- if incorrect, it will be 1985 * caught by the caller's _CRS flags comparison. 1986 */ 1987 prsirqlistp = acpi_insert_prs_irq_ent( 1988 prsirqlistp, 1989 apic_irq_table[irq]->airq_share, irq, 1990 &iflags, &irqlistent->acpi_prs_prv); 1991 } 1992 1993 /* Go to the next irqlist entry */ 1994 irqlistent = irqlistent->next; 1995 } 1996 1997 return (prsirqlistp); 1998 } 1999 2000 /* 2001 * Configures the irq for the interrupt link device identified by 2002 * acpipsmlnkp. 2003 * 2004 * Gets the current and the list of possible irq settings for the 2005 * device. If apic_unconditional_srs is not set, and the current 2006 * resource setting is in the list of possible irq settings, 2007 * current irq resource setting is passed to the caller. 2008 * 2009 * Otherwise, picks an irq number from the list of possible irq 2010 * settings, and sets the irq of the device to this value. 2011 * If prefer_crs is set, among a set of irq numbers in the list that have 2012 * the least number of devices sharing the interrupt, we pick current irq 2013 * resource setting if it is a member of this set. 2014 * 2015 * Passes the irq number in the value pointed to by pci_irqp, and 2016 * polarity and sensitivity in the structure pointed to by dipintrflagp 2017 * to the caller. 2018 * 2019 * Note that if setting the irq resource failed, but successfuly obtained 2020 * the current irq resource settings, passes the current irq resources 2021 * and considers it a success. 2022 * 2023 * Returns: 2024 * ACPI_PSM_SUCCESS on success. 2025 * 2026 * ACPI_PSM_FAILURE if an error occured during the configuration or 2027 * if a suitable irq was not found for this device, or if setting the 2028 * irq resource and obtaining the current resource fails. 2029 * 2030 */ 2031 static int 2032 apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip, 2033 int *pci_irqp, iflag_t *dipintr_flagp) 2034 { 2035 int32_t irq; 2036 int cur_irq = -1; 2037 acpi_irqlist_t *irqlistp; 2038 prs_irq_list_t *prs_irq_listp, *prs_irq_entp; 2039 boolean_t found_irq = B_FALSE; 2040 2041 dipintr_flagp->bustype = BUS_PCI; 2042 2043 if ((acpi_get_possible_irq_resources(acpipsmlnkp, &irqlistp)) 2044 == ACPI_PSM_FAILURE) { 2045 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Unable to determine " 2046 "or assign IRQ for device %s, instance #%d: The system was " 2047 "unable to get the list of potential IRQs from ACPI.", 2048 psm_name, ddi_get_name(dip), ddi_get_instance(dip))); 2049 2050 return (ACPI_PSM_FAILURE); 2051 } 2052 2053 if ((acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq, 2054 dipintr_flagp) == ACPI_PSM_SUCCESS) && (!apic_unconditional_srs) && 2055 (cur_irq > 0)) { 2056 /* 2057 * If an IRQ is set in CRS and that IRQ exists in the set 2058 * returned from _PRS, return that IRQ, otherwise print 2059 * a warning 2060 */ 2061 2062 if (acpi_irqlist_find_irq(irqlistp, cur_irq, NULL) 2063 == ACPI_PSM_SUCCESS) { 2064 2065 ASSERT(pci_irqp != NULL); 2066 *pci_irqp = cur_irq; 2067 acpi_free_irqlist(irqlistp); 2068 return (ACPI_PSM_SUCCESS); 2069 } 2070 2071 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find the " 2072 "current irq %d for device %s, instance #%d in ACPI's " 2073 "list of possible irqs for this device. Picking one from " 2074 " the latter list.", psm_name, cur_irq, ddi_get_name(dip), 2075 ddi_get_instance(dip))); 2076 } 2077 2078 if ((prs_irq_listp = apic_choose_irqs_from_prs(irqlistp, dip, 2079 cur_irq)) == NULL) { 2080 2081 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find a " 2082 "suitable irq from the list of possible irqs for device " 2083 "%s, instance #%d in ACPI's list of possible irqs", 2084 psm_name, ddi_get_name(dip), ddi_get_instance(dip))); 2085 2086 acpi_free_irqlist(irqlistp); 2087 return (ACPI_PSM_FAILURE); 2088 } 2089 2090 acpi_free_irqlist(irqlistp); 2091 2092 for (prs_irq_entp = prs_irq_listp; 2093 prs_irq_entp != NULL && found_irq == B_FALSE; 2094 prs_irq_entp = prs_irq_entp->next) { 2095 2096 acpipsmlnkp->acpi_prs_prv = prs_irq_entp->prsprv; 2097 irq = prs_irq_entp->irq; 2098 2099 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Setting irq %d for " 2100 "device %s instance #%d\n", psm_name, irq, 2101 ddi_get_name(dip), ddi_get_instance(dip))); 2102 2103 if ((acpi_set_irq_resource(acpipsmlnkp, irq)) 2104 == ACPI_PSM_SUCCESS) { 2105 /* 2106 * setting irq was successful, check to make sure CRS 2107 * reflects that. If CRS does not agree with what we 2108 * set, return the irq that was set. 2109 */ 2110 2111 if (acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq, 2112 dipintr_flagp) == ACPI_PSM_SUCCESS) { 2113 2114 if (cur_irq != irq) 2115 APIC_VERBOSE_IRQ((CE_WARN, 2116 "!%s: IRQ resource set " 2117 "(irqno %d) for device %s " 2118 "instance #%d, differs from " 2119 "current setting irqno %d", 2120 psm_name, irq, ddi_get_name(dip), 2121 ddi_get_instance(dip), cur_irq)); 2122 } else { 2123 /* 2124 * On at least one system, there was a bug in 2125 * a DSDT method called by _STA, causing _STA to 2126 * indicate that the link device was disabled 2127 * (when, in fact, it was enabled). Since _SRS 2128 * succeeded, assume that _CRS is lying and use 2129 * the iflags from this _PRS interrupt choice. 2130 * If we're wrong about the flags, the polarity 2131 * will be incorrect and we may get an interrupt 2132 * storm, but there's not much else we can do 2133 * at this point. 2134 */ 2135 *dipintr_flagp = prs_irq_entp->intrflags; 2136 } 2137 2138 /* 2139 * Return the irq that was set, and not what _CRS 2140 * reports, since _CRS has been seen to return 2141 * different IRQs than what was passed to _SRS on some 2142 * systems (and just not return successfully on others). 2143 */ 2144 cur_irq = irq; 2145 found_irq = B_TRUE; 2146 } else { 2147 APIC_VERBOSE_IRQ((CE_WARN, "!%s: set resource " 2148 "irq %d failed for device %s instance #%d", 2149 psm_name, irq, ddi_get_name(dip), 2150 ddi_get_instance(dip))); 2151 2152 if (cur_irq == -1) { 2153 acpi_destroy_prs_irq_list(&prs_irq_listp); 2154 return (ACPI_PSM_FAILURE); 2155 } 2156 } 2157 } 2158 2159 acpi_destroy_prs_irq_list(&prs_irq_listp); 2160 2161 if (!found_irq) 2162 return (ACPI_PSM_FAILURE); 2163 2164 ASSERT(pci_irqp != NULL); 2165 *pci_irqp = cur_irq; 2166 return (ACPI_PSM_SUCCESS); 2167 } 2168 2169 void 2170 ioapic_disable_redirection() 2171 { 2172 int ioapic_ix; 2173 int intin_max; 2174 int intin_ix; 2175 2176 /* Disable the I/O APIC redirection entries */ 2177 for (ioapic_ix = 0; ioapic_ix < apic_io_max; ioapic_ix++) { 2178 2179 /* Bits 23-16 define the maximum redirection entries */ 2180 intin_max = (ioapic_read(ioapic_ix, APIC_VERS_CMD) >> 16) 2181 & 0xff; 2182 2183 for (intin_ix = 0; intin_ix <= intin_max; intin_ix++) { 2184 /* 2185 * The assumption here is that this is safe, even for 2186 * systems with IOAPICs that suffer from the hardware 2187 * erratum because all devices have been quiesced before 2188 * this function is called from apic_shutdown() 2189 * (or equivalent). If that assumption turns out to be 2190 * false, this mask operation can induce the same 2191 * erratum result we're trying to avoid. 2192 */ 2193 ioapic_write(ioapic_ix, APIC_RDT_CMD + 2 * intin_ix, 2194 AV_MASK); 2195 } 2196 } 2197 } 2198 2199 /* 2200 * Looks for an IOAPIC with the specified physical address in the /ioapics 2201 * node in the device tree (created by the PCI enumerator). 2202 */ 2203 static boolean_t 2204 apic_is_ioapic_AMD_813x(uint32_t physaddr) 2205 { 2206 /* 2207 * Look in /ioapics, for the ioapic with 2208 * the physical address given 2209 */ 2210 dev_info_t *ioapicsnode = ddi_find_devinfo(IOAPICS_NODE_NAME, -1, 0); 2211 dev_info_t *ioapic_child; 2212 boolean_t rv = B_FALSE; 2213 int vid, did; 2214 uint64_t ioapic_paddr; 2215 boolean_t done = B_FALSE; 2216 2217 if (ioapicsnode == NULL) 2218 return (B_FALSE); 2219 2220 /* Load first child: */ 2221 ioapic_child = ddi_get_child(ioapicsnode); 2222 while (!done && ioapic_child != 0) { /* Iterate over children */ 2223 2224 if ((ioapic_paddr = (uint64_t)ddi_prop_get_int64(DDI_DEV_T_ANY, 2225 ioapic_child, DDI_PROP_DONTPASS, "reg", 0)) 2226 != 0 && physaddr == ioapic_paddr) { 2227 2228 vid = ddi_prop_get_int(DDI_DEV_T_ANY, ioapic_child, 2229 DDI_PROP_DONTPASS, IOAPICS_PROP_VENID, 0); 2230 2231 if (vid == VENID_AMD) { 2232 2233 did = ddi_prop_get_int(DDI_DEV_T_ANY, 2234 ioapic_child, DDI_PROP_DONTPASS, 2235 IOAPICS_PROP_DEVID, 0); 2236 2237 if (did == DEVID_8131_IOAPIC || 2238 did == DEVID_8132_IOAPIC) { 2239 rv = B_TRUE; 2240 done = B_TRUE; 2241 } 2242 } 2243 } 2244 2245 if (!done) 2246 ioapic_child = ddi_get_next_sibling(ioapic_child); 2247 } 2248 2249 /* The ioapics node was held by ddi_find_devinfo, so release it */ 2250 ndi_rele_devi(ioapicsnode); 2251 return (rv); 2252 } 2253 2254 struct apic_state { 2255 int32_t as_task_reg; 2256 int32_t as_dest_reg; 2257 int32_t as_format_reg; 2258 int32_t as_local_timer; 2259 int32_t as_pcint_vect; 2260 int32_t as_int_vect0; 2261 int32_t as_int_vect1; 2262 int32_t as_err_vect; 2263 int32_t as_init_count; 2264 int32_t as_divide_reg; 2265 int32_t as_spur_int_reg; 2266 uint32_t as_ioapic_ids[MAX_IO_APIC]; 2267 }; 2268 2269 2270 static int 2271 apic_acpi_enter_apicmode(void) 2272 { 2273 ACPI_OBJECT_LIST arglist; 2274 ACPI_OBJECT arg; 2275 ACPI_STATUS status; 2276 2277 /* Setup parameter object */ 2278 arglist.Count = 1; 2279 arglist.Pointer = &arg; 2280 arg.Type = ACPI_TYPE_INTEGER; 2281 arg.Integer.Value = ACPI_APIC_MODE; 2282 2283 status = AcpiEvaluateObject(NULL, "\\_PIC", &arglist, NULL); 2284 /* 2285 * Per ACPI spec - section 5.8.1 _PIC Method 2286 * calling the \_PIC control method is optional for the OS 2287 * and might not be found. It's ok to not fail in such cases. 2288 * This is the case on linux KVM and qemu (status AE_NOT_FOUND) 2289 */ 2290 if (ACPI_FAILURE(status) && (status != AE_NOT_FOUND)) { 2291 cmn_err(CE_NOTE, 2292 "!apic: Reporting APIC mode failed (via _PIC), err: 0x%x", 2293 ACPI_FAILURE(status)); 2294 return (PSM_FAILURE); 2295 } else { 2296 return (PSM_SUCCESS); 2297 } 2298 } 2299 2300 2301 static void 2302 apic_save_state(struct apic_state *sp) 2303 { 2304 int i, cpuid; 2305 ulong_t iflag; 2306 2307 PMD(PMD_SX, ("apic_save_state %p\n", (void *)sp)) 2308 /* 2309 * First the local APIC. 2310 */ 2311 sp->as_task_reg = apic_reg_ops->apic_get_pri(); 2312 sp->as_dest_reg = apic_reg_ops->apic_read(APIC_DEST_REG); 2313 if (apic_mode == LOCAL_APIC) 2314 sp->as_format_reg = apic_reg_ops->apic_read(APIC_FORMAT_REG); 2315 sp->as_local_timer = apic_reg_ops->apic_read(APIC_LOCAL_TIMER); 2316 sp->as_pcint_vect = apic_reg_ops->apic_read(APIC_PCINT_VECT); 2317 sp->as_int_vect0 = apic_reg_ops->apic_read(APIC_INT_VECT0); 2318 sp->as_int_vect1 = apic_reg_ops->apic_read(APIC_INT_VECT1); 2319 sp->as_err_vect = apic_reg_ops->apic_read(APIC_ERR_VECT); 2320 sp->as_init_count = apic_reg_ops->apic_read(APIC_INIT_COUNT); 2321 sp->as_divide_reg = apic_reg_ops->apic_read(APIC_DIVIDE_REG); 2322 sp->as_spur_int_reg = apic_reg_ops->apic_read(APIC_SPUR_INT_REG); 2323 2324 /* 2325 * If on the boot processor then save the IOAPICs' IDs 2326 */ 2327 if ((cpuid = psm_get_cpu_id()) == 0) { 2328 2329 iflag = intr_clear(); 2330 lock_set(&apic_ioapic_lock); 2331 2332 for (i = 0; i < apic_io_max; i++) 2333 sp->as_ioapic_ids[i] = ioapic_read(i, APIC_ID_CMD); 2334 2335 lock_clear(&apic_ioapic_lock); 2336 intr_restore(iflag); 2337 } 2338 2339 /* apic_state() is currently invoked only in Suspend/Resume */ 2340 apic_cpus[cpuid].aci_status |= APIC_CPU_SUSPEND; 2341 } 2342 2343 static void 2344 apic_restore_state(struct apic_state *sp) 2345 { 2346 int i; 2347 ulong_t iflag; 2348 2349 /* 2350 * First the local APIC. 2351 */ 2352 apic_reg_ops->apic_write_task_reg(sp->as_task_reg); 2353 if (apic_mode == LOCAL_APIC) { 2354 apic_reg_ops->apic_write(APIC_DEST_REG, sp->as_dest_reg); 2355 apic_reg_ops->apic_write(APIC_FORMAT_REG, sp->as_format_reg); 2356 } 2357 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, sp->as_local_timer); 2358 apic_reg_ops->apic_write(APIC_PCINT_VECT, sp->as_pcint_vect); 2359 apic_reg_ops->apic_write(APIC_INT_VECT0, sp->as_int_vect0); 2360 apic_reg_ops->apic_write(APIC_INT_VECT1, sp->as_int_vect1); 2361 apic_reg_ops->apic_write(APIC_ERR_VECT, sp->as_err_vect); 2362 apic_reg_ops->apic_write(APIC_INIT_COUNT, sp->as_init_count); 2363 apic_reg_ops->apic_write(APIC_DIVIDE_REG, sp->as_divide_reg); 2364 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, sp->as_spur_int_reg); 2365 2366 /* 2367 * the following only needs to be done once, so we do it on the 2368 * boot processor, since we know that we only have one of those 2369 */ 2370 if (psm_get_cpu_id() == 0) { 2371 2372 iflag = intr_clear(); 2373 lock_set(&apic_ioapic_lock); 2374 2375 /* Restore IOAPICs' APIC IDs */ 2376 for (i = 0; i < apic_io_max; i++) { 2377 ioapic_write(i, APIC_ID_CMD, sp->as_ioapic_ids[i]); 2378 } 2379 2380 lock_clear(&apic_ioapic_lock); 2381 intr_restore(iflag); 2382 2383 /* 2384 * Reenter APIC mode before restoring LNK devices 2385 */ 2386 (void) apic_acpi_enter_apicmode(); 2387 2388 /* 2389 * restore acpi link device mappings 2390 */ 2391 acpi_restore_link_devices(); 2392 } 2393 } 2394 2395 /* 2396 * Returns 0 on success 2397 */ 2398 int 2399 apic_state(psm_state_request_t *rp) 2400 { 2401 PMD(PMD_SX, ("apic_state ")) 2402 switch (rp->psr_cmd) { 2403 case PSM_STATE_ALLOC: 2404 rp->req.psm_state_req.psr_state = 2405 kmem_zalloc(sizeof (struct apic_state), KM_NOSLEEP); 2406 if (rp->req.psm_state_req.psr_state == NULL) 2407 return (ENOMEM); 2408 rp->req.psm_state_req.psr_state_size = 2409 sizeof (struct apic_state); 2410 PMD(PMD_SX, (":STATE_ALLOC: state %p, size %lx\n", 2411 rp->req.psm_state_req.psr_state, 2412 rp->req.psm_state_req.psr_state_size)) 2413 return (0); 2414 2415 case PSM_STATE_FREE: 2416 kmem_free(rp->req.psm_state_req.psr_state, 2417 rp->req.psm_state_req.psr_state_size); 2418 PMD(PMD_SX, (" STATE_FREE: state %p, size %lx\n", 2419 rp->req.psm_state_req.psr_state, 2420 rp->req.psm_state_req.psr_state_size)) 2421 return (0); 2422 2423 case PSM_STATE_SAVE: 2424 PMD(PMD_SX, (" STATE_SAVE: state %p, size %lx\n", 2425 rp->req.psm_state_req.psr_state, 2426 rp->req.psm_state_req.psr_state_size)) 2427 apic_save_state(rp->req.psm_state_req.psr_state); 2428 return (0); 2429 2430 case PSM_STATE_RESTORE: 2431 apic_restore_state(rp->req.psm_state_req.psr_state); 2432 PMD(PMD_SX, (" STATE_RESTORE: state %p, size %lx\n", 2433 rp->req.psm_state_req.psr_state, 2434 rp->req.psm_state_req.psr_state_size)) 2435 return (0); 2436 2437 default: 2438 return (EINVAL); 2439 } 2440 } 2441