1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include <sys/mca_x86.h> 28 #include <sys/cpu_module_impl.h> 29 #include <sys/cpu_module_ms.h> 30 #include <sys/cmn_err.h> 31 #include <sys/cpuvar.h> 32 #include <sys/pghw.h> 33 #include <sys/x86_archext.h> 34 #include <sys/sysmacros.h> 35 #include <sys/regset.h> 36 #include <sys/privregs.h> 37 #include <sys/systm.h> 38 #include <sys/types.h> 39 #include <sys/log.h> 40 #include <sys/psw.h> 41 #include <sys/fm/protocol.h> 42 #include <sys/fm/util.h> 43 #include <sys/errorq.h> 44 #include <sys/mca_x86.h> 45 #include <sys/fm/cpu/GMCA.h> 46 #include <sys/sysevent.h> 47 #include <sys/ontrap.h> 48 49 #include "gcpu.h" 50 51 /* 52 * Clear to log telemetry found at initialization. While processor docs 53 * say you should process this telemetry on all but Intel family 0x6 54 * there are way too many exceptions and we want to avoid bogus 55 * diagnoses. 56 */ 57 int gcpu_suppress_log_on_init = 1; 58 59 /* 60 * gcpu_mca_stack_flag is a debug assist option to capture a stack trace at 61 * error logout time. The stack will be included in the ereport if the 62 * error type selects stack inclusion, or in all cases if 63 * gcpu_mca_stack_ereport_include is nonzero. 64 */ 65 int gcpu_mca_stack_flag = 0; 66 int gcpu_mca_stack_ereport_include = 0; 67 68 /* 69 * The number of times to re-read MCA telemetry to try to obtain a 70 * consistent snapshot if we find it to be changing under our feet. 71 */ 72 int gcpu_mca_telemetry_retries = 5; 73 74 int gcpu_mca_cmci_throttling_threshold = 10; 75 int gcpu_mca_cmci_reenable_threshold = 1000; 76 77 static gcpu_error_disp_t gcpu_errtypes[] = { 78 79 /* 80 * Unclassified 81 */ 82 { 83 FM_EREPORT_CPU_GENERIC_UNCLASSIFIED, 84 NULL, 85 FM_EREPORT_PAYLOAD_FLAGS_COMMON, 86 MCAX86_SIMPLE_UNCLASSIFIED_MASKON, 87 MCAX86_SIMPLE_UNCLASSIFIED_MASKOFF 88 }, 89 90 /* 91 * Microcode ROM Parity Error 92 */ 93 { 94 FM_EREPORT_CPU_GENERIC_MC_CODE_PARITY, 95 NULL, 96 FM_EREPORT_PAYLOAD_FLAGS_COMMON, 97 MCAX86_SIMPLE_MC_CODE_PARITY_MASKON, 98 MCAX86_SIMPLE_MC_CODE_PARITY_MASKOFF 99 }, 100 101 /* 102 * External - BINIT# from another processor during power-on config 103 */ 104 { 105 FM_EREPORT_CPU_GENERIC_EXTERNAL, 106 NULL, 107 FM_EREPORT_PAYLOAD_FLAGS_COMMON, 108 MCAX86_SIMPLE_EXTERNAL_MASKON, 109 MCAX86_SIMPLE_EXTERNAL_MASKOFF 110 }, 111 112 /* 113 * Functional redundancy check master/slave error 114 */ 115 { 116 FM_EREPORT_CPU_GENERIC_FRC, 117 NULL, 118 FM_EREPORT_PAYLOAD_FLAGS_COMMON, 119 MCAX86_SIMPLE_FRC_MASKON, 120 MCAX86_SIMPLE_FRC_MASKOFF 121 }, 122 123 /* 124 * Internal parity error 125 */ 126 { 127 FM_EREPORT_CPU_GENERIC_INTERNAL_PARITY, 128 NULL, 129 FM_EREPORT_PAYLOAD_FLAGS_COMMON, 130 MCAX86_SIMPLE_INTERNAL_PARITY_MASKON, 131 MCAX86_SIMPLE_INTERNAL_PARITY_MASKOFF 132 }, 133 134 135 /* 136 * Internal timer error 137 */ 138 { 139 FM_EREPORT_CPU_GENERIC_INTERNAL_TIMER, 140 NULL, 141 FM_EREPORT_PAYLOAD_FLAGS_COMMON, 142 MCAX86_SIMPLE_INTERNAL_TIMER_MASKON, 143 MCAX86_SIMPLE_INTERNAL_TIMER_MASKOFF 144 }, 145 146 /* 147 * Internal unclassified 148 */ 149 { 150 FM_EREPORT_CPU_GENERIC_INTERNAL_UNCLASS, 151 NULL, 152 FM_EREPORT_PAYLOAD_FLAGS_COMMON, 153 MCAX86_SIMPLE_INTERNAL_UNCLASS_MASK_MASKON, 154 MCAX86_SIMPLE_INTERNAL_UNCLASS_MASK_MASKOFF 155 }, 156 157 /* 158 * Compound error codes - generic memory hierarchy 159 */ 160 { 161 FM_EREPORT_CPU_GENERIC_GENMEMHIER, 162 NULL, 163 FM_EREPORT_PAYLOAD_FLAGS_COMMON, /* yes, no compound name */ 164 MCAX86_COMPOUND_GENERIC_MEMHIER_MASKON, 165 MCAX86_COMPOUND_GENERIC_MEMHIER_MASKOFF 166 }, 167 168 /* 169 * Compound error codes - TLB errors 170 */ 171 { 172 FM_EREPORT_CPU_GENERIC_TLB, 173 "%1$s" "TLB" "%2$s" "_ERR", 174 FM_EREPORT_PAYLOAD_FLAGS_COMPOUND_ERR, 175 MCAX86_COMPOUND_TLB_MASKON, 176 MCAX86_COMPOUND_TLB_MASKOFF 177 }, 178 179 /* 180 * Compound error codes - memory hierarchy 181 */ 182 { 183 FM_EREPORT_CPU_GENERIC_MEMHIER, 184 "%1$s" "CACHE" "%2$s" "_" "%3$s" "_ERR", 185 FM_EREPORT_PAYLOAD_FLAGS_COMPOUND_ERR, 186 MCAX86_COMPOUND_MEMHIER_MASKON, 187 MCAX86_COMPOUND_MEMHIER_MASKOFF 188 }, 189 190 /* 191 * Compound error codes - bus and interconnect errors 192 */ 193 { 194 FM_EREPORT_CPU_GENERIC_BUS_INTERCONNECT, 195 "BUS" "%2$s" "_" "%4$s" "_" "%3$s" "_" "%5$s" "_" "%6$s" "_ERR", 196 FM_EREPORT_PAYLOAD_FLAGS_COMPOUND_ERR, 197 MCAX86_COMPOUND_BUS_INTERCONNECT_MASKON, 198 MCAX86_COMPOUND_BUS_INTERCONNECT_MASKOFF 199 }, 200 /* 201 * Compound error codes - memory controller errors 202 */ 203 { 204 FM_EREPORT_CPU_GENERIC_MEMORY_CONTROLLER, 205 "MC" "_" "%8$s" "_" "%9$s" "_ERR", 206 FM_EREPORT_PAYLOAD_FLAGS_COMPOUND_ERR, 207 MCAX86_COMPOUND_MEMORY_CONTROLLER_MASKON, 208 MCAX86_COMPOUND_MEMORY_CONTROLLER_MASKOFF 209 }, 210 }; 211 212 static gcpu_error_disp_t gcpu_unknown = { 213 FM_EREPORT_CPU_GENERIC_UNKNOWN, 214 "UNKNOWN", 215 FM_EREPORT_PAYLOAD_FLAGS_COMMON, 216 0, 217 0 218 }; 219 220 static errorq_t *gcpu_mca_queue; 221 static kmutex_t gcpu_mca_queue_lock; 222 223 static const gcpu_error_disp_t * 224 gcpu_disp_match(uint16_t code) 225 { 226 const gcpu_error_disp_t *ged = gcpu_errtypes; 227 int i; 228 229 for (i = 0; i < sizeof (gcpu_errtypes) / sizeof (gcpu_error_disp_t); 230 i++, ged++) { 231 uint16_t on = ged->ged_errcode_mask_on; 232 uint16_t off = ged->ged_errcode_mask_off; 233 234 if ((code & on) == on && (code & off) == 0) 235 return (ged); 236 } 237 238 return (NULL); 239 } 240 241 static uint8_t 242 bit_strip(uint16_t code, uint16_t mask, uint16_t shift) 243 { 244 return ((uint8_t)(code & mask) >> shift); 245 } 246 247 #define BIT_STRIP(code, name) \ 248 bit_strip(code, MCAX86_ERRCODE_##name##_MASK, \ 249 MCAX86_ERRCODE_##name##_SHIFT) 250 251 #define GCPU_MNEMONIC_UNDEF "undefined" 252 #define GCPU_MNEMONIC_RESVD "reserved" 253 254 /* 255 * Mappings of TT, LL, RRRR, PP, II and T values to compound error name 256 * mnemonics and to ereport class name components. 257 */ 258 259 struct gcpu_mnexp { 260 const char *mne_compound; /* used in expanding compound errname */ 261 const char *mne_ereport; /* used in expanding ereport class */ 262 }; 263 264 static struct gcpu_mnexp gcpu_TT_mnemonics[] = { /* MCAX86_ERRCODE_TT_* */ 265 { "I", FM_EREPORT_CPU_GENERIC_TT_INSTR }, /* INSTR */ 266 { "D", FM_EREPORT_CPU_GENERIC_TT_DATA }, /* DATA */ 267 { "G", FM_EREPORT_CPU_GENERIC_TT_GEN }, /* GEN */ 268 { GCPU_MNEMONIC_UNDEF, "" } 269 }; 270 271 static struct gcpu_mnexp gcpu_LL_mnemonics[] = { /* MCAX86_ERRCODE_LL_* */ 272 { "LO", FM_EREPORT_CPU_GENERIC_LL_L0 }, /* L0 */ 273 { "L1", FM_EREPORT_CPU_GENERIC_LL_L1 }, /* L1 */ 274 { "L2", FM_EREPORT_CPU_GENERIC_LL_L2 }, /* L2 */ 275 { "LG", FM_EREPORT_CPU_GENERIC_LL_LG } /* LG */ 276 }; 277 278 static struct gcpu_mnexp gcpu_RRRR_mnemonics[] = { /* MCAX86_ERRCODE_RRRR_* */ 279 { "ERR", FM_EREPORT_CPU_GENERIC_RRRR_ERR }, /* ERR */ 280 { "RD", FM_EREPORT_CPU_GENERIC_RRRR_RD }, /* RD */ 281 { "WR", FM_EREPORT_CPU_GENERIC_RRRR_WR }, /* WR */ 282 { "DRD", FM_EREPORT_CPU_GENERIC_RRRR_DRD }, /* DRD */ 283 { "DWR", FM_EREPORT_CPU_GENERIC_RRRR_DWR }, /* DWR */ 284 { "IRD", FM_EREPORT_CPU_GENERIC_RRRR_IRD }, /* IRD */ 285 { "PREFETCH", FM_EREPORT_CPU_GENERIC_RRRR_PREFETCH }, /* PREFETCH */ 286 { "EVICT", FM_EREPORT_CPU_GENERIC_RRRR_EVICT }, /* EVICT */ 287 { "SNOOP", FM_EREPORT_CPU_GENERIC_RRRR_SNOOP }, /* SNOOP */ 288 }; 289 290 static struct gcpu_mnexp gcpu_PP_mnemonics[] = { /* MCAX86_ERRCODE_PP_* */ 291 { "SRC", FM_EREPORT_CPU_GENERIC_PP_SRC }, /* SRC */ 292 { "RES", FM_EREPORT_CPU_GENERIC_PP_RES }, /* RES */ 293 { "OBS", FM_EREPORT_CPU_GENERIC_PP_OBS }, /* OBS */ 294 { "", FM_EREPORT_CPU_GENERIC_PP_GEN } /* GEN */ 295 }; 296 297 static struct gcpu_mnexp gcpu_II_mnemonics[] = { /* MCAX86_ERRCODE_II_* */ 298 { "M", FM_EREPORT_CPU_GENERIC_II_MEM }, /* MEM */ 299 { GCPU_MNEMONIC_RESVD, "" }, 300 { "IO", FM_EREPORT_CPU_GENERIC_II_IO }, /* IO */ 301 { "", FM_EREPORT_CPU_GENERIC_II_GEN } /* GEN */ 302 }; 303 304 static struct gcpu_mnexp gcpu_T_mnemonics[] = { /* MCAX86_ERRCODE_T_* */ 305 { "NOTIMEOUT", FM_EREPORT_CPU_GENERIC_T_NOTIMEOUT }, /* NONE */ 306 { "TIMEOUT", FM_EREPORT_CPU_GENERIC_T_TIMEOUT } /* TIMEOUT */ 307 }; 308 309 static struct gcpu_mnexp gcpu_CCCC_mnemonics[] = { /* MCAX86_ERRCODE_CCCC_* */ 310 { "CH0", FM_EREPORT_CPU_GENERIC_CCCC }, /* CH0 */ 311 { "CH1", FM_EREPORT_CPU_GENERIC_CCCC }, /* CH1 */ 312 { "CH2", FM_EREPORT_CPU_GENERIC_CCCC }, /* CH2 */ 313 { "CH3", FM_EREPORT_CPU_GENERIC_CCCC }, /* CH3 */ 314 { "CH4", FM_EREPORT_CPU_GENERIC_CCCC }, /* CH4 */ 315 { "CH5", FM_EREPORT_CPU_GENERIC_CCCC }, /* CH5 */ 316 { "CH6", FM_EREPORT_CPU_GENERIC_CCCC }, /* CH6 */ 317 { "CH7", FM_EREPORT_CPU_GENERIC_CCCC }, /* CH7 */ 318 { "CH8", FM_EREPORT_CPU_GENERIC_CCCC }, /* CH8 */ 319 { "CH9", FM_EREPORT_CPU_GENERIC_CCCC }, /* CH9 */ 320 { "CH10", FM_EREPORT_CPU_GENERIC_CCCC }, /* CH10 */ 321 { "CH11", FM_EREPORT_CPU_GENERIC_CCCC }, /* CH11 */ 322 { "CH12", FM_EREPORT_CPU_GENERIC_CCCC }, /* CH12 */ 323 { "CH13", FM_EREPORT_CPU_GENERIC_CCCC }, /* CH13 */ 324 { "CH14", FM_EREPORT_CPU_GENERIC_CCCC }, /* CH14 */ 325 { "CH", FM_EREPORT_CPU_GENERIC_CCCC } /* GEN */ 326 }; 327 328 static struct gcpu_mnexp gcpu_MMM_mnemonics[] = { /* MCAX86_ERRCODE_MMM_* */ 329 { "GEN", FM_EREPORT_CPU_GENERIC_MMM_ERR }, /* GEN ERR */ 330 { "RD", FM_EREPORT_CPU_GENERIC_MMM_RD }, /* READ */ 331 { "WR", FM_EREPORT_CPU_GENERIC_MMM_WR }, /* WRITE */ 332 { "ADDR_CMD", FM_EREPORT_CPU_GENERIC_MMM_ADRCMD }, /* ADDR, CMD */ 333 { GCPU_MNEMONIC_RESVD, ""}, /* RESERVED */ 334 { GCPU_MNEMONIC_RESVD, ""}, /* RESERVED */ 335 { GCPU_MNEMONIC_RESVD, ""}, /* RESERVED */ 336 { GCPU_MNEMONIC_RESVD, ""} /* RESERVED */ 337 }; 338 339 enum gcpu_mn_namespace { 340 GCPU_MN_NAMESPACE_COMPOUND, 341 GCPU_MN_NAMESPACE_EREPORT 342 }; 343 344 static const char * 345 gcpu_mnemonic(const struct gcpu_mnexp *tbl, size_t tbl_sz, uint8_t val, 346 enum gcpu_mn_namespace nspace) 347 { 348 if (val >= tbl_sz) 349 return (GCPU_MNEMONIC_UNDEF); /* for all namespaces */ 350 351 switch (nspace) { 352 case GCPU_MN_NAMESPACE_COMPOUND: 353 return (tbl[val].mne_compound); 354 /*NOTREACHED*/ 355 356 case GCPU_MN_NAMESPACE_EREPORT: 357 return (tbl[val].mne_ereport); 358 /*NOTREACHED*/ 359 360 default: 361 return (GCPU_MNEMONIC_UNDEF); 362 /*NOTREACHED*/ 363 } 364 } 365 366 /* 367 * The ereport class leaf component is either a simple string with no 368 * format specifiers, or a string with one or more embedded %n$s specifiers - 369 * positional selection for string arguments. The kernel snprintf does 370 * not support %n$ (and teaching it to do so is too big a headache) so 371 * we will expand this restricted format string ourselves. 372 */ 373 374 #define GCPU_CLASS_VARCOMPS 9 375 376 #define GCPU_MNEMONIC(code, name, nspace) \ 377 gcpu_mnemonic(gcpu_##name##_mnemonics, \ 378 sizeof (gcpu_##name##_mnemonics) / sizeof (struct gcpu_mnexp), \ 379 BIT_STRIP(code, name), nspace) 380 381 static void 382 gcpu_mn_fmt(const char *fmt, char *buf, size_t buflen, uint64_t status, 383 enum gcpu_mn_namespace nspace) 384 { 385 uint16_t code = MCAX86_ERRCODE(status); 386 const char *mn[GCPU_CLASS_VARCOMPS]; 387 char *p = buf; /* current position in buf */ 388 char *q = buf + buflen; /* pointer past last char in buf */ 389 int which, expfmtchar, error; 390 char c; 391 392 mn[0] = GCPU_MNEMONIC(code, TT, nspace); 393 mn[1] = GCPU_MNEMONIC(code, LL, nspace); 394 mn[2] = GCPU_MNEMONIC(code, RRRR, nspace); 395 mn[3] = GCPU_MNEMONIC(code, PP, nspace); 396 mn[4] = GCPU_MNEMONIC(code, II, nspace); 397 mn[5] = GCPU_MNEMONIC(code, T, nspace); 398 mn[6] = (status & MSR_MC_STATUS_UC) ? "_uc" : ""; 399 mn[7] = GCPU_MNEMONIC(code, CCCC, nspace); 400 mn[8] = GCPU_MNEMONIC(code, MMM, nspace); 401 402 while (p < q - 1 && (c = *fmt++) != '\0') { 403 if (c != '%') { 404 /* not the beginning of a format specifier - copy */ 405 *p++ = c; 406 continue; 407 } 408 409 error = 0; 410 which = -1; 411 expfmtchar = -1; 412 413 nextfmt: 414 if ((c = *fmt++) == '\0') 415 break; /* early termination of fmt specifier */ 416 417 switch (c) { 418 case '1': 419 case '2': 420 case '3': 421 case '4': 422 case '5': 423 case '6': 424 case '7': 425 case '8': 426 case '9': 427 if (which != -1) { /* allow only one positional digit */ 428 error++; 429 break; 430 } 431 which = c - '1'; 432 goto nextfmt; 433 /*NOTREACHED*/ 434 435 case '$': 436 if (which == -1) { /* no position specified */ 437 error++; 438 break; 439 } 440 expfmtchar = 's'; 441 goto nextfmt; 442 /*NOTREACHED*/ 443 444 case 's': 445 if (expfmtchar != 's') { 446 error++; 447 break; 448 } 449 (void) snprintf(p, (uintptr_t)q - (uintptr_t)p, "%s", 450 mn[which]); 451 p += strlen(p); 452 break; 453 454 default: 455 error++; 456 break; 457 } 458 459 if (error) 460 break; 461 } 462 463 *p = '\0'; /* NUL termination */ 464 } 465 466 static void 467 gcpu_erpt_clsfmt(const char *fmt, char *buf, size_t buflen, uint64_t status, 468 const char *cpuclass, const char *leafclass) 469 { 470 char *p = buf; /* current position in buf */ 471 char *q = buf + buflen; /* pointer past last char in buf */ 472 473 (void) snprintf(buf, (uintptr_t)q - (uintptr_t)p, "%s.%s.", 474 FM_ERROR_CPU, cpuclass ? cpuclass : FM_EREPORT_CPU_GENERIC); 475 476 p += strlen(p); 477 if (p >= q) 478 return; 479 480 if (leafclass == NULL) { 481 gcpu_mn_fmt(fmt, p, (uintptr_t)q - (uintptr_t)p, status, 482 GCPU_MN_NAMESPACE_EREPORT); 483 } else { 484 (void) snprintf(p, (uintptr_t)q - (uintptr_t)p, "%s", 485 leafclass); 486 } 487 } 488 489 /* 490 * Create an "hc" scheme FMRI identifying the given cpu. If we don't know 491 * the actual topology/connectivity of cpus in the system, so we'll 492 * apply /motherboard=0/chip=.../cpu=... 493 */ 494 static nvlist_t * 495 gcpu_fmri_create(cmi_hdl_t hdl, nv_alloc_t *nva) 496 { 497 nvlist_t *nvl; 498 499 if ((nvl = fm_nvlist_create(nva)) == NULL) 500 return (NULL); 501 502 if (cmi_hdl_mstrand(hdl)) { 503 fm_fmri_hc_set(nvl, FM_HC_SCHEME_VERSION, NULL, NULL, 4, 504 "motherboard", 0, 505 "chip", cmi_hdl_chipid(hdl), 506 "core", cmi_hdl_coreid(hdl), 507 "strand", cmi_hdl_strandid(hdl)); 508 } else { 509 fm_fmri_hc_set(nvl, FM_HC_SCHEME_VERSION, NULL, NULL, 3, 510 "motherboard", 0, 511 "chip", cmi_hdl_chipid(hdl), 512 "cpu", cmi_hdl_coreid(hdl)); 513 } 514 515 return (nvl); 516 } 517 518 int gcpu_bleat_count_thresh = 5; 519 hrtime_t gcpu_bleat_min_interval = 10 * 1000000000ULL; 520 521 /* 522 * Called when we are unable to propogate a logout structure onto an 523 * errorq for subsequent ereport preparation and logging etc. The caller 524 * should usually only decide to call this for severe errors - those we 525 * suspect we may need to panic for. 526 */ 527 static void 528 gcpu_bleat(cmi_hdl_t hdl, gcpu_logout_t *gcl) 529 { 530 hrtime_t now = gethrtime_waitfree(); 531 static hrtime_t gcpu_last_bleat; 532 gcpu_bank_logout_t *gbl; 533 static int bleatcount; 534 int i; 535 536 /* 537 * Throttle spamming of the console. The first gcpu_bleat_count_thresh 538 * can come as fast as we like, but once we've spammed that many 539 * to the console we require a minimum interval to pass before 540 * any more complaints. 541 */ 542 if (++bleatcount > gcpu_bleat_count_thresh) { 543 if (now - gcpu_last_bleat < gcpu_bleat_min_interval) 544 return; 545 else 546 bleatcount = 0; 547 } 548 gcpu_last_bleat = now; 549 550 cmn_err(CE_WARN, 551 "Machine-Check Errors unlogged on chip %d core %d strand %d, " 552 "raw dump follows", cmi_hdl_chipid(hdl), cmi_hdl_coreid(hdl), 553 cmi_hdl_strandid(hdl)); 554 cmn_err(CE_WARN, "MCG_STATUS 0x%016llx", 555 (u_longlong_t)gcl->gcl_mcg_status); 556 for (i = 0, gbl = &gcl->gcl_data[0]; i < gcl->gcl_nbanks; i++, gbl++) { 557 uint64_t status = gbl->gbl_status; 558 559 if (!(status & MSR_MC_STATUS_VAL)) 560 continue; 561 562 switch (status & (MSR_MC_STATUS_ADDRV | MSR_MC_STATUS_MISCV)) { 563 case MSR_MC_STATUS_ADDRV | MSR_MC_STATUS_MISCV: 564 cmn_err(CE_WARN, "Bank %d (offset 0x%llx) " 565 "STAT 0x%016llx ADDR 0x%016llx MISC 0x%016llx", 566 i, IA32_MSR_MC(i, STATUS), 567 (u_longlong_t)status, 568 (u_longlong_t)gbl->gbl_addr, 569 (u_longlong_t)gbl->gbl_misc); 570 break; 571 572 case MSR_MC_STATUS_ADDRV: 573 cmn_err(CE_WARN, "Bank %d (offset 0x%llx) " 574 "STAT 0x%016llx ADDR 0x%016llx", 575 i, IA32_MSR_MC(i, STATUS), 576 (u_longlong_t)status, 577 (u_longlong_t)gbl->gbl_addr); 578 break; 579 580 case MSR_MC_STATUS_MISCV: 581 cmn_err(CE_WARN, "Bank %d (offset 0x%llx) " 582 "STAT 0x%016llx MISC 0x%016llx", 583 i, IA32_MSR_MC(i, STATUS), 584 (u_longlong_t)status, 585 (u_longlong_t)gbl->gbl_misc); 586 break; 587 588 default: 589 cmn_err(CE_WARN, "Bank %d (offset 0x%llx) " 590 "STAT 0x%016llx", 591 i, IA32_MSR_MC(i, STATUS), 592 (u_longlong_t)status); 593 break; 594 595 } 596 } 597 } 598 599 #define _GCPU_BSTATUS(status, what) \ 600 FM_EREPORT_PAYLOAD_NAME_MC_STATUS_##what, DATA_TYPE_BOOLEAN_VALUE, \ 601 (status) & MSR_MC_STATUS_##what ? B_TRUE : B_FALSE 602 603 static void 604 gcpu_ereport_add_logout(nvlist_t *ereport, const gcpu_logout_t *gcl, 605 uint_t bankno, const gcpu_error_disp_t *ged, uint16_t code) 606 { 607 uint64_t members = ged ? ged->ged_ereport_members : 608 FM_EREPORT_PAYLOAD_FLAGS_COMMON; 609 uint64_t mcg = gcl->gcl_mcg_status; 610 int mcip = mcg & MCG_STATUS_MCIP; 611 const gcpu_bank_logout_t *gbl = &gcl->gcl_data[bankno]; 612 uint64_t bstat = gbl->gbl_status; 613 614 /* 615 * Include the compound error name if requested and if this 616 * is a compound error type. 617 */ 618 if (members & FM_EREPORT_PAYLOAD_FLAG_COMPOUND_ERR && ged && 619 ged->ged_compound_fmt != NULL) { 620 char buf[FM_MAX_CLASS]; 621 622 gcpu_mn_fmt(ged->ged_compound_fmt, buf, sizeof (buf), code, 623 GCPU_MN_NAMESPACE_COMPOUND); 624 fm_payload_set(ereport, FM_EREPORT_PAYLOAD_NAME_COMPOUND_ERR, 625 DATA_TYPE_STRING, buf, NULL); 626 } 627 628 /* 629 * Include disposition information for this error 630 */ 631 if (members & FM_EREPORT_PAYLOAD_FLAG_DISP && 632 gbl->gbl_disp != 0) { 633 int i, empty = 1; 634 char buf[128]; 635 char *p = buf, *q = buf + 128; 636 static struct _gcpu_disp_name { 637 uint64_t dv; 638 const char *dn; 639 } disp_names[] = { 640 { CMI_ERRDISP_CURCTXBAD, 641 "processor_context_corrupt" }, 642 { CMI_ERRDISP_RIPV_INVALID, 643 "return_ip_invalid" }, 644 { CMI_ERRDISP_UC_UNCONSTRAINED, 645 "unconstrained" }, 646 { CMI_ERRDISP_FORCEFATAL, 647 "forcefatal" }, 648 { CMI_ERRDISP_IGNORED, 649 "ignored" }, 650 { CMI_ERRDISP_PCC_CLEARED, 651 "corrupt_context_cleared" }, 652 { CMI_ERRDISP_UC_CLEARED, 653 "uncorrected_data_cleared" }, 654 { CMI_ERRDISP_POISONED, 655 "poisoned" }, 656 { CMI_ERRDISP_INCONSISTENT, 657 "telemetry_unstable" }, 658 }; 659 660 for (i = 0; i < sizeof (disp_names) / 661 sizeof (struct _gcpu_disp_name); i++) { 662 if ((gbl->gbl_disp & disp_names[i].dv) == 0) 663 continue; 664 665 (void) snprintf(p, (uintptr_t)q - (uintptr_t)p, 666 "%s%s", empty ? "" : ",", disp_names[i].dn); 667 p += strlen(p); 668 empty = 0; 669 } 670 671 if (p != buf) 672 fm_payload_set(ereport, FM_EREPORT_PAYLOAD_NAME_DISP, 673 DATA_TYPE_STRING, buf, NULL); 674 } 675 676 /* 677 * If MCG_STATUS is included add that and an indication of whether 678 * this ereport was the result of a machine check or poll. 679 */ 680 if (members & FM_EREPORT_PAYLOAD_FLAG_MCG_STATUS) { 681 fm_payload_set(ereport, FM_EREPORT_PAYLOAD_NAME_MCG_STATUS, 682 DATA_TYPE_UINT64, mcg, NULL); 683 684 fm_payload_set(ereport, FM_EREPORT_PAYLOAD_NAME_MCG_STATUS_MCIP, 685 DATA_TYPE_BOOLEAN_VALUE, mcip ? B_TRUE : B_FALSE, NULL); 686 } 687 688 /* 689 * If an instruction pointer is to be included add one provided 690 * MCG_STATUS indicated it is valid; meaningless for polled events. 691 */ 692 if (mcip && members & FM_EREPORT_PAYLOAD_FLAG_IP && 693 mcg & MCG_STATUS_EIPV) { 694 fm_payload_set(ereport, FM_EREPORT_PAYLOAD_NAME_IP, 695 DATA_TYPE_UINT64, gcl->gcl_ip, NULL); 696 } 697 698 /* 699 * Add an indication of whether the trap occured during privileged code. 700 */ 701 if (mcip && members & FM_EREPORT_PAYLOAD_FLAG_PRIV) { 702 fm_payload_set(ereport, FM_EREPORT_PAYLOAD_NAME_PRIV, 703 DATA_TYPE_BOOLEAN_VALUE, 704 gcl->gcl_flags & GCPU_GCL_F_PRIV ? B_TRUE : B_FALSE, NULL); 705 } 706 707 /* 708 * If requested, add the index of the MCA bank. This indicates the 709 * n'th bank of 4 MCA registers, and does not necessarily correspond 710 * to MCi_* - use the bank offset to correlate 711 */ 712 if (members & FM_EREPORT_PAYLOAD_FLAG_BANK_NUM) { 713 fm_payload_set(ereport, 714 /* Bank number */ 715 FM_EREPORT_PAYLOAD_NAME_BANK_NUM, DATA_TYPE_UINT8, bankno, 716 /* Offset of MCi_CTL */ 717 FM_EREPORT_PAYLOAD_NAME_BANK_MSR_OFFSET, DATA_TYPE_UINT64, 718 IA32_MSR_MC(bankno, CTL), 719 NULL); 720 } 721 722 /* 723 * Add MCi_STATUS if requested, and decode it. 724 */ 725 if (members & FM_EREPORT_PAYLOAD_FLAG_MC_STATUS) { 726 const char *tbes[] = { 727 "No tracking", /* 00 */ 728 "Green - below threshold", /* 01 */ 729 "Yellow - above threshold", /* 10 */ 730 "Reserved" /* 11 */ 731 }; 732 733 fm_payload_set(ereport, 734 /* Bank MCi_STATUS */ 735 FM_EREPORT_PAYLOAD_NAME_MC_STATUS, DATA_TYPE_UINT64, bstat, 736 /* Overflow? */ 737 _GCPU_BSTATUS(bstat, OVER), 738 /* Uncorrected? */ 739 _GCPU_BSTATUS(bstat, UC), 740 /* Enabled? */ 741 _GCPU_BSTATUS(bstat, EN), 742 /* Processor context corrupt? */ 743 _GCPU_BSTATUS(bstat, PCC), 744 /* Error code */ 745 FM_EREPORT_PAYLOAD_NAME_MC_STATUS_ERRCODE, 746 DATA_TYPE_UINT16, MCAX86_ERRCODE(bstat), 747 /* Model-specific error code */ 748 FM_EREPORT_PAYLOAD_NAME_MC_STATUS_EXTERRCODE, 749 DATA_TYPE_UINT16, MCAX86_MSERRCODE(bstat), 750 NULL); 751 752 /* 753 * If MCG_CAP.TES_P indicates that that thresholding info 754 * is present in the architural component of the bank status 755 * then include threshold information for this bank. 756 */ 757 if (gcl->gcl_flags & GCPU_GCL_F_TES_P) { 758 fm_payload_set(ereport, 759 FM_EREPORT_PAYLOAD_NAME_MC_STATUS_TES, 760 DATA_TYPE_STRING, tbes[MCAX86_TBES_VALUE(bstat)], 761 NULL); 762 } 763 } 764 765 /* 766 * MCi_ADDR info if requested and valid. 767 */ 768 if (members & FM_EREPORT_PAYLOAD_FLAG_MC_ADDR && 769 bstat & MSR_MC_STATUS_ADDRV) { 770 fm_payload_set(ereport, FM_EREPORT_PAYLOAD_NAME_MC_ADDR, 771 DATA_TYPE_UINT64, gbl->gbl_addr, NULL); 772 } 773 774 /* 775 * MCi_MISC if requested and MCi_STATUS.MISCV). 776 */ 777 if (members & FM_EREPORT_PAYLOAD_FLAG_MC_MISC && 778 bstat & MSR_MC_STATUS_MISCV) { 779 fm_payload_set(ereport, FM_EREPORT_PAYLOAD_NAME_MC_MISC, 780 DATA_TYPE_UINT64, gbl->gbl_misc, NULL); 781 } 782 783 } 784 785 /* 786 * Construct and post an ereport based on the logout information from a 787 * single MCA bank. We are not necessarily running on the cpu that 788 * detected the error. 789 */ 790 static void 791 gcpu_ereport_post(const gcpu_logout_t *gcl, int bankidx, 792 const gcpu_error_disp_t *ged, cms_cookie_t mscookie, uint64_t status) 793 { 794 gcpu_data_t *gcpu = gcl->gcl_gcpu; 795 cmi_hdl_t hdl = gcpu->gcpu_hdl; 796 const gcpu_bank_logout_t *gbl = &gcl->gcl_data[bankidx]; 797 const char *cpuclass = NULL, *leafclass = NULL; 798 uint16_t code = MCAX86_ERRCODE(status); 799 errorq_elem_t *eqep, *scr_eqep; 800 nvlist_t *ereport, *detector; 801 char buf[FM_MAX_CLASS]; 802 const char *classfmt; 803 nv_alloc_t *nva; 804 805 if (panicstr) { 806 if ((eqep = errorq_reserve(ereport_errorq)) == NULL) 807 return; 808 ereport = errorq_elem_nvl(ereport_errorq, eqep); 809 810 /* 811 * Allocate another element for scratch space, but fallback 812 * to the one we have if that fails. We'd like to use the 813 * additional scratch space for nvlist construction. 814 */ 815 if ((scr_eqep = errorq_reserve(ereport_errorq)) != NULL) 816 nva = errorq_elem_nva(ereport_errorq, scr_eqep); 817 else 818 nva = errorq_elem_nva(ereport_errorq, eqep); 819 } else { 820 ereport = fm_nvlist_create(NULL); 821 nva = NULL; 822 } 823 824 if (ereport == NULL) 825 return; 826 827 /* 828 * Common payload data required by the protocol: 829 * - ereport class 830 * - detector 831 * - ENA 832 */ 833 834 /* 835 * Ereport class - call into model-specific support to allow it to 836 * provide a cpu class or leaf class, otherwise calculate our own. 837 */ 838 cms_ereport_class(hdl, mscookie, &cpuclass, &leafclass); 839 classfmt = ged ? ged->ged_class_fmt : FM_EREPORT_CPU_GENERIC_UNKNOWN; 840 gcpu_erpt_clsfmt(classfmt, buf, sizeof (buf), status, cpuclass, 841 leafclass); 842 843 /* 844 * The detector FMRI. 845 */ 846 if ((detector = cms_ereport_detector(hdl, mscookie, nva)) == NULL) 847 detector = gcpu_fmri_create(hdl, nva); 848 849 /* 850 * Should we define a new ENA format 3?? for chip/core/strand? 851 * It will be better when virtualized. 852 */ 853 fm_ereport_set(ereport, FM_EREPORT_VERSION, buf, 854 fm_ena_generate_cpu(gcl->gcl_timestamp, 855 cmi_hdl_chipid(hdl) << 6 | cmi_hdl_coreid(hdl) << 3 | 856 cmi_hdl_strandid(hdl), FM_ENA_FMT1), detector, NULL); 857 858 if (panicstr) { 859 fm_nvlist_destroy(detector, FM_NVA_RETAIN); 860 nv_alloc_reset(nva); 861 } else { 862 fm_nvlist_destroy(detector, FM_NVA_FREE); 863 } 864 865 /* 866 * Add the architectural ereport class-specific payload data. 867 */ 868 gcpu_ereport_add_logout(ereport, gcl, bankidx, ged, code); 869 870 /* 871 * Allow model-specific code to add ereport members. 872 */ 873 cms_ereport_add_logout(hdl, ereport, nva, bankidx, gbl->gbl_status, 874 gbl->gbl_addr, gbl->gbl_misc, gcl->gcl_ms_logout, mscookie); 875 876 /* 877 * Include stack if options is turned on and either selected in 878 * the payload member bitmask or inclusion is forced. 879 */ 880 if (gcpu_mca_stack_flag && 881 (cms_ereport_includestack(hdl, mscookie) == 882 B_TRUE || gcpu_mca_stack_ereport_include)) { 883 fm_payload_stack_add(ereport, gcl->gcl_stack, 884 gcl->gcl_stackdepth); 885 } 886 887 /* 888 * Post ereport. 889 */ 890 if (panicstr) { 891 errorq_commit(ereport_errorq, eqep, ERRORQ_SYNC); 892 if (scr_eqep) 893 errorq_cancel(ereport_errorq, scr_eqep); 894 } else { 895 (void) fm_ereport_post(ereport, EVCH_TRYHARD); 896 fm_nvlist_destroy(ereport, FM_NVA_FREE); 897 } 898 899 } 900 901 /*ARGSUSED*/ 902 void 903 gcpu_mca_drain(void *ignored, const void *data, const errorq_elem_t *eqe) 904 { 905 const gcpu_logout_t *gcl = data; 906 const gcpu_bank_logout_t *gbl; 907 int i; 908 909 for (i = 0, gbl = &gcl->gcl_data[0]; i < gcl->gcl_nbanks; i++, gbl++) { 910 const gcpu_error_disp_t *gened; 911 cms_cookie_t mscookie; 912 913 if (gbl->gbl_status & MSR_MC_STATUS_VAL && 914 !(gbl->gbl_disp & CMI_ERRDISP_INCONSISTENT)) { 915 uint16_t code = MCAX86_ERRCODE(gbl->gbl_status); 916 917 /* 918 * Perform a match based on IA32 MCA architectural 919 * components alone. 920 */ 921 gened = gcpu_disp_match(code); /* may be NULL */ 922 923 /* 924 * Now see if an model-specific match can be made. 925 */ 926 mscookie = cms_disp_match(gcl->gcl_gcpu->gcpu_hdl, i, 927 gbl->gbl_status, gbl->gbl_addr, gbl->gbl_misc, 928 gcl->gcl_ms_logout); 929 930 /* 931 * Prepare and dispatch an ereport for logging and 932 * diagnosis. 933 */ 934 gcpu_ereport_post(gcl, i, gened, mscookie, 935 gbl->gbl_status); 936 } else if (gbl->gbl_status & MSR_MC_STATUS_VAL && 937 (gbl->gbl_disp & CMI_ERRDISP_INCONSISTENT)) { 938 /* 939 * Telemetry kept changing as we tried to read 940 * it. Force an unknown ereport leafclass but 941 * keep the telemetry unchanged for logging. 942 */ 943 gcpu_ereport_post(gcl, i, &gcpu_unknown, NULL, 944 gbl->gbl_status); 945 } 946 } 947 } 948 949 static size_t gcpu_mca_queue_datasz = 0; 950 951 /* 952 * The following code is ready to make a weak attempt at growing the 953 * errorq structure size. Since it is not foolproof (we don't know 954 * who may already be producing to the outgoing errorq) our caller 955 * instead assures that we'll always be called with no greater data 956 * size than on our first call. 957 */ 958 static void 959 gcpu_errorq_init(size_t datasz) 960 { 961 int slots; 962 963 mutex_enter(&gcpu_mca_queue_lock); 964 965 if (gcpu_mca_queue_datasz >= datasz) { 966 mutex_exit(&gcpu_mca_queue_lock); 967 return; 968 } 969 970 membar_producer(); 971 if (gcpu_mca_queue) { 972 gcpu_mca_queue_datasz = 0; 973 errorq_destroy(gcpu_mca_queue); 974 } 975 976 slots = MAX(GCPU_MCA_ERRS_PERCPU * max_ncpus, GCPU_MCA_MIN_ERRORS); 977 slots = MIN(slots, GCPU_MCA_MAX_ERRORS); 978 979 gcpu_mca_queue = errorq_create("gcpu_mca_queue", gcpu_mca_drain, 980 NULL, slots, datasz, 1, ERRORQ_VITAL); 981 982 if (gcpu_mca_queue != NULL) 983 gcpu_mca_queue_datasz = datasz; 984 985 mutex_exit(&gcpu_mca_queue_lock); 986 } 987 988 /* 989 * Perform MCA initialization as described in section 14.6 of Intel 64 990 * and IA-32 Architectures Software Developer's Manual Volume 3A. 991 */ 992 993 static uint_t global_nbanks; 994 995 void 996 gcpu_mca_init(cmi_hdl_t hdl) 997 { 998 gcpu_data_t *gcpu = cmi_hdl_getcmidata(hdl); 999 uint64_t cap; 1000 uint_t vendor = cmi_hdl_vendor(hdl); 1001 uint_t family = cmi_hdl_family(hdl); 1002 gcpu_mca_t *mca = &gcpu->gcpu_mca; 1003 int mcg_ctl_present; 1004 uint_t nbanks; 1005 size_t mslsz; 1006 int i; 1007 int mcg_ctl2_present; 1008 uint32_t cmci_capable = 0; 1009 1010 if (gcpu == NULL) 1011 return; 1012 1013 /* 1014 * Protect from some silly /etc/system settings. 1015 */ 1016 if (gcpu_mca_telemetry_retries < 0 || gcpu_mca_telemetry_retries > 100) 1017 gcpu_mca_telemetry_retries = 5; 1018 1019 if (cmi_hdl_rdmsr(hdl, IA32_MSR_MCG_CAP, &cap) != CMI_SUCCESS) 1020 return; 1021 1022 /* 1023 * CPU startup code only calls cmi_mca_init if x86_feature indicates 1024 * both MCA and MCE support (i.e., X86_MCA). P5, K6, and earlier 1025 * processors, which have their own * more primitive way of doing 1026 * machine checks, will not have cmi_mca_init called since their 1027 * CPUID information will not indicate both MCA and MCE features. 1028 */ 1029 #ifndef __xpv 1030 ASSERT(x86_feature & X86_MCA); 1031 #endif /* __xpv */ 1032 1033 /* 1034 * Determine whether the IA32_MCG_CTL register is present. If it 1035 * is we will enable all features by writing -1 to it towards 1036 * the end of this initialization; if it is absent then volume 3A 1037 * says we must nonetheless continue to initialize the individual 1038 * banks. 1039 */ 1040 mcg_ctl_present = cap & MCG_CAP_CTL_P; 1041 mcg_ctl2_present = cap & MCG_CAP_CTL2_P; 1042 1043 /* 1044 * We squirell values away for inspection/debugging. 1045 */ 1046 mca->gcpu_mca_bioscfg.bios_mcg_cap = cap; 1047 if (mcg_ctl_present) 1048 (void) cmi_hdl_rdmsr(hdl, IA32_MSR_MCG_CTL, 1049 &mca->gcpu_mca_bioscfg.bios_mcg_ctl); 1050 1051 /* 1052 * Determine the number of error-reporting banks implemented. 1053 */ 1054 mca->gcpu_mca_nbanks = nbanks = cap & MCG_CAP_COUNT_MASK; 1055 1056 if (nbanks != 0 && global_nbanks == 0) 1057 global_nbanks = nbanks; /* no race - BSP will get here first */ 1058 1059 /* 1060 * If someone is hiding the number of banks (perhaps we are fully 1061 * virtualized?) or if this processor has more banks than the 1062 * first to set global_nbanks then bail. The latter requirement 1063 * is because we need to size our errorq data structure and we 1064 * don't want to have to grow the errorq (destroy and recreate) 1065 * which may just lose some telemetry. 1066 */ 1067 if (nbanks == 0 || nbanks > global_nbanks) 1068 return; 1069 1070 mca->gcpu_mca_bioscfg.bios_bankcfg = kmem_zalloc(nbanks * 1071 sizeof (struct gcpu_bios_bankcfg), KM_SLEEP); 1072 1073 /* 1074 * Calculate the size we need to allocate for a gcpu_logout_t 1075 * with a gcl_data array big enough for all banks of this cpu. 1076 * Add any space requested by the model-specific logout support. 1077 */ 1078 mslsz = cms_logout_size(hdl); 1079 mca->gcpu_mca_lgsz = sizeof (gcpu_logout_t) + 1080 (nbanks - 1) * sizeof (gcpu_bank_logout_t) + mslsz; 1081 1082 for (i = 0; i < GCPU_MCA_LOGOUT_NUM; i++) { 1083 gcpu_logout_t *gcl; 1084 1085 mca->gcpu_mca_logout[i] = gcl = 1086 kmem_zalloc(mca->gcpu_mca_lgsz, KM_SLEEP); 1087 gcl->gcl_gcpu = gcpu; 1088 gcl->gcl_nbanks = nbanks; 1089 gcl->gcl_ms_logout = (mslsz == 0) ? NULL : 1090 (char *)(&gcl->gcl_data[0]) + nbanks * 1091 sizeof (gcpu_bank_logout_t); 1092 1093 } 1094 mca->gcpu_mca_nextpoll_idx = GCPU_MCA_LOGOUT_POLLER_1; 1095 1096 mca->gcpu_bank_cmci = kmem_zalloc(sizeof (gcpu_mca_cmci_t) * nbanks, 1097 KM_SLEEP); 1098 1099 /* 1100 * Create our errorq to transport the logout structures. This 1101 * can fail so users of gcpu_mca_queue must be prepared for NULL. 1102 */ 1103 gcpu_errorq_init(mca->gcpu_mca_lgsz); 1104 1105 /* 1106 * Not knowing which, if any, banks are shared between cores we 1107 * assure serialization of MCA bank initialization by each cpu 1108 * on the chip. On chip architectures in which some banks are 1109 * shared this will mean the shared resource is initialized more 1110 * than once - we're simply aiming to avoid simultaneous MSR writes 1111 * to the shared resource. 1112 * 1113 * Even with these precautions, some platforms may yield a GP fault 1114 * if a core other than a designated master tries to write anything 1115 * but all 0's to MCi_{STATUS,ADDR,CTL}. So we will perform 1116 * those writes under on_trap protection. 1117 */ 1118 mutex_enter(&gcpu->gcpu_shared->gcpus_cfglock); 1119 1120 /* 1121 * Initialize poller data, but don't start polling yet. 1122 */ 1123 gcpu_mca_poll_init(hdl); 1124 1125 /* 1126 * Work out which MCA banks we will initialize. In MCA logout 1127 * code we will only read those banks which we initialize here. 1128 */ 1129 for (i = 0; i < nbanks; i++) { 1130 /* 1131 * On AMD family 6 we must not enable 1132 * machine check from bank 0 detectors. 1133 * AMD case reports are that enabling bank 0 (DC) produces 1134 * spurious machine checks. 1135 * For Intel we let plug-in choose to skip bank if plug-in 1136 * is enabled otherwise we skip bank 0 for family 6 1137 */ 1138 if (i == 0 && 1139 (((vendor == X86_VENDOR_Intel && !cms_present(hdl)) || 1140 vendor == X86_VENDOR_AMD) && family == 6)) 1141 continue; 1142 1143 if (cms_bankctl_skipinit(hdl, i)) 1144 continue; 1145 1146 /* 1147 * Record which MCA banks were enabled, both from the 1148 * point of view of this core and accumulating for the 1149 * whole chip (if some cores share a bank we must be 1150 * sure either can logout from it). 1151 */ 1152 mca->gcpu_actv_banks |= 1 << i; 1153 atomic_or_32(&gcpu->gcpu_shared->gcpus_actv_banks, 1 << i); 1154 1155 /* 1156 * check CMCI capability 1157 */ 1158 if (mcg_ctl2_present) { 1159 uint64_t ctl2; 1160 uint32_t cap = 0; 1161 (void) cmi_hdl_rdmsr(hdl, IA32_MSR_MC_CTL2(i), &ctl2); 1162 if (ctl2 & MSR_MC_CTL2_EN) 1163 continue; 1164 ctl2 |= MSR_MC_CTL2_EN; 1165 (void) cmi_hdl_wrmsr(hdl, IA32_MSR_MC_CTL2(i), ctl2); 1166 (void) cmi_hdl_rdmsr(hdl, IA32_MSR_MC_CTL2(i), &ctl2); 1167 mca->gcpu_bank_cmci[i].cmci_cap = cap = 1168 (ctl2 & MSR_MC_CTL2_EN) ? 1 : 0; 1169 if (cap) 1170 cmci_capable ++; 1171 /* 1172 * Set threshold to 1 while unset the en field, to avoid 1173 * CMCI trigged before APIC LVT entry init. 1174 */ 1175 ctl2 = ctl2 & (~MSR_MC_CTL2_EN) | 1; 1176 (void) cmi_hdl_wrmsr(hdl, IA32_MSR_MC_CTL2(i), ctl2); 1177 1178 /* 1179 * init cmci related count 1180 */ 1181 mca->gcpu_bank_cmci[i].cmci_enabled = 0; 1182 mca->gcpu_bank_cmci[i].drtcmci = 0; 1183 mca->gcpu_bank_cmci[i].ncmci = 0; 1184 } 1185 } 1186 if (cmci_capable) 1187 cmi_enable_cmci = 1; 1188 1189 /* 1190 * Log any valid telemetry lurking in the MCA banks, but do not 1191 * clear the status registers. Ignore the disposition returned - 1192 * we have already paniced or reset for any nasty errors found here. 1193 * 1194 * Intel vol 3A says that we should not do this on family 0x6, 1195 * and that for any extended family the BIOS clears things 1196 * on power-on reset so you'll only potentially find valid telemetry 1197 * on warm reset (we do it for both - on power-on reset we should 1198 * just see zeroes). 1199 * 1200 * AMD docs since K7 say we should process anything we find here. 1201 */ 1202 if (!gcpu_suppress_log_on_init && 1203 (vendor == X86_VENDOR_Intel && family >= 0xf || 1204 vendor == X86_VENDOR_AMD)) 1205 gcpu_mca_logout(hdl, NULL, -1ULL, NULL, B_FALSE, 1206 GCPU_MPT_WHAT_POKE_ERR); 1207 1208 /* 1209 * Initialize all MCi_CTL and clear all MCi_STATUS, allowing the 1210 * model-specific module the power of veto. 1211 */ 1212 for (i = 0; i < nbanks; i++) { 1213 struct gcpu_bios_bankcfg *bcfgp = 1214 mca->gcpu_mca_bioscfg.bios_bankcfg + i; 1215 1216 /* 1217 * Stash inherited bank MCA state, even for banks we will 1218 * not initialize ourselves. Do not read the MISC register 1219 * unconditionally - on some processors that will #GP on 1220 * banks that do not implement the MISC register (would be 1221 * caught by on_trap, anyway). 1222 */ 1223 (void) cmi_hdl_rdmsr(hdl, IA32_MSR_MC(i, CTL), 1224 &bcfgp->bios_bank_ctl); 1225 1226 (void) cmi_hdl_rdmsr(hdl, IA32_MSR_MC(i, STATUS), 1227 &bcfgp->bios_bank_status); 1228 1229 if (bcfgp->bios_bank_status & MSR_MC_STATUS_ADDRV) 1230 (void) cmi_hdl_rdmsr(hdl, IA32_MSR_MC(i, ADDR), 1231 &bcfgp->bios_bank_addr); 1232 1233 /* 1234 * In some old BIOS the status value after boot can indicate 1235 * MISCV when there is actually no MISC register for 1236 * that bank. The following read could therefore 1237 * aggravate a general protection fault. This should be 1238 * caught by on_trap, but the #GP fault handler is busted 1239 * and can suffer a double fault even before we get to 1240 * trap() to check for on_trap protection. Until that 1241 * issue is fixed we remove the one access that we know 1242 * can cause a #GP. 1243 * 1244 * if (bcfgp->bios_bank_status & MSR_MC_STATUS_MISCV) 1245 * (void) cmi_hdl_rdmsr(hdl, IA32_MSR_MC(i, MISC), 1246 * &bcfgp->bios_bank_misc); 1247 */ 1248 bcfgp->bios_bank_misc = 0; 1249 1250 if (!(mca->gcpu_actv_banks & 1 << i)) 1251 continue; 1252 1253 (void) cmi_hdl_wrmsr(hdl, IA32_MSR_MC(i, CTL), 1254 cms_bankctl_val(hdl, i, -1ULL)); 1255 1256 if (!cms_bankstatus_skipinit(hdl, i)) { 1257 (void) cmi_hdl_wrmsr(hdl, IA32_MSR_MC(i, STATUS), 1258 cms_bankstatus_val(hdl, i, 0ULL)); 1259 } 1260 } 1261 1262 /* 1263 * Now let the model-specific support perform further initialization 1264 * of non-architectural features. 1265 */ 1266 cms_mca_init(hdl, nbanks); 1267 1268 (void) cmi_hdl_wrmsr(hdl, IA32_MSR_MCG_STATUS, 0ULL); 1269 membar_producer(); 1270 1271 /* enable all machine-check features */ 1272 if (mcg_ctl_present) 1273 (void) cmi_hdl_wrmsr(hdl, IA32_MSR_MCG_CTL, 1274 cms_mcgctl_val(hdl, nbanks, -1ULL)); 1275 1276 mutex_exit(&gcpu->gcpu_shared->gcpus_cfglock); 1277 1278 /* enable machine-check exception in CR4 */ 1279 cmi_hdl_enable_mce(hdl); 1280 } 1281 1282 static uint64_t 1283 gcpu_mca_process(cmi_hdl_t hdl, struct regs *rp, int nerr, gcpu_data_t *gcpu, 1284 gcpu_logout_t *gcl, int ismc, gcpu_mce_status_t *mcesp) 1285 { 1286 int curctxbad = 0, unconstrained = 0, forcefatal = 0; 1287 gcpu_mca_t *mca = &gcpu->gcpu_mca; 1288 int nbanks = mca->gcpu_mca_nbanks; 1289 gcpu_mce_status_t mce; 1290 gcpu_bank_logout_t *gbl; 1291 uint64_t disp = 0; 1292 int i; 1293 1294 if (mcesp == NULL) 1295 mcesp = &mce; 1296 1297 mcesp->mce_nerr = nerr; 1298 1299 mcesp->mce_npcc = mcesp->mce_npcc_ok = mcesp->mce_nuc = 1300 mcesp->mce_nuc_ok = mcesp->mce_nuc_poisoned = 1301 mcesp->mce_forcefatal = mcesp->mce_ignored = 0; 1302 1303 /* 1304 * If this a machine check then if the return instruction pointer 1305 * is not valid the current context is lost. 1306 */ 1307 if (ismc && !(gcl->gcl_mcg_status & MCG_STATUS_RIPV)) 1308 disp |= CMI_ERRDISP_RIPV_INVALID; 1309 1310 for (i = 0, gbl = &gcl->gcl_data[0]; i < nbanks; i++, gbl++) { 1311 uint64_t mcistatus = gbl->gbl_status; 1312 uint32_t ms_scope; 1313 int pcc, uc; 1314 int poisoned; 1315 1316 if (!(mcistatus & MSR_MC_STATUS_VAL)) 1317 continue; 1318 1319 if (gbl->gbl_disp & CMI_ERRDISP_INCONSISTENT) 1320 continue; 1321 1322 pcc = (mcistatus & MSR_MC_STATUS_PCC) != 0; 1323 uc = (mcistatus & MSR_MC_STATUS_UC) != 0; 1324 mcesp->mce_npcc += pcc; 1325 mcesp->mce_nuc += uc; 1326 1327 ms_scope = cms_error_action(hdl, ismc, i, mcistatus, 1328 gbl->gbl_addr, gbl->gbl_misc, gcl->gcl_ms_logout); 1329 1330 if (pcc && ms_scope & CMS_ERRSCOPE_CURCONTEXT_OK) { 1331 pcc = 0; 1332 mcesp->mce_npcc_ok++; 1333 gbl->gbl_disp |= CMI_ERRDISP_PCC_CLEARED; 1334 } 1335 1336 if (uc && ms_scope & CMS_ERRSCOPE_CLEARED_UC) { 1337 uc = 0; 1338 mcesp->mce_nuc_ok++; 1339 gbl->gbl_disp |= CMI_ERRDISP_UC_CLEARED; 1340 } 1341 1342 if (uc) { 1343 poisoned = (ms_scope & CMS_ERRSCOPE_POISONED) != 0; 1344 if (poisoned) { 1345 mcesp->mce_nuc_poisoned++; 1346 gbl->gbl_disp |= CMI_ERRDISP_POISONED; 1347 } 1348 } 1349 1350 if ((ms_scope & CMS_ERRSCOPE_IGNORE_ERR) == 0) { 1351 /* 1352 * We're not being instructed to ignore the error, 1353 * so apply our standard disposition logic to it. 1354 */ 1355 if (uc && !poisoned) { 1356 unconstrained++; 1357 gbl->gbl_disp |= disp | 1358 CMI_ERRDISP_UC_UNCONSTRAINED; 1359 } 1360 1361 if (pcc && ismc) { 1362 curctxbad++; 1363 gbl->gbl_disp |= disp | 1364 CMI_ERRDISP_CURCTXBAD; 1365 } 1366 1367 /* 1368 * Even if the above may not indicate that the error 1369 * is terminal, model-specific support may insist 1370 * that we treat it as such. Such errors wil be 1371 * fatal even if discovered via poll. 1372 */ 1373 if (ms_scope & CMS_ERRSCOPE_FORCE_FATAL) { 1374 forcefatal++; 1375 mcesp->mce_forcefatal++; 1376 gbl->gbl_disp |= disp | 1377 CMI_ERRDISP_FORCEFATAL; 1378 } 1379 } else { 1380 mcesp->mce_ignored++; 1381 gbl->gbl_disp |= disp | CMI_ERRDISP_IGNORED; 1382 } 1383 } 1384 1385 if (unconstrained > 0) 1386 disp |= CMI_ERRDISP_UC_UNCONSTRAINED; 1387 1388 if (curctxbad > 0) 1389 disp |= CMI_ERRDISP_CURCTXBAD; 1390 1391 if (forcefatal > 0) 1392 disp |= CMI_ERRDISP_FORCEFATAL; 1393 1394 if (gcpu_mca_queue != NULL) { 1395 int how; 1396 1397 if (ismc) { 1398 how = cmi_mce_response(rp, disp) ? 1399 ERRORQ_ASYNC : /* no panic, so arrange drain */ 1400 ERRORQ_SYNC; /* panic flow will drain */ 1401 } else { 1402 how = (disp & CMI_ERRDISP_FORCEFATAL && 1403 cmi_panic_on_ue()) ? 1404 ERRORQ_SYNC : /* poller will panic */ 1405 ERRORQ_ASYNC; /* no panic */ 1406 } 1407 1408 errorq_dispatch(gcpu_mca_queue, gcl, mca->gcpu_mca_lgsz, how); 1409 } else if (disp != 0) { 1410 gcpu_bleat(hdl, gcl); 1411 } 1412 1413 mcesp->mce_disp = disp; 1414 1415 return (disp); 1416 } 1417 1418 /* 1419 * Gather error telemetry from our source, and then submit it for 1420 * processing. 1421 */ 1422 1423 #define IS_MCE_CANDIDATE(status) (((status) & MSR_MC_STATUS_EN) != 0 && \ 1424 ((status) & (MSR_MC_STATUS_UC | MSR_MC_STATUS_PCC)) != 0) 1425 1426 #define STATUS_EQV(s1, s2) \ 1427 (((s1) & ~MSR_MC_STATUS_OVER) == ((s2) & ~MSR_MC_STATUS_OVER)) 1428 1429 static uint32_t gcpu_deferrred_polled_clears; 1430 1431 static void 1432 gcpu_cmci_logout(cmi_hdl_t hdl, int bank, gcpu_mca_cmci_t *bank_cmci_p, 1433 uint64_t status, int what) 1434 { 1435 uint64_t ctl2; 1436 1437 if (bank_cmci_p->cmci_cap && (what == GCPU_MPT_WHAT_CYC_ERR) && 1438 (!(status & MSR_MC_STATUS_VAL) || ((status & MSR_MC_STATUS_VAL) && 1439 !(status & MSR_MC_STATUS_CEC_MASK)))) { 1440 1441 if (!(bank_cmci_p->cmci_enabled)) { 1442 /* 1443 * when cmci is disabled, and the bank has no error or 1444 * no corrected error for 1445 * gcpu_mca_cmci_reenable_threshold consecutive polls, 1446 * turn on this bank's cmci. 1447 */ 1448 1449 bank_cmci_p->drtcmci ++; 1450 1451 if (bank_cmci_p->drtcmci >= 1452 gcpu_mca_cmci_reenable_threshold) { 1453 1454 /* turn on cmci */ 1455 1456 (void) cmi_hdl_rdmsr(hdl, 1457 IA32_MSR_MC_CTL2(bank), &ctl2); 1458 ctl2 |= MSR_MC_CTL2_EN; 1459 (void) cmi_hdl_wrmsr(hdl, 1460 IA32_MSR_MC_CTL2(bank), ctl2); 1461 1462 /* reset counter and set flag */ 1463 bank_cmci_p->drtcmci = 0; 1464 bank_cmci_p->cmci_enabled = 1; 1465 } 1466 } else { 1467 /* 1468 * when cmci is enabled,if is in cyclic poll and the 1469 * bank has no error or no corrected error, reset ncmci 1470 * counter 1471 */ 1472 bank_cmci_p->ncmci = 0; 1473 } 1474 } 1475 } 1476 1477 static void 1478 gcpu_cmci_throttle(cmi_hdl_t hdl, int bank, gcpu_mca_cmci_t *bank_cmci_p, 1479 int what) 1480 { 1481 uint64_t ctl2 = 0; 1482 1483 /* 1484 * if cmci of this bank occurred beyond 1485 * gcpu_mca_cmci_throttling_threshold between 2 polls, 1486 * turn off this bank's CMCI; 1487 */ 1488 if (bank_cmci_p->cmci_enabled && what == GCPU_MPT_WHAT_CMCI_ERR) { 1489 1490 /* if it is cmci trap, increase the count */ 1491 bank_cmci_p->ncmci++; 1492 1493 if (bank_cmci_p->ncmci >= gcpu_mca_cmci_throttling_threshold) { 1494 1495 /* turn off cmci */ 1496 1497 (void) cmi_hdl_rdmsr(hdl, IA32_MSR_MC_CTL2(bank), 1498 &ctl2); 1499 ctl2 &= ~MSR_MC_CTL2_EN; 1500 (void) cmi_hdl_wrmsr(hdl, IA32_MSR_MC_CTL2(bank), 1501 ctl2); 1502 1503 /* clear the flag and count */ 1504 1505 bank_cmci_p->cmci_enabled = 0; 1506 bank_cmci_p->ncmci = 0; 1507 } 1508 } 1509 } 1510 1511 void 1512 gcpu_mca_logout(cmi_hdl_t hdl, struct regs *rp, uint64_t bankmask, 1513 gcpu_mce_status_t *mcesp, boolean_t clrstatus, int what) 1514 { 1515 gcpu_data_t *gcpu = cmi_hdl_getcmidata(hdl); 1516 gcpu_mca_t *mca = &gcpu->gcpu_mca; 1517 int nbanks = mca->gcpu_mca_nbanks; 1518 gcpu_bank_logout_t *gbl, *pgbl; 1519 gcpu_logout_t *gcl, *pgcl; 1520 int ismc = (rp != NULL); 1521 int ispoll = !ismc; 1522 int i, nerr = 0; 1523 cmi_errno_t err; 1524 uint64_t mcg_status; 1525 uint64_t disp; 1526 uint64_t cap; 1527 1528 if (cmi_hdl_rdmsr(hdl, IA32_MSR_MCG_STATUS, &mcg_status) != 1529 CMI_SUCCESS || cmi_hdl_rdmsr(hdl, IA32_MSR_MCG_CAP, &cap) != 1530 CMI_SUCCESS) { 1531 if (mcesp != NULL) 1532 mcesp->mce_nerr = mcesp->mce_disp = 0; 1533 return; 1534 } 1535 1536 if (ismc) { 1537 gcl = mca->gcpu_mca_logout[GCPU_MCA_LOGOUT_EXCEPTION]; 1538 } else { 1539 int pidx = mca->gcpu_mca_nextpoll_idx; 1540 int ppidx = (pidx == GCPU_MCA_LOGOUT_POLLER_1) ? 1541 GCPU_MCA_LOGOUT_POLLER_2 : GCPU_MCA_LOGOUT_POLLER_1; 1542 1543 gcl = mca->gcpu_mca_logout[pidx]; /* current logout */ 1544 pgcl = mca->gcpu_mca_logout[ppidx]; /* previous logout */ 1545 mca->gcpu_mca_nextpoll_idx = ppidx; /* switch next time */ 1546 } 1547 1548 gcl->gcl_timestamp = gethrtime_waitfree(); 1549 gcl->gcl_mcg_status = mcg_status; 1550 gcl->gcl_ip = rp ? rp->r_pc : 0; 1551 1552 gcl->gcl_flags = (rp && USERMODE(rp->r_cs)) ? GCPU_GCL_F_PRIV : 0; 1553 if (cap & MCG_CAP_TES_P) 1554 gcl->gcl_flags |= GCPU_GCL_F_TES_P; 1555 1556 for (i = 0, gbl = &gcl->gcl_data[0]; i < nbanks; i++, gbl++) { 1557 uint64_t status, status2, addr, misc; 1558 int retries = gcpu_mca_telemetry_retries; 1559 1560 gbl->gbl_status = 0; 1561 gbl->gbl_disp = 0; 1562 gbl->gbl_clrdefcnt = 0; 1563 1564 /* 1565 * Only logout from MCA banks we have initialized from at 1566 * least one core. If a core shares an MCA bank with another 1567 * but perhaps lost the race to initialize it, then it must 1568 * still be allowed to logout from the shared bank. 1569 */ 1570 if (!(gcpu->gcpu_shared->gcpus_actv_banks & 1 << i)) 1571 continue; 1572 1573 /* 1574 * On a poll look only at the banks we've been asked to check. 1575 */ 1576 if (rp == NULL && !(bankmask & 1 << i)) 1577 continue; 1578 1579 1580 if (cmi_hdl_rdmsr(hdl, IA32_MSR_MC(i, STATUS), &status) != 1581 CMI_SUCCESS) 1582 continue; 1583 1584 gcpu_cmci_logout(hdl, i, &mca->gcpu_bank_cmci[i], status, what); 1585 1586 retry: 1587 if (!(status & MSR_MC_STATUS_VAL)) 1588 continue; 1589 1590 addr = -1; 1591 misc = 0; 1592 1593 if (status & MSR_MC_STATUS_ADDRV) 1594 (void) cmi_hdl_rdmsr(hdl, IA32_MSR_MC(i, ADDR), &addr); 1595 1596 if (status & MSR_MC_STATUS_MISCV) 1597 (void) cmi_hdl_rdmsr(hdl, IA32_MSR_MC(i, MISC), &misc); 1598 1599 gcpu_cmci_throttle(hdl, i, &mca->gcpu_bank_cmci[i], what); 1600 1601 /* 1602 * Allow the model-specific code to extract bank telemetry. 1603 */ 1604 cms_bank_logout(hdl, i, status, addr, misc, gcl->gcl_ms_logout); 1605 1606 /* 1607 * Not all cpu models assure us that the status/address/misc 1608 * data will not change during the above sequence of MSR reads, 1609 * or that it can only change by the addition of the OVerflow 1610 * bit to the status register. If the status has changed 1611 * other than in the overflow bit then we attempt to reread 1612 * for a consistent snapshot, but eventually give up and 1613 * go with what we've got. We only perform this check 1614 * for a poll - a further #MC during a #MC will reset, and 1615 * polled errors should not overwrite higher-priority 1616 * trapping errors (but could set the overflow bit). 1617 */ 1618 if (ispoll && (err = cmi_hdl_rdmsr(hdl, IA32_MSR_MC(i, STATUS), 1619 &status2)) == CMI_SUCCESS) { 1620 if (!STATUS_EQV(status, status2)) { 1621 if (retries-- > 0) { 1622 status = status2; 1623 goto retry; 1624 } else { 1625 gbl->gbl_disp |= 1626 CMI_ERRDISP_INCONSISTENT; 1627 } 1628 } 1629 } else if (ispoll && err != CMI_SUCCESS) { 1630 gbl->gbl_disp |= CMI_ERRDISP_INCONSISTENT; 1631 } 1632 1633 nerr++; 1634 gbl->gbl_status = status; 1635 gbl->gbl_addr = addr; 1636 gbl->gbl_misc = misc; 1637 1638 if (clrstatus == B_FALSE) 1639 goto serialize; 1640 1641 /* 1642 * For machine checks we always clear status here. For polls 1643 * we must be a little more cautious since there is an 1644 * outside chance that we may clear telemetry from a shared 1645 * MCA bank on which a sibling core is machine checking. 1646 * 1647 * For polled observations of errors that look like they may 1648 * produce a machine check (UC/PCC and ENabled, although these 1649 * do not guarantee a machine check on error occurence) 1650 * we will not clear the status at this wakeup unless 1651 * we saw the same status at the previous poll. We will 1652 * always process and log the current observations - it 1653 * is only the clearing of MCi_STATUS which may be 1654 * deferred until the next wakeup. 1655 */ 1656 if (ismc || !IS_MCE_CANDIDATE(status)) { 1657 (void) cmi_hdl_wrmsr(hdl, IA32_MSR_MC(i, STATUS), 0ULL); 1658 goto serialize; 1659 } 1660 1661 /* 1662 * We have a polled observation of a machine check 1663 * candidate. If we saw essentially the same status at the 1664 * last poll then clear the status now since this appears 1665 * not to be a #MC candidate after all. If we see quite 1666 * different status now then do not clear, but reconsider at 1667 * the next poll. In no actual machine check clears 1668 * the status in the interim then the status should not 1669 * keep changing forever (meaning we'd never clear it) 1670 * since before long we'll simply have latched the highest- 1671 * priority error and set the OVerflow bit. Nonetheless 1672 * we count how many times we defer clearing and after 1673 * a while insist on clearing the status. 1674 */ 1675 pgbl = &pgcl->gcl_data[i]; 1676 if (pgbl->gbl_clrdefcnt != 0) { 1677 /* We deferred clear on this bank at last wakeup */ 1678 if (STATUS_EQV(status, pgcl->gcl_data[i].gbl_status) || 1679 pgbl->gbl_clrdefcnt > 5) { 1680 /* 1681 * Status is unchanged so clear it now and, 1682 * since we have already logged this info, 1683 * avoid logging it again. 1684 */ 1685 gbl->gbl_status = 0; 1686 nerr--; 1687 (void) cmi_hdl_wrmsr(hdl, 1688 IA32_MSR_MC(i, STATUS), 0ULL); 1689 } else { 1690 /* Record deferral for next wakeup */ 1691 gbl->gbl_clrdefcnt = pgbl->gbl_clrdefcnt + 1; 1692 } 1693 } else { 1694 /* Record initial deferral for next wakeup */ 1695 gbl->gbl_clrdefcnt = 1; 1696 gcpu_deferrred_polled_clears++; 1697 } 1698 1699 serialize: 1700 /* 1701 * Intel Vol 3A says to execute a serializing instruction 1702 * here, ie CPUID. Well WRMSR is also defined to be 1703 * serializing, so the status clear above should suffice. 1704 * To be a good citizen, and since some clears are deferred, 1705 * we'll execute a CPUID instruction here. 1706 */ 1707 { 1708 struct cpuid_regs tmp; 1709 (void) __cpuid_insn(&tmp); 1710 } 1711 } 1712 1713 if (gcpu_mca_stack_flag) 1714 gcl->gcl_stackdepth = getpcstack(gcl->gcl_stack, FM_STK_DEPTH); 1715 else 1716 gcl->gcl_stackdepth = 0; 1717 1718 /* 1719 * Decide our disposition for this error or errors, and submit for 1720 * logging and subsequent diagnosis. 1721 */ 1722 if (nerr != 0) { 1723 disp = gcpu_mca_process(hdl, rp, nerr, gcpu, gcl, ismc, mcesp); 1724 } else { 1725 disp = 0; 1726 if (mcesp) { 1727 mcesp->mce_nerr = mcesp->mce_disp = 0; 1728 } 1729 } 1730 1731 /* 1732 * Clear MCG_STATUS if MCIP is set (machine check in progress). 1733 * If a second #MC had occured before now the system would have 1734 * reset. We can only do thise once gcpu_mca_process has copied 1735 * the logout structure. 1736 */ 1737 if (ismc && mcg_status & MCG_STATUS_MCIP) 1738 (void) cmi_hdl_wrmsr(hdl, IA32_MSR_MCG_STATUS, 0); 1739 1740 /* 1741 * At this point we have read and logged all telemetry that is visible 1742 * under the MCA. On architectures for which the NorthBridge is 1743 * on-chip this may include NB-observed errors, but where the NB 1744 * is off chip it may have been the source of the #MC request and 1745 * so we must call into the memory-controller driver to give it 1746 * a chance to log errors. 1747 */ 1748 if (ismc) { 1749 int willpanic = (cmi_mce_response(rp, disp) == 0); 1750 cmi_mc_logout(hdl, 1, willpanic); 1751 } 1752 } 1753 1754 int gcpu_mca_trap_vomit_summary = 0; 1755 1756 /* 1757 * On a native machine check exception we come here from mcetrap via 1758 * cmi_mca_trap. A machine check on one cpu of a chip does not trap others 1759 * cpus of the chip, so it is possible that another cpu on this chip could 1760 * initiate a poll while we're in the #mc handler; it is also possible that 1761 * this trap has occured during a poll on this cpu. So we must acquire 1762 * the chip-wide poll lock, but be careful to avoid deadlock. 1763 * 1764 * The 'data' pointer cannot be NULL due to init order. 1765 */ 1766 uint64_t 1767 gcpu_mca_trap(cmi_hdl_t hdl, struct regs *rp) 1768 { 1769 gcpu_data_t *gcpu = cmi_hdl_getcmidata(hdl); 1770 kmutex_t *poll_lock = NULL; 1771 gcpu_mce_status_t mce; 1772 uint64_t mcg_status; 1773 int tooklock = 0; 1774 1775 if (cmi_hdl_rdmsr(hdl, IA32_MSR_MCG_STATUS, &mcg_status) != 1776 CMI_SUCCESS || !(mcg_status & MCG_STATUS_MCIP)) 1777 return (0); 1778 1779 /* 1780 * Synchronize with any poller from another core that may happen 1781 * to share access to one or more of the MCA banks. 1782 */ 1783 if (gcpu->gcpu_shared != NULL) 1784 poll_lock = &gcpu->gcpu_shared->gcpus_poll_lock; 1785 1786 if (poll_lock != NULL && !mutex_owned(poll_lock)) { 1787 /* 1788 * The lock is not owned by the thread we have 1789 * interrupted. Spin for this adaptive lock. 1790 */ 1791 while (!mutex_tryenter(poll_lock)) { 1792 while (mutex_owner(poll_lock) != NULL) 1793 ; 1794 } 1795 tooklock = 1; 1796 } 1797 1798 gcpu_mca_logout(hdl, rp, 0, &mce, B_TRUE, GCPU_MPT_WHAT_MC_ERR); 1799 1800 if (tooklock) 1801 mutex_exit(poll_lock); 1802 1803 /* 1804 * gcpu_mca_trap_vomit_summary may be set for debug assistance. 1805 */ 1806 if (mce.mce_nerr != 0 && gcpu_mca_trap_vomit_summary) { 1807 cmn_err(CE_WARN, "MCE: %u errors, disp=0x%llx, " 1808 "%u PCC (%u ok), " 1809 "%u UC (%d ok, %u poisoned), " 1810 "%u forcefatal, %u ignored", 1811 mce.mce_nerr, (u_longlong_t)mce.mce_disp, 1812 mce.mce_npcc, mce.mce_npcc_ok, 1813 mce.mce_nuc, mce.mce_nuc_ok, mce.mce_nuc_poisoned, 1814 mce.mce_forcefatal, mce.mce_ignored); 1815 } 1816 1817 return (mce.mce_disp); 1818 } 1819 1820 /*ARGSUSED*/ 1821 void 1822 gcpu_faulted_enter(cmi_hdl_t hdl) 1823 { 1824 /* Nothing to do here */ 1825 } 1826 1827 /*ARGSUSED*/ 1828 void 1829 gcpu_faulted_exit(cmi_hdl_t hdl) 1830 { 1831 gcpu_data_t *gcpu = cmi_hdl_getcmidata(hdl); 1832 1833 gcpu->gcpu_mca.gcpu_mca_flags |= GCPU_MCA_F_UNFAULTING; 1834 } 1835 1836 /* 1837 * Write the requested values to the indicated MSRs. Having no knowledge 1838 * of the model-specific requirements for writing to these model-specific 1839 * registers, we will only blindly write to those MSRs if the 'force' 1840 * argument is nonzero. That option should only be used in prototyping 1841 * and debugging. 1842 */ 1843 /*ARGSUSED*/ 1844 cmi_errno_t 1845 gcpu_msrinject(cmi_hdl_t hdl, cmi_mca_regs_t *regs, uint_t nregs, 1846 int force) 1847 { 1848 int i, errs = 0; 1849 1850 for (i = 0; i < nregs; i++) { 1851 uint_t msr = regs[i].cmr_msrnum; 1852 uint64_t val = regs[i].cmr_msrval; 1853 1854 if (cms_present(hdl)) { 1855 if (cms_msrinject(hdl, msr, val) != CMS_SUCCESS) 1856 errs++; 1857 } else if (force) { 1858 errs += (cmi_hdl_wrmsr(hdl, msr, val) != CMI_SUCCESS); 1859 } else { 1860 errs++; 1861 } 1862 } 1863 1864 return (errs == 0 ? CMI_SUCCESS : CMIERR_UNKNOWN); 1865 } 1866