1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/regset.h> 31 #include <sys/privregs.h> 32 #include <sys/pci_impl.h> 33 #include <sys/cpuvar.h> 34 #include <sys/x86_archext.h> 35 #include <sys/cmn_err.h> 36 #include <sys/systm.h> 37 #include <sys/sysmacros.h> 38 #include <sys/chip.h> 39 #include <sys/cyclic.h> 40 #include <sys/cpu_module_impl.h> 41 #include <sys/pci_cfgspace_impl.h> 42 #include <sys/sysevent.h> 43 #include <sys/smbios.h> 44 #include <sys/mca_x86.h> 45 #include <sys/mca_amd.h> 46 #include <sys/mc.h> 47 #include <sys/mc_amd.h> 48 #include <sys/psw.h> 49 #include <sys/ddi.h> 50 #include <sys/sunddi.h> 51 #include <sys/sdt.h> 52 #include <sys/fm/util.h> 53 #include <sys/fm/protocol.h> 54 #include <sys/fm/cpu/AMD.h> 55 #include <sys/acpi/acpi.h> 56 #include <sys/acpi/acpi_pci.h> 57 #include <sys/acpica.h> 58 59 #include "ao.h" 60 #include "ao_mca_disp.h" 61 62 #define AO_REVS_FG (X86_CHIPREV_AMD_F_REV_F | X86_CHIPREV_AMD_F_REV_G) 63 64 errorq_t *ao_mca_queue; /* machine-check ereport queue */ 65 int ao_mca_stack_flag = 0; /* record stack trace in ereports */ 66 int ao_mca_smi_disable = 1; /* attempt to disable SMI polling */ 67 68 ao_bank_regs_t ao_bank_regs[AMD_MCA_BANK_COUNT] = { 69 { AMD_MSR_DC_STATUS, AMD_MSR_DC_ADDR, AMD_MSR_DC_MISC }, 70 { AMD_MSR_IC_STATUS, AMD_MSR_IC_ADDR, AMD_MSR_IC_MISC }, 71 { AMD_MSR_BU_STATUS, AMD_MSR_BU_ADDR, AMD_MSR_BU_MISC }, 72 { AMD_MSR_LS_STATUS, AMD_MSR_LS_ADDR, AMD_MSR_LS_MISC }, 73 { AMD_MSR_NB_STATUS, AMD_MSR_NB_ADDR, AMD_MSR_NB_MISC } 74 }; 75 76 struct ao_ctl_init { 77 uint32_t ctl_revmask; /* rev(s) to which this applies */ 78 uint64_t ctl_bits; /* mca ctl reg bitmask to set */ 79 }; 80 81 /* 82 * Additional NB MCA ctl initialization for revs F and G 83 */ 84 static const struct ao_ctl_init ao_nb_ctl_init[] = { 85 { AO_REVS_FG, AMD_NB_CTL_INIT_REV_FG }, 86 { X86_CHIPREV_UNKNOWN, 0 } 87 }; 88 89 typedef struct ao_bank_cfg { 90 uint_t bank_ctl; 91 uint_t bank_ctl_mask; 92 uint64_t bank_ctl_init_cmn; /* Common init value */ 93 const struct ao_ctl_init *bank_ctl_init_extra; /* Extra for each rev */ 94 void (*bank_misc_initfunc)(ao_data_t *, uint32_t); 95 uint_t bank_status; 96 uint_t bank_addr; 97 } ao_bank_cfg_t; 98 99 static void nb_mcamisc_init(ao_data_t *, uint32_t); 100 101 static const ao_bank_cfg_t ao_bank_cfgs[] = { 102 { AMD_MSR_DC_CTL, AMD_MSR_DC_MASK, AMD_DC_CTL_INIT_CMN, 103 NULL, NULL, AMD_MSR_DC_STATUS, AMD_MSR_DC_ADDR }, 104 { AMD_MSR_IC_CTL, AMD_MSR_IC_MASK, AMD_IC_CTL_INIT_CMN, 105 NULL, NULL, AMD_MSR_IC_STATUS, AMD_MSR_IC_ADDR }, 106 { AMD_MSR_BU_CTL, AMD_MSR_BU_MASK, AMD_BU_CTL_INIT_CMN, 107 NULL, NULL, AMD_MSR_BU_STATUS, AMD_MSR_BU_ADDR }, 108 { AMD_MSR_LS_CTL, AMD_MSR_LS_MASK, AMD_LS_CTL_INIT_CMN, 109 NULL, NULL, AMD_MSR_LS_STATUS, AMD_MSR_LS_ADDR }, 110 { AMD_MSR_NB_CTL, AMD_MSR_NB_MASK, AMD_NB_CTL_INIT_CMN, 111 &ao_nb_ctl_init[0], nb_mcamisc_init, 112 AMD_MSR_NB_STATUS, AMD_MSR_NB_ADDR } 113 }; 114 115 static const ao_error_disp_t ao_disp_unknown = { 116 FM_EREPORT_CPU_AMD_UNKNOWN, 117 FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_UNKNOWN 118 }; 119 120 /* 121 * This is quite awful but necessary to work around x86 system vendor's view of 122 * the world. Other operating systems (you know who you are) don't understand 123 * Opteron-specific error handling, so BIOS and system vendors often hide these 124 * conditions from them by using SMI polling to copy out any errors from the 125 * machine-check registers. When Solaris runs on a system with this feature, 126 * we want to disable the SMI polling so we can use FMA instead. Sadly, there 127 * isn't even a standard self-describing way to express the whole situation, 128 * so we have to resort to hard-coded values. This should all be changed to 129 * be a self-describing vendor-specific SMBIOS structure in the future. 130 */ 131 static const struct ao_smi_disable { 132 const char *asd_sys_vendor; /* SMB_TYPE_SYSTEM vendor prefix */ 133 const char *asd_bios_vendor; /* SMB_TYPE_BIOS vendor prefix */ 134 uint8_t asd_code; /* output code for SMI disable */ 135 } ao_smi_disable[] = { 136 { "Sun Microsystems", "American Megatrends", 0x59 }, 137 { NULL, NULL, 0 } 138 }; 139 140 static int 141 ao_disp_match_r4(uint16_t ref, uint8_t r4) 142 { 143 static const uint16_t ao_r4_map[] = { 144 AO_MCA_R4_BIT_GEN, /* AMD_ERRCODE_R4_GEN */ 145 AO_MCA_R4_BIT_RD, /* AMD_ERRCODE_R4_RD */ 146 AO_MCA_R4_BIT_WR, /* AMD_ERRCODE_R4_WR */ 147 AO_MCA_R4_BIT_DRD, /* AMD_ERRCODE_R4_DRD */ 148 AO_MCA_R4_BIT_DWR, /* AMD_ERRCODE_R4_DWR */ 149 AO_MCA_R4_BIT_IRD, /* AMD_ERRCODE_R4_IRD */ 150 AO_MCA_R4_BIT_PREFETCH, /* AMD_ERRCODE_R4_PREFETCH */ 151 AO_MCA_R4_BIT_EVICT, /* AMD_ERRCODE_R4_EVICT */ 152 AO_MCA_R4_BIT_SNOOP /* AMD_ERRCODE_R4_SNOOP */ 153 }; 154 155 ASSERT(r4 < sizeof (ao_r4_map) / sizeof (uint16_t)); 156 157 return ((ref & ao_r4_map[r4]) != 0); 158 } 159 160 static int 161 ao_disp_match_pp(uint8_t ref, uint8_t pp) 162 { 163 static const uint8_t ao_pp_map[] = { 164 AO_MCA_PP_BIT_SRC, /* AMD_ERRCODE_PP_SRC */ 165 AO_MCA_PP_BIT_RSP, /* AMD_ERRCODE_PP_RSP */ 166 AO_MCA_PP_BIT_OBS, /* AMD_ERRCODE_PP_OBS */ 167 AO_MCA_PP_BIT_GEN /* AMD_ERRCODE_PP_GEN */ 168 }; 169 170 ASSERT(pp < sizeof (ao_pp_map) / sizeof (uint8_t)); 171 172 return ((ref & ao_pp_map[pp]) != 0); 173 } 174 175 static int 176 ao_disp_match_ii(uint8_t ref, uint8_t ii) 177 { 178 static const uint8_t ao_ii_map[] = { 179 AO_MCA_II_BIT_MEM, /* AMD_ERRCODE_II_MEM */ 180 0, 181 AO_MCA_II_BIT_IO, /* AMD_ERRCODE_II_IO */ 182 AO_MCA_II_BIT_GEN /* AMD_ERRCODE_II_GEN */ 183 }; 184 185 ASSERT(ii < sizeof (ao_ii_map) / sizeof (uint8_t)); 186 187 return ((ref & ao_ii_map[ii]) != 0); 188 } 189 190 static uint8_t 191 bit_strip(uint16_t *codep, uint16_t mask, uint16_t shift) 192 { 193 uint8_t val = (*codep & mask) >> shift; 194 *codep &= ~mask; 195 return (val); 196 } 197 198 #define BIT_STRIP(codep, name) \ 199 bit_strip(codep, AMD_ERRCODE_##name##_MASK, AMD_ERRCODE_##name##_SHIFT) 200 201 static int 202 ao_disp_match_one(const ao_error_disp_t *aed, uint64_t status, uint32_t rev, 203 int bankno) 204 { 205 uint16_t code = status & AMD_ERRCODE_MASK; 206 uint8_t extcode = (status & AMD_ERREXT_MASK) >> AMD_ERREXT_SHIFT; 207 uint64_t stat_mask = aed->aed_stat_mask; 208 uint64_t stat_mask_res = aed->aed_stat_mask_res; 209 210 /* 211 * If the bank's status register indicates overflow, then we can no 212 * longer rely on the value of CECC: our experience with actual fault 213 * injection has shown that multiple CE's overwriting each other shows 214 * AMD_BANK_STAT_CECC and AMD_BANK_STAT_UECC both set to zero. This 215 * should be clarified in a future BKDG or by the Revision Guide. 216 * This behaviour is fixed in revision F. 217 */ 218 if (bankno == AMD_MCA_BANK_NB && 219 !X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_F_REV_F) && 220 status & AMD_BANK_STAT_OVER) { 221 stat_mask &= ~AMD_BANK_STAT_CECC; 222 stat_mask_res &= ~AMD_BANK_STAT_CECC; 223 } 224 225 if ((status & stat_mask) != stat_mask_res) 226 return (0); 227 228 /* 229 * r4 and pp bits are stored separately, so we mask off and compare them 230 * for the code types that use them. Once we've taken the r4 and pp 231 * bits out of the equation, we can directly compare the resulting code 232 * with the one stored in the ao_error_disp_t. 233 */ 234 if (AMD_ERRCODE_ISMEM(code)) { 235 uint8_t r4 = BIT_STRIP(&code, R4); 236 237 if (!ao_disp_match_r4(aed->aed_stat_r4_bits, r4)) 238 return (0); 239 240 } else if (AMD_ERRCODE_ISBUS(code)) { 241 uint8_t r4 = BIT_STRIP(&code, R4); 242 uint8_t pp = BIT_STRIP(&code, PP); 243 uint8_t ii = BIT_STRIP(&code, II); 244 245 if (!ao_disp_match_r4(aed->aed_stat_r4_bits, r4) || 246 !ao_disp_match_pp(aed->aed_stat_pp_bits, pp) || 247 !ao_disp_match_ii(aed->aed_stat_ii_bits, ii)) 248 return (0); 249 } 250 251 return (code == aed->aed_stat_code && extcode == aed->aed_stat_extcode); 252 } 253 254 static const ao_error_disp_t * 255 ao_disp_match(uint_t bankno, uint64_t status, uint32_t rev) 256 { 257 const ao_error_disp_t *aed; 258 259 for (aed = ao_error_disp[bankno]; aed->aed_stat_mask != 0; aed++) { 260 if (ao_disp_match_one(aed, status, rev, bankno)) 261 return (aed); 262 } 263 264 return (&ao_disp_unknown); 265 } 266 267 void 268 ao_pcicfg_write(uint_t chipid, uint_t func, uint_t reg, uint32_t val) 269 { 270 ASSERT(chipid + 24 <= 31); 271 ASSERT((func & 7) == func); 272 ASSERT((reg & 3) == 0 && reg < 256); 273 274 pci_mech1_putl(0, chipid + 24, func, reg, val); 275 } 276 277 uint32_t 278 ao_pcicfg_read(uint_t chipid, uint_t func, uint_t reg) 279 { 280 ASSERT(chipid + 24 <= 31); 281 ASSERT((func & 7) == func); 282 ASSERT((reg & 3) == 0 && reg < 256); 283 284 return (pci_mech1_getl(0, chipid + 24, func, reg)); 285 } 286 287 /* 288 * ao_chip_once returns 1 if the caller should perform the operation for 289 * this chip, or 0 if some other core has already performed the operation. 290 */ 291 292 int 293 ao_chip_once(ao_data_t *ao, enum ao_cfgonce_bitnum what) 294 { 295 return (atomic_set_long_excl(&ao->ao_shared->aos_cfgonce, what) == 0 ? 296 1 : 0); 297 } 298 299 /* 300 * Setup individual bank detectors after stashing their bios settings. 301 * The 'donb' argument indicates whether this core should configured 302 * the shared NorthBridhe MSRs. 303 */ 304 static void 305 ao_bank_cfg(ao_data_t *ao, uint32_t rev, int donb) 306 { 307 ao_mca_t *mca = &ao->ao_mca; 308 struct ao_chipshared *aos = ao->ao_shared; 309 ao_bios_cfg_t *bcfg = &mca->ao_mca_bios_cfg; 310 const ao_bank_cfg_t *bankcfg = ao_bank_cfgs; 311 const struct ao_ctl_init *extrap; 312 uint64_t mcictl; 313 int i; 314 315 for (i = 0; i < AMD_MCA_BANK_COUNT; i++, bankcfg++) { 316 if (i == AMD_MCA_BANK_NB && donb == 0) { 317 bcfg->bcfg_bank_ctl[i] = 0xbaddcafe; 318 bcfg->bcfg_bank_mask[i] = 0xbaddcafe; 319 continue; 320 } else if (i == AMD_MCA_BANK_NB) { 321 aos->aos_bcfg_nb_ctl = rdmsr(bankcfg->bank_ctl); 322 aos->aos_bcfg_nb_mask = rdmsr(bankcfg->bank_ctl_mask); 323 } else { 324 bcfg->bcfg_bank_ctl[i] = rdmsr(bankcfg->bank_ctl); 325 bcfg->bcfg_bank_mask[i] = rdmsr(bankcfg->bank_ctl_mask); 326 } 327 328 /* Initialize MCi_CTL register for this bank */ 329 mcictl = bankcfg->bank_ctl_init_cmn; 330 if ((extrap = bankcfg->bank_ctl_init_extra) != NULL) { 331 while (extrap->ctl_revmask != X86_CHIPREV_UNKNOWN) { 332 if (X86_CHIPREV_MATCH(rev, extrap->ctl_revmask)) 333 mcictl |= extrap->ctl_bits; 334 extrap++; 335 } 336 } 337 wrmsr(bankcfg->bank_ctl, mcictl); 338 339 /* Initialize the MCi_MISC register for this bank */ 340 if (bankcfg->bank_misc_initfunc != NULL) 341 (bankcfg->bank_misc_initfunc)(ao, rev); 342 } 343 } 344 345 /* 346 * This knob exists in case any platform has a problem with our default 347 * policy of disabling any interrupt registered in the NB MC4_MISC 348 * register. Setting this may cause Solaris and external entities 349 * who also have an interest in this register to argue over available 350 * telemetry (so setting it is generally not recommended). 351 */ 352 int ao_nb_cfg_mc4misc_noseize = 0; 353 354 /* 355 * The BIOS may have setup to receive SMI on counter overflow. It may also 356 * have locked various fields or made them read-only. We will clear any 357 * SMI request and leave the register locked. We will also clear the 358 * counter and enable counting - while we don't use the counter it is nice 359 * to have it enabled for verification and debug work. 360 */ 361 static void 362 nb_mcamisc_init(ao_data_t *ao, uint32_t rev) 363 { 364 uint64_t hwcr, oldhwcr; 365 uint64_t val; 366 int locked; 367 368 if (!X86_CHIPREV_MATCH(rev, AO_REVS_FG)) 369 return; 370 371 ao->ao_shared->aos_bcfg_nb_misc = val = rdmsr(AMD_MSR_NB_MISC); 372 373 if (ao_nb_cfg_mc4misc_noseize) 374 return; /* stash BIOS value, but no changes */ 375 376 locked = val & AMD_NB_MISC_LOCKED; 377 378 /* 379 * The Valid bit tells us whether the CtrP bit is defined; if it 380 * is the CtrP bit tells us whether an ErrCount field is present. 381 * If not then there is nothing for us to do. 382 */ 383 if (!(val & AMD_NB_MISC_VALID) || !(val & AMD_NB_MISC_CTRP)) 384 return; 385 386 if (locked) { 387 oldhwcr = rdmsr(MSR_AMD_HWCR); 388 hwcr = oldhwcr | AMD_HWCR_MCI_STATUS_WREN; 389 wrmsr(MSR_AMD_HWCR, hwcr); 390 } 391 392 val |= AMD_NB_MISC_CNTEN; /* enable ECC error counting */ 393 val &= ~AMD_NB_MISC_ERRCOUNT_MASK; /* clear ErrCount */ 394 val &= ~AMD_NB_MISC_OVRFLW; /* clear Ovrflw */ 395 val &= ~AMD_NB_MISC_INTTYPE_MASK; /* no interrupt on overflow */ 396 val |= AMD_NB_MISC_LOCKED; 397 398 wrmsr(AMD_MSR_NB_MISC, val); 399 400 if (locked) 401 wrmsr(MSR_AMD_HWCR, oldhwcr); 402 } 403 404 /* 405 * NorthBridge (NB) Configuration. 406 * 407 * We add and remove bits from the BIOS-configured value, rather than 408 * writing an absolute value. The variables ao_nb_cfg_{add,remove}_cmn and 409 * ap_nb_cfg_{add,remove}_revFG are available for modification via kmdb 410 * and /etc/system. The revision-specific adds and removes are applied 411 * after the common changes, and one write is made to the config register. 412 * These are not intended for watchdog configuration via these variables - 413 * use the watchdog policy below. 414 */ 415 416 /* 417 * Bits to be added to the NB configuration register - all revs. 418 */ 419 uint32_t ao_nb_cfg_add_cmn = AMD_NB_CFG_ADD_CMN; 420 421 /* 422 * Bits to be cleared from the NB configuration register - all revs. 423 */ 424 uint32_t ao_nb_cfg_remove_cmn = AMD_NB_CFG_REMOVE_CMN; 425 426 /* 427 * Bits to be added to the NB configuration register - revs F and G. 428 */ 429 uint32_t ao_nb_cfg_add_revFG = AMD_NB_CFG_ADD_REV_FG; 430 431 /* 432 * Bits to be cleared from the NB configuration register - revs F and G. 433 */ 434 uint32_t ao_nb_cfg_remove_revFG = AMD_NB_CFG_REMOVE_REV_FG; 435 436 struct ao_nb_cfg { 437 uint32_t cfg_revmask; 438 uint32_t *cfg_add_p; 439 uint32_t *cfg_remove_p; 440 }; 441 442 static const struct ao_nb_cfg ao_cfg_extra[] = { 443 { AO_REVS_FG, &ao_nb_cfg_add_revFG, &ao_nb_cfg_remove_revFG }, 444 { X86_CHIPREV_UNKNOWN, NULL, NULL } 445 }; 446 447 /* 448 * Bits to be used if we configure the NorthBridge (NB) Watchdog. The watchdog 449 * triggers a machine check exception when no response to an NB system access 450 * occurs within a specified time interval. 451 */ 452 uint32_t ao_nb_cfg_wdog = 453 AMD_NB_CFG_WDOGTMRCNTSEL_4095 | 454 AMD_NB_CFG_WDOGTMRBASESEL_1MS; 455 456 /* 457 * The default watchdog policy is to enable it (at the above rate) if it 458 * is disabled; if it is enabled then we leave it enabled at the rate 459 * chosen by the BIOS. 460 */ 461 enum { 462 AO_NB_WDOG_LEAVEALONE, /* Don't touch watchdog config */ 463 AO_NB_WDOG_DISABLE, /* Always disable watchdog */ 464 AO_NB_WDOG_ENABLE_IF_DISABLED, /* If disabled, enable at our rate */ 465 AO_NB_WDOG_ENABLE_FORCE_RATE /* Enable and set our rate */ 466 } ao_nb_watchdog_policy = AO_NB_WDOG_ENABLE_IF_DISABLED; 467 468 static void 469 ao_nb_cfg(ao_data_t *ao, uint32_t rev) 470 { 471 const struct ao_nb_cfg *nbcp = &ao_cfg_extra[0]; 472 uint_t chipid = chip_plat_get_chipid(CPU); 473 uint32_t val; 474 475 /* 476 * Read the NorthBridge (NB) configuration register in PCI space, 477 * modify the settings accordingly, and store the new value back. 478 */ 479 ao->ao_shared->aos_bcfg_nb_cfg = val = 480 ao_pcicfg_read(chipid, AMD_NB_FUNC, AMD_NB_REG_CFG); 481 482 switch (ao_nb_watchdog_policy) { 483 case AO_NB_WDOG_LEAVEALONE: 484 break; 485 486 case AO_NB_WDOG_DISABLE: 487 val &= ~AMD_NB_CFG_WDOGTMRBASESEL_MASK; 488 val &= ~AMD_NB_CFG_WDOGTMRCNTSEL_MASK; 489 val |= AMD_NB_CFG_WDOGTMRDIS; 490 break; 491 492 default: 493 cmn_err(CE_NOTE, "ao_nb_watchdog_policy=%d unrecognised, " 494 "using default policy", ao_nb_watchdog_policy); 495 /*FALLTHRU*/ 496 497 case AO_NB_WDOG_ENABLE_IF_DISABLED: 498 if (val & AMD_NB_CFG_WDOGTMRDIS) 499 break; /* if enabled leave rate intact */ 500 /*FALLTHRU*/ 501 502 case AO_NB_WDOG_ENABLE_FORCE_RATE: 503 val &= ~AMD_NB_CFG_WDOGTMRBASESEL_MASK; 504 val &= ~AMD_NB_CFG_WDOGTMRCNTSEL_MASK; 505 val &= ~AMD_NB_CFG_WDOGTMRDIS; 506 val |= ao_nb_cfg_wdog; 507 break; 508 } 509 510 /* 511 * Now apply bit adds and removes, first those common to all revs 512 * and then the revision-specific ones. 513 */ 514 val &= ~ao_nb_cfg_remove_cmn; 515 val |= ao_nb_cfg_add_cmn; 516 517 while (nbcp->cfg_revmask != X86_CHIPREV_UNKNOWN) { 518 if (X86_CHIPREV_MATCH(rev, nbcp->cfg_revmask)) { 519 val &= ~(*nbcp->cfg_remove_p); 520 val |= *nbcp->cfg_add_p; 521 } 522 nbcp++; 523 } 524 525 ao_pcicfg_write(chipid, AMD_NB_FUNC, AMD_NB_REG_CFG, val); 526 } 527 528 /* 529 * This knob exists in case any platform has a problem with our default 530 * policy of disabling any interrupt registered in the online spare 531 * control register. Setting this may cause Solaris and external entities 532 * who also have an interest in this register to argue over available 533 * telemetry (so setting it is generally not recommended). 534 */ 535 int ao_nb_cfg_sparectl_noseize = 0; 536 537 /* 538 * Setup the online spare control register (revs F and G). We disable 539 * any interrupt registered by the BIOS and zero all error counts. 540 */ 541 static void 542 ao_sparectl_cfg(ao_data_t *ao) 543 { 544 uint_t chipid = chip_plat_get_chipid(CPU); 545 union mcreg_sparectl sparectl; 546 int chan, cs; 547 548 ao->ao_shared->aos_bcfg_nb_sparectl = MCREG_VAL32(&sparectl) = 549 ao_pcicfg_read(chipid, AMD_NB_FUNC, AMD_NB_REG_SPARECTL); 550 551 if (ao_nb_cfg_sparectl_noseize) 552 return; /* stash BIOS value, but no changes */ 553 554 /* 555 * If the BIOS has requested SMI interrupt type for ECC count 556 * overflow for a chip-select or channel force those off. 557 */ 558 MCREG_FIELD_revFG(&sparectl, EccErrInt) = 0; 559 MCREG_FIELD_revFG(&sparectl, SwapDoneInt) = 0; 560 561 /* Enable writing to the EccErrCnt field */ 562 MCREG_FIELD_revFG(&sparectl, EccErrCntWrEn) = 1; 563 564 /* First write, preparing for writes to EccErrCnt */ 565 ao_pcicfg_write(chipid, AMD_NB_FUNC, AMD_NB_REG_SPARECTL, 566 MCREG_VAL32(&sparectl)); 567 568 /* 569 * Zero EccErrCnt and write this back to all chan/cs combinations. 570 */ 571 MCREG_FIELD_revFG(&sparectl, EccErrCnt) = 0; 572 for (chan = 0; chan < MC_CHIP_NDRAMCHAN; chan++) { 573 MCREG_FIELD_revFG(&sparectl, EccErrCntDramChan) = chan; 574 575 for (cs = 0; cs < MC_CHIP_NCS; cs++) { 576 MCREG_FIELD_revFG(&sparectl, EccErrCntDramCs) = cs; 577 ao_pcicfg_write(chipid, AMD_NB_FUNC, 578 AMD_NB_REG_SPARECTL, MCREG_VAL32(&sparectl)); 579 } 580 } 581 } 582 583 /* 584 * Capture the machine-check exception state into our per-CPU logout area, and 585 * dispatch a copy of the logout area to our error queue for ereport creation. 586 * If 'rp' is non-NULL, we're being called from trap context; otherwise we're 587 * being polled or poked by the injector. We return the number of errors 588 * found through 'np', and a boolean indicating whether the error is fatal. 589 * The caller is expected to call fm_panic() if we return fatal (non-zero). 590 */ 591 int 592 ao_mca_logout(ao_cpu_logout_t *acl, struct regs *rp, int *np, int skipnb, 593 uint32_t rev) 594 { 595 uint64_t mcg_status = rdmsr(IA32_MSR_MCG_STATUS); 596 int i, fatal = 0, n = 0; 597 598 acl->acl_timestamp = gethrtime_waitfree(); 599 acl->acl_mcg_status = mcg_status; 600 acl->acl_ip = rp ? rp->r_pc : 0; 601 acl->acl_flags = 0; 602 603 /* 604 * Iterate over the banks of machine-check registers, read the address 605 * and status registers into the logout area, and clear status as we go. 606 * Also read the MCi_MISC register is MCi_STATUS.MISCV indicates that 607 * there is valid info there (as it will in revisions F and G for 608 * NorthBridge ECC errors). 609 */ 610 for (i = 0; i < AMD_MCA_BANK_COUNT; i++) { 611 ao_bank_logout_t *abl = &acl->acl_banks[i]; 612 613 if (i == AMD_MCA_BANK_NB && skipnb) { 614 abl->abl_status = 0; 615 continue; 616 } 617 618 abl->abl_addr = rdmsr(ao_bank_regs[i].abr_addr); 619 abl->abl_status = rdmsr(ao_bank_regs[i].abr_status); 620 621 if (abl->abl_status & AMD_BANK_STAT_MISCV) 622 abl->abl_misc = rdmsr(ao_bank_regs[i].abr_misc); 623 else 624 abl->abl_misc = 0; 625 626 if (abl->abl_status & AMD_BANK_STAT_VALID) 627 wrmsr(ao_bank_regs[i].abr_status, 0); 628 } 629 630 if (rp == NULL || !USERMODE(rp->r_cs)) 631 acl->acl_flags |= AO_ACL_F_PRIV; 632 633 if (ao_mca_stack_flag) 634 acl->acl_stackdepth = getpcstack(acl->acl_stack, FM_STK_DEPTH); 635 else 636 acl->acl_stackdepth = 0; 637 638 /* 639 * Clear MCG_STATUS, indicating that machine-check trap processing is 640 * complete. Once we do this, another machine-check trap can occur 641 * (if another occurs up to this point then the system will reset). 642 */ 643 if (mcg_status & MCG_STATUS_MCIP) 644 wrmsr(IA32_MSR_MCG_STATUS, 0); 645 646 /* 647 * If we took a machine-check trap, then the error is fatal if the 648 * return instruction pointer is not valid in the global register. 649 */ 650 if (rp != NULL && !(acl->acl_mcg_status & MCG_STATUS_RIPV)) 651 fatal++; 652 653 /* 654 * Now iterate over the saved logout area, determining whether the 655 * error that we saw is fatal or not based upon our dispositions 656 * and the hardware's indicators of whether or not we can resume. 657 */ 658 for (i = 0; i < AMD_MCA_BANK_COUNT; i++) { 659 ao_bank_logout_t *abl = &acl->acl_banks[i]; 660 const ao_error_disp_t *aed; 661 uint8_t when; 662 663 if (!(abl->abl_status & AMD_BANK_STAT_VALID)) 664 continue; 665 666 aed = ao_disp_match(i, abl->abl_status, rev); 667 if ((when = aed->aed_panic_when) != AO_AED_PANIC_NEVER) { 668 if ((when & AO_AED_PANIC_ALWAYS) || 669 ((when & AO_AED_PANIC_IFMCE) && rp != NULL)) { 670 fatal++; 671 } 672 } 673 674 /* 675 * If we are taking a machine-check exception and our context 676 * is corrupt, then we must die. 677 */ 678 if (rp != NULL && abl->abl_status & AMD_BANK_STAT_PCC) 679 fatal++; 680 681 /* 682 * The overflow bit is set if the bank detects an error but 683 * the valid bit of its status register is already set 684 * (software has not yet read and cleared it). Enabled 685 * (for mc# reporting) errors overwrite disabled errors, 686 * uncorrectable errors overwrite correctable errors, 687 * uncorrectable errors are not overwritten. 688 * 689 * For the NB detector bank the overflow bit will not be 690 * set for repeated correctable errors on revisions D and 691 * earlier; it will be set on revisions E and later. 692 * On revision E, however, the CorrECC bit does appear 693 * to clear in these circumstances. Since we can enable 694 * machine-check exception on NB correctables we need to 695 * be careful here; we never enable mc# for correctable from 696 * other banks. 697 * 698 * Our solution will be to declare a machine-check exception 699 * fatal if the overflow bit is set except in the case of 700 * revision F on the NB detector bank for which CorrECC 701 * is indicated. Machine-check exception for NB correctables 702 * on rev E is explicitly not supported. 703 */ 704 if (rp != NULL && abl->abl_status & AMD_BANK_STAT_OVER && 705 !(i == AMD_MCA_BANK_NB && 706 X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_F_REV_F) && 707 abl->abl_status & AMD_BANK_STAT_CECC)) 708 fatal++; 709 710 /* 711 * If we are taking a machine-check exception and we don't 712 * recognize the error case at all, then assume it's fatal. 713 * This will need to change if we eventually use the Opteron 714 * Rev E exception mechanism for detecting correctable errors. 715 */ 716 if (rp != NULL && aed == &ao_disp_unknown) 717 fatal++; 718 719 n++; 720 } 721 722 if (n > 0) { 723 errorq_dispatch(ao_mca_queue, acl, sizeof (ao_cpu_logout_t), 724 fatal && cmi_panic_on_uncorrectable_error ? 725 ERRORQ_SYNC : ERRORQ_ASYNC); 726 } 727 728 if (np != NULL) 729 *np = n; /* return number of errors found to caller */ 730 731 return (fatal != 0); 732 } 733 734 static uint_t 735 ao_ereport_synd(ao_data_t *ao, const ao_bank_logout_t *abl, uint_t *typep, 736 int is_nb) 737 { 738 if (is_nb) { 739 if (ao->ao_shared->aos_bcfg_nb_cfg & AMD_NB_CFG_CHIPKILLECCEN) { 740 *typep = AMD_SYNDTYPE_CHIPKILL; 741 return (AMD_NB_STAT_CKSYND(abl->abl_status)); 742 } else { 743 *typep = AMD_SYNDTYPE_ECC; 744 return (AMD_BANK_SYND(abl->abl_status)); 745 } 746 } else { 747 *typep = AMD_SYNDTYPE_ECC; 748 return (AMD_BANK_SYND(abl->abl_status)); 749 } 750 } 751 752 static void 753 ao_ereport_create_resource_elem(nvlist_t **nvlp, nv_alloc_t *nva, 754 mc_unum_t *unump, int dimmnum) 755 { 756 nvlist_t *snvl; 757 *nvlp = fm_nvlist_create(nva); /* freed by caller */ 758 759 snvl = fm_nvlist_create(nva); 760 761 (void) nvlist_add_uint64(snvl, FM_FMRI_HC_SPECIFIC_OFFSET, 762 unump->unum_offset); 763 764 fm_fmri_hc_set(*nvlp, FM_HC_SCHEME_VERSION, NULL, snvl, 5, 765 "motherboard", unump->unum_board, 766 "chip", unump->unum_chip, 767 "memory-controller", unump->unum_mc, 768 "dimm", unump->unum_dimms[dimmnum], 769 "rank", unump->unum_rank); 770 771 fm_nvlist_destroy(snvl, nva ? FM_NVA_RETAIN : FM_NVA_FREE); 772 } 773 774 static void 775 ao_ereport_add_resource(nvlist_t *payload, nv_alloc_t *nva, mc_unum_t *unump) 776 { 777 778 nvlist_t *elems[MC_UNUM_NDIMM]; 779 int nelems = 0; 780 int i; 781 782 for (i = 0; i < MC_UNUM_NDIMM; i++) { 783 if (unump->unum_dimms[i] == MC_INVALNUM) 784 break; 785 ao_ereport_create_resource_elem(&elems[nelems++], nva, 786 unump, i); 787 } 788 789 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_RESOURCE, 790 DATA_TYPE_NVLIST_ARRAY, nelems, elems, NULL); 791 792 for (i = 0; i < nelems; i++) 793 fm_nvlist_destroy(elems[i], nva ? FM_NVA_RETAIN : FM_NVA_FREE); 794 } 795 796 static void 797 ao_ereport_add_logout(ao_data_t *ao, nvlist_t *payload, nv_alloc_t *nva, 798 const ao_cpu_logout_t *acl, uint_t bankno, const ao_error_disp_t *aed) 799 { 800 uint64_t members = aed->aed_ereport_members; 801 const ao_bank_logout_t *abl = &acl->acl_banks[bankno]; 802 uint_t synd, syndtype; 803 804 synd = ao_ereport_synd(ao, abl, &syndtype, bankno == AMD_MCA_BANK_NB); 805 806 if (members & FM_EREPORT_PAYLOAD_FLAG_BANK_STAT) { 807 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_BANK_STAT, 808 DATA_TYPE_UINT64, abl->abl_status, NULL); 809 } 810 811 if (members & FM_EREPORT_PAYLOAD_FLAG_BANK_NUM) { 812 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_BANK_NUM, 813 DATA_TYPE_UINT8, bankno, NULL); 814 } 815 816 if (members & FM_EREPORT_PAYLOAD_FLAG_ADDR) { 817 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_ADDR, 818 DATA_TYPE_UINT64, abl->abl_addr, NULL); 819 } 820 821 if (members & FM_EREPORT_PAYLOAD_FLAG_ADDR_VALID) { 822 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_ADDR_VALID, 823 DATA_TYPE_BOOLEAN_VALUE, (abl->abl_status & 824 AMD_BANK_STAT_ADDRV) ? B_TRUE : B_FALSE, NULL); 825 } 826 827 if (members & FM_EREPORT_PAYLOAD_FLAG_BANK_MISC) { 828 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_BANK_MISC, 829 DATA_TYPE_UINT64, abl->abl_misc, NULL); 830 } 831 832 if (members & FM_EREPORT_PAYLOAD_FLAG_SYND) { 833 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_SYND, 834 DATA_TYPE_UINT16, synd, NULL); 835 } 836 837 if (members & FM_EREPORT_PAYLOAD_FLAG_SYND_TYPE) { 838 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_SYND_TYPE, 839 DATA_TYPE_STRING, (syndtype == AMD_SYNDTYPE_CHIPKILL ? 840 "C" : "E"), NULL); 841 } 842 843 if (members & FM_EREPORT_PAYLOAD_FLAG_IP) { 844 uint64_t ip = (acl->acl_mcg_status & MCG_STATUS_EIPV) ? 845 acl->acl_ip : 0; 846 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_IP, 847 DATA_TYPE_UINT64, ip, NULL); 848 } 849 850 if (members & FM_EREPORT_PAYLOAD_FLAG_PRIV) { 851 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_PRIV, 852 DATA_TYPE_BOOLEAN_VALUE, (acl->acl_flags & AO_ACL_F_PRIV) ? 853 B_TRUE : B_FALSE, NULL); 854 } 855 856 if (members & FM_EREPORT_PAYLOAD_FLAG_RESOURCE) { 857 mc_unum_t unum; 858 int addrvalid; 859 860 addrvalid = (members & FM_EREPORT_PAYLOAD_FLAG_ADDR) && 861 (members & FM_EREPORT_PAYLOAD_FLAG_ADDR_VALID) && 862 (abl->abl_status & AMD_BANK_STAT_ADDRV); 863 864 if (addrvalid && ao_mc_patounum(ao, abl->abl_addr, synd, 865 syndtype, &unum)) 866 ao_ereport_add_resource(payload, nva, &unum); 867 } 868 869 if (ao_mca_stack_flag && members & FM_EREPORT_PAYLOAD_FLAG_STACK) { 870 fm_payload_stack_add(payload, acl->acl_stack, 871 acl->acl_stackdepth); 872 } 873 } 874 875 static void 876 ao_ereport_post(const ao_cpu_logout_t *acl, 877 int bankno, const ao_error_disp_t *aed) 878 { 879 ao_data_t *ao = acl->acl_ao; 880 errorq_elem_t *eqep, *scr_eqep; 881 nvlist_t *ereport, *detector; 882 nv_alloc_t *nva = NULL; 883 char buf[FM_MAX_CLASS]; 884 885 if (panicstr) { 886 if ((eqep = errorq_reserve(ereport_errorq)) == NULL) 887 return; 888 ereport = errorq_elem_nvl(ereport_errorq, eqep); 889 890 /* 891 * Now try to allocate another element for scratch space and 892 * use that for further scratch space (eg for constructing 893 * nvlists to add the main ereport). If we can't reserve 894 * a scratch element just fallback to working within the 895 * element we already have, and hope for the best. All this 896 * is necessary because the fixed buffer nv allocator does 897 * not reclaim freed space and nvlist construction is 898 * expensive. 899 */ 900 if ((scr_eqep = errorq_reserve(ereport_errorq)) != NULL) 901 nva = errorq_elem_nva(ereport_errorq, scr_eqep); 902 else 903 nva = errorq_elem_nva(ereport_errorq, eqep); 904 } else { 905 ereport = fm_nvlist_create(NULL); 906 } 907 908 /* 909 * Create the "hc" scheme detector FMRI identifying this cpu 910 */ 911 detector = ao_fmri_create(ao, nva); 912 913 /* 914 * Encode all the common data into the ereport. 915 */ 916 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s.%s", 917 FM_ERROR_CPU, "amd", aed->aed_class); 918 919 fm_ereport_set(ereport, FM_EREPORT_VERSION, buf, 920 fm_ena_generate_cpu(acl->acl_timestamp, ao->ao_cpu->cpu_id, 921 FM_ENA_FMT1), detector, NULL); 922 923 /* 924 * We're done with 'detector' so reclaim the scratch space. 925 */ 926 if (panicstr) { 927 fm_nvlist_destroy(detector, FM_NVA_RETAIN); 928 nv_alloc_reset(nva); 929 } else { 930 fm_nvlist_destroy(detector, FM_NVA_FREE); 931 } 932 933 /* 934 * Encode the error-specific data that was saved in the logout area. 935 */ 936 ao_ereport_add_logout(ao, ereport, nva, acl, bankno, aed); 937 938 if (panicstr) { 939 errorq_commit(ereport_errorq, eqep, ERRORQ_SYNC); 940 if (scr_eqep) 941 errorq_cancel(ereport_errorq, scr_eqep); 942 } else { 943 (void) fm_ereport_post(ereport, EVCH_TRYHARD); 944 fm_nvlist_destroy(ereport, FM_NVA_FREE); 945 } 946 } 947 948 /*ARGSUSED*/ 949 void 950 ao_mca_drain(void *ignored, const void *data, const errorq_elem_t *eqe) 951 { 952 const ao_cpu_logout_t *acl = data; 953 uint32_t rev = acl->acl_ao->ao_shared->aos_chiprev; 954 int i; 955 956 for (i = 0; i < AMD_MCA_BANK_COUNT; i++) { 957 const ao_bank_logout_t *abl = &acl->acl_banks[i]; 958 const ao_error_disp_t *aed; 959 960 if (abl->abl_status & AMD_BANK_STAT_VALID) { 961 aed = ao_disp_match(i, abl->abl_status, rev); 962 ao_ereport_post(acl, i, aed); 963 } 964 } 965 } 966 967 /* 968 * Machine check interrupt handler - we jump here from mcetrap. 969 * 970 * A sibling core may attempt to poll the NorthBridge during the 971 * time we are performing the logout. So we coordinate NB access 972 * of all cores of the same chip via a per-chip lock. If the lock 973 * is held on a sibling core then we spin for it here; if the 974 * lock is held by the thread we have interrupted then we do 975 * not acquire the lock but can proceed safe in the knowledge that 976 * the lock owner can't actually perform any NB accesses. This 977 * requires that threads that take the aos_nb_poll_lock do not 978 * block and that they disable preemption while they hold the lock. 979 * It also requires that the lock be adaptive since mutex_owner does 980 * not work for spin locks. 981 */ 982 static int ao_mca_path1, ao_mca_path2; 983 int 984 ao_mca_trap(void *data, struct regs *rp) 985 { 986 ao_data_t *ao = data; 987 ao_mca_t *mca = &ao->ao_mca; 988 ao_cpu_logout_t *acl = &mca->ao_mca_logout[AO_MCA_LOGOUT_EXCEPTION]; 989 kmutex_t *nblock = NULL; 990 int tooklock = 0; 991 int rv; 992 993 if (ao->ao_shared != NULL) 994 nblock = &ao->ao_shared->aos_nb_poll_lock; 995 996 if (nblock && !mutex_owned(nblock)) { 997 /* 998 * The mutex is not owned by the thread we have interrupted 999 * (since the holder may not block or be preempted once the 1000 * lock is acquired). We will spin for this adaptive lock. 1001 */ 1002 ++ao_mca_path1; 1003 while (!mutex_tryenter(nblock)) { 1004 while (mutex_owner(nblock) != NULL) 1005 ; 1006 } 1007 tooklock = 1; 1008 } else { 1009 ++ao_mca_path2; 1010 } 1011 1012 rv = ao_mca_logout(acl, rp, NULL, 0, ao->ao_shared->aos_chiprev); 1013 1014 if (tooklock) 1015 mutex_exit(&ao->ao_shared->aos_nb_poll_lock); 1016 1017 return (rv); 1018 } 1019 1020 /*ARGSUSED*/ 1021 int 1022 ao_mca_inject(void *data, cmi_mca_regs_t *regs, uint_t nregs) 1023 { 1024 uint64_t hwcr, oldhwcr; 1025 int i; 1026 1027 oldhwcr = rdmsr(MSR_AMD_HWCR); 1028 hwcr = oldhwcr | AMD_HWCR_MCI_STATUS_WREN; 1029 wrmsr(MSR_AMD_HWCR, hwcr); 1030 1031 for (i = 0; i < nregs; i++) 1032 wrmsr(regs[i].cmr_msrnum, regs[i].cmr_msrval); 1033 1034 wrmsr(MSR_AMD_HWCR, oldhwcr); 1035 return (0); 1036 } 1037 1038 void 1039 ao_mca_init(void *data) 1040 { 1041 ao_data_t *ao = data; 1042 ao_mca_t *mca = &ao->ao_mca; 1043 uint64_t cap; 1044 uint32_t rev; 1045 int donb; 1046 int i; 1047 1048 ASSERT(x86_feature & X86_MCA); 1049 cap = rdmsr(IA32_MSR_MCG_CAP); 1050 ASSERT(cap & MCG_CAP_CTL_P); 1051 1052 /* 1053 * If the hardware's bank count is different than what we expect, then 1054 * we're running on some Opteron variant that we don't understand yet. 1055 */ 1056 if ((cap & MCG_CAP_COUNT_MASK) != AMD_MCA_BANK_COUNT) { 1057 cmn_err(CE_WARN, "CPU %d has %llu MCA banks; expected %u: " 1058 "disabling MCA on this CPU", ao->ao_cpu->cpu_id, 1059 (u_longlong_t)cap & MCG_CAP_COUNT_MASK, AMD_MCA_BANK_COUNT); 1060 return; 1061 } 1062 1063 /* 1064 * Configure the logout areas. We preset every logout area's acl_ao 1065 * pointer to refer back to our per-CPU state for errorq drain usage. 1066 */ 1067 for (i = 0; i < AO_MCA_LOGOUT_NUM; i++) 1068 mca->ao_mca_logout[i].acl_ao = ao; 1069 1070 /* LINTED: logical expression always true */ 1071 ASSERT(sizeof (ao_bank_cfgs) / sizeof (ao_bank_cfg_t) == 1072 AMD_MCA_BANK_COUNT); 1073 1074 rev = ao->ao_shared->aos_chiprev = cpuid_getchiprev(ao->ao_cpu); 1075 1076 /* 1077 * Must this core perform NB MCA configuration? This must be done 1078 * by just one core. 1079 */ 1080 donb = ao_chip_once(ao, AO_CFGONCE_NBMCA); 1081 1082 /* 1083 * Initialize poller data, but don't start polling yet. 1084 */ 1085 ao_mca_poll_init(ao, donb); 1086 1087 /* 1088 * Configure the bank MCi_CTL register to nominate which error 1089 * types for each bank will produce a machine-check (we'll poll 1090 * for others). Correctable error types mentioned in these MCi_CTL 1091 * settings won't actually produce an exception unless an additional 1092 * (and undocumented) bit is set elsewhere - the poller must still 1093 * handle these. 1094 */ 1095 ao_bank_cfg(ao, rev, donb); 1096 1097 /* 1098 * Modify the MCA NB Configuration Register. 1099 */ 1100 if (donb) 1101 ao_nb_cfg(ao, rev); 1102 1103 /* 1104 * Setup the Online Spare Control Register 1105 */ 1106 if (donb && X86_CHIPREV_MATCH(rev, AO_REVS_FG)) { 1107 ao_sparectl_cfg(ao); 1108 } 1109 1110 /* 1111 * Enable all error reporting banks (icache, dcache, ...). This 1112 * enables error detection, as opposed to error reporting above. 1113 */ 1114 wrmsr(IA32_MSR_MCG_CTL, AMD_MCG_EN_ALL); 1115 1116 /* 1117 * Throw away all existing bank state. We do this because some BIOSes, 1118 * perhaps during POST, do things to the machine that cause MCA state 1119 * to be updated. If we interpret this state as an actual error, we 1120 * may end up indicting something that's not actually broken. 1121 */ 1122 for (i = 0; i < AMD_MCA_BANK_COUNT; i++) { 1123 if (!donb) 1124 continue; 1125 1126 wrmsr(ao_bank_cfgs[i].bank_status, 0ULL); 1127 } 1128 1129 wrmsr(IA32_MSR_MCG_STATUS, 0ULL); 1130 membar_producer(); 1131 1132 setcr4(getcr4() | CR4_MCE); /* enable #mc exceptions */ 1133 } 1134 1135 /* 1136 * Note that although this cpu module is loaded before the PSMs are 1137 * loaded (and hence before acpica is loaded), this function is 1138 * called from post_startup(), after PSMs are initialized and acpica 1139 * is loaded. 1140 */ 1141 static int 1142 ao_acpi_find_smicmd(int *asd_port) 1143 { 1144 FADT_DESCRIPTOR *fadt = NULL; 1145 1146 /* 1147 * AcpiGetFirmwareTable works even if ACPI is disabled, so a failure 1148 * here means we weren't able to retreive a pointer to the FADT. 1149 */ 1150 if (AcpiGetFirmwareTable(FADT_SIG, 1, ACPI_LOGICAL_ADDRESSING, 1151 (ACPI_TABLE_HEADER **)&fadt) != AE_OK) 1152 return (-1); 1153 1154 ASSERT(fadt != NULL); 1155 1156 *asd_port = fadt->SmiCmd; 1157 return (0); 1158 } 1159 1160 /*ARGSUSED*/ 1161 void 1162 ao_mca_post_init(void *data) 1163 { 1164 const struct ao_smi_disable *asd; 1165 id_t id; 1166 int rv = -1, asd_port; 1167 1168 smbios_system_t sy; 1169 smbios_bios_t sb; 1170 smbios_info_t si; 1171 1172 /* 1173 * Fetch the System and BIOS vendor strings from SMBIOS and see if they 1174 * match a value in our table. If so, disable SMI error polling. This 1175 * is grotesque and should be replaced by self-describing vendor- 1176 * specific SMBIOS data or a specification enhancement instead. 1177 */ 1178 if (ao_mca_smi_disable && ksmbios != NULL && 1179 smbios_info_bios(ksmbios, &sb) != SMB_ERR && 1180 (id = smbios_info_system(ksmbios, &sy)) != SMB_ERR && 1181 smbios_info_common(ksmbios, id, &si) != SMB_ERR) { 1182 1183 for (asd = ao_smi_disable; asd->asd_sys_vendor != NULL; asd++) { 1184 if (strncmp(asd->asd_sys_vendor, si.smbi_manufacturer, 1185 strlen(asd->asd_sys_vendor)) != 0 || 1186 strncmp(asd->asd_bios_vendor, sb.smbb_vendor, 1187 strlen(asd->asd_bios_vendor)) != 0) 1188 continue; 1189 1190 /* 1191 * Look for the SMI_CMD port in the ACPI FADT, 1192 * if the port is 0, this platform doesn't support 1193 * SMM, so there is no SMI error polling to disable. 1194 */ 1195 if ((rv = ao_acpi_find_smicmd(&asd_port)) == 0 && 1196 asd_port != 0) { 1197 cmn_err(CE_CONT, "?SMI polling disabled in " 1198 "favor of Solaris Fault Management for " 1199 "AMD Processors\n"); 1200 1201 outb(asd_port, asd->asd_code); 1202 1203 } else if (rv < 0) { 1204 cmn_err(CE_CONT, "?Solaris Fault Management " 1205 "for AMD Processors could not disable SMI " 1206 "polling because an error occurred while " 1207 "trying to determine the SMI command port " 1208 "from the ACPI FADT table\n"); 1209 } 1210 break; 1211 } 1212 } 1213 1214 ao_mca_poll_start(); 1215 } 1216 1217 /* 1218 * Called after a CPU has been marked with CPU_FAULTED. Not called on the 1219 * faulted CPU. cpu_lock is held. 1220 */ 1221 /*ARGSUSED*/ 1222 void 1223 ao_faulted_enter(void *data) 1224 { 1225 /* 1226 * Nothing to do here. We'd like to turn off the faulted CPU's 1227 * correctable error detectors, but that can only be done by the 1228 * faulted CPU itself. cpu_get_state() will now return P_FAULTED, 1229 * allowing the poller to skip this CPU until it is re-enabled. 1230 */ 1231 } 1232 1233 /* 1234 * Called after the CPU_FAULTED bit has been cleared from a previously-faulted 1235 * CPU. Not called on the faulted CPU. cpu_lock is held. 1236 */ 1237 void 1238 ao_faulted_exit(void *data) 1239 { 1240 ao_data_t *ao = data; 1241 1242 /* 1243 * We'd like to clear the faulted CPU's MCi_STATUS registers so as to 1244 * avoid generating ereports for errors which occurred while the CPU was 1245 * officially faulted. Unfortunately, those registers can only be 1246 * cleared by the CPU itself, so we can't do it here. 1247 * 1248 * We're going to set the UNFAULTING bit on the formerly-faulted CPU's 1249 * MCA state. This will tell the poller that the MCi_STATUS registers 1250 * can't yet be trusted. The poller, which is the first thing we 1251 * control that'll execute on that CPU, will clear the registers, and 1252 * will then clear the bit. 1253 */ 1254 1255 ao->ao_mca.ao_mca_flags |= AO_MCA_F_UNFAULTING; 1256 } 1257