1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_VGAREG_H 28 #define _SYS_VGAREG_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * VGA frame buffer hardware definitions. 38 */ 39 40 #define VGA8_DEPTH 8 41 #define VGA8_CMAP_ENTRIES 256 42 #define VGA_TEXT_CMAP_ENTRIES 64 43 44 /* 45 * General VGA registers 46 * These are relative to their register set, which 47 * the 3c0-3df set. 48 */ 49 #define VGA_ATR_AD 0x00 50 #define VGA_ATR_DATA 0x01 51 #define VGA_MISC_W 0x02 52 #define VGA_SEQ_ADR 0x04 53 #define VGA_SEQ_DATA 0x05 54 #define VGA_DAC_BASE 0x06 55 #define VGA_DAC_AD_MK 0x06 56 #define VGA_DAC_RD_AD 0x07 57 #define VGA_DAC_STS 0x07 58 #define VGA_DAC_WR_AD 0x08 59 #define VGA_DAC_DATA 0x09 60 #define VGA_MISC_R 0x0c 61 #define VGA_GRC_ADR 0x0e 62 #define VGA_GRC_DATA 0x0f 63 #define VGA_CRTC_ADR 0x14 64 #define VGA_CRTC_DATA 0x15 65 #define CGA_STAT 0x1a 66 67 /* 68 * Attribute controller index bits 69 */ 70 #define VGA_ATR_ENB_PLT 0x20 71 72 /* 73 * Miscellaneous output bits 74 */ 75 #define VGA_MISC_IOA_SEL 0x01 76 #define VGA_MISC_ENB_RAM 0x02 77 #define VGA_MISC_VCLK 0x0c 78 #define VGA_MISC_VCLK0 0x00 79 #define VGA_MISC_VCLK1 0x04 80 #define VGA_MISC_VCLK2 0x08 81 #define VGA_MISC_VCLK3 0x0c 82 #define VGA_MISC_PGSL 0x20 83 #define VGA_MISC_HSP 0x40 84 #define VGA_MISC_VSP 0x80 85 86 /* 87 * CRT Controller registers 88 */ 89 #define VGA_CRTC_H_TOTAL 0x00 90 #define VGA_CRTC_H_D_END 0x01 91 #define VGA_CRTC_S_H_BLNK 0x02 92 #define VGA_CRTC_E_H_BLNK 0x03 93 #define VGA_CRTC_E_H_BLNK_PUT_EHB(n) \ 94 ((n)&0x1f) 95 #define VGA_CRTC_S_H_SY_P 0x04 96 #define VGA_CRTC_E_H_SY_P 0x05 97 #define VGA_CRTC_E_H_SY_P_HOR_SKW_SHIFT 5 98 #define VGA_CRTC_E_H_SY_P_HOR_SKW 0x60 99 #define VGA_CRTC_E_H_SY_P_EHB5 7 100 #define VGA_CRTC_E_H_SY_P_PUT_HOR_SKW(skew) \ 101 ((skew)<<VGA_CRTC_E_H_SY_P_HOR_SKW_SHIFT) 102 #define VGA_CRTC_E_H_SY_P_PUT_EHB(n) \ 103 ((((n)>>5)&1)<<VGA_CRTC_E_H_SY_P_EHB5) 104 #define VGA_CRTC_E_H_SY_P_PUT_EHS(n) \ 105 ((n)&0x1f) 106 #define VGA_CRTC_V_TOTAL 0x06 107 #define VGA_CRTC_OVFL_REG 0x07 108 #define VGA_CRTC_OVFL_REG_VT8 0 109 #define VGA_CRTC_OVFL_REG_VDE8 1 110 #define VGA_CRTC_OVFL_REG_VRS8 2 111 #define VGA_CRTC_OVFL_REG_SVB8 3 112 #define VGA_CRTC_OVFL_REG_LCM8 4 113 #define VGA_CRTC_OVFL_REG_VT9 5 114 #define VGA_CRTC_OVFL_REG_VDE9 6 115 #define VGA_CRTC_OVFL_REG_VRS9 7 116 #define VGA_CRTC_OVFL_REG_PUT_VT(n) \ 117 ((((n)>>8)&1)<<VGA_CRTC_OVFL_REG_VT8) \ 118 | ((((n)>>9)&1)<<VGA_CRTC_OVFL_REG_VT9) 119 #define VGA_CRTC_OVFL_REG_PUT_VDE(n) \ 120 ((((n)>>8)&1)<<VGA_CRTC_OVFL_REG_VDE8) \ 121 | ((((n)>>9)&1)<<VGA_CRTC_OVFL_REG_VDE9) 122 #define VGA_CRTC_OVFL_REG_PUT_VRS(n) \ 123 ((((n)>>8)&1)<<VGA_CRTC_OVFL_REG_VRS8) \ 124 | ((((n)>>9)&1)<<VGA_CRTC_OVFL_REG_VRS9) 125 #define VGA_CRTC_OVFL_REG_PUT_LCM(n) \ 126 ((((n)>>8)&1)<<VGA_CRTC_OVFL_REG_LCM8) 127 #define VGA_CRTC_OVFL_REG_PUT_SVB(n) \ 128 ((((n)>>8)&1)<<VGA_CRTC_OVFL_REG_SVB8) 129 #define VGA_CRTC_P_R_SCAN 0x08 130 #define VGA_CRTC_MAX_S_LN 0x09 131 #define VGA_CRTC_MAX_S_LN_SVB9 5 132 #define VGA_CRTC_MAX_S_LN_LCM9 6 133 #define VGA_CRTC_MAX_S_LN_PUT_SVB(n) \ 134 ((((n)>>9)&1)<<VGA_CRTC_MAX_S_LN_SVB9) 135 #define VGA_CRTC_MAX_S_LN_PUT_LCM(n) \ 136 ((((n)>>9)&1)<<VGA_CRTC_MAX_S_LN_LCM9) 137 #define VGA_CRTC_CSSL 0x0a 138 #define VGA_CRTC_CESL 0x0b 139 #define VGA_CRTC_STAH 0x0c 140 #define VGA_CRTC_STAL 0x0d 141 #define VGA_CRTC_CLAH 0x0e 142 #define VGA_CRTC_CLAL 0x0f 143 #define VGA_CRTC_VRS 0x10 144 #define VGA_CRTC_VRE 0x11 145 #define VGA_CRTC_VRE_LOCK 0x80 146 #define VGA_CRTC_VRE_DIS_VINT 0x20 147 #define VGA_CRTC_VRE_PUT_VRE(n) \ 148 ((n)&0x0f) 149 #define VGA_CRTC_VDE 0x12 150 #define VGA_CRTC_SCREEN_OFFSET 0x13 151 #define VGA_CRTC_ULL 0x14 152 #define VGA_CRTC_SVB 0x15 153 #define VGA_CRTC_EVB 0x16 154 #define VGA_CRTC_CRT_MD 0x17 155 #define VGA_CRTC_CRT_MD_2BK_CGA 0x01 156 #define VGA_CRTC_CRT_MD_4BK_HGC 0x02 157 #define VGA_CRTC_CRT_MD_VT_X2 0x04 158 #define VGA_CRTC_CRT_MD_WRD_MODE 0x08 159 #define VGA_CRTC_CRT_MD_ADW_16K 0x20 160 #define VGA_CRTC_CRT_MD_BYTE_MODE 0x40 161 #define VGA_CRTC_CRT_MD_NO_RESET 0x80 162 #define VGA_CRTC_LCM 0x18 163 164 /* 165 * Sequencer registers 166 */ 167 #define VGA_SEQ_RST_SYN 0x00 168 #define VGA_SEQ_RST_SYN_ASYNC_RESET 0x00 169 #define VGA_SEQ_RST_SYN_NO_ASYNC_RESET 0x01 170 #define VGA_SEQ_RST_SYN_SYNC_RESET 0x00 171 #define VGA_SEQ_RST_SYN_NO_SYNC_RESET 0x02 172 #define VGA_SEQ_CLK_MODE 0x01 173 #define VGA_SEQ_CLK_MODE_8DC 0x01 174 #define VGA_SEQ_EN_WT_PL 0x02 175 #define VGA_SEQ_EN_WT_PL_ALL 0x0f 176 #define VGA_SEQ_MEM_MODE 0x04 177 #define VGA_SEQ_MEM_MODE_EXT_MEM 0x02 178 #define VGA_SEQ_MEM_MODE_SEQ_MODE 0x04 179 #define VGA_SEQ_MEM_MODE_CHN_4M 0x08 180 181 /* 182 * Graphics Controller 183 */ 184 #define VGA_GRC_SET_RST_DT 0x00 185 #define VGA_GRC_EN_S_R_DT 0x01 186 #define VGA_GRC_COLOR_CMP 0x02 187 #define VGA_GRC_WT_ROP_RTC 0x03 188 #define VGA_GRC_RD_PL_SL 0x04 189 #define VGA_GRC_GRP_MODE 0x05 190 #define VGA_GRC_GRP_MODE_SHF_MODE_256 0x40 191 #define VGA_GRC_MISC_GM 0x06 192 #define VGA_GRC_MISC_GM_GRAPH 0x01 193 #define VGA_GRC_MISC_GM_MEM_MAP_1 0x04 194 #define VGA_GRC_CMP_DNTC 0x07 195 #define VGA_GRC_CMP_DNTC_ALL 0x0f 196 #define VGA_GRC_BIT_MASK 0x08 197 198 /* 199 * Attribute controller registers 200 */ 201 #define VGA_ATR_PLT_REG 0x00 202 #define VGA_ATR_NUM_PLT 0x10 203 #define VGA_ATR_MODE 0x10 204 #define VGA_ATR_MODE_GRAPH 0x01 205 #define VGA_ATR_MODE_9WIDE 0x04 206 #define VGA_ATR_MODE_BLINK 0x08 207 #define VGA_ATR_MODE_256CLR 0x40 208 #define VGA_ATR_BDR_CLR 0x11 209 #define VGA_ATR_DISP_PLN 0x12 210 #define VGA_ATR_DISP_PLN_ALL 0x0f 211 #define VGA_ATR_H_PX_PAN 0x13 212 #define VGA_ATR_PX_PADD 0x14 213 214 /* 215 * Low-memory frame buffer definitions. These are relative to the 216 * A0000 register set. 217 */ 218 #define VGA_MONO_BASE 0x10000 /* Base of monochrome text */ 219 #define VGA_COLOR_BASE 0x18000 /* Base of color text */ 220 #define VGA_TEXT_SIZE 0x8000 /* Size of text frame buffer */ 221 222 #ifdef __cplusplus 223 } 224 #endif 225 226 #endif /* _SYS_VGAREG_H */ 227