1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_USB_UHCID_H 28 #define _SYS_USB_UHCID_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * Universal Host Controller Driver (UHCI) 38 * 39 * The UHCI driver is a driver which interfaces to the Universal 40 * Serial Bus Driver (USBA) and the Host Controller (HC). The interface to 41 * the Host Controller is defined by the Universal Host Controller Interface. 42 * 43 * This file contains the data structures for the UHCI driver. 44 */ 45 #include <sys/types.h> 46 #include <sys/pci.h> 47 #include <sys/kstat.h> 48 49 #include <sys/usb/usba/usbai_version.h> 50 #include <sys/usb/usba.h> 51 #include <sys/usb/usba/usba_types.h> 52 53 #include <sys/usb/usba/genconsole.h> 54 #include <sys/usb/usba/hcdi.h> 55 56 #include <sys/usb/hubd/hub.h> 57 #include <sys/usb/usba/hubdi.h> 58 #include <sys/usb/hubd/hubdvar.h> 59 60 #include <sys/usb/hcd/uhci/uhci.h> 61 62 /* limit the xfer size for bulk */ 63 #define UHCI_BULK_MAX_XFER_SIZE (124*1024) /* Max bulk xfer size */ 64 65 /* Maximum allowable data transfer size per transaction */ 66 #define UHCI_MAX_TD_XFER_SIZE 0x2000 /* Maximum data per transaction */ 67 68 /* 69 * Generic UHCI Macro definitions 70 */ 71 #define UHCI_UNDERRUN_OCCURRED 0x1234 72 #define UHCI_OVERRUN_OCCURRED 0x5678 73 #define UHCI_PROP_MASK 0x01000020 74 #define UHCI_RESET_DELAY 15000 75 #define UHCI_TIMEWAIT 10000 76 77 #define MAX_SOF_WAIT_COUNT 2 78 #define MAX_RH_PORTS 2 79 #define DISCONNECTED 2 80 #define POLLING_FREQ_7MS 7 81 #define PCI_CONF_IOBASE 0x20 82 #define PCI_CONF_IOBASE_MASK 0xffe0 83 84 #define UHCI_ONE_SECOND drv_usectohz(1000000) 85 #define UHCI_ONE_MS drv_usectohz(1000) 86 #define UHCI_32_MS drv_usectohz(32*1000) 87 #define UHCI_MAX_INSTS 4 88 89 #define POLLED_RAW_BUF_SIZE 8 90 91 /* Default time out values for bulk and ctrl commands */ 92 #define UHCI_CTRL_TIMEOUT 5 93 #define UHCI_BULK_TIMEOUT 60 94 95 /* UHCI root hub structure */ 96 typedef struct uhci_root_hub_info { 97 uint_t rh_status; /* Last RH status */ 98 uint_t rh_num_ports; /* #ports on the root */ 99 100 /* Last status of ports */ 101 uint_t rh_port_status[MAX_RH_PORTS]; 102 uint_t rh_port_changes[MAX_RH_PORTS]; 103 uint_t rh_port_state[MAX_RH_PORTS]; /* See below */ 104 105 usba_pipe_handle_data_t *rh_intr_pipe_handle; /* RH intr pipe hndle */ 106 usb_hub_descr_t rh_descr; /* RH descr's copy */ 107 uint_t rh_pipe_state; /* RH intr pipe state */ 108 109 usb_intr_req_t *rh_curr_intr_reqp; /* Current intr req */ 110 usb_intr_req_t *rh_client_intr_req; /* save IN request */ 111 } uhci_root_hub_info_t; 112 113 /* 114 * UHCI Host Controller per instance data structure 115 * 116 * The Host Controller Driver (HCD) maintains the state of Host Controller 117 * (HC). There is an uhci_state structure per instance of the UHCI 118 * host controller. 119 */ 120 typedef struct uhci_state { 121 dev_info_t *uhci_dip; /* dip of HC */ 122 uint_t uhci_instance; 123 usba_hcdi_ops_t *uhci_hcdi_ops; /* HCDI structure */ 124 125 uint_t uhci_dma_addr_bind_flag; 126 127 /* Flag of uhci controller initialization */ 128 boolean_t uhci_ctlr_init_flag; 129 130 hc_regs_t *uhci_regsp; /* Host ctlr regs */ 131 ddi_acc_handle_t uhci_regs_handle; /* Reg handle */ 132 133 ddi_acc_handle_t uhci_config_handle; /* Config space hndle */ 134 135 /* Frame interval reg */ 136 uint_t uhci_frame_interval; 137 ddi_dma_attr_t uhci_dma_attr; /* DMA attributes */ 138 139 ddi_intr_handle_t *uhci_htable; /* intr handle */ 140 int uhci_intr_type; /* intr type used */ 141 int uhci_intr_cnt; /* # of intrs inuse */ 142 uint_t uhci_intr_pri; /* intr priority */ 143 int uhci_intr_cap; /* intr capabilities */ 144 kmutex_t uhci_int_mutex; /* Mutex for struct */ 145 146 frame_lst_table_t *uhci_frame_lst_tablep; /* Virtual HCCA ptr */ 147 uhci_td_t *uhci_isoc_q_tailp[NUM_FRAME_LST_ENTRIES]; 148 149 ddi_dma_cookie_t uhci_flt_cookie; /* DMA cookie */ 150 ddi_dma_handle_t uhci_flt_dma_handle; /* DMA handle */ 151 ddi_acc_handle_t uhci_flt_mem_handle; /* Memory handle */ 152 153 /* 154 * There are two pools of memory. One pool contains the memory for 155 * the transfer descriptors and other pool contains the memory for 156 * the Queue Head pointers. The advantage of the pools is that it's 157 * easy to go back and forth between the iommu and the cpu addresses. 158 * 159 * The pools are protected by the int_mutex because the memory 160 * in the pools may be accessed by either the host controller or the 161 * host controller driver. 162 */ 163 164 /* General transfer descriptor pool */ 165 uhci_td_t *uhci_td_pool_addr; /* Start of the pool */ 166 ddi_dma_cookie_t uhci_td_pool_cookie; /* DMA cookie */ 167 ddi_dma_handle_t uhci_td_pool_dma_handle; /* DMA hndle */ 168 ddi_acc_handle_t uhci_td_pool_mem_handle; /* Mem hndle */ 169 170 /* Endpoint descriptor pool */ 171 queue_head_t *uhci_qh_pool_addr; /* Start of the pool */ 172 ddi_dma_cookie_t uhci_qh_pool_cookie; /* DMA cookie */ 173 ddi_dma_handle_t uhci_qh_pool_dma_handle; /* DMA handle */ 174 ddi_acc_handle_t uhci_qh_pool_mem_handle; /* Mem handle */ 175 176 /* Semaphore to serialize opens and closes */ 177 ksema_t uhci_ocsem; 178 179 /* Timeout id of the root hub status change pipe handler */ 180 timeout_id_t uhci_timeout_id; 181 182 /* Timeout id of the ctrl/bulk/intr xfers timeout */ 183 timeout_id_t uhci_cmd_timeout_id; 184 185 /* 186 * Bandwidth fields 187 * 188 * The uhci_bandwidth array keeps track of the allocated bandwidth 189 * for this host controller. The uhci_bandwidth_isoch_sum field 190 * represents the sum of the allocated isochronous bandwidth. The 191 * total bandwidth allocated for least allocated list out of the 32 192 * interrupt lists is represented by the uhci_bandwdith_intr_min 193 * field. 194 */ 195 uint_t uhci_bandwidth[NUM_FRAME_LST_ENTRIES]; 196 uint_t uhci_bandwidth_isoch_sum; 197 uint_t uhci_bandwidth_intr_min; 198 199 uhci_root_hub_info_t uhci_root_hub; /* Root hub info */ 200 201 uhci_td_t *uhci_outst_tds_head; 202 uhci_td_t *uhci_outst_tds_tail; 203 204 queue_head_t *uhci_ctrl_xfers_q_head; 205 queue_head_t *uhci_ctrl_xfers_q_tail; 206 queue_head_t *uhci_bulk_xfers_q_head; 207 queue_head_t *uhci_bulk_xfers_q_tail; 208 209 kcondvar_t uhci_cv_SOF; 210 uchar_t uhci_cv_signal; 211 212 /* Polled I/O support */ 213 frame_lst_table_t uhci_polled_save_IntTble[1024]; 214 uint_t uhci_polled_count; 215 uint32_t uhci_polled_flag; 216 217 /* Software frame number */ 218 usb_frame_number_t uhci_sw_frnum; 219 220 /* Number of pending bulk commands */ 221 uint32_t uhci_pending_bulk_cmds; 222 223 /* logging support */ 224 usb_log_handle_t uhci_log_hdl; 225 226 /* 227 * TD's used for the generation of interrupt 228 */ 229 queue_head_t *uhci_isoc_qh; 230 uhci_td_t *uhci_sof_td; 231 uhci_td_t *uhci_isoc_td; 232 233 /* 234 * Keep io base address, for debugging purpose 235 */ 236 uint_t uhci_iobase; 237 238 /* 239 * kstat structures 240 */ 241 kstat_t *uhci_intrs_stats; 242 kstat_t *uhci_total_stats; 243 kstat_t *uhci_count_stats[USB_N_COUNT_KSTATS]; 244 } uhci_state_t; 245 246 247 /* 248 * uhci_dma_addr_bind_flag values 249 * 250 * This flag indicates if the various DMA addresses allocated by the UHCI 251 * have been bound to their respective handles. This is needed to recover 252 * without errors from uhci_cleanup when it calls ddi_dma_unbind_handle() 253 */ 254 #define UHCI_TD_POOL_BOUND 0x01 /* for TD pools */ 255 #define UHCI_QH_POOL_BOUND 0x02 /* for QH pools */ 256 #define UHCI_FLA_POOL_BOUND 0x04 /* for Host Ctrlr Framelist Area */ 257 258 /* 259 * Definitions for uhci_polled_flag 260 * The flag is set to UHCI_POLLED_FLAG_FALSE by default. The flags is 261 * set to UHCI_POLLED_FLAG_TD_COMPL when shifting from normal mode to 262 * polled mode and if the normal TD is completed at that time. And the 263 * flag is set to UHCI_POLLED_FLAG_TRUE while exiting from the polled 264 * mode. In the timeout handler for root hub status change, this flag 265 * is checked. If set to UHCI_POLLED_FLAG_TRUE, the routine 266 * uhci_process_submitted_td_queue() to process the completed TD. 267 */ 268 #define UHCI_POLLED_FLAG_FALSE 0 269 #define UHCI_POLLED_FLAG_TRUE 1 270 #define UHCI_POLLED_FLAG_TD_COMPL 2 271 272 /* 273 * Pipe private structure 274 * 275 * There is an instance of this structure per pipe. This structure holds 276 * HCD specific pipe information. A pointer to this structure is kept in 277 * the USBA pipe handle (usba_pipe_handle_data_t). 278 */ 279 typedef struct uhci_pipe_private { 280 usba_pipe_handle_data_t *pp_pipe_handle; /* Back ptr to pipe handle */ 281 queue_head_t *pp_qh; /* Pipe's ept */ 282 uint_t pp_state; /* See below */ 283 usb_pipe_policy_t pp_policy; /* Copy of the pipe policy */ 284 uint_t pp_node; /* Node in lattice */ 285 uchar_t pp_data_toggle; /* save data toggle bit */ 286 287 /* 288 * Each pipe may have multiple transfer wrappers. Each transfer 289 * wrapper represents a USB transfer on the bus. A transfer is 290 * made up of one or more transactions. 291 */ 292 struct uhci_trans_wrapper *pp_tw_head; /* Head of the list */ 293 struct uhci_trans_wrapper *pp_tw_tail; /* Tail of the list */ 294 295 /* 296 * Starting frame number at which next isoc TD will be inserted 297 * for this pipe 298 */ 299 uint64_t pp_frame_num; 300 301 /* 302 * HCD gets Interrupt/Isochronous IN polling request only once and 303 * it has to insert next polling requests after completion of first 304 * request until either stop polling/pipe close is called. So HCD 305 * has to take copy of the original Interrupt/Isochronous IN request. 306 */ 307 usb_opaque_t pp_client_periodic_in_reqp; 308 } uhci_pipe_private_t; 309 310 /* warlock directives, stable data */ 311 _NOTE(MUTEX_PROTECTS_DATA(uhci_state_t::uhci_int_mutex, uhci_pipe_private_t)) 312 _NOTE(LOCK_ORDER(uhci_state::uhci_int_mutex \ 313 usba_pipe_handle_data::p_mutex \ 314 usba_device::usb_mutex \ 315 usba_ph_impl::usba_ph_mutex)) 316 _NOTE(SCHEME_PROTECTS_DATA("private mutex", kstat_io)) 317 _NOTE(SCHEME_PROTECTS_DATA("unshared", usb_isoc_pkt_descr)) 318 319 /* 320 * Pipe states 321 * 322 * uhci pipe states will be similar to usba. Refer usbai.h. 323 */ 324 #define UHCI_PIPE_STATE_IDLE 1 /* Pipe has opened,ready state */ 325 #define UHCI_PIPE_STATE_ACTIVE 2 /* Polling the endpoint,busy state */ 326 327 /* 328 * to indicate if we are in close/reset so that we can issue callbacks to 329 * IN packets that are pending 330 */ 331 #define UHCI_IN_CLOSE 4 332 #define UHCI_IN_RESET 5 333 #define UHCI_IN_ERROR 6 334 335 /* Function prototype */ 336 typedef void (*uhci_handler_function_t) (uhci_state_t *uhcip, uhci_td_t *td); 337 338 /* 339 * Transfer wrapper 340 * 341 * The transfer wrapper represents a USB transfer on the bus and there 342 * is one instance per USB transfer. A transfer is made up of one or 343 * more transactions. 344 * 345 * Control and bulk pipes will have one transfer wrapper per transfer 346 * and where as Isochronous and Interrupt pipes will only have one 347 * transfer wrapper. The transfers wrapper are continually reused for 348 * the Interrupt and Isochronous pipes as those pipes are polled. 349 */ 350 typedef struct uhci_trans_wrapper { 351 struct uhci_trans_wrapper *tw_next; /* Next wrapper */ 352 uhci_pipe_private_t *tw_pipe_private; 353 size_t tw_length; /* Txfer length */ 354 uint_t tw_tmp; /* Temp variable */ 355 ddi_dma_handle_t tw_dmahandle; /* DMA handle */ 356 ddi_acc_handle_t tw_accesshandle; /* Acc hndle */ 357 char *tw_buf; /* Buffer for txfer */ 358 ddi_dma_cookie_t tw_cookie; /* DMA cookie */ 359 int tw_ctrl_state; /* See below */ 360 uhci_td_t *tw_hctd_head; /* Head TD */ 361 uhci_td_t *tw_hctd_tail; /* Tail TD */ 362 uint_t tw_direction; /* Direction of TD */ 363 usb_flags_t tw_flags; /* Flags */ 364 365 /* 366 * This is the function to call when this td is done. This way 367 * we don't have to look in the td to figure out what kind it is. 368 */ 369 uhci_handler_function_t tw_handle_td; 370 371 /* 372 * This is the callback value used when processing a done td. 373 */ 374 usb_opaque_t tw_handle_callback_value; 375 376 uint_t tw_bytes_xfered; 377 uint_t tw_bytes_pending; 378 379 /* Maximum amount of time for this command */ 380 uint_t tw_timeout_cnt; 381 382 usb_isoc_req_t *tw_isoc_req; 383 uhci_bulk_isoc_xfer_t tw_xfer_info; 384 385 /* This is used to avoid multiple tw deallocation */ 386 uint_t tw_claim; 387 388 /* 389 * Pointer to the data in case of send command 390 */ 391 mblk_t *tw_data; 392 393 /* save a copy of current request */ 394 usb_opaque_t tw_curr_xfer_reqp; 395 } uhci_trans_wrapper_t; 396 397 /* set timeout flag so as to decrement timeout_cnt only once */ 398 #define TW_TIMEOUT_FLAG 0x1000 399 400 /* Macro for changing the data toggle */ 401 #define ADJ_DATA_TOGGLE(pp) \ 402 (pp)->pp_data_toggle = ((pp)->pp_data_toggle == 0) ? 1 : 0; 403 404 /* 405 * Macros for setting/getting information 406 */ 407 #define Get_OpReg32(addr) ddi_get32(uhcip->uhci_regs_handle, \ 408 (uint32_t *)&uhcip->uhci_regsp->addr) 409 #define Get_OpReg16(addr) ddi_get16(uhcip->uhci_regs_handle, \ 410 (uint16_t *)&uhcip->uhci_regsp->addr) 411 #define Get_OpReg8(addr) ddi_get8(uhcip->uhci_regs_handle, \ 412 (uchar_t *)&uhcip->uhci_regsp->addr) 413 414 #define Set_OpReg32(addr, val) ddi_put32(uhcip->uhci_regs_handle, \ 415 ((uint32_t *)&uhcip->uhci_regsp->addr), \ 416 ((int32_t)(val))) 417 #define Set_OpReg16(addr, val) ddi_put16(uhcip->uhci_regs_handle, \ 418 ((uint16_t *)&uhcip->uhci_regsp->addr), \ 419 ((int16_t)(val))) 420 421 #define QH_PADDR(addr) \ 422 ((uint32_t)(uhcip->uhci_qh_pool_cookie.dmac_address + \ 423 (uint32_t)((uintptr_t)(addr) - \ 424 (uintptr_t)uhcip->uhci_qh_pool_addr))) 425 426 427 #define QH_VADDR(addr) \ 428 ((void *)(((uint32_t)(addr) - \ 429 (uint32_t)uhcip->uhci_qh_pool_cookie.dmac_address) + \ 430 (char *)uhcip->uhci_qh_pool_addr)) 431 432 #define TD_PADDR(addr) \ 433 ((uint32_t)uhcip->uhci_td_pool_cookie.dmac_address + \ 434 (uint32_t)((uintptr_t)(addr) - \ 435 (uintptr_t)(uhcip->uhci_td_pool_addr))) 436 437 #define BULKTD_PADDR(x, addr)\ 438 ((uint32_t)((uintptr_t)(addr) - (uintptr_t)x->pool_addr) + \ 439 (uint32_t)(x)->cookie.dmac_address) 440 441 #define BULKTD_VADDR(x, addr)\ 442 ((void *)(((uint32_t)(addr) - \ 443 (uint32_t)(x)->cookie.dmac_address) + \ 444 (char *)(x)->pool_addr)) 445 446 #define ISOCTD_PADDR(x, addr)\ 447 ((uint32_t)((uintptr_t)(addr) - (uintptr_t)(x)->pool_addr) + \ 448 (uint32_t)(x)->cookie.dmac_address) 449 450 #define TD_VADDR(addr) \ 451 ((void *)(((uint32_t)(addr) - \ 452 (uint32_t)uhcip->uhci_td_pool_cookie.dmac_address) + \ 453 (char *)uhcip->uhci_td_pool_addr)) 454 455 /* 456 * If the terminate bit is cleared, there shouldn't be any 457 * race condition problems. If the host controller reads the 458 * bit before the driver has a chance to set the bit, the bit 459 * will be reread on the next frame. 460 */ 461 #define UHCI_SET_TERMINATE_BIT(addr) \ 462 SetQH32(uhcip, addr, GetQH32(uhcip, (addr)) | HC_END_OF_LIST) 463 #define UHCI_CLEAR_TERMINATE_BIT(addr) \ 464 SetQH32(uhcip, addr, GetQH32(uhcip, (addr)) & ~HC_END_OF_LIST) 465 466 #define UHCI_XFER_TYPE(ept) ((ept)->bmAttributes & USB_EP_ATTR_MASK) 467 #define UHCI_XFER_DIR(ept) ((ept)->bEndpointAddress & \ 468 USB_EP_DIR_MASK) 469 470 /* 471 * for HCD based kstats: 472 * uhci_intrs_stats_t structure 473 */ 474 typedef struct uhci_intrs_stats { 475 struct kstat_named uhci_intrs_hc_halted; 476 struct kstat_named uhci_intrs_hc_process_err; 477 struct kstat_named uhci_intrs_host_sys_err; 478 struct kstat_named uhci_intrs_resume_detected; 479 struct kstat_named uhci_intrs_usb_err_intr; 480 struct kstat_named uhci_intrs_usb_intr; 481 struct kstat_named uhci_intrs_total; 482 struct kstat_named uhci_intrs_not_claimed; 483 } uhci_intrs_stats_t; 484 485 /* 486 * uhci defines for kstats 487 */ 488 #define UHCI_INTRS_STATS(uhci) ((uhci)->uhci_intrs_stats) 489 #define UHCI_INTRS_STATS_DATA(uhci) \ 490 ((uhci_intrs_stats_t *)UHCI_INTRS_STATS((uhci))->ks_data) 491 492 #define UHCI_TOTAL_STATS(uhci) ((uhci)->uhci_total_stats) 493 #define UHCI_TOTAL_STATS_DATA(uhci) (KSTAT_IO_PTR((uhci)->uhci_total_stats)) 494 #define UHCI_CTRL_STATS(uhci) \ 495 (KSTAT_IO_PTR((uhci)->uhci_count_stats[USB_EP_ATTR_CONTROL])) 496 #define UHCI_BULK_STATS(uhci) \ 497 (KSTAT_IO_PTR((uhci)->uhci_count_stats[USB_EP_ATTR_BULK])) 498 #define UHCI_INTR_STATS(uhci) \ 499 (KSTAT_IO_PTR((uhci)->uhci_count_stats[USB_EP_ATTR_INTR])) 500 #define UHCI_ISOC_STATS(uhci) \ 501 (KSTAT_IO_PTR((uhci)->uhci_count_stats[USB_EP_ATTR_ISOCH])) 502 503 #define UHCI_UNIT(dev) (getminor((dev)) & ~HUBD_IS_ROOT_HUB) 504 505 #define UHCI_PERIODIC_ENDPOINT(ept) \ 506 (((((ept)->bmAttributes) & USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) || \ 507 ((((ept)->bmAttributes) & USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH)) 508 509 /* 510 * Debug printing Masks 511 */ 512 #define PRINT_MASK_ATTA 0x00000001 /* Attach time */ 513 #define PRINT_MASK_LISTS 0x00000002 /* List management */ 514 #define PRINT_MASK_ROOT_HUB 0x00000004 /* Root hub stuff */ 515 #define PRINT_MASK_ALLOC 0x00000008 /* Alloc/dealloc descr */ 516 #define PRINT_MASK_INTR 0x00000010 /* Interrupt handling */ 517 #define PRINT_MASK_BW 0x00000020 /* Bandwidth */ 518 #define PRINT_MASK_CBOPS 0x00000040 /* CB-OPS */ 519 #define PRINT_MASK_HCDI 0x00000080 /* HCDI entry points */ 520 #define PRINT_MASK_DUMPING 0x00000100 /* Dump HCD state info */ 521 #define PRINT_MASK_ISOC 0x00000200 /* For ISOC xfers */ 522 523 #define PRINT_MASK_ALL 0xFFFFFFFF 524 525 #ifdef __cplusplus 526 } 527 #endif 528 529 #endif /* _SYS_USB_UHCID_H */ 530