1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_USB_OHCID_H 27 #define _SYS_USB_OHCID_H 28 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* 35 * Open Host Controller Driver (OHCI) 36 * 37 * The USB Open Host Controller driver is a software driver which interfaces 38 * to the Universal Serial Bus layer (USBA) and the USB Open Host Controller. 39 * The interface to USB Open Host Controller is defined by the OpenHCI Host 40 * Controller Interface. 41 * 42 * This header file describes the data structures required for the USB Open 43 * Host Controller Driver to maintain state of USB Open Host Controller, to 44 * perform different USB transfers and for the bandwidth allocations. 45 */ 46 47 #include <sys/usb/hcd/openhci/ohci.h> 48 #include <sys/usb/hcd/openhci/ohci_hub.h> 49 50 /* 51 * OpenHCI interrupt status information structure 52 * 53 * The Host Controller Driver (HCD) has to maintain two different sets of 54 * Host Controller (HC) state information that includes HC registers, the 55 * interrupt tables etc.. for the normal and polled modes. In addition, 56 * suppose if we switched to polled mode while ohci interrupt handler is 57 * executing in the normal mode then we need to save the interrupt status 58 * information that includes interrupts for which ohci interrupt handler 59 * is called and HCCA done head list in the polled mode. This infromation 60 * will be used later in normal mode to service those missed interrupts. 61 * This will avoid race conditions like missing of normal mode's ohci SOF 62 * and WriteDoneHead interrupts because of this polled switch. 63 */ 64 typedef struct ohci_save_intr_sts { 65 /* 66 * The following field has set of flags & these flags will be set 67 * in the ohci interrupt handler to indicate that currently ohci 68 * interrupt handler is in execution and also while critical code 69 * execution within the ohci interrupt handler. These flags will 70 * be verified in polled mode while saving the normal mode's ohci 71 * interrupt status information. 72 */ 73 uint_t ohci_intr_flag; /* Intr handler flags */ 74 75 /* 76 * The following fields will be used to save the interrupt status 77 * and the HCCA done head list that the ohci interrupt handler is 78 * currently handling. 79 */ 80 uint_t ohci_curr_intr_sts; /* Current interrupts */ 81 ohci_td_t *ohci_curr_done_lst; /* Current done head */ 82 83 /* 84 * The following fields will be used to save the interrupt status 85 * and the HCCA done list currently being handled by the critical 86 * section of the ohci interrupt handler.. 87 */ 88 uint_t ohci_critical_intr_sts; /* Critical interrupts */ 89 ohci_td_t *ohci_critical_done_lst; /* Critical done head */ 90 91 /* 92 * The following fields will be used to save the interrupt status 93 * and HCCA done head list by the polled code if an interrupt is 94 * pending when polled code is entered. These missed interrupts & 95 * done list will be serviced either in current normal mode ohci 96 * interrupt handler execution or during the next ohci interrupt 97 * handler execution. 98 */ 99 uint_t ohci_missed_intr_sts; /* Missed interrupts */ 100 ohci_td_t *ohci_missed_done_lst; /* Missed done head */ 101 } ohci_save_intr_sts_t; 102 103 /* 104 * These flags will be set in the the normal mode ohci interrupt handler 105 * to indicate that currently ohci interrupt handler is in execution and 106 * also while critical code execution within the ohci interrupt handler. 107 * These flags will be verified in the polled mode while saving the normal 108 * mode's ohci interrupt status infromation. 109 */ 110 #define OHCI_INTR_HANDLING 0x01 /* Handling ohci intrs */ 111 #define OHCI_INTR_CRITICAL 0x02 /* Critical intr code */ 112 113 114 /* 115 * OpenHCI Host Controller state structure 116 * 117 * The Host Controller Driver (HCD) maintains the state of Host Controller 118 * (HC). There is an ohci_state structure per instance of the OpenHCI 119 * host controller. 120 */ 121 122 typedef struct ohci_state { 123 dev_info_t *ohci_dip; /* Dip of HC */ 124 uint_t ohci_instance; 125 usba_hcdi_ops_t *ohci_hcdi_ops; /* HCDI structure */ 126 uint_t ohci_flags; /* Used for cleanup */ 127 uint16_t ohci_vendor_id; /* chip vendor */ 128 uint16_t ohci_device_id; /* chip device */ 129 uint8_t ohci_rev_id; /* chip revison */ 130 131 ohci_regs_t *ohci_regsp; /* Host ctlr regs */ 132 ddi_acc_handle_t ohci_regs_handle; /* Reg handle */ 133 134 ddi_acc_handle_t ohci_config_handle; /* Config space hndle */ 135 uint_t ohci_frame_interval; /* Frme inter reg */ 136 ddi_dma_attr_t ohci_dma_attr; /* DMA attributes */ 137 138 ddi_intr_handle_t *ohci_htable; /* intr handle */ 139 int ohci_intr_type; /* intr type used */ 140 int ohci_intr_cnt; /* # of intrs inuse */ 141 uint_t ohci_intr_pri; /* intr priority */ 142 int ohci_intr_cap; /* intr capabilities */ 143 boolean_t ohci_msi_enabled; /* default to true */ 144 kmutex_t ohci_int_mutex; /* Mutex for struct */ 145 146 /* HCCA area */ 147 ohci_hcca_t *ohci_hccap; /* Virtual HCCA ptr */ 148 ddi_dma_cookie_t ohci_hcca_cookie; /* DMA cookie */ 149 ddi_dma_handle_t ohci_hcca_dma_handle; /* DMA handle */ 150 ddi_acc_handle_t ohci_hcca_mem_handle; /* Memory handle */ 151 152 /* 153 * There are two pools of memory. One pool contains the memory for 154 * the transfer descriptors and other pool contains the memory for 155 * the endpoint descriptors. The advantage of the pools is that it's 156 * easy to go back and forth between the iommu and the cpu addresses. 157 * 158 * The pools are protected by the ohci_int_mutex because the memory 159 * in the pools may be accessed by either the host controller or the 160 * host controller driver. 161 */ 162 163 /* General transfer descriptor pool */ 164 ohci_td_t *ohci_td_pool_addr; /* Start of the pool */ 165 ddi_dma_cookie_t ohci_td_pool_cookie; /* DMA cookie */ 166 ddi_dma_handle_t ohci_td_pool_dma_handle; /* DMA hndle */ 167 ddi_acc_handle_t ohci_td_pool_mem_handle; /* Mem hndle */ 168 169 /* Endpoint descriptor pool */ 170 ohci_ed_t *ohci_ed_pool_addr; /* Start of the pool */ 171 ddi_dma_cookie_t ohci_ed_pool_cookie; /* DMA cookie */ 172 ddi_dma_handle_t ohci_ed_pool_dma_handle; /* DMA handle */ 173 ddi_acc_handle_t ohci_ed_pool_mem_handle; /* Mem handle */ 174 uint_t ohci_dma_addr_bind_flag; /* DMA flag */ 175 176 /* Condition variables */ 177 kcondvar_t ohci_SOF_cv; /* SOF variable */ 178 179 /* Semaphore to serialize opens and closes */ 180 ksema_t ohci_ocsem; 181 182 /* 183 * Bandwidth fields 184 * 185 * The ohci_bandwidth array keeps track of the allocated bandwidth 186 * for this host controller. The total bandwidth allocated for least 187 * allocated list out of the 32 periodic lists is represented by the 188 * ohci_periodic_minimum_bandwidth field. 189 */ 190 uint_t ohci_periodic_minimum_bandwidth; 191 uint_t ohci_periodic_bandwidth[NUM_INTR_ED_LISTS]; 192 193 /* Different transfer open pipe counts */ 194 uint_t ohci_open_pipe_count; 195 uint_t ohci_open_ctrl_pipe_count; 196 uint_t ohci_open_bulk_pipe_count; 197 uint_t ohci_open_periodic_pipe_count; 198 uint_t ohci_open_isoch_pipe_count; 199 /* 200 * Endpoint Reclamation List 201 * 202 * The interrupt or isochronous list processing cannot be stopped 203 * when a periodic endpoint is removed from the list. The endpoints 204 * are detached from the interrupt lattice tree and put on to the 205 * reclaimation list. On next SOF interrupt all those endpoints, 206 * which are on the reclaimation list will be deallocated. 207 */ 208 ohci_ed_t *ohci_reclaim_list; /* Reclaimation list */ 209 210 ohci_root_hub_t ohci_root_hub; /* Root hub info */ 211 212 /* 213 * Global transfer timeout handling & this transfer timeout handling 214 * will be per USB Host Controller. 215 */ 216 struct ohci_trans_wrapper *ohci_timeout_list; /* Timeout List */ 217 timeout_id_t ohci_timer_id; /* Timer id */ 218 219 /* Frame number overflow information */ 220 usb_frame_number_t ohci_fno; 221 222 /* For Schedule Overrun error counter */ 223 uint_t ohci_so_error; 224 225 /* For host controller error counter */ 226 uint_t ohci_hc_error; 227 228 /* For SOF interrupt event */ 229 boolean_t ohci_sof_flag; 230 231 /* Openhci Host Controller Software State information */ 232 uint_t ohci_hc_soft_state; 233 234 /* 235 * ohci_save_intr_stats is used to save the normal mode interrupt 236 * status information while executing interrupt handler & also by 237 * the polled code if an interrupt is pending for the normal mode 238 * when polled code is entered. 239 */ 240 ohci_save_intr_sts_t ohci_save_intr_sts; 241 242 /* 243 * Saved copy of the ohci registers of the normal mode & change 244 * required ohci registers values for the polled mode operation. 245 * Before returning from the polled mode to normal mode replace 246 * the required current registers with this saved ohci registers 247 * copy. 248 */ 249 ohci_regs_t ohci_polled_save_regs; 250 251 /* 252 * Saved copy of the interrupt table used in normal ohci mode and 253 * replace this table by another interrupt table that used in the 254 * POLLED mode. 255 */ 256 ohci_ed_t *ohci_polled_save_IntTble[NUM_INTR_ED_LISTS]; 257 258 /* ohci polled mode enter counter for the input devices */ 259 uint_t ohci_polled_enter_count; 260 261 /* 262 * Counter for polled mode and used in suspend mode to see if 263 * there is a input device connected. 264 */ 265 uint_t ohci_polled_kbd_count; 266 267 /* Done list for the Polled mode */ 268 ohci_td_t *ohci_polled_done_list; 269 270 /* Log handle for debug, console, log messages */ 271 usb_log_handle_t ohci_log_hdl; 272 273 /* Kstat structures */ 274 kstat_t *ohci_intrs_stats; 275 kstat_t *ohci_total_stats; 276 kstat_t *ohci_count_stats[USB_N_COUNT_KSTATS]; 277 } ohci_state_t; 278 279 typedef struct ohci_intrs_stats { 280 struct kstat_named ohci_hcr_intr_so; 281 struct kstat_named ohci_hcr_intr_wdh; 282 struct kstat_named ohci_hcr_intr_sof; 283 struct kstat_named ohci_hcr_intr_rd; 284 struct kstat_named ohci_hcr_intr_ue; 285 struct kstat_named ohci_hcr_intr_fno; 286 struct kstat_named ohci_hcr_intr_rhsc; 287 struct kstat_named ohci_hcr_intr_oc; 288 struct kstat_named ohci_hcr_intr_not_claimed; 289 struct kstat_named ohci_hcr_intr_total; 290 } ohci_intrs_stats_t; 291 292 /* 293 * ohci kstat defines 294 */ 295 #define OHCI_INTRS_STATS(ohci) ((ohci)->ohci_intrs_stats) 296 #define OHCI_INTRS_STATS_DATA(ohci) \ 297 ((ohci_intrs_stats_t *)OHCI_INTRS_STATS((ohci))->ks_data) 298 299 #define OHCI_TOTAL_STATS(ohci) ((ohci)->ohci_total_stats) 300 #define OHCI_TOTAL_STATS_DATA(ohci) (KSTAT_IO_PTR((ohci)->ohci_total_stats)) 301 #define OHCI_CTRL_STATS(ohci) \ 302 (KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_CONTROL])) 303 #define OHCI_BULK_STATS(ohci) \ 304 (KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_BULK])) 305 #define OHCI_INTR_STATS(ohci) \ 306 (KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_INTR])) 307 #define OHCI_ISOC_STATS(ohci) \ 308 (KSTAT_IO_PTR((ohci)->ohci_count_stats[USB_EP_ATTR_ISOCH])) 309 310 /* warlock directives, stable data */ 311 _NOTE(MUTEX_PROTECTS_DATA(ohci_state_t::ohci_int_mutex, ohci_state_t)) 312 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_intr_pri)) 313 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_dip)) 314 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_regsp)) 315 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_instance)) 316 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_vendor_id)) 317 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_device_id)) 318 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_rev_id)) 319 320 /* this may not be stable data in the future */ 321 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_td_pool_addr)) 322 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_td_pool_mem_handle)) 323 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_ed_pool_addr)) 324 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_ed_pool_mem_handle)) 325 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_td_pool_cookie)) 326 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_ed_pool_cookie)) 327 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_hcca_mem_handle)) 328 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_hccap)) 329 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_dma_addr_bind_flag)) 330 _NOTE(DATA_READABLE_WITHOUT_LOCK(ohci_state_t::ohci_log_hdl)) 331 332 _NOTE(LOCK_ORDER(ohci_state::ohci_int_mutex \ 333 usba_pipe_handle_data::p_mutex \ 334 usba_device::usb_mutex \ 335 usba_ph_impl::usba_ph_mutex)) 336 337 /* 338 * Host Contoller Software States 339 * 340 * OHCI_CTLR_INIT_STATE: 341 * The host controller soft state will be set to this during the 342 * ohci_attach. 343 * 344 * OHCI_CTLR_SUSPEND_STATE: 345 * The host controller soft state will be set to this during the 346 * ohci_cpr_suspend. 347 * 348 * OHCI_CTLR_OPERATIONAL_STATE: 349 * The host controller soft state will be set to this after moving 350 * host controller to operational state and host controller start 351 * generating SOF successfully. 352 * 353 * OHCI_CTLR_ERROR_STATE: 354 * The host controller soft state will be set to this during the 355 * no SOF or UE error conditions. 356 * 357 * Under this state or condition, only pipe stop polling, pipe reset 358 * and pipe close are allowed. But all other entry points like pipe 359 * open, get/set pipe policy, cotrol send/receive, bulk send/receive 360 * isoch send/receive, start polling etc. will fail. 361 * 362 * State Diagram for the host controller software state 363 * 364 * 365 * ohci_attach->[INIT_STATE] 366 * | 367 * | -------->----[ERROR_STATE]--<-----------<--- 368 * | | Failure (UE/no SOF condition) | 369 * | ^ ^ 370 * V | Success | 371 * ohci_init_ctlr--->--------[OPERATIONAL_STATE]------>-ohci_send/recv/polling 372 * ^ | 373 * | | 374 * | V 375 * -<-ohci_cpr_resume--[SUSPEND_STATE]-<-ohci_cpr_suspend 376 */ 377 #define OHCI_CTLR_INIT_STATE 0 /* Initilization state */ 378 #define OHCI_CTLR_SUSPEND_STATE 1 /* Suspend state */ 379 #define OHCI_CTLR_OPERATIONAL_STATE 2 /* Operational state */ 380 #define OHCI_CTLR_ERROR_STATE 3 /* Ue error or no sof state */ 381 382 /* 383 * Define all ohci's Vendor-id and Device-id Here 384 */ 385 #define RIO_VENDOR 0x108e 386 #define RIO_DEVICE 0x1103 387 #define OHCI_IS_RIO(ohcip) (ohcip->ohci_vendor_id == RIO_VENDOR) 388 389 /* 390 * Periodic and non-periodic macros 391 */ 392 #define OHCI_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 393 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) ||\ 394 ((endpoint->bmAttributes &\ 395 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH)) 396 397 #define OHCI_NON_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 398 USB_EP_ATTR_MASK) == USB_EP_ATTR_CONTROL) ||\ 399 ((endpoint->bmAttributes &\ 400 USB_EP_ATTR_MASK) == USB_EP_ATTR_BULK)) 401 402 /* 403 * OHCI ED and TD Pool sizes. 404 */ 405 #define OHCI_ED_POOL_SIZE 100 406 #define OHCI_TD_POOL_SIZE 200 407 408 /* 409 * ohci_dma_addr_bind_flag values 410 * 411 * This flag indicates if the various DMA addresses allocated by the OHCI 412 * have been bound to their respective handles. This is needed to recover 413 * without errors from ohci_cleanup when it calls ddi_dma_unbind_handle() 414 */ 415 #define OHCI_TD_POOL_BOUND 0x01 /* For TD pools */ 416 #define OHCI_ED_POOL_BOUND 0x02 /* For ED pools */ 417 #define OHCI_HCCA_DMA_BOUND 0x04 /* For HCCA area */ 418 419 /* 420 * Maximum SOF wait count 421 */ 422 #define MAX_SOF_WAIT_COUNT 2 /* Wait for maximum SOF frames */ 423 424 425 /* 426 * Pipe private structure 427 * 428 * There is an instance of this structure per pipe. This structure holds 429 * HCD specific pipe information. A pointer to this structure is kept in 430 * the USBA pipe handle (usba_pipe_handle_data_t). 431 */ 432 typedef struct ohci_pipe_private { 433 usba_pipe_handle_data_t *pp_pipe_handle; /* Back ptr to handle */ 434 ohci_ed_t *pp_ept; /* Pipe's ept */ 435 436 /* State of the pipe */ 437 uint_t pp_state; /* See below */ 438 439 /* Local copy of the pipe policy */ 440 usb_pipe_policy_t pp_policy; 441 442 /* For Periodic Pipes Only */ 443 uint_t pp_node; /* Node in lattice */ 444 uint_t pp_cur_periodic_req_cnt; /* Curr req count */ 445 uint_t pp_max_periodic_req_cnt; /* Max req count */ 446 447 /* For isochronous pipe only */ 448 usb_frame_number_t pp_next_frame_number; /* Next frame no */ 449 450 /* 451 * Each pipe may have multiple transfer wrappers. Each transfer 452 * wrapper represents a USB transfer on the bus. A transfer is 453 * made up of one or more transactions. 454 */ 455 struct ohci_trans_wrapper *pp_tw_head; /* Head of the list */ 456 struct ohci_trans_wrapper *pp_tw_tail; /* Tail of the list */ 457 458 /* Done td count */ 459 uint_t pp_count_done_tds; /* Done td count */ 460 461 /* Errors */ 462 usb_cr_t pp_error; /* Pipe error */ 463 464 /* Flags */ 465 uint_t pp_flag; /* Flags */ 466 467 /* Condition variable for transfers completion event */ 468 kcondvar_t pp_xfer_cmpl_cv; /* Xfer completion */ 469 470 /* 471 * HCD gets Interrupt/Isochronous IN polling request only once and 472 * it has to insert next polling requests after completion of first 473 * request until either stop polling/pipe close is called. So HCD 474 * has to take copy of the original Interrupt/Isochronous IN request. 475 */ 476 usb_opaque_t pp_client_periodic_in_reqp; 477 } ohci_pipe_private_t; 478 479 /* warlock directives, stable data */ 480 _NOTE(MUTEX_PROTECTS_DATA(ohci_state_t::ohci_int_mutex, ohci_pipe_private_t)) 481 482 /* 483 * Pipe states 484 * 485 * ohci pipe states will be similar to usba. Refer usbai.h. 486 */ 487 #define OHCI_PIPE_STATE_IDLE 1 /* Pipe is in ready state */ 488 #define OHCI_PIPE_STATE_ACTIVE 2 /* Pipe is in busy state */ 489 #define OHCI_PIPE_STATE_ERROR 3 /* Pipe is in error state */ 490 491 /* Additional ohci pipe states for the ohci_pipe_cleanup */ 492 #define OHCI_PIPE_STATE_CLOSE 4 /* Pipe close */ 493 #define OHCI_PIPE_STATE_RESET 5 /* Pipe reset */ 494 #define OHCI_PIPE_STATE_STOP_POLLING 6 /* Pipe stop polling */ 495 496 /* 497 * Pipe specific Flags 498 */ 499 #define OHCI_ISOC_XFER_CONTINUE 1 /* For isoc transfers */ 500 501 /* 502 * The maximum allowable usb isochronous data transfer size or maximum 503 * number of isochronous data packets. 504 * 505 * Each usb isochronous request must not exceed multiples of isochronous 506 * endpoint packet size and OHCI_MAX_ISOC_PKTS_PER_XFER. 507 * 508 * Ex: usb isochronous endpoint maximum packet size is 64 bytes 509 * maximum usb isochronous request will be OHCI_MAX_ISOC_PKTS_PER_XFER 510 * * 64 bytes 511 */ 512 #define OHCI_MAX_ISOC_PKTS_PER_XFER 256 /* Max pkts per req */ 513 514 /* 515 * The ohci supports maximum of eight isochronous data packets per transfer 516 * descriptor. 517 */ 518 #define OHCI_ISOC_PKTS_PER_TD 8 /* Packets per TD */ 519 520 /* 521 * USB frame offset 522 * 523 * Add appropriate frame offset to the current usb frame number and use it 524 * as a starting frame number for a given usb isochronous request. 525 */ 526 #define OHCI_FRAME_OFFSET 2 /* Frame offset */ 527 528 /* 529 * Default usb isochronous receive packets per request before ohci will do 530 * callback. 531 */ 532 #define OHCI_DEFAULT_ISOC_RCV_PKTS 1 /* isoc pkts per req */ 533 534 /* 535 * Different interrupt polling intervals supported 536 */ 537 #define INTR_1MS_POLL 1 538 #define INTR_2MS_POLL 2 539 #define INTR_4MS_POLL 4 540 #define INTR_8MS_POLL 8 541 #define INTR_16MS_POLL 16 542 #define INTR_32MS_POLL 32 543 544 /* 545 * Number of interrupt/isochronous transfer requests that should 546 * be maintained on the interrupt/isochronous endpoint corresponding 547 * to different polling intervals supported. 548 */ 549 #define INTR_1MS_REQS 4 /* 1ms polling interval */ 550 #define INTR_2MS_REQS 2 /* 2ms polling interval */ 551 #define INTR_XMS_REQS 1 /* Between 4ms and 32ms */ 552 553 /* Function prototype */ 554 typedef void (*ohci_handler_function_t)( 555 ohci_state_t *ohcip, 556 ohci_pipe_private_t *pp, 557 struct ohci_trans_wrapper *tw, 558 ohci_td_t *td, 559 void *ohci_handle_callback_value); 560 561 562 /* 563 * Transfer wrapper 564 * 565 * The transfer wrapper represents a USB transfer on the bus and there 566 * is one instance per USB transfer. A transfer is made up of one or 567 * more transactions. OHCI uses one TD for one transaction. So one 568 * transfer wrapper may have one or more TDs associated. 569 * 570 * Control and bulk pipes will have one transfer wrapper per transfer 571 * and where as Isochronous and Interrupt pipes will only have one 572 * transfer wrapper. The transfers wrapper are continually reused for 573 * the Interrupt and Isochronous pipes as those pipes are polled. 574 * 575 * Control, bulk and interrupt transfers will have one DMA buffer per 576 * transfer. The data to be transferred are contained in the DMA buffer 577 * which is virtually contiguous but physically discontiguous. When 578 * preparing the TDs for a USB transfer, the DMA cookies contained in 579 * the buffer need to be walked through to retrieve the DMA addresses. 580 * 581 * Isochronous transfers may have multiple DMA buffers per transfer 582 * with each isoc TD having a DMA buffer. And one isoc TD may hold up to 583 * eight isoc packets, but two cookies at most. 584 */ 585 typedef struct ohci_trans_wrapper { 586 struct ohci_trans_wrapper *tw_next; /* Next wrapper */ 587 ohci_pipe_private_t *tw_pipe_private; /* Back ptr */ 588 ddi_dma_handle_t tw_dmahandle; /* DMA handle */ 589 ddi_acc_handle_t tw_accesshandle; /* Acc hndle */ 590 ddi_dma_cookie_t tw_cookie; /* DMA cookie */ 591 uint32_t tw_id; /* 32bit ID */ 592 size_t tw_length; /* Txfer length */ 593 char *tw_buf; /* Buffer for Xfer */ 594 uint_t tw_ncookies; /* DMA cookie count */ 595 uint_t tw_cookie_idx; /* DMA cookie index */ 596 size_t tw_dma_offs; /* DMA buffer offset */ 597 usb_flags_t tw_flags; /* Flags */ 598 uint_t tw_num_tds; /* Number of TDs */ 599 ohci_td_t *tw_hctd_head; /* Head TD */ 600 ohci_td_t *tw_hctd_tail; /* Tail TD */ 601 uint_t tw_direction; /* Direction of TD */ 602 uint_t tw_pkt_idx; /* packet index */ 603 604 /* We preallocate all the td's for each tw and place them here */ 605 ohci_td_t *tw_hctd_free_list; 606 607 /* Current transfer request pointer */ 608 usb_opaque_t tw_curr_xfer_reqp; 609 610 /* Current isochronous packet descriptor pointer */ 611 usb_isoc_pkt_descr_t *tw_curr_isoc_pktp; 612 613 /* Isochronous DMA handlers and buffer pointers are stored here */ 614 ohci_isoc_buf_t *tw_isoc_bufs; 615 size_t tw_isoc_strtlen; 616 617 /* Transfer timeout information */ 618 uint_t tw_timeout; /* Timeout value */ 619 struct ohci_trans_wrapper *tw_timeout_next; /* Xfer Timeout Q */ 620 621 /* 622 * This is the function to call when this td is done. This way 623 * we don't have to look in the td to figure out what kind it is. 624 */ 625 ohci_handler_function_t tw_handle_td; 626 627 /* 628 * This is the callback value used when processing a done td. 629 */ 630 usb_opaque_t tw_handle_callback_value; 631 } ohci_trans_wrapper_t; 632 633 _NOTE(MUTEX_PROTECTS_DATA(ohci_state_t::ohci_int_mutex, ohci_trans_wrapper)) 634 635 636 /* 637 * Time waits for the different OHCI specific operations. 638 * These timeout values are specified in terms of microseconds. 639 */ 640 #define OHCI_RESET_TIMEWAIT 10000 /* HC reset waiting time */ 641 #define OHCI_RESUME_TIMEWAIT 40000 /* HC resume waiting time */ 642 #define OHCI_TIMEWAIT 10000 /* HC any other waiting time */ 643 644 /* These timeout values are specified in seconds */ 645 #define OHCI_DEFAULT_XFER_TIMEOUT 5 /* Default transfer timeout */ 646 #define OHCI_MAX_SOF_TIMEWAIT 3 /* Maximum SOF waiting time */ 647 #define OHCI_XFER_CMPL_TIMEWAIT 3 /* Xfers completion timewait */ 648 649 /* OHCI flags for general use */ 650 #define OHCI_FLAGS_NOSLEEP 0x000 /* Don't wait for SOF */ 651 #define OHCI_FLAGS_SLEEP 0x100 /* Wait for SOF */ 652 #define OHCI_FLAGS_DMA_SYNC 0x200 /* Call ddi_dma_sync */ 653 654 /* 655 * Maximum allowable data transfer size per transaction as supported 656 * by OHCI is 8k. (See Open Host Controller Interface Spec rev 1.0a) 657 */ 658 #define OHCI_MAX_TD_XFER_SIZE 0x2000 /* Maxmum data per transaction */ 659 660 /* 661 * One OHCI TD allows two physically discontiguous pages. The page size 662 * is 4k. 663 */ 664 #define OHCI_MAX_TD_BUF_SIZE 0x1000 665 666 /* 667 * The maximum allowable bulk data transfer size. It can be different 668 * from OHCI_MAX_TD_XFER_SIZE and if it is more then ohci driver will 669 * take care of breaking a bulk data request into multiples of ohci 670 * OHCI_MAX_TD_XFER_SIZE until request is satisfied. Currently this 671 * value is set to 256k bytes. 672 */ 673 #define OHCI_MAX_BULK_XFER_SIZE 0x40000 /* Maximum bulk transfer size */ 674 675 /* 676 * Timeout flags 677 * 678 * These flags will be used to stop the timer before timeout handler 679 * gets executed. 680 */ 681 #define OHCI_REMOVE_XFER_IFLAST 1 /* Stop the timer if it is last TD */ 682 #define OHCI_REMOVE_XFER_ALWAYS 2 /* Stop the timer without condition */ 683 684 685 /* 686 * Bandwidth allocation 687 * 688 * The following definitions are used during bandwidth calculations 689 * for a given endpoint maximum packet size. 690 */ 691 #define MAX_USB_BUS_BANDWIDTH 1500 /* Up to 1500 bytes per frame */ 692 #define MAX_POLL_INTERVAL 255 /* Maximum polling interval */ 693 #define MIN_POLL_INTERVAL 1 /* Minimum polling interval */ 694 #define SOF 6 /* Length in bytes of SOF */ 695 #define EOF 4 /* Length in bytes of EOF */ 696 #define TREE_HEIGHT 5 /* Log base 2 of 32 */ 697 698 /* 699 * Minimum polling interval for low speed endpoint 700 * 701 * According USB Specifications, a full-speed endpoint can specify 702 * a desired polling interval 1ms to 255ms and a low speed endpoints 703 * are limited to specifying only 10ms to 255ms. But some old keyboards 704 * and mice uses polling interval of 8ms. For compatibility purpose, 705 * we are using polling interval between 8ms and 255ms for low speed 706 * endpoints. But ohci driver will reject any low speed endpoints which 707 * request polling interval less than 8ms. 708 */ 709 #define MIN_LOW_SPEED_POLL_INTERVAL 8 710 711 /* 712 * For non-periodic transfers, reserve atleast for one low-speed device 713 * transaction. According to USB Bandwidth Analysis white paper and also 714 * as per OHCI Specification 1.0a, section 7.3.5, page 123, one low-speed 715 * transaction takes 0x628h full speed bits (197 bytes), which comes to 716 * around 13% of USB frame time. 717 * 718 * The periodic transfers will get around 87% of USB frame time. 719 */ 720 #define MAX_NON_PERIODIC_BANDWIDTH 197 721 #define MAX_PERIODIC_BANDWIDTH (MAX_USB_BUS_BANDWIDTH - SOF - \ 722 EOF - MAX_NON_PERIODIC_BANDWIDTH) 723 724 /* 725 * The USB periodic transfers like interrupt and isochronous transfers 726 * after completion of SOF and USB non-periodic transfers. 727 */ 728 #define PERIODIC_XFER_STARTS (MAX_USB_BUS_BANDWIDTH - \ 729 SOF - MAX_NON_PERIODIC_BANDWIDTH) 730 731 /* Number of Bits Per Byte */ 732 #define BITS_PER_BYTE 8 733 734 /* 735 * The following are the protocol overheads in terms of Bytes for the 736 * different transfer types. All these protocol overhead values are 737 * derived from the 5.9.3 section of USB Specification and with the 738 * help of Bandwidth Analysis white paper which is posted on the USB 739 * developer forum. 740 */ 741 #define FS_NON_ISOC_PROTO_OVERHEAD 14 742 #define FS_ISOC_INPUT_PROTO_OVERHEAD 11 743 #define FS_ISOC_OUTPUT_PROTO_OVERHEAD 10 744 #define LOW_SPEED_PROTO_OVERHEAD 97 745 #define HUB_LOW_SPEED_PROTO_OVERHEAD 01 746 747 /* 748 * The Host Controller (HC) delays are the USB host controller specific 749 * delays. The value shown below is the host controller delay for the 750 * RIO USB host controller. This value was calculated and given by the 751 * Sun USB hardware people. 752 */ 753 #define HOST_CONTROLLER_DELAY 18 754 755 /* 756 * The low speed clock below represents that to transmit one low-speed 757 * bit takes eight times more than one full speed bit time. 758 */ 759 #define LOW_SPEED_CLOCK 8 760 761 762 /* 763 * Macros for setting/getting information 764 */ 765 #define Get_ED(addr) ddi_get32(ohcip->ohci_ed_pool_mem_handle, \ 766 (uint32_t *)&addr) 767 768 #define Set_ED(addr, val) ddi_put32(ohcip->ohci_ed_pool_mem_handle, \ 769 ((uint32_t *)&addr), \ 770 ((int32_t)(val))) 771 772 #define Get_TD(addr) ddi_get32(ohcip->ohci_td_pool_mem_handle, \ 773 (uint32_t *)&addr) 774 775 #define Set_TD(addr, val) ddi_put32(ohcip->ohci_td_pool_mem_handle, \ 776 ((uint32_t *)&addr), \ 777 ((uint32_t)(uintptr_t)(val))) 778 779 #define Get_HCCA(addr) ddi_get32(ohcip->ohci_hcca_mem_handle, \ 780 (uint32_t *)&addr) 781 782 #define Set_HCCA(addr, val) ddi_put32(ohcip->ohci_hcca_mem_handle, \ 783 ((uint32_t *)&addr), \ 784 ((int32_t)(val))) 785 786 #define Get_OpReg(addr) ddi_get32(ohcip->ohci_regs_handle, \ 787 (uint32_t *)&ohcip->ohci_regsp->addr) 788 789 #define Set_OpReg(addr, val) ddi_put32(ohcip->ohci_regs_handle, \ 790 ((uint32_t *)&ohcip->ohci_regsp->addr), \ 791 ((int32_t)(val))) 792 793 #define Sync_HCCA(ohcip) (void) ddi_dma_sync( \ 794 ohcip->ohci_hcca_dma_handle, \ 795 0, sizeof (ohci_hcca_t), \ 796 DDI_DMA_SYNC_FORCPU); 797 798 #define Sync_ED_TD_Pool(ohcip) (void) ddi_dma_sync( \ 799 ohcip->ohci_ed_pool_dma_handle, \ 800 0, OHCI_ED_POOL_SIZE * sizeof (ohci_ed_t), \ 801 DDI_DMA_SYNC_FORCPU); \ 802 (void) ddi_dma_sync( \ 803 ohcip->ohci_td_pool_dma_handle, \ 804 0, OHCI_TD_POOL_SIZE * sizeof (ohci_td_t), \ 805 DDI_DMA_SYNC_FORCPU); 806 807 #define Sync_IO_Buffer(dma_handle, length) \ 808 (void) ddi_dma_sync(dma_handle, \ 809 0, length, DDI_DMA_SYNC_FORCPU); 810 811 /* 812 * Macros to speed handling of 32bit IDs 813 */ 814 #define OHCI_GET_ID(x) id32_alloc((void *)(x), KM_SLEEP) 815 #define OHCI_LOOKUP_ID(x) id32_lookup((x)) 816 #define OHCI_FREE_ID(x) id32_free((x)) 817 818 819 /* 820 * Miscellaneous definitions. 821 */ 822 823 /* Data toggle bits */ 824 #define DATA0 0 825 #define DATA1 1 826 827 /* sKip bit actions */ 828 #define CLEAR_sKip 0 829 #define SET_sKip 1 830 831 typedef uint_t skip_bit_t; 832 833 /* 834 * Setup Packet 835 */ 836 typedef struct setup_pkt { 837 uchar_t bmRequestType; 838 uchar_t bRequest; 839 ushort_t wValue; 840 ushort_t wIndex; 841 ushort_t wLength; 842 }setup_pkt_t; 843 844 #define SETUP_SIZE 8 /* Setup packet is always 8 bytes */ 845 846 #define REQUEST_TYPE_OFFSET 0 847 #define REQUEST_OFFSET 1 848 #define VALUE_OFFSET 2 849 #define INDEX_OFFSET 4 850 #define LENGTH_OFFSET 6 851 852 #define TYPE_DEV_TO_HOST 0x80000000 853 #define DEVICE 0x00000001 854 #define CONFIGURATION 0x00000002 855 856 /* 857 * The following are used in attach to indicate 858 * what has been succesfully allocated, so detach 859 * can remove them. 860 */ 861 #define OHCI_ATTACH 0x01 /* ohci driver initilization */ 862 #define OHCI_ZALLOC 0x02 /* Memory for ohci state structure */ 863 #define OHCI_INTR 0x04 /* Interrupt handler registered */ 864 #define OHCI_USBAREG 0x08 /* USBA registered */ 865 #define OHCI_RHREG 0x10 /* Root hub driver loaded */ 866 867 #define OHCI_UNIT(dev) (getminor((dev)) & ~HUBD_IS_ROOT_HUB) 868 869 /* 870 * Debug printing 871 * Masks 872 */ 873 #define PRINT_MASK_ATTA 0x00000001 /* Attach time */ 874 #define PRINT_MASK_LISTS 0x00000002 /* List management */ 875 #define PRINT_MASK_ROOT_HUB 0x00000004 /* Root hub stuff */ 876 #define PRINT_MASK_ALLOC 0x00000008 /* Alloc/dealloc descr */ 877 #define PRINT_MASK_INTR 0x00000010 /* Interrupt handling */ 878 #define PRINT_MASK_BW 0x00000020 /* Bandwidth */ 879 #define PRINT_MASK_CBOPS 0x00000040 /* CB-OPS */ 880 #define PRINT_MASK_HCDI 0x00000080 /* HCDI entry points */ 881 #define PRINT_MASK_DUMPING 0x00000100 /* Dump ohci info */ 882 #define PRINT_MASK_ALL 0xFFFFFFFF 883 884 885 /* Polling support */ 886 int ohci_hcdi_polled_input_init( 887 usba_pipe_handle_data_t *ph, 888 uchar_t **polled_buf, 889 usb_console_info_impl_t *info); 890 int ohci_hcdi_polled_input_enter( 891 usb_console_info_impl_t *info); 892 int ohci_hcdi_polled_read( 893 usb_console_info_impl_t *info, 894 uint_t *num_characters); 895 int ohci_hcdi_polled_input_exit( 896 usb_console_info_impl_t *info); 897 int ohci_hcdi_polled_input_fini( 898 usb_console_info_impl_t *info); 899 900 /* Root hub related functions */ 901 int ohci_init_root_hub( 902 ohci_state_t *ohcip); 903 int ohci_load_root_hub_driver( 904 ohci_state_t *ohcip); 905 int ohci_unload_root_hub_driver( 906 ohci_state_t *ohcip); 907 int ohci_handle_root_hub_pipe_open( 908 usba_pipe_handle_data_t *ph, 909 usb_flags_t flags); 910 int ohci_handle_root_hub_pipe_close( 911 usba_pipe_handle_data_t *ph); 912 int ohci_handle_root_hub_pipe_reset( 913 usba_pipe_handle_data_t *ph, 914 usb_flags_t flags); 915 int ohci_handle_root_hub_request( 916 ohci_state_t *ohcip, 917 usba_pipe_handle_data_t *ph, 918 usb_ctrl_req_t *ctrl_reqp); 919 int ohci_handle_root_hub_pipe_start_intr_polling( 920 usba_pipe_handle_data_t *ph, 921 usb_intr_req_t *intr_reqp, 922 usb_flags_t flags); 923 void ohci_handle_root_hub_pipe_stop_intr_polling( 924 usba_pipe_handle_data_t *ph, 925 usb_flags_t flags); 926 void ohci_handle_root_hub_status_change(void *arg); 927 928 /* Endpoint Descriptor (ED) related functions */ 929 ohci_ed_t *ohci_alloc_hc_ed( 930 ohci_state_t *ohcip, 931 usba_pipe_handle_data_t *ph); 932 void ohci_deallocate_ed( 933 ohci_state_t *ohcip, 934 ohci_ed_t *old_ed); 935 uint32_t ohci_ed_cpu_to_iommu( 936 ohci_state_t *ohcip, 937 ohci_ed_t *addr); 938 939 /* Transfer Descriptor (TD) related functions */ 940 int ohci_start_periodic_pipe_polling( 941 ohci_state_t *ohcip, 942 usba_pipe_handle_data_t *ph, 943 usb_opaque_t periodic_in_reqp, 944 usb_flags_t flags); 945 void ohci_traverse_tds( 946 ohci_state_t *ohcip, 947 usba_pipe_handle_data_t *ph); 948 void ohci_deallocate_td( 949 ohci_state_t *ohcip, 950 ohci_td_t *old_td); 951 uint32_t ohci_td_cpu_to_iommu( 952 ohci_state_t *ohcip, 953 ohci_td_t *addr); 954 ohci_td_t *ohci_td_iommu_to_cpu( 955 ohci_state_t *ohcip, 956 uintptr_t addr); 957 size_t ohci_get_td_residue( 958 ohci_state_t *ohcip, 959 ohci_td_t *td); 960 void ohci_init_td( 961 ohci_state_t *ohcip, 962 ohci_trans_wrapper_t *tw, 963 uint32_t hctd_dma_offs, 964 size_t hctd_length, 965 ohci_td_t *td); 966 967 /* Transfer Wrapper (TW) functions */ 968 void ohci_deallocate_tw_resources( 969 ohci_state_t *ohcip, 970 ohci_pipe_private_t *pp, 971 ohci_trans_wrapper_t *tw); 972 973 /* Interrupt Handling functions */ 974 void ohci_handle_frame_number_overflow( 975 ohci_state_t *ohcip); 976 977 /* Miscillaneous functions */ 978 ohci_state_t *ohci_obtain_state( 979 dev_info_t *dip); 980 int ohci_state_is_operational( 981 ohci_state_t *ohcip); 982 int ohci_do_soft_reset( 983 ohci_state_t *ohcip); 984 usb_frame_number_t ohci_get_current_frame_number( 985 ohci_state_t *ohcip); 986 void ohci_handle_outstanding_requests( 987 ohci_state_t *ohcip, 988 ohci_pipe_private_t *pp); 989 990 #ifdef __cplusplus 991 } 992 #endif 993 994 #endif /* _SYS_USB_OHCID_H */ 995